186 _model = v;
187 } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
188 _revision = v;
189 }
190 }
191 }
192 fclose(f);
193 }
194
195 // Enable vendor specific features
196
197 // ThunderX
198 if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
199 if (_variant == 0) _features |= CPU_DMB_ATOMICS;
200 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
201 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
202 }
203 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
204 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
205 }
206 }
207 // ThunderX2
208 if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
209 (_cpu == CPU_BROADCOM && (_model == 0x516))) {
210 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
211 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
212 }
213 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
214 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
215 }
216 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
217 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
218 }
219 }
220
221 if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) _features |= CPU_A53MAC;
222 if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
223 // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
224 // we assume the worst and assume we could be on a big little system and have
225 // undisclosed A53 cores which we could be swapped to at any stage
226 if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
227
228 sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
229 if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
230 if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
231 if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
232 if (auxv & HWCAP_AES) strcat(buf, ", aes");
233 if (auxv & HWCAP_SHA1) strcat(buf, ", sha1");
234 if (auxv & HWCAP_SHA2) strcat(buf, ", sha256");
235 if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse");
236
237 _features_string = os::strdup(buf);
238
239 if (FLAG_IS_DEFAULT(UseCRC32)) {
240 UseCRC32 = (auxv & HWCAP_CRC32) != 0;
241 }
|
186 _model = v;
187 } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
188 _revision = v;
189 }
190 }
191 }
192 fclose(f);
193 }
194
195 // Enable vendor specific features
196
197 // ThunderX
198 if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
199 if (_variant == 0) _features |= CPU_DMB_ATOMICS;
200 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
201 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
202 }
203 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
204 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
205 }
206 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
207 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
208 }
209 }
210
211 // ThunderX2
212 if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
213 (_cpu == CPU_BROADCOM && (_model == 0x516))) {
214 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
215 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
216 }
217 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
218 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
219 }
220 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
221 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
222 }
223 }
224
225 // Cortex A53
226 if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) {
227 _features |= CPU_A53MAC;
228 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
229 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
230 }
231 }
232
233 // Cortex A73
234 if (_cpu == CPU_ARM && (_model == 0xd09 || _model2 == 0xd09)) {
235 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
236 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
237 }
238 // A73 is faster with short-and-easy-for-speculative-execution-loop
239 if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
240 FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
241 }
242 }
243
244 if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
245 // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
246 // we assume the worst and assume we could be on a big little system and have
247 // undisclosed A53 cores which we could be swapped to at any stage
248 if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
249
250 sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
251 if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
252 if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
253 if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
254 if (auxv & HWCAP_AES) strcat(buf, ", aes");
255 if (auxv & HWCAP_SHA1) strcat(buf, ", sha1");
256 if (auxv & HWCAP_SHA2) strcat(buf, ", sha256");
257 if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse");
258
259 _features_string = os::strdup(buf);
260
261 if (FLAG_IS_DEFAULT(UseCRC32)) {
262 UseCRC32 = (auxv & HWCAP_CRC32) != 0;
263 }
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