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src/hotspot/cpu/aarch64/assembler_aarch64.hpp
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*** 2279,2288 ****
--- 2279,2356 ----
INSN(aesmc, 0b0100111000101000011010);
INSN(aesimc, 0b0100111000101000011110);
#undef INSN
+ // vect1 += vect2*scalar. FMLA-Vector-Scalar-Double
+ void fmlavsd(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, int index) {
+ assert(index == 0 || index == 1, "Incorrect index");
+ starti;
+ f(0b01001111110, 31, 21);
+ rf(Vm, 16);
+ f(0b0001, 15, 12);
+ f(index, 11);
+ f(0, 10);
+ rf(Vn, 5);
+ rf(Vd, 0);
+ }
+
+ // vect1 += vect2*vect3. FMLA-Vector-Vector-Double
+ void fmlavvd(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
+ starti;
+ // 01001110011 Rm 110011 Rn Rd
+ f(0b01001110011, 31, 21);
+ rf(Vm, 16);
+ f(0b110011, 15, 10);
+ rf(Vn, 5);
+ rf(Vd, 0);
+ }
+
+ // Floating-point Reciprocal Estimate for single precision
+ void frecpe(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) {
+ assert(type == D || type == S, "Wrong type for frecpe");
+ starti;
+ f(0b010111101, 31, 23);
+ f(type == D ? 1 : 0, 22);
+ f(0b100001110110, 21, 10);
+ rf(Vn, 5), rf(Vd, 0);
+ }
+
+ // (double) {a, b} -> (a + b)
+ void faddpd(FloatRegister Vd, FloatRegister Vn) {
+ starti;
+ f(0b0111111001110000110110, 31, 10);
+ rf(Vn, 5), rf(Vd, 0);
+ }
+
+ // fmulxvd is vect(Vn)*Vm[index]. FMULX-Vector-Scalar-Double
+ void fmulxvsd(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, int index) {
+ assert(index == 0 || index == 1, "Incorrect index");
+ //Q=1, sz=1,L=0, M:Rm = Vm, H=index for T2D
+ starti;
+ f(0b01101111110, 31, 21);
+ rf(Vm, 16);
+ f(0b1001, 15, 12);
+ f(index, 11);
+ f(0, 10);
+ rf(Vn, 5);
+ rf(Vd, 0);
+ }
+
+ // fmulxsd is LO64(Vn)*Vm[index]. FULX-Scalar-Double
+ void fmulxssd(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, int index) {
+ // sz = 1, L = 0, H = index, M:Rm = Vm
+ starti;
+ f(0b01111111110, 31, 21);
+ rf(Vm, 16);
+ f(0b1001, 15, 12);
+ f(index, 11);
+ f(0, 10);
+ rf(Vn, 5);
+ rf(Vd, 0);
+ }
+
void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
starti;
assert(T != Q, "invalid register variant");
f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
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