1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
28
29 #include "asm/register.hpp"
30
31 // definitions of various symbolic names for machine registers
32
33 // First intercalls between C and Java which use 8 general registers
34 // and 8 floating registers
35
36 // we also have to copy between x86 and ARM registers but that's a
37 // secondary complication -- not all code employing C call convention
38 // executes as x86 code though -- we generate some of it
39
40 class Argument {
41 public:
42 enum {
43 n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
44 n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... )
45
46 n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
47 n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ...
48 };
49 };
50
51 REGISTER_DECLARATION(Register, c_rarg0, r0);
52 REGISTER_DECLARATION(Register, c_rarg1, r1);
53 REGISTER_DECLARATION(Register, c_rarg2, r2);
54 REGISTER_DECLARATION(Register, c_rarg3, r3);
55 REGISTER_DECLARATION(Register, c_rarg4, r4);
56 REGISTER_DECLARATION(Register, c_rarg5, r5);
57 REGISTER_DECLARATION(Register, c_rarg6, r6);
58 REGISTER_DECLARATION(Register, c_rarg7, r7);
59
60 REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
61 REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
62 REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
63 REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
64 REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
65 REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
66 REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
67 REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
68
69 // Symbolically name the register arguments used by the Java calling convention.
70 // We have control over the convention for java so we can do what we please.
71 // What pleases us is to offset the java calling convention so that when
72 // we call a suitable jni method the arguments are lined up and we don't
73 // have to do much shuffling. A suitable jni method is non-static and a
74 // small number of arguments
75 //
76 // |--------------------------------------------------------------------|
77 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 |
78 // |--------------------------------------------------------------------|
79 // | r0 r1 r2 r3 r4 r5 r6 r7 |
80 // |--------------------------------------------------------------------|
81 // | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 |
82 // |--------------------------------------------------------------------|
83
84
85 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
86 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
87 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
88 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
89 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
90 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
91 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
92 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
93
94 // Java floating args are passed as per C
95
96 REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
97 REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
98 REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
99 REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
100 REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
101 REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
102 REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
103 REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
104
105 // registers used to hold VM data either temporarily within a method
106 // or across method calls
107
108 // volatile (caller-save) registers
109
110 // r8 is used for indirect result location return
111 // we use it and r9 as scratch registers
112 REGISTER_DECLARATION(Register, rscratch1, r8);
113 REGISTER_DECLARATION(Register, rscratch2, r9);
114
115 // current method -- must be in a call-clobbered register
116 REGISTER_DECLARATION(Register, rmethod, r12);
117
118 // non-volatile (callee-save) registers are r16-29
119 // of which the following are dedicated global state
120
121 // link register
122 REGISTER_DECLARATION(Register, lr, r30);
123 // frame pointer
124 REGISTER_DECLARATION(Register, rfp, r29);
125 // current thread
126 REGISTER_DECLARATION(Register, rthread, r28);
127 // base of heap
128 REGISTER_DECLARATION(Register, rheapbase, r27);
129 // constant pool cache
130 REGISTER_DECLARATION(Register, rcpool, r26);
131 // monitors allocated on stack
132 REGISTER_DECLARATION(Register, rmonitors, r25);
133 // locals on stack
134 REGISTER_DECLARATION(Register, rlocals, r24);
135 // bytecode pointer
136 REGISTER_DECLARATION(Register, rbcp, r22);
137 // Dispatch table base
138 REGISTER_DECLARATION(Register, rdispatch, r21);
139 // Java stack pointer
140 REGISTER_DECLARATION(Register, esp, r20);
141
142 #define assert_cond(ARG1) assert(ARG1, #ARG1)
143
144 namespace asm_util {
145 uint32_t encode_logical_immediate(bool is32, uint64_t imm);
146 };
147
148 using namespace asm_util;
149
150
151 class Assembler;
152
153 class Instruction_aarch64 {
154 unsigned insn;
155 #ifdef ASSERT
156 unsigned bits;
157 #endif
158 Assembler *assem;
159
160 public:
161
162 Instruction_aarch64(class Assembler *as) {
163 #ifdef ASSERT
164 bits = 0;
165 #endif
166 insn = 0;
167 assem = as;
168 }
169
170 inline ~Instruction_aarch64();
171
172 unsigned &get_insn() { return insn; }
173 #ifdef ASSERT
174 unsigned &get_bits() { return bits; }
175 #endif
176
177 static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
178 union {
179 unsigned u;
180 int n;
181 };
182
183 u = val << (31 - hi);
184 n = n >> (31 - hi + lo);
185 return n;
186 }
187
188 static inline uint32_t extract(uint32_t val, int msb, int lsb) {
189 int nbits = msb - lsb + 1;
190 assert_cond(msb >= lsb);
191 uint32_t mask = (1U << nbits) - 1;
192 uint32_t result = val >> lsb;
193 result &= mask;
194 return result;
195 }
196
197 static inline int32_t sextract(uint32_t val, int msb, int lsb) {
198 uint32_t uval = extract(val, msb, lsb);
199 return extend(uval, msb - lsb);
200 }
201
202 static void patch(address a, int msb, int lsb, unsigned long val) {
203 int nbits = msb - lsb + 1;
204 guarantee(val < (1U << nbits), "Field too big for insn");
205 assert_cond(msb >= lsb);
206 unsigned mask = (1U << nbits) - 1;
207 val <<= lsb;
208 mask <<= lsb;
209 unsigned target = *(unsigned *)a;
210 target &= ~mask;
211 target |= val;
212 *(unsigned *)a = target;
213 }
214
215 static void spatch(address a, int msb, int lsb, long val) {
216 int nbits = msb - lsb + 1;
217 long chk = val >> (nbits - 1);
218 guarantee (chk == -1 || chk == 0, "Field too big for insn");
219 unsigned uval = val;
220 unsigned mask = (1U << nbits) - 1;
221 uval &= mask;
222 uval <<= lsb;
223 mask <<= lsb;
224 unsigned target = *(unsigned *)a;
225 target &= ~mask;
226 target |= uval;
227 *(unsigned *)a = target;
228 }
229
230 void f(unsigned val, int msb, int lsb) {
231 int nbits = msb - lsb + 1;
232 guarantee(val < (1U << nbits), "Field too big for insn");
233 assert_cond(msb >= lsb);
234 unsigned mask = (1U << nbits) - 1;
235 val <<= lsb;
236 mask <<= lsb;
237 insn |= val;
238 assert_cond((bits & mask) == 0);
239 #ifdef ASSERT
240 bits |= mask;
241 #endif
242 }
243
244 void f(unsigned val, int bit) {
245 f(val, bit, bit);
246 }
247
248 void sf(long val, int msb, int lsb) {
249 int nbits = msb - lsb + 1;
250 long chk = val >> (nbits - 1);
251 guarantee (chk == -1 || chk == 0, "Field too big for insn");
252 unsigned uval = val;
253 unsigned mask = (1U << nbits) - 1;
254 uval &= mask;
255 f(uval, lsb + nbits - 1, lsb);
256 }
257
258 void rf(Register r, int lsb) {
259 f(r->encoding_nocheck(), lsb + 4, lsb);
260 }
261
262 // reg|ZR
263 void zrf(Register r, int lsb) {
264 f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
265 }
266
267 // reg|SP
268 void srf(Register r, int lsb) {
269 f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
270 }
271
272 void rf(FloatRegister r, int lsb) {
273 f(r->encoding_nocheck(), lsb + 4, lsb);
274 }
275
276 unsigned get(int msb = 31, int lsb = 0) {
277 int nbits = msb - lsb + 1;
278 unsigned mask = ((1U << nbits) - 1) << lsb;
279 assert_cond(bits & mask == mask);
280 return (insn & mask) >> lsb;
281 }
282
283 void fixed(unsigned value, unsigned mask) {
284 assert_cond ((mask & bits) == 0);
285 #ifdef ASSERT
286 bits |= mask;
287 #endif
288 insn |= value;
289 }
290 };
291
292 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
293
294 class PrePost {
295 int _offset;
296 Register _r;
297 public:
298 PrePost(Register reg, int o) : _r(reg), _offset(o) { }
299 int offset() { return _offset; }
300 Register reg() { return _r; }
301 };
302
303 class Pre : public PrePost {
304 public:
305 Pre(Register reg, int o) : PrePost(reg, o) { }
306 };
307 class Post : public PrePost {
308 public:
309 Post(Register reg, int o) : PrePost(reg, o) { }
310 };
311
312 namespace ext
313 {
314 enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
315 };
316
317 // abs methods which cannot overflow and so are well-defined across
318 // the entire domain of integer types.
319 static inline unsigned int uabs(unsigned int n) {
320 union {
321 unsigned int result;
322 int value;
323 };
324 result = n;
325 if (value < 0) result = -result;
326 return result;
327 }
328 static inline unsigned long uabs(unsigned long n) {
329 union {
330 unsigned long result;
331 long value;
332 };
333 result = n;
334 if (value < 0) result = -result;
335 return result;
336 }
337 static inline unsigned long uabs(long n) { return uabs((unsigned long)n); }
338 static inline unsigned long uabs(int n) { return uabs((unsigned int)n); }
339
340 // Addressing modes
341 class Address {
342 public:
343
344 enum mode { no_mode, base_plus_offset, pre, post, pcrel,
345 base_plus_offset_reg, literal };
346
347 // Shift and extend for base reg + reg offset addressing
348 class extend {
349 int _option, _shift;
350 ext::operation _op;
351 public:
352 extend() { }
353 extend(int s, int o, ext::operation op) : _shift(s), _option(o), _op(op) { }
354 int option() const{ return _option; }
355 int shift() const { return _shift; }
356 ext::operation op() const { return _op; }
357 };
358 class uxtw : public extend {
359 public:
360 uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
361 };
362 class lsl : public extend {
363 public:
364 lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
365 };
366 class sxtw : public extend {
367 public:
368 sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
369 };
370 class sxtx : public extend {
371 public:
372 sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
373 };
374
375 private:
376 Register _base;
377 Register _index;
378 long _offset;
379 enum mode _mode;
380 extend _ext;
381
382 RelocationHolder _rspec;
383
384 // Typically we use AddressLiterals we want to use their rval
385 // However in some situations we want the lval (effect address) of
386 // the item. We provide a special factory for making those lvals.
387 bool _is_lval;
388
389 // If the target is far we'll need to load the ea of this to a
390 // register to reach it. Otherwise if near we can do PC-relative
391 // addressing.
392 address _target;
393
394 public:
395 Address()
396 : _mode(no_mode) { }
397 Address(Register r)
398 : _mode(base_plus_offset), _base(r), _offset(0), _index(noreg), _target(0) { }
399 Address(Register r, int o)
400 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
401 Address(Register r, long o)
402 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
403 Address(Register r, unsigned long o)
404 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
405 #ifdef ASSERT
406 Address(Register r, ByteSize disp)
407 : _mode(base_plus_offset), _base(r), _offset(in_bytes(disp)),
408 _index(noreg), _target(0) { }
409 #endif
410 Address(Register r, Register r1, extend ext = lsl())
411 : _mode(base_plus_offset_reg), _base(r), _index(r1),
412 _ext(ext), _offset(0), _target(0) { }
413 Address(Pre p)
414 : _mode(pre), _base(p.reg()), _offset(p.offset()) { }
415 Address(Post p)
416 : _mode(post), _base(p.reg()), _offset(p.offset()), _target(0) { }
417 Address(address target, RelocationHolder const& rspec)
418 : _mode(literal),
419 _rspec(rspec),
420 _is_lval(false),
421 _target(target) { }
422 Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
423 Address(Register base, RegisterOrConstant index, extend ext = lsl())
424 : _base (base),
425 _ext(ext), _offset(0), _target(0) {
426 if (index.is_register()) {
427 _mode = base_plus_offset_reg;
428 _index = index.as_register();
429 } else {
430 guarantee(ext.option() == ext::uxtx, "should be");
431 assert(index.is_constant(), "should be");
432 _mode = base_plus_offset;
433 _offset = index.as_constant() << ext.shift();
434 }
435 }
436
437 Register base() const {
438 guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
439 | _mode == post),
440 "wrong mode");
441 return _base;
442 }
443 long offset() const {
444 return _offset;
445 }
446 Register index() const {
447 return _index;
448 }
449 mode getMode() const {
450 return _mode;
451 }
452 bool uses(Register reg) const { return _base == reg || _index == reg; }
453 address target() const { return _target; }
454 const RelocationHolder& rspec() const { return _rspec; }
455
456 void encode(Instruction_aarch64 *i) const {
457 i->f(0b111, 29, 27);
458 i->srf(_base, 5);
459
460 switch(_mode) {
461 case base_plus_offset:
462 {
463 unsigned size = i->get(31, 30);
464 if (i->get(26, 26) && i->get(23, 23)) {
465 // SIMD Q Type - Size = 128 bits
466 assert(size == 0, "bad size");
467 size = 0b100;
468 }
469 unsigned mask = (1 << size) - 1;
470 if (_offset < 0 || _offset & mask)
471 {
472 i->f(0b00, 25, 24);
473 i->f(0, 21), i->f(0b00, 11, 10);
474 i->sf(_offset, 20, 12);
475 } else {
476 i->f(0b01, 25, 24);
477 i->f(_offset >> size, 21, 10);
478 }
479 }
480 break;
481
482 case base_plus_offset_reg:
483 {
484 i->f(0b00, 25, 24);
485 i->f(1, 21);
486 i->rf(_index, 16);
487 i->f(_ext.option(), 15, 13);
488 unsigned size = i->get(31, 30);
489 if (i->get(26, 26) && i->get(23, 23)) {
490 // SIMD Q Type - Size = 128 bits
491 assert(size == 0, "bad size");
492 size = 0b100;
493 }
494 if (size == 0) // It's a byte
495 i->f(_ext.shift() >= 0, 12);
496 else {
497 if (_ext.shift() > 0)
498 assert(_ext.shift() == (int)size, "bad shift");
499 i->f(_ext.shift() > 0, 12);
500 }
501 i->f(0b10, 11, 10);
502 }
503 break;
504
505 case pre:
506 i->f(0b00, 25, 24);
507 i->f(0, 21), i->f(0b11, 11, 10);
508 i->sf(_offset, 20, 12);
509 break;
510
511 case post:
512 i->f(0b00, 25, 24);
513 i->f(0, 21), i->f(0b01, 11, 10);
514 i->sf(_offset, 20, 12);
515 break;
516
517 default:
518 ShouldNotReachHere();
519 }
520 }
521
522 void encode_pair(Instruction_aarch64 *i) const {
523 switch(_mode) {
524 case base_plus_offset:
525 i->f(0b010, 25, 23);
526 break;
527 case pre:
528 i->f(0b011, 25, 23);
529 break;
530 case post:
531 i->f(0b001, 25, 23);
532 break;
533 default:
534 ShouldNotReachHere();
535 }
536
537 unsigned size; // Operand shift in 32-bit words
538
539 if (i->get(26, 26)) { // float
540 switch(i->get(31, 30)) {
541 case 0b10:
542 size = 2; break;
543 case 0b01:
544 size = 1; break;
545 case 0b00:
546 size = 0; break;
547 default:
548 ShouldNotReachHere();
549 size = 0; // unreachable
550 }
551 } else {
552 size = i->get(31, 31);
553 }
554
555 size = 4 << size;
556 guarantee(_offset % size == 0, "bad offset");
557 i->sf(_offset / size, 21, 15);
558 i->srf(_base, 5);
559 }
560
561 void encode_nontemporal_pair(Instruction_aarch64 *i) const {
562 // Only base + offset is allowed
563 i->f(0b000, 25, 23);
564 unsigned size = i->get(31, 31);
565 size = 4 << size;
566 guarantee(_offset % size == 0, "bad offset");
567 i->sf(_offset / size, 21, 15);
568 i->srf(_base, 5);
569 guarantee(_mode == Address::base_plus_offset,
570 "Bad addressing mode for non-temporal op");
571 }
572
573 void lea(MacroAssembler *, Register) const;
574
575 static bool offset_ok_for_immed(long offset, int shift = 0) {
576 unsigned mask = (1 << shift) - 1;
577 if (offset < 0 || offset & mask) {
578 return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset
579 } else {
580 return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset
581 }
582 }
583 };
584
585 // Convience classes
586 class RuntimeAddress: public Address {
587
588 public:
589
590 RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
591
592 };
593
594 class OopAddress: public Address {
595
596 public:
597
598 OopAddress(address target) : Address(target, relocInfo::oop_type){}
599
600 };
601
602 class ExternalAddress: public Address {
603 private:
604 static relocInfo::relocType reloc_for_target(address target) {
605 // Sometimes ExternalAddress is used for values which aren't
606 // exactly addresses, like the card table base.
607 // external_word_type can't be used for values in the first page
608 // so just skip the reloc in that case.
609 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
610 }
611
612 public:
613
614 ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
615
616 };
617
618 class InternalAddress: public Address {
619
620 public:
621
622 InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
623 };
624
625 const int FPUStateSizeInWords = 32 * 2;
626 typedef enum {
627 PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
628 PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
629 PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
630 } prfop;
631
632 class Assembler : public AbstractAssembler {
633
634 #ifndef PRODUCT
635 static const unsigned long asm_bp;
636
637 void emit_long(jint x) {
638 if ((unsigned long)pc() == asm_bp)
639 asm volatile ("nop");
640 AbstractAssembler::emit_int32(x);
641 }
642 #else
643 void emit_long(jint x) {
644 AbstractAssembler::emit_int32(x);
645 }
646 #endif
647
648 public:
649
650 enum { instruction_size = 4 };
651
652 Address adjust(Register base, int offset, bool preIncrement) {
653 if (preIncrement)
654 return Address(Pre(base, offset));
655 else
656 return Address(Post(base, offset));
657 }
658
659 Address pre(Register base, int offset) {
660 return adjust(base, offset, true);
661 }
662
663 Address post (Register base, int offset) {
664 return adjust(base, offset, false);
665 }
666
667 Instruction_aarch64* current;
668
669 void set_current(Instruction_aarch64* i) { current = i; }
670
671 void f(unsigned val, int msb, int lsb) {
672 current->f(val, msb, lsb);
673 }
674 void f(unsigned val, int msb) {
675 current->f(val, msb, msb);
676 }
677 void sf(long val, int msb, int lsb) {
678 current->sf(val, msb, lsb);
679 }
680 void rf(Register reg, int lsb) {
681 current->rf(reg, lsb);
682 }
683 void srf(Register reg, int lsb) {
684 current->srf(reg, lsb);
685 }
686 void zrf(Register reg, int lsb) {
687 current->zrf(reg, lsb);
688 }
689 void rf(FloatRegister reg, int lsb) {
690 current->rf(reg, lsb);
691 }
692 void fixed(unsigned value, unsigned mask) {
693 current->fixed(value, mask);
694 }
695
696 void emit() {
697 emit_long(current->get_insn());
698 assert_cond(current->get_bits() == 0xffffffff);
699 current = NULL;
700 }
701
702 typedef void (Assembler::* uncond_branch_insn)(address dest);
703 typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
704 typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
705 typedef void (Assembler::* prefetch_insn)(address target, prfop);
706
707 void wrap_label(Label &L, uncond_branch_insn insn);
708 void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
709 void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
710 void wrap_label(Label &L, prfop, prefetch_insn insn);
711
712 // PC-rel. addressing
713
714 void adr(Register Rd, address dest);
715 void _adrp(Register Rd, address dest);
716
717 void adr(Register Rd, const Address &dest);
718 void _adrp(Register Rd, const Address &dest);
719
720 void adr(Register Rd, Label &L) {
721 wrap_label(Rd, L, &Assembler::Assembler::adr);
722 }
723 void _adrp(Register Rd, Label &L) {
724 wrap_label(Rd, L, &Assembler::_adrp);
725 }
726
727 void adrp(Register Rd, const Address &dest, unsigned long &offset);
728
729 #undef INSN
730
731 void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
732 int negated_op);
733
734 // Add/subtract (immediate)
735 #define INSN(NAME, decode, negated) \
736 void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \
737 starti; \
738 f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
739 zrf(Rd, 0), srf(Rn, 5); \
740 } \
741 \
742 void NAME(Register Rd, Register Rn, unsigned imm) { \
743 starti; \
744 add_sub_immediate(Rd, Rn, imm, decode, negated); \
745 }
746
747 INSN(addsw, 0b001, 0b011);
748 INSN(subsw, 0b011, 0b001);
749 INSN(adds, 0b101, 0b111);
750 INSN(subs, 0b111, 0b101);
751
752 #undef INSN
753
754 #define INSN(NAME, decode, negated) \
755 void NAME(Register Rd, Register Rn, unsigned imm) { \
756 starti; \
757 add_sub_immediate(Rd, Rn, imm, decode, negated); \
758 }
759
760 INSN(addw, 0b000, 0b010);
761 INSN(subw, 0b010, 0b000);
762 INSN(add, 0b100, 0b110);
763 INSN(sub, 0b110, 0b100);
764
765 #undef INSN
766
767 // Logical (immediate)
768 #define INSN(NAME, decode, is32) \
769 void NAME(Register Rd, Register Rn, uint64_t imm) { \
770 starti; \
771 uint32_t val = encode_logical_immediate(is32, imm); \
772 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
773 srf(Rd, 0), zrf(Rn, 5); \
774 }
775
776 INSN(andw, 0b000, true);
777 INSN(orrw, 0b001, true);
778 INSN(eorw, 0b010, true);
779 INSN(andr, 0b100, false);
780 INSN(orr, 0b101, false);
781 INSN(eor, 0b110, false);
782
783 #undef INSN
784
785 #define INSN(NAME, decode, is32) \
786 void NAME(Register Rd, Register Rn, uint64_t imm) { \
787 starti; \
788 uint32_t val = encode_logical_immediate(is32, imm); \
789 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
790 zrf(Rd, 0), zrf(Rn, 5); \
791 }
792
793 INSN(ands, 0b111, false);
794 INSN(andsw, 0b011, true);
795
796 #undef INSN
797
798 // Move wide (immediate)
799 #define INSN(NAME, opcode) \
800 void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \
801 assert_cond((shift/16)*16 == shift); \
802 starti; \
803 f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \
804 f(imm, 20, 5); \
805 rf(Rd, 0); \
806 }
807
808 INSN(movnw, 0b000);
809 INSN(movzw, 0b010);
810 INSN(movkw, 0b011);
811 INSN(movn, 0b100);
812 INSN(movz, 0b110);
813 INSN(movk, 0b111);
814
815 #undef INSN
816
817 // Bitfield
818 #define INSN(NAME, opcode) \
819 void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \
820 starti; \
821 f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \
822 zrf(Rn, 5), rf(Rd, 0); \
823 }
824
825 INSN(sbfmw, 0b0001001100);
826 INSN(bfmw, 0b0011001100);
827 INSN(ubfmw, 0b0101001100);
828 INSN(sbfm, 0b1001001101);
829 INSN(bfm, 0b1011001101);
830 INSN(ubfm, 0b1101001101);
831
832 #undef INSN
833
834 // Extract
835 #define INSN(NAME, opcode) \
836 void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \
837 starti; \
838 f(opcode, 31, 21), f(imms, 15, 10); \
839 rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
840 }
841
842 INSN(extrw, 0b00010011100);
843 INSN(extr, 0b10010011110);
844
845 #undef INSN
846
847 // The maximum range of a branch is fixed for the AArch64
848 // architecture. In debug mode we shrink it in order to test
849 // trampolines, but not so small that branches in the interpreter
850 // are out of range.
851 static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
852
853 static bool reachable_from_branch_at(address branch, address target) {
854 return uabs(target - branch) < branch_range;
855 }
856
857 // Unconditional branch (immediate)
858 #define INSN(NAME, opcode) \
859 void NAME(address dest) { \
860 starti; \
861 long offset = (dest - pc()) >> 2; \
862 DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
863 f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \
864 } \
865 void NAME(Label &L) { \
866 wrap_label(L, &Assembler::NAME); \
867 } \
868 void NAME(const Address &dest);
869
870 INSN(b, 0);
871 INSN(bl, 1);
872
873 #undef INSN
874
875 // Compare & branch (immediate)
876 #define INSN(NAME, opcode) \
877 void NAME(Register Rt, address dest) { \
878 long offset = (dest - pc()) >> 2; \
879 starti; \
880 f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \
881 } \
882 void NAME(Register Rt, Label &L) { \
883 wrap_label(Rt, L, &Assembler::NAME); \
884 }
885
886 INSN(cbzw, 0b00110100);
887 INSN(cbnzw, 0b00110101);
888 INSN(cbz, 0b10110100);
889 INSN(cbnz, 0b10110101);
890
891 #undef INSN
892
893 // Test & branch (immediate)
894 #define INSN(NAME, opcode) \
895 void NAME(Register Rt, int bitpos, address dest) { \
896 long offset = (dest - pc()) >> 2; \
897 int b5 = bitpos >> 5; \
898 bitpos &= 0x1f; \
899 starti; \
900 f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
901 rf(Rt, 0); \
902 } \
903 void NAME(Register Rt, int bitpos, Label &L) { \
904 wrap_label(Rt, bitpos, L, &Assembler::NAME); \
905 }
906
907 INSN(tbz, 0b0110110);
908 INSN(tbnz, 0b0110111);
909
910 #undef INSN
911
912 // Conditional branch (immediate)
913 enum Condition
914 {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
915
916 void br(Condition cond, address dest) {
917 long offset = (dest - pc()) >> 2;
918 starti;
919 f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
920 }
921
922 #define INSN(NAME, cond) \
923 void NAME(address dest) { \
924 br(cond, dest); \
925 }
926
927 INSN(beq, EQ);
928 INSN(bne, NE);
929 INSN(bhs, HS);
930 INSN(bcs, CS);
931 INSN(blo, LO);
932 INSN(bcc, CC);
933 INSN(bmi, MI);
934 INSN(bpl, PL);
935 INSN(bvs, VS);
936 INSN(bvc, VC);
937 INSN(bhi, HI);
938 INSN(bls, LS);
939 INSN(bge, GE);
940 INSN(blt, LT);
941 INSN(bgt, GT);
942 INSN(ble, LE);
943 INSN(bal, AL);
944 INSN(bnv, NV);
945
946 void br(Condition cc, Label &L);
947
948 #undef INSN
949
950 // Exception generation
951 void generate_exception(int opc, int op2, int LL, unsigned imm) {
952 starti;
953 f(0b11010100, 31, 24);
954 f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
955 }
956
957 #define INSN(NAME, opc, op2, LL) \
958 void NAME(unsigned imm) { \
959 generate_exception(opc, op2, LL, imm); \
960 }
961
962 INSN(svc, 0b000, 0, 0b01);
963 INSN(hvc, 0b000, 0, 0b10);
964 INSN(smc, 0b000, 0, 0b11);
965 INSN(brk, 0b001, 0, 0b00);
966 INSN(hlt, 0b010, 0, 0b00);
967 INSN(dpcs1, 0b101, 0, 0b01);
968 INSN(dpcs2, 0b101, 0, 0b10);
969 INSN(dpcs3, 0b101, 0, 0b11);
970
971 #undef INSN
972
973 // System
974 void system(int op0, int op1, int CRn, int CRm, int op2,
975 Register rt = dummy_reg)
976 {
977 starti;
978 f(0b11010101000, 31, 21);
979 f(op0, 20, 19);
980 f(op1, 18, 16);
981 f(CRn, 15, 12);
982 f(CRm, 11, 8);
983 f(op2, 7, 5);
984 rf(rt, 0);
985 }
986
987 void hint(int imm) {
988 system(0b00, 0b011, 0b0010, 0b0000, imm);
989 }
990
991 void nop() {
992 hint(0);
993 }
994
995 void yield() {
996 hint(1);
997 }
998
999 void wfe() {
1000 hint(2);
1001 }
1002
1003 void wfi() {
1004 hint(3);
1005 }
1006
1007 void sev() {
1008 hint(4);
1009 }
1010
1011 void sevl() {
1012 hint(5);
1013 }
1014
1015 // we only provide mrs and msr for the special purpose system
1016 // registers where op1 (instr[20:19]) == 11 and, (currently) only
1017 // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1018
1019 void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1020 starti;
1021 f(0b1101010100011, 31, 19);
1022 f(op1, 18, 16);
1023 f(CRn, 15, 12);
1024 f(CRm, 11, 8);
1025 f(op2, 7, 5);
1026 // writing zr is ok
1027 zrf(rt, 0);
1028 }
1029
1030 void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1031 starti;
1032 f(0b1101010100111, 31, 19);
1033 f(op1, 18, 16);
1034 f(CRn, 15, 12);
1035 f(CRm, 11, 8);
1036 f(op2, 7, 5);
1037 // reading to zr is a mistake
1038 rf(rt, 0);
1039 }
1040
1041 enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1042 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1043
1044 void dsb(barrier imm) {
1045 system(0b00, 0b011, 0b00011, imm, 0b100);
1046 }
1047
1048 void dmb(barrier imm) {
1049 system(0b00, 0b011, 0b00011, imm, 0b101);
1050 }
1051
1052 void isb() {
1053 system(0b00, 0b011, 0b00011, SY, 0b110);
1054 }
1055
1056 void sys(int op1, int CRn, int CRm, int op2,
1057 Register rt = (Register)0b11111) {
1058 system(0b01, op1, CRn, CRm, op2, rt);
1059 }
1060
1061 // Only implement operations accessible from EL0 or higher, i.e.,
1062 // op1 CRn CRm op2
1063 // IC IVAU 3 7 5 1
1064 // DC CVAC 3 7 10 1
1065 // DC CVAU 3 7 11 1
1066 // DC CIVAC 3 7 14 1
1067 // DC ZVA 3 7 4 1
1068 // So only deal with the CRm field.
1069 enum icache_maintenance {IVAU = 0b0101};
1070 enum dcache_maintenance {CVAC = 0b1010, CVAU = 0b1011, CIVAC = 0b1110, ZVA = 0b100};
1071
1072 void dc(dcache_maintenance cm, Register Rt) {
1073 sys(0b011, 0b0111, cm, 0b001, Rt);
1074 }
1075
1076 void ic(icache_maintenance cm, Register Rt) {
1077 sys(0b011, 0b0111, cm, 0b001, Rt);
1078 }
1079
1080 // A more convenient access to dmb for our purposes
1081 enum Membar_mask_bits {
1082 // We can use ISH for a barrier because the ARM ARM says "This
1083 // architecture assumes that all Processing Elements that use the
1084 // same operating system or hypervisor are in the same Inner
1085 // Shareable shareability domain."
1086 StoreStore = ISHST,
1087 LoadStore = ISHLD,
1088 LoadLoad = ISHLD,
1089 StoreLoad = ISH,
1090 AnyAny = ISH
1091 };
1092
1093 void membar(Membar_mask_bits order_constraint) {
1094 dmb(Assembler::barrier(order_constraint));
1095 }
1096
1097 // Unconditional branch (register)
1098 void branch_reg(Register R, int opc) {
1099 starti;
1100 f(0b1101011, 31, 25);
1101 f(opc, 24, 21);
1102 f(0b11111000000, 20, 10);
1103 rf(R, 5);
1104 f(0b00000, 4, 0);
1105 }
1106
1107 #define INSN(NAME, opc) \
1108 void NAME(Register R) { \
1109 branch_reg(R, opc); \
1110 }
1111
1112 INSN(br, 0b0000);
1113 INSN(blr, 0b0001);
1114 INSN(ret, 0b0010);
1115
1116 void ret(void *p); // This forces a compile-time error for ret(0)
1117
1118 #undef INSN
1119
1120 #define INSN(NAME, opc) \
1121 void NAME() { \
1122 branch_reg(dummy_reg, opc); \
1123 }
1124
1125 INSN(eret, 0b0100);
1126 INSN(drps, 0b0101);
1127
1128 #undef INSN
1129
1130 // Load/store exclusive
1131 enum operand_size { byte, halfword, word, xword };
1132
1133 void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1134 Register Rn, enum operand_size sz, int op, bool ordered) {
1135 starti;
1136 f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1137 rf(Rs, 16), f(ordered, 15), rf(Rt2, 10), rf(Rn, 5), rf(Rt1, 0);
1138 }
1139
1140 void load_exclusive(Register dst, Register addr,
1141 enum operand_size sz, bool ordered) {
1142 load_store_exclusive(dummy_reg, dst, dummy_reg, addr,
1143 sz, 0b010, ordered);
1144 }
1145
1146 void store_exclusive(Register status, Register new_val, Register addr,
1147 enum operand_size sz, bool ordered) {
1148 load_store_exclusive(status, new_val, dummy_reg, addr,
1149 sz, 0b000, ordered);
1150 }
1151
1152 #define INSN4(NAME, sz, op, o0) /* Four registers */ \
1153 void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \
1154 guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \
1155 load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \
1156 }
1157
1158 #define INSN3(NAME, sz, op, o0) /* Three registers */ \
1159 void NAME(Register Rs, Register Rt, Register Rn) { \
1160 guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1161 load_store_exclusive(Rs, Rt, dummy_reg, Rn, sz, op, o0); \
1162 }
1163
1164 #define INSN2(NAME, sz, op, o0) /* Two registers */ \
1165 void NAME(Register Rt, Register Rn) { \
1166 load_store_exclusive(dummy_reg, Rt, dummy_reg, \
1167 Rn, sz, op, o0); \
1168 }
1169
1170 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
1171 void NAME(Register Rt1, Register Rt2, Register Rn) { \
1172 guarantee(Rt1 != Rt2, "unpredictable instruction"); \
1173 load_store_exclusive(dummy_reg, Rt1, Rt2, Rn, sz, op, o0); \
1174 }
1175
1176 // bytes
1177 INSN3(stxrb, byte, 0b000, 0);
1178 INSN3(stlxrb, byte, 0b000, 1);
1179 INSN2(ldxrb, byte, 0b010, 0);
1180 INSN2(ldaxrb, byte, 0b010, 1);
1181 INSN2(stlrb, byte, 0b100, 1);
1182 INSN2(ldarb, byte, 0b110, 1);
1183
1184 // halfwords
1185 INSN3(stxrh, halfword, 0b000, 0);
1186 INSN3(stlxrh, halfword, 0b000, 1);
1187 INSN2(ldxrh, halfword, 0b010, 0);
1188 INSN2(ldaxrh, halfword, 0b010, 1);
1189 INSN2(stlrh, halfword, 0b100, 1);
1190 INSN2(ldarh, halfword, 0b110, 1);
1191
1192 // words
1193 INSN3(stxrw, word, 0b000, 0);
1194 INSN3(stlxrw, word, 0b000, 1);
1195 INSN4(stxpw, word, 0b001, 0);
1196 INSN4(stlxpw, word, 0b001, 1);
1197 INSN2(ldxrw, word, 0b010, 0);
1198 INSN2(ldaxrw, word, 0b010, 1);
1199 INSN_FOO(ldxpw, word, 0b011, 0);
1200 INSN_FOO(ldaxpw, word, 0b011, 1);
1201 INSN2(stlrw, word, 0b100, 1);
1202 INSN2(ldarw, word, 0b110, 1);
1203
1204 // xwords
1205 INSN3(stxr, xword, 0b000, 0);
1206 INSN3(stlxr, xword, 0b000, 1);
1207 INSN4(stxp, xword, 0b001, 0);
1208 INSN4(stlxp, xword, 0b001, 1);
1209 INSN2(ldxr, xword, 0b010, 0);
1210 INSN2(ldaxr, xword, 0b010, 1);
1211 INSN_FOO(ldxp, xword, 0b011, 0);
1212 INSN_FOO(ldaxp, xword, 0b011, 1);
1213 INSN2(stlr, xword, 0b100, 1);
1214 INSN2(ldar, xword, 0b110, 1);
1215
1216 #undef INSN2
1217 #undef INSN3
1218 #undef INSN4
1219 #undef INSN_FOO
1220
1221 // 8.1 Compare and swap extensions
1222 void lse_cas(Register Rs, Register Rt, Register Rn,
1223 enum operand_size sz, bool a, bool r, bool not_pair) {
1224 starti;
1225 if (! not_pair) { // Pair
1226 assert(sz == word || sz == xword, "invalid size");
1227 /* The size bit is in bit 30, not 31 */
1228 sz = (operand_size)(sz == word ? 0b00:0b01);
1229 }
1230 f(sz, 31, 30), f(0b001000, 29, 24), f(1, 23), f(a, 22), f(1, 21);
1231 rf(Rs, 16), f(r, 15), f(0b11111, 14, 10), rf(Rn, 5), rf(Rt, 0);
1232 }
1233
1234 // CAS
1235 #define INSN(NAME, a, r) \
1236 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1237 assert(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1238 lse_cas(Rs, Rt, Rn, sz, a, r, true); \
1239 }
1240 INSN(cas, false, false)
1241 INSN(casa, true, false)
1242 INSN(casl, false, true)
1243 INSN(casal, true, true)
1244 #undef INSN
1245
1246 // CASP
1247 #define INSN(NAME, a, r) \
1248 void NAME(operand_size sz, Register Rs, Register Rs1, \
1249 Register Rt, Register Rt1, Register Rn) { \
1250 assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 && \
1251 Rs->successor() == Rs1 && Rt->successor() == Rt1 && \
1252 Rs != Rn && Rs1 != Rn && Rs != Rt, "invalid registers"); \
1253 lse_cas(Rs, Rt, Rn, sz, a, r, false); \
1254 }
1255 INSN(casp, false, false)
1256 INSN(caspa, true, false)
1257 INSN(caspl, false, true)
1258 INSN(caspal, true, true)
1259 #undef INSN
1260
1261 // 8.1 Atomic operations
1262 void lse_atomic(Register Rs, Register Rt, Register Rn,
1263 enum operand_size sz, int op1, int op2, bool a, bool r) {
1264 starti;
1265 f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21);
1266 rf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), rf(Rn, 5), zrf(Rt, 0);
1267 }
1268
1269 #define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2) \
1270 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1271 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, false); \
1272 } \
1273 void NAME_A(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1274 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, false); \
1275 } \
1276 void NAME_L(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1277 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, true); \
1278 } \
1279 void NAME_AL(operand_size sz, Register Rs, Register Rt, Register Rn) {\
1280 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, true); \
1281 }
1282 INSN(ldadd, ldadda, ldaddl, ldaddal, 0, 0b000);
1283 INSN(ldbic, ldbica, ldbicl, ldbical, 0, 0b001);
1284 INSN(ldeor, ldeora, ldeorl, ldeoral, 0, 0b010);
1285 INSN(ldorr, ldorra, ldorrl, ldorral, 0, 0b011);
1286 INSN(ldsmax, ldsmaxa, ldsmaxl, ldsmaxal, 0, 0b100);
1287 INSN(ldsmin, ldsmina, ldsminl, ldsminal, 0, 0b101);
1288 INSN(ldumax, ldumaxa, ldumaxl, ldumaxal, 0, 0b110);
1289 INSN(ldumin, ldumina, lduminl, lduminal, 0, 0b111);
1290 INSN(swp, swpa, swpl, swpal, 1, 0b000);
1291 #undef INSN
1292
1293 // Load register (literal)
1294 #define INSN(NAME, opc, V) \
1295 void NAME(Register Rt, address dest) { \
1296 long offset = (dest - pc()) >> 2; \
1297 starti; \
1298 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1299 sf(offset, 23, 5); \
1300 rf(Rt, 0); \
1301 } \
1302 void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \
1303 InstructionMark im(this); \
1304 guarantee(rtype == relocInfo::internal_word_type, \
1305 "only internal_word_type relocs make sense here"); \
1306 code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
1307 NAME(Rt, dest); \
1308 } \
1309 void NAME(Register Rt, Label &L) { \
1310 wrap_label(Rt, L, &Assembler::NAME); \
1311 }
1312
1313 INSN(ldrw, 0b00, 0);
1314 INSN(ldr, 0b01, 0);
1315 INSN(ldrsw, 0b10, 0);
1316
1317 #undef INSN
1318
1319 #define INSN(NAME, opc, V) \
1320 void NAME(FloatRegister Rt, address dest) { \
1321 long offset = (dest - pc()) >> 2; \
1322 starti; \
1323 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1324 sf(offset, 23, 5); \
1325 rf((Register)Rt, 0); \
1326 }
1327
1328 INSN(ldrs, 0b00, 1);
1329 INSN(ldrd, 0b01, 1);
1330 INSN(ldrq, 0b10, 1);
1331
1332 #undef INSN
1333
1334 #define INSN(NAME, opc, V) \
1335 void NAME(address dest, prfop op = PLDL1KEEP) { \
1336 long offset = (dest - pc()) >> 2; \
1337 starti; \
1338 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1339 sf(offset, 23, 5); \
1340 f(op, 4, 0); \
1341 } \
1342 void NAME(Label &L, prfop op = PLDL1KEEP) { \
1343 wrap_label(L, op, &Assembler::NAME); \
1344 }
1345
1346 INSN(prfm, 0b11, 0);
1347
1348 #undef INSN
1349
1350 // Load/store
1351 void ld_st1(int opc, int p1, int V, int L,
1352 Register Rt1, Register Rt2, Address adr, bool no_allocate) {
1353 starti;
1354 f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
1355 zrf(Rt2, 10), zrf(Rt1, 0);
1356 if (no_allocate) {
1357 adr.encode_nontemporal_pair(current);
1358 } else {
1359 adr.encode_pair(current);
1360 }
1361 }
1362
1363 // Load/store register pair (offset)
1364 #define INSN(NAME, size, p1, V, L, no_allocate) \
1365 void NAME(Register Rt1, Register Rt2, Address adr) { \
1366 ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
1367 }
1368
1369 INSN(stpw, 0b00, 0b101, 0, 0, false);
1370 INSN(ldpw, 0b00, 0b101, 0, 1, false);
1371 INSN(ldpsw, 0b01, 0b101, 0, 1, false);
1372 INSN(stp, 0b10, 0b101, 0, 0, false);
1373 INSN(ldp, 0b10, 0b101, 0, 1, false);
1374
1375 // Load/store no-allocate pair (offset)
1376 INSN(stnpw, 0b00, 0b101, 0, 0, true);
1377 INSN(ldnpw, 0b00, 0b101, 0, 1, true);
1378 INSN(stnp, 0b10, 0b101, 0, 0, true);
1379 INSN(ldnp, 0b10, 0b101, 0, 1, true);
1380
1381 #undef INSN
1382
1383 #define INSN(NAME, size, p1, V, L, no_allocate) \
1384 void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \
1385 ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
1386 }
1387
1388 INSN(stps, 0b00, 0b101, 1, 0, false);
1389 INSN(ldps, 0b00, 0b101, 1, 1, false);
1390 INSN(stpd, 0b01, 0b101, 1, 0, false);
1391 INSN(ldpd, 0b01, 0b101, 1, 1, false);
1392 INSN(stpq, 0b10, 0b101, 1, 0, false);
1393 INSN(ldpq, 0b10, 0b101, 1, 1, false);
1394
1395 #undef INSN
1396
1397 // Load/store register (all modes)
1398 void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
1399 starti;
1400
1401 f(V, 26); // general reg?
1402 zrf(Rt, 0);
1403
1404 // Encoding for literal loads is done here (rather than pushed
1405 // down into Address::encode) because the encoding of this
1406 // instruction is too different from all of the other forms to
1407 // make it worth sharing.
1408 if (adr.getMode() == Address::literal) {
1409 assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
1410 assert(op == 0b01, "literal form can only be used with loads");
1411 f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
1412 long offset = (adr.target() - pc()) >> 2;
1413 sf(offset, 23, 5);
1414 code_section()->relocate(pc(), adr.rspec());
1415 return;
1416 }
1417
1418 f(size, 31, 30);
1419 f(op, 23, 22); // str
1420 adr.encode(current);
1421 }
1422
1423 #define INSN(NAME, size, op) \
1424 void NAME(Register Rt, const Address &adr) { \
1425 ld_st2(Rt, adr, size, op); \
1426 } \
1427
1428 INSN(str, 0b11, 0b00);
1429 INSN(strw, 0b10, 0b00);
1430 INSN(strb, 0b00, 0b00);
1431 INSN(strh, 0b01, 0b00);
1432
1433 INSN(ldr, 0b11, 0b01);
1434 INSN(ldrw, 0b10, 0b01);
1435 INSN(ldrb, 0b00, 0b01);
1436 INSN(ldrh, 0b01, 0b01);
1437
1438 INSN(ldrsb, 0b00, 0b10);
1439 INSN(ldrsbw, 0b00, 0b11);
1440 INSN(ldrsh, 0b01, 0b10);
1441 INSN(ldrshw, 0b01, 0b11);
1442 INSN(ldrsw, 0b10, 0b10);
1443
1444 #undef INSN
1445
1446 #define INSN(NAME, size, op) \
1447 void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \
1448 ld_st2((Register)pfop, adr, size, op); \
1449 }
1450
1451 INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
1452 // writeback modes, but the assembler
1453 // doesn't enfore that.
1454
1455 #undef INSN
1456
1457 #define INSN(NAME, size, op) \
1458 void NAME(FloatRegister Rt, const Address &adr) { \
1459 ld_st2((Register)Rt, adr, size, op, 1); \
1460 }
1461
1462 INSN(strd, 0b11, 0b00);
1463 INSN(strs, 0b10, 0b00);
1464 INSN(ldrd, 0b11, 0b01);
1465 INSN(ldrs, 0b10, 0b01);
1466 INSN(strq, 0b00, 0b10);
1467 INSN(ldrq, 0x00, 0b11);
1468
1469 #undef INSN
1470
1471 enum shift_kind { LSL, LSR, ASR, ROR };
1472
1473 void op_shifted_reg(unsigned decode,
1474 enum shift_kind kind, unsigned shift,
1475 unsigned size, unsigned op) {
1476 f(size, 31);
1477 f(op, 30, 29);
1478 f(decode, 28, 24);
1479 f(shift, 15, 10);
1480 f(kind, 23, 22);
1481 }
1482
1483 // Logical (shifted register)
1484 #define INSN(NAME, size, op, N) \
1485 void NAME(Register Rd, Register Rn, Register Rm, \
1486 enum shift_kind kind = LSL, unsigned shift = 0) { \
1487 starti; \
1488 f(N, 21); \
1489 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1490 op_shifted_reg(0b01010, kind, shift, size, op); \
1491 }
1492
1493 INSN(andr, 1, 0b00, 0);
1494 INSN(orr, 1, 0b01, 0);
1495 INSN(eor, 1, 0b10, 0);
1496 INSN(ands, 1, 0b11, 0);
1497 INSN(andw, 0, 0b00, 0);
1498 INSN(orrw, 0, 0b01, 0);
1499 INSN(eorw, 0, 0b10, 0);
1500 INSN(andsw, 0, 0b11, 0);
1501
1502 INSN(bic, 1, 0b00, 1);
1503 INSN(orn, 1, 0b01, 1);
1504 INSN(eon, 1, 0b10, 1);
1505 INSN(bics, 1, 0b11, 1);
1506 INSN(bicw, 0, 0b00, 1);
1507 INSN(ornw, 0, 0b01, 1);
1508 INSN(eonw, 0, 0b10, 1);
1509 INSN(bicsw, 0, 0b11, 1);
1510
1511 #undef INSN
1512
1513 // Aliases for short forms of orn
1514 void mvn(Register Rd, Register Rm,
1515 enum shift_kind kind = LSL, unsigned shift = 0) {
1516 orn(Rd, zr, Rm, kind, shift);
1517 }
1518
1519 void mvnw(Register Rd, Register Rm,
1520 enum shift_kind kind = LSL, unsigned shift = 0) {
1521 ornw(Rd, zr, Rm, kind, shift);
1522 }
1523
1524 // Add/subtract (shifted register)
1525 #define INSN(NAME, size, op) \
1526 void NAME(Register Rd, Register Rn, Register Rm, \
1527 enum shift_kind kind, unsigned shift = 0) { \
1528 starti; \
1529 f(0, 21); \
1530 assert_cond(kind != ROR); \
1531 zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \
1532 op_shifted_reg(0b01011, kind, shift, size, op); \
1533 }
1534
1535 INSN(add, 1, 0b000);
1536 INSN(sub, 1, 0b10);
1537 INSN(addw, 0, 0b000);
1538 INSN(subw, 0, 0b10);
1539
1540 INSN(adds, 1, 0b001);
1541 INSN(subs, 1, 0b11);
1542 INSN(addsw, 0, 0b001);
1543 INSN(subsw, 0, 0b11);
1544
1545 #undef INSN
1546
1547 // Add/subtract (extended register)
1548 #define INSN(NAME, op) \
1549 void NAME(Register Rd, Register Rn, Register Rm, \
1550 ext::operation option, int amount = 0) { \
1551 starti; \
1552 zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \
1553 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1554 }
1555
1556 void add_sub_extended_reg(unsigned op, unsigned decode,
1557 Register Rd, Register Rn, Register Rm,
1558 unsigned opt, ext::operation option, unsigned imm) {
1559 guarantee(imm <= 4, "shift amount must be < 4");
1560 f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
1561 f(option, 15, 13), f(imm, 12, 10);
1562 }
1563
1564 INSN(addw, 0b000);
1565 INSN(subw, 0b010);
1566 INSN(add, 0b100);
1567 INSN(sub, 0b110);
1568
1569 #undef INSN
1570
1571 #define INSN(NAME, op) \
1572 void NAME(Register Rd, Register Rn, Register Rm, \
1573 ext::operation option, int amount = 0) { \
1574 starti; \
1575 zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \
1576 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1577 }
1578
1579 INSN(addsw, 0b001);
1580 INSN(subsw, 0b011);
1581 INSN(adds, 0b101);
1582 INSN(subs, 0b111);
1583
1584 #undef INSN
1585
1586 // Aliases for short forms of add and sub
1587 #define INSN(NAME) \
1588 void NAME(Register Rd, Register Rn, Register Rm) { \
1589 if (Rd == sp || Rn == sp) \
1590 NAME(Rd, Rn, Rm, ext::uxtx); \
1591 else \
1592 NAME(Rd, Rn, Rm, LSL); \
1593 }
1594
1595 INSN(addw);
1596 INSN(subw);
1597 INSN(add);
1598 INSN(sub);
1599
1600 INSN(addsw);
1601 INSN(subsw);
1602 INSN(adds);
1603 INSN(subs);
1604
1605 #undef INSN
1606
1607 // Add/subtract (with carry)
1608 void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
1609 starti;
1610 f(op, 31, 29);
1611 f(0b11010000, 28, 21);
1612 f(0b000000, 15, 10);
1613 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
1614 }
1615
1616 #define INSN(NAME, op) \
1617 void NAME(Register Rd, Register Rn, Register Rm) { \
1618 add_sub_carry(op, Rd, Rn, Rm); \
1619 }
1620
1621 INSN(adcw, 0b000);
1622 INSN(adcsw, 0b001);
1623 INSN(sbcw, 0b010);
1624 INSN(sbcsw, 0b011);
1625 INSN(adc, 0b100);
1626 INSN(adcs, 0b101);
1627 INSN(sbc,0b110);
1628 INSN(sbcs, 0b111);
1629
1630 #undef INSN
1631
1632 // Conditional compare (both kinds)
1633 void conditional_compare(unsigned op, int o2, int o3,
1634 Register Rn, unsigned imm5, unsigned nzcv,
1635 unsigned cond) {
1636 f(op, 31, 29);
1637 f(0b11010010, 28, 21);
1638 f(cond, 15, 12);
1639 f(o2, 10);
1640 f(o3, 4);
1641 f(nzcv, 3, 0);
1642 f(imm5, 20, 16), rf(Rn, 5);
1643 }
1644
1645 #define INSN(NAME, op) \
1646 void NAME(Register Rn, Register Rm, int imm, Condition cond) { \
1647 starti; \
1648 f(0, 11); \
1649 conditional_compare(op, 0, 0, Rn, (uintptr_t)Rm, imm, cond); \
1650 } \
1651 \
1652 void NAME(Register Rn, int imm5, int imm, Condition cond) { \
1653 starti; \
1654 f(1, 11); \
1655 conditional_compare(op, 0, 0, Rn, imm5, imm, cond); \
1656 }
1657
1658 INSN(ccmnw, 0b001);
1659 INSN(ccmpw, 0b011);
1660 INSN(ccmn, 0b101);
1661 INSN(ccmp, 0b111);
1662
1663 #undef INSN
1664
1665 // Conditional select
1666 void conditional_select(unsigned op, unsigned op2,
1667 Register Rd, Register Rn, Register Rm,
1668 unsigned cond) {
1669 starti;
1670 f(op, 31, 29);
1671 f(0b11010100, 28, 21);
1672 f(cond, 15, 12);
1673 f(op2, 11, 10);
1674 zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
1675 }
1676
1677 #define INSN(NAME, op, op2) \
1678 void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
1679 conditional_select(op, op2, Rd, Rn, Rm, cond); \
1680 }
1681
1682 INSN(cselw, 0b000, 0b00);
1683 INSN(csincw, 0b000, 0b01);
1684 INSN(csinvw, 0b010, 0b00);
1685 INSN(csnegw, 0b010, 0b01);
1686 INSN(csel, 0b100, 0b00);
1687 INSN(csinc, 0b100, 0b01);
1688 INSN(csinv, 0b110, 0b00);
1689 INSN(csneg, 0b110, 0b01);
1690
1691 #undef INSN
1692
1693 // Data processing
1694 void data_processing(unsigned op29, unsigned opcode,
1695 Register Rd, Register Rn) {
1696 f(op29, 31, 29), f(0b11010110, 28, 21);
1697 f(opcode, 15, 10);
1698 rf(Rn, 5), rf(Rd, 0);
1699 }
1700
1701 // (1 source)
1702 #define INSN(NAME, op29, opcode2, opcode) \
1703 void NAME(Register Rd, Register Rn) { \
1704 starti; \
1705 f(opcode2, 20, 16); \
1706 data_processing(op29, opcode, Rd, Rn); \
1707 }
1708
1709 INSN(rbitw, 0b010, 0b00000, 0b00000);
1710 INSN(rev16w, 0b010, 0b00000, 0b00001);
1711 INSN(revw, 0b010, 0b00000, 0b00010);
1712 INSN(clzw, 0b010, 0b00000, 0b00100);
1713 INSN(clsw, 0b010, 0b00000, 0b00101);
1714
1715 INSN(rbit, 0b110, 0b00000, 0b00000);
1716 INSN(rev16, 0b110, 0b00000, 0b00001);
1717 INSN(rev32, 0b110, 0b00000, 0b00010);
1718 INSN(rev, 0b110, 0b00000, 0b00011);
1719 INSN(clz, 0b110, 0b00000, 0b00100);
1720 INSN(cls, 0b110, 0b00000, 0b00101);
1721
1722 #undef INSN
1723
1724 // (2 sources)
1725 #define INSN(NAME, op29, opcode) \
1726 void NAME(Register Rd, Register Rn, Register Rm) { \
1727 starti; \
1728 rf(Rm, 16); \
1729 data_processing(op29, opcode, Rd, Rn); \
1730 }
1731
1732 INSN(udivw, 0b000, 0b000010);
1733 INSN(sdivw, 0b000, 0b000011);
1734 INSN(lslvw, 0b000, 0b001000);
1735 INSN(lsrvw, 0b000, 0b001001);
1736 INSN(asrvw, 0b000, 0b001010);
1737 INSN(rorvw, 0b000, 0b001011);
1738
1739 INSN(udiv, 0b100, 0b000010);
1740 INSN(sdiv, 0b100, 0b000011);
1741 INSN(lslv, 0b100, 0b001000);
1742 INSN(lsrv, 0b100, 0b001001);
1743 INSN(asrv, 0b100, 0b001010);
1744 INSN(rorv, 0b100, 0b001011);
1745
1746 #undef INSN
1747
1748 // (3 sources)
1749 void data_processing(unsigned op54, unsigned op31, unsigned o0,
1750 Register Rd, Register Rn, Register Rm,
1751 Register Ra) {
1752 starti;
1753 f(op54, 31, 29), f(0b11011, 28, 24);
1754 f(op31, 23, 21), f(o0, 15);
1755 zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
1756 }
1757
1758 #define INSN(NAME, op54, op31, o0) \
1759 void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \
1760 data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \
1761 }
1762
1763 INSN(maddw, 0b000, 0b000, 0);
1764 INSN(msubw, 0b000, 0b000, 1);
1765 INSN(madd, 0b100, 0b000, 0);
1766 INSN(msub, 0b100, 0b000, 1);
1767 INSN(smaddl, 0b100, 0b001, 0);
1768 INSN(smsubl, 0b100, 0b001, 1);
1769 INSN(umaddl, 0b100, 0b101, 0);
1770 INSN(umsubl, 0b100, 0b101, 1);
1771
1772 #undef INSN
1773
1774 #define INSN(NAME, op54, op31, o0) \
1775 void NAME(Register Rd, Register Rn, Register Rm) { \
1776 data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \
1777 }
1778
1779 INSN(smulh, 0b100, 0b010, 0);
1780 INSN(umulh, 0b100, 0b110, 0);
1781
1782 #undef INSN
1783
1784 // Floating-point data-processing (1 source)
1785 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1786 FloatRegister Vd, FloatRegister Vn) {
1787 starti;
1788 f(op31, 31, 29);
1789 f(0b11110, 28, 24);
1790 f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
1791 rf(Vn, 5), rf(Vd, 0);
1792 }
1793
1794 #define INSN(NAME, op31, type, opcode) \
1795 void NAME(FloatRegister Vd, FloatRegister Vn) { \
1796 data_processing(op31, type, opcode, Vd, Vn); \
1797 }
1798
1799 private:
1800 INSN(i_fmovs, 0b000, 0b00, 0b000000);
1801 public:
1802 INSN(fabss, 0b000, 0b00, 0b000001);
1803 INSN(fnegs, 0b000, 0b00, 0b000010);
1804 INSN(fsqrts, 0b000, 0b00, 0b000011);
1805 INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision
1806
1807 private:
1808 INSN(i_fmovd, 0b000, 0b01, 0b000000);
1809 public:
1810 INSN(fabsd, 0b000, 0b01, 0b000001);
1811 INSN(fnegd, 0b000, 0b01, 0b000010);
1812 INSN(fsqrtd, 0b000, 0b01, 0b000011);
1813 INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision
1814
1815 void fmovd(FloatRegister Vd, FloatRegister Vn) {
1816 assert(Vd != Vn, "should be");
1817 i_fmovd(Vd, Vn);
1818 }
1819
1820 void fmovs(FloatRegister Vd, FloatRegister Vn) {
1821 assert(Vd != Vn, "should be");
1822 i_fmovs(Vd, Vn);
1823 }
1824
1825 #undef INSN
1826
1827 // Floating-point data-processing (2 source)
1828 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1829 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1830 starti;
1831 f(op31, 31, 29);
1832 f(0b11110, 28, 24);
1833 f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1834 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1835 }
1836
1837 #define INSN(NAME, op31, type, opcode) \
1838 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \
1839 data_processing(op31, type, opcode, Vd, Vn, Vm); \
1840 }
1841
1842 INSN(fmuls, 0b000, 0b00, 0b0000);
1843 INSN(fdivs, 0b000, 0b00, 0b0001);
1844 INSN(fadds, 0b000, 0b00, 0b0010);
1845 INSN(fsubs, 0b000, 0b00, 0b0011);
1846 INSN(fnmuls, 0b000, 0b00, 0b1000);
1847
1848 INSN(fmuld, 0b000, 0b01, 0b0000);
1849 INSN(fdivd, 0b000, 0b01, 0b0001);
1850 INSN(faddd, 0b000, 0b01, 0b0010);
1851 INSN(fsubd, 0b000, 0b01, 0b0011);
1852 INSN(fnmuld, 0b000, 0b01, 0b1000);
1853
1854 #undef INSN
1855
1856 // Floating-point data-processing (3 source)
1857 void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1858 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1859 FloatRegister Va) {
1860 starti;
1861 f(op31, 31, 29);
1862 f(0b11111, 28, 24);
1863 f(type, 23, 22), f(o1, 21), f(o0, 15);
1864 rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1865 }
1866
1867 #define INSN(NAME, op31, type, o1, o0) \
1868 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \
1869 FloatRegister Va) { \
1870 data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \
1871 }
1872
1873 INSN(fmadds, 0b000, 0b00, 0, 0);
1874 INSN(fmsubs, 0b000, 0b00, 0, 1);
1875 INSN(fnmadds, 0b000, 0b00, 1, 0);
1876 INSN(fnmsubs, 0b000, 0b00, 1, 1);
1877
1878 INSN(fmaddd, 0b000, 0b01, 0, 0);
1879 INSN(fmsubd, 0b000, 0b01, 0, 1);
1880 INSN(fnmaddd, 0b000, 0b01, 1, 0);
1881 INSN(fnmsub, 0b000, 0b01, 1, 1);
1882
1883 #undef INSN
1884
1885 // Floating-point conditional select
1886 void fp_conditional_select(unsigned op31, unsigned type,
1887 unsigned op1, unsigned op2,
1888 Condition cond, FloatRegister Vd,
1889 FloatRegister Vn, FloatRegister Vm) {
1890 starti;
1891 f(op31, 31, 29);
1892 f(0b11110, 28, 24);
1893 f(type, 23, 22);
1894 f(op1, 21, 21);
1895 f(op2, 11, 10);
1896 f(cond, 15, 12);
1897 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1898 }
1899
1900 #define INSN(NAME, op31, type, op1, op2) \
1901 void NAME(FloatRegister Vd, FloatRegister Vn, \
1902 FloatRegister Vm, Condition cond) { \
1903 fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \
1904 }
1905
1906 INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
1907 INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
1908
1909 #undef INSN
1910
1911 // Floating-point<->integer conversions
1912 void float_int_convert(unsigned op31, unsigned type,
1913 unsigned rmode, unsigned opcode,
1914 Register Rd, Register Rn) {
1915 starti;
1916 f(op31, 31, 29);
1917 f(0b11110, 28, 24);
1918 f(type, 23, 22), f(1, 21), f(rmode, 20, 19);
1919 f(opcode, 18, 16), f(0b000000, 15, 10);
1920 zrf(Rn, 5), zrf(Rd, 0);
1921 }
1922
1923 #define INSN(NAME, op31, type, rmode, opcode) \
1924 void NAME(Register Rd, FloatRegister Vn) { \
1925 float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \
1926 }
1927
1928 INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
1929 INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000);
1930 INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000);
1931 INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000);
1932
1933 INSN(fmovs, 0b000, 0b00, 0b00, 0b110);
1934 INSN(fmovd, 0b100, 0b01, 0b00, 0b110);
1935
1936 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110);
1937
1938 #undef INSN
1939
1940 #define INSN(NAME, op31, type, rmode, opcode) \
1941 void NAME(FloatRegister Vd, Register Rn) { \
1942 float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \
1943 }
1944
1945 INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
1946 INSN(fmovd, 0b100, 0b01, 0b00, 0b111);
1947
1948 INSN(scvtfws, 0b000, 0b00, 0b00, 0b010);
1949 INSN(scvtfs, 0b100, 0b00, 0b00, 0b010);
1950 INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010);
1951 INSN(scvtfd, 0b100, 0b01, 0b00, 0b010);
1952
1953 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
1954
1955 #undef INSN
1956
1957 // Floating-point compare
1958 void float_compare(unsigned op31, unsigned type,
1959 unsigned op, unsigned op2,
1960 FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
1961 starti;
1962 f(op31, 31, 29);
1963 f(0b11110, 28, 24);
1964 f(type, 23, 22), f(1, 21);
1965 f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
1966 rf(Vn, 5), rf(Vm, 16);
1967 }
1968
1969
1970 #define INSN(NAME, op31, type, op, op2) \
1971 void NAME(FloatRegister Vn, FloatRegister Vm) { \
1972 float_compare(op31, type, op, op2, Vn, Vm); \
1973 }
1974
1975 #define INSN1(NAME, op31, type, op, op2) \
1976 void NAME(FloatRegister Vn, double d) { \
1977 assert_cond(d == 0.0); \
1978 float_compare(op31, type, op, op2, Vn); \
1979 }
1980
1981 INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
1982 INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
1983 // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
1984 // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
1985
1986 INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000);
1987 INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000);
1988 // INSN(fcmped, 0b000, 0b01, 0b00, 0b10000);
1989 // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
1990
1991 #undef INSN
1992 #undef INSN1
1993
1994 // Floating-point Move (immediate)
1995 private:
1996 unsigned pack(double value);
1997
1998 void fmov_imm(FloatRegister Vn, double value, unsigned size) {
1999 starti;
2000 f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
2001 f(pack(value), 20, 13), f(0b10000000, 12, 5);
2002 rf(Vn, 0);
2003 }
2004
2005 public:
2006
2007 void fmovs(FloatRegister Vn, double value) {
2008 if (value)
2009 fmov_imm(Vn, value, 0b00);
2010 else
2011 fmovs(Vn, zr);
2012 }
2013 void fmovd(FloatRegister Vn, double value) {
2014 if (value)
2015 fmov_imm(Vn, value, 0b01);
2016 else
2017 fmovd(Vn, zr);
2018 }
2019
2020 /* SIMD extensions
2021 *
2022 * We just use FloatRegister in the following. They are exactly the same
2023 * as SIMD registers.
2024 */
2025 public:
2026
2027 enum SIMD_Arrangement {
2028 T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
2029 };
2030
2031 enum SIMD_RegVariant {
2032 B, H, S, D, Q
2033 };
2034
2035 #define INSN(NAME, op) \
2036 void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \
2037 ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
2038 } \
2039
2040 INSN(ldr, 1);
2041 INSN(str, 0);
2042
2043 #undef INSN
2044
2045 private:
2046
2047 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
2048 starti;
2049 f(0,31), f((int)T & 1, 30);
2050 f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
2051 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2052 }
2053 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2054 int imm, int op1, int op2) {
2055 starti;
2056 f(0,31), f((int)T & 1, 30);
2057 f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
2058 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2059 }
2060 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2061 Register Xm, int op1, int op2) {
2062 starti;
2063 f(0,31), f((int)T & 1, 30);
2064 f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
2065 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2066 }
2067
2068 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2) {
2069 switch (a.getMode()) {
2070 case Address::base_plus_offset:
2071 guarantee(a.offset() == 0, "no offset allowed here");
2072 ld_st(Vt, T, a.base(), op1, op2);
2073 break;
2074 case Address::post:
2075 ld_st(Vt, T, a.base(), a.offset(), op1, op2);
2076 break;
2077 case Address::base_plus_offset_reg:
2078 ld_st(Vt, T, a.base(), a.index(), op1, op2);
2079 break;
2080 default:
2081 ShouldNotReachHere();
2082 }
2083 }
2084
2085 public:
2086
2087 #define INSN1(NAME, op1, op2) \
2088 void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \
2089 ld_st(Vt, T, a, op1, op2); \
2090 }
2091
2092 #define INSN2(NAME, op1, op2) \
2093 void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
2094 assert(Vt->successor() == Vt2, "Registers must be ordered"); \
2095 ld_st(Vt, T, a, op1, op2); \
2096 }
2097
2098 #define INSN3(NAME, op1, op2) \
2099 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
2100 SIMD_Arrangement T, const Address &a) { \
2101 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \
2102 "Registers must be ordered"); \
2103 ld_st(Vt, T, a, op1, op2); \
2104 }
2105
2106 #define INSN4(NAME, op1, op2) \
2107 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
2108 FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \
2109 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \
2110 Vt3->successor() == Vt4, "Registers must be ordered"); \
2111 ld_st(Vt, T, a, op1, op2); \
2112 }
2113
2114 INSN1(ld1, 0b001100010, 0b0111);
2115 INSN2(ld1, 0b001100010, 0b1010);
2116 INSN3(ld1, 0b001100010, 0b0110);
2117 INSN4(ld1, 0b001100010, 0b0010);
2118
2119 INSN2(ld2, 0b001100010, 0b1000);
2120 INSN3(ld3, 0b001100010, 0b0100);
2121 INSN4(ld4, 0b001100010, 0b0000);
2122
2123 INSN1(st1, 0b001100000, 0b0111);
2124 INSN2(st1, 0b001100000, 0b1010);
2125 INSN3(st1, 0b001100000, 0b0110);
2126 INSN4(st1, 0b001100000, 0b0010);
2127
2128 INSN2(st2, 0b001100000, 0b1000);
2129 INSN3(st3, 0b001100000, 0b0100);
2130 INSN4(st4, 0b001100000, 0b0000);
2131
2132 INSN1(ld1r, 0b001101010, 0b1100);
2133 INSN2(ld2r, 0b001101011, 0b1100);
2134 INSN3(ld3r, 0b001101010, 0b1110);
2135 INSN4(ld4r, 0b001101011, 0b1110);
2136
2137 #undef INSN1
2138 #undef INSN2
2139 #undef INSN3
2140 #undef INSN4
2141
2142 #define INSN(NAME, opc) \
2143 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2144 starti; \
2145 assert(T == T8B || T == T16B, "must be T8B or T16B"); \
2146 f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \
2147 rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2148 }
2149
2150 INSN(eor, 0b101110001);
2151 INSN(orr, 0b001110101);
2152 INSN(andr, 0b001110001);
2153 INSN(bic, 0b001110011);
2154 INSN(bif, 0b101110111);
2155 INSN(bit, 0b101110101);
2156 INSN(bsl, 0b101110011);
2157 INSN(orn, 0b001110111);
2158
2159 #undef INSN
2160
2161 #define INSN(NAME, opc, opc2) \
2162 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2163 starti; \
2164 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2165 f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \
2166 rf(Vn, 5), rf(Vd, 0); \
2167 }
2168
2169 INSN(addv, 0, 0b100001);
2170 INSN(subv, 1, 0b100001);
2171 INSN(mulv, 0, 0b100111);
2172 INSN(mlav, 0, 0b100101);
2173 INSN(mlsv, 1, 0b100101);
2174 INSN(sshl, 0, 0b010001);
2175 INSN(ushl, 1, 0b010001);
2176
2177 #undef INSN
2178
2179 #define INSN(NAME, opc, opc2) \
2180 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2181 starti; \
2182 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2183 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
2184 rf(Vn, 5), rf(Vd, 0); \
2185 }
2186
2187 INSN(absr, 0, 0b100000101110);
2188 INSN(negr, 1, 0b100000101110);
2189 INSN(notr, 1, 0b100000010110);
2190 INSN(addv, 0, 0b110001101110);
2191 INSN(cls, 0, 0b100000010010);
2192 INSN(clz, 1, 0b100000010010);
2193 INSN(cnt, 0, 0b100000010110);
2194
2195 #undef INSN
2196
2197 #define INSN(NAME, op0, cmode0) \
2198 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \
2199 unsigned cmode = cmode0; \
2200 unsigned op = op0; \
2201 starti; \
2202 assert(lsl == 0 || \
2203 ((T == T4H || T == T8H) && lsl == 8) || \
2204 ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \
2205 cmode |= lsl >> 2; \
2206 if (T == T4H || T == T8H) cmode |= 0b1000; \
2207 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
2208 assert(op == 0 && cmode0 == 0, "must be MOVI"); \
2209 cmode = 0b1110; \
2210 if (T == T1D || T == T2D) op = 1; \
2211 } \
2212 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \
2213 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
2214 rf(Vd, 0); \
2215 }
2216
2217 INSN(movi, 0, 0);
2218 INSN(orri, 0, 1);
2219 INSN(mvni, 1, 0);
2220 INSN(bici, 1, 1);
2221
2222 #undef INSN
2223
2224 #define INSN(NAME, op1, op2, op3) \
2225 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2226 starti; \
2227 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2228 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \
2229 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2230 }
2231
2232 INSN(fadd, 0, 0, 0b110101);
2233 INSN(fdiv, 1, 0, 0b111111);
2234 INSN(fmul, 1, 0, 0b110111);
2235 INSN(fsub, 0, 1, 0b110101);
2236 INSN(fmla, 0, 0, 0b110011);
2237 INSN(fmls, 0, 1, 0b110011);
2238
2239 #undef INSN
2240
2241 #define INSN(NAME, opc) \
2242 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2243 starti; \
2244 assert(T == T4S, "arrangement must be T4S"); \
2245 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2246 }
2247
2248 INSN(sha1c, 0b000000);
2249 INSN(sha1m, 0b001000);
2250 INSN(sha1p, 0b000100);
2251 INSN(sha1su0, 0b001100);
2252 INSN(sha256h2, 0b010100);
2253 INSN(sha256h, 0b010000);
2254 INSN(sha256su1, 0b011000);
2255
2256 #undef INSN
2257
2258 #define INSN(NAME, opc) \
2259 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2260 starti; \
2261 assert(T == T4S, "arrangement must be T4S"); \
2262 f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2263 }
2264
2265 INSN(sha1h, 0b000010);
2266 INSN(sha1su1, 0b000110);
2267 INSN(sha256su0, 0b001010);
2268
2269 #undef INSN
2270
2271 #define INSN(NAME, opc) \
2272 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2273 starti; \
2274 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2275 }
2276
2277 INSN(aese, 0b0100111000101000010010);
2278 INSN(aesd, 0b0100111000101000010110);
2279 INSN(aesmc, 0b0100111000101000011010);
2280 INSN(aesimc, 0b0100111000101000011110);
2281
2282 #undef INSN
2283
2284 // vect1 += vect2*scalar. FMLA-Vector-Scalar-Double
2285 void fmlavsd(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, int index) {
2286 assert(index == 0 || index == 1, "Incorrect index");
2287 starti;
2288 f(0b01001111110, 31, 21);
2289 rf(Vm, 16);
2290 f(0b0001, 15, 12);
2291 f(index, 11);
2292 f(0, 10);
2293 rf(Vn, 5);
2294 rf(Vd, 0);
2295 }
2296
2297 // vect1 += vect2*vect3. FMLA-Vector-Vector-Double
2298 void fmlavvd(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
2299 starti;
2300 // 01001110011 Rm 110011 Rn Rd
2301 f(0b01001110011, 31, 21);
2302 rf(Vm, 16);
2303 f(0b110011, 15, 10);
2304 rf(Vn, 5);
2305 rf(Vd, 0);
2306 }
2307
2308 // Floating-point Reciprocal Estimate for single precision
2309 void frecpe(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) {
2310 assert(type == D || type == S, "Wrong type for frecpe");
2311 starti;
2312 f(0b010111101, 31, 23);
2313 f(type == D ? 1 : 0, 22);
2314 f(0b100001110110, 21, 10);
2315 rf(Vn, 5), rf(Vd, 0);
2316 }
2317
2318 // (double) {a, b} -> (a + b)
2319 void faddpd(FloatRegister Vd, FloatRegister Vn) {
2320 starti;
2321 f(0b0111111001110000110110, 31, 10);
2322 rf(Vn, 5), rf(Vd, 0);
2323 }
2324
2325 // fmulxvd is vect(Vn)*Vm[index]. FMULX-Vector-Scalar-Double
2326 void fmulxvsd(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, int index) {
2327 assert(index == 0 || index == 1, "Incorrect index");
2328 //Q=1, sz=1,L=0, M:Rm = Vm, H=index for T2D
2329 starti;
2330 f(0b01101111110, 31, 21);
2331 rf(Vm, 16);
2332 f(0b1001, 15, 12);
2333 f(index, 11);
2334 f(0, 10);
2335 rf(Vn, 5);
2336 rf(Vd, 0);
2337 }
2338
2339 // fmulxsd is LO64(Vn)*Vm[index]. FULX-Scalar-Double
2340 void fmulxssd(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, int index) {
2341 // sz = 1, L = 0, H = index, M:Rm = Vm
2342 starti;
2343 f(0b01111111110, 31, 21);
2344 rf(Vm, 16);
2345 f(0b1001, 15, 12);
2346 f(index, 11);
2347 f(0, 10);
2348 rf(Vn, 5);
2349 rf(Vd, 0);
2350 }
2351
2352 void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
2353 starti;
2354 assert(T != Q, "invalid register variant");
2355 f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
2356 f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2357 }
2358
2359 void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
2360 starti;
2361 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
2362 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10);
2363 rf(Vn, 5), rf(Rd, 0);
2364 }
2365
2366 #define INSN(NAME, opc, opc2, isSHR) \
2367 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \
2368 starti; \
2369 /* The encodings for the immh:immb fields (bits 22:16) in *SHR are \
2370 * 0001 xxx 8B/16B, shift = 16 - UInt(immh:immb) \
2371 * 001x xxx 4H/8H, shift = 32 - UInt(immh:immb) \
2372 * 01xx xxx 2S/4S, shift = 64 - UInt(immh:immb) \
2373 * 1xxx xxx 1D/2D, shift = 128 - UInt(immh:immb) \
2374 * (1D is RESERVED) \
2375 * for SHL shift is calculated as: \
2376 * 0001 xxx 8B/16B, shift = UInt(immh:immb) - 8 \
2377 * 001x xxx 4H/8H, shift = UInt(immh:immb) - 16 \
2378 * 01xx xxx 2S/4S, shift = UInt(immh:immb) - 32 \
2379 * 1xxx xxx 1D/2D, shift = UInt(immh:immb) - 64 \
2380 * (1D is RESERVED) \
2381 */ \
2382 assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \
2383 int cVal = (1 << (((T >> 1) + 3) + (isSHR ? 1 : 0))); \
2384 int encodedShift = isSHR ? cVal - shift : cVal + shift; \
2385 f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \
2386 f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2387 }
2388
2389 INSN(shl, 0, 0b010101, /* isSHR = */ false);
2390 INSN(sshr, 0, 0b000001, /* isSHR = */ true);
2391 INSN(ushr, 1, 0b000001, /* isSHR = */ true);
2392
2393 #undef INSN
2394
2395 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2396 starti;
2397 /* The encodings for the immh:immb fields (bits 22:16) are
2398 * 0001 xxx 8H, 8B/16b shift = xxx
2399 * 001x xxx 4S, 4H/8H shift = xxxx
2400 * 01xx xxx 2D, 2S/4S shift = xxxxx
2401 * 1xxx xxx RESERVED
2402 */
2403 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2404 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2405 f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
2406 f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2407 }
2408 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2409 ushll(Vd, Ta, Vn, Tb, shift);
2410 }
2411
2412 void uzp1(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T, int op = 0){
2413 starti;
2414 f(0, 31), f((T & 0x1), 30), f(0b001110, 29, 24), f((T >> 1), 23, 22), f(0, 21);
2415 rf(Vm, 16), f(0, 15), f(op, 14), f(0b0110, 13, 10), rf(Vn, 5), rf(Vd, 0);
2416 }
2417 void uzp2(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T){
2418 uzp1(Vd, Vn, Vm, T, 1);
2419 }
2420
2421 // Move from general purpose register
2422 // mov Vd.T[index], Rn
2423 void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
2424 starti;
2425 f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2426 f(0b000111, 15, 10), rf(Xn, 5), rf(Vd, 0);
2427 }
2428
2429 // Move to general purpose register
2430 // mov Rd, Vn.T[index]
2431 void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
2432 starti;
2433 f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
2434 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2435 f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
2436 }
2437
2438 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2439 starti;
2440 assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
2441 (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
2442 int size = (Ta == T1Q) ? 0b11 : 0b00;
2443 f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
2444 f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
2445 }
2446 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2447 assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
2448 pmull(Vd, Ta, Vn, Vm, Tb);
2449 }
2450
2451 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2452 starti;
2453 int size_b = (int)Tb >> 1;
2454 int size_a = (int)Ta >> 1;
2455 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
2456 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
2457 f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
2458 }
2459
2460 void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
2461 {
2462 starti;
2463 assert(T != T1D, "reserved encoding");
2464 f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2465 f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), rf(Xs, 5), rf(Vd, 0);
2466 }
2467
2468 void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
2469 {
2470 starti;
2471 assert(T != T1D, "reserved encoding");
2472 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2473 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2474 f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2475 }
2476
2477 // AdvSIMD ZIP/UZP/TRN
2478 #define INSN(NAME, opcode) \
2479 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2480 starti; \
2481 f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15); \
2482 f(opcode, 14, 12), f(0b10, 11, 10); \
2483 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); \
2484 f(T & 1, 30), f(T >> 1, 23, 22); \
2485 }
2486
2487 INSN(uzp1, 0b001);
2488 INSN(trn1, 0b010);
2489 INSN(zip1, 0b011);
2490 INSN(uzp2, 0b101);
2491 INSN(trn2, 0b110);
2492 INSN(zip2, 0b111);
2493
2494 #undef INSN
2495
2496 // CRC32 instructions
2497 #define INSN(NAME, c, sf, sz) \
2498 void NAME(Register Rd, Register Rn, Register Rm) { \
2499 starti; \
2500 f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12); \
2501 f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
2502 }
2503
2504 INSN(crc32b, 0, 0, 0b00);
2505 INSN(crc32h, 0, 0, 0b01);
2506 INSN(crc32w, 0, 0, 0b10);
2507 INSN(crc32x, 0, 1, 0b11);
2508 INSN(crc32cb, 1, 0, 0b00);
2509 INSN(crc32ch, 1, 0, 0b01);
2510 INSN(crc32cw, 1, 0, 0b10);
2511 INSN(crc32cx, 1, 1, 0b11);
2512
2513 #undef INSN
2514
2515 // Table vector lookup
2516 #define INSN(NAME, op) \
2517 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \
2518 starti; \
2519 assert(T == T8B || T == T16B, "invalid arrangement"); \
2520 assert(0 < registers && registers <= 4, "invalid number of registers"); \
2521 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \
2522 f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2523 }
2524
2525 INSN(tbl, 0);
2526 INSN(tbx, 1);
2527
2528 #undef INSN
2529
2530 // AdvSIMD two-reg misc
2531 #define INSN(NAME, U, opcode) \
2532 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2533 starti; \
2534 assert((ASSERTION), MSG); \
2535 f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24); \
2536 f((int)(T >> 1), 23, 22), f(0b10000, 21, 17), f(opcode, 16, 12); \
2537 f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2538 }
2539
2540 #define MSG "invalid arrangement"
2541
2542 #define ASSERTION (T == T2S || T == T4S || T == T2D)
2543 INSN(fsqrt, 1, 0b11111);
2544 INSN(fabs, 0, 0b01111);
2545 INSN(fneg, 1, 0b01111);
2546 #undef ASSERTION
2547
2548 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
2549 INSN(rev64, 0, 0b00000);
2550 #undef ASSERTION
2551
2552 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
2553 INSN(rev32, 1, 0b00000);
2554 private:
2555 INSN(_rbit, 1, 0b00101);
2556 public:
2557
2558 #undef ASSERTION
2559
2560 #define ASSERTION (T == T8B || T == T16B)
2561 INSN(rev16, 0, 0b00001);
2562 // RBIT only allows T8B and T16B but encodes them oddly. Argh...
2563 void rbit(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
2564 assert((ASSERTION), MSG);
2565 _rbit(Vd, SIMD_Arrangement(T & 1 | 0b010), Vn);
2566 }
2567 #undef ASSERTION
2568
2569 #undef MSG
2570
2571 #undef INSN
2572
2573 void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
2574 {
2575 starti;
2576 assert(T == T8B || T == T16B, "invalid arrangement");
2577 assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
2578 f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
2579 rf(Vm, 16), f(0, 15), f(index, 14, 11);
2580 f(0, 10), rf(Vn, 5), rf(Vd, 0);
2581 }
2582
2583 /* Simulator extensions to the ISA
2584
2585 haltsim
2586
2587 takes no arguments, causes the sim to enter a debug break and then
2588 return from the simulator run() call with STATUS_HALT? The linking
2589 code will call fatal() when it sees STATUS_HALT.
2590
2591 blrt Xn, Wm
2592 blrt Xn, #gpargs, #fpargs, #type
2593 Xn holds the 64 bit x86 branch_address
2594 call format is encoded either as immediate data in the call
2595 or in register Wm. In the latter case
2596 Wm[13..6] = #gpargs,
2597 Wm[5..2] = #fpargs,
2598 Wm[1,0] = #type
2599
2600 calls the x86 code address 'branch_address' supplied in Xn passing
2601 arguments taken from the general and floating point registers according
2602 to the supplied counts 'gpargs' and 'fpargs'. may return a result in r0
2603 or v0 according to the the return type #type' where
2604
2605 address branch_address;
2606 uimm4 gpargs;
2607 uimm4 fpargs;
2608 enum ReturnType type;
2609
2610 enum ReturnType
2611 {
2612 void_ret = 0,
2613 int_ret = 1,
2614 long_ret = 1,
2615 obj_ret = 1, // i.e. same as long
2616 float_ret = 2,
2617 double_ret = 3
2618 }
2619
2620 notify
2621
2622 notifies the simulator of a transfer of control. instr[14:0]
2623 identifies the type of change of control.
2624
2625 0 ==> initial entry to a method.
2626
2627 1 ==> return into a method from a submethod call.
2628
2629 2 ==> exit out of Java method code.
2630
2631 3 ==> start execution for a new bytecode.
2632
2633 in cases 1 and 2 the simulator is expected to use a JVM callback to
2634 identify the name of the specific method being executed. in case 4
2635 the simulator is expected to use a JVM callback to identify the
2636 bytecode index.
2637
2638 Instruction encodings
2639 ---------------------
2640
2641 These are encoded in the space with instr[28:25] = 00 which is
2642 unallocated. Encodings are
2643
2644 10987654321098765432109876543210
2645 PSEUDO_HALT = 0x11100000000000000000000000000000
2646 PSEUDO_BLRT = 0x11000000000000000_______________
2647 PSEUDO_BLRTR = 0x1100000000000000100000__________
2648 PSEUDO_NOTIFY = 0x10100000000000000_______________
2649
2650 instr[31,29] = op1 : 111 ==> HALT, 110 ==> BLRT/BLRTR, 101 ==> NOTIFY
2651
2652 for BLRT
2653 instr[14,11] = #gpargs, instr[10,7] = #fpargs
2654 instr[6,5] = #type, instr[4,0] = Rn
2655 for BLRTR
2656 instr[9,5] = Rm, instr[4,0] = Rn
2657 for NOTIFY
2658 instr[14:0] = type : 0 ==> entry, 1 ==> reentry, 2 ==> exit, 3 ==> bcstart
2659 */
2660
2661 enum NotifyType { method_entry, method_reentry, method_exit, bytecode_start };
2662
2663 virtual void notify(int type) {
2664 if (UseBuiltinSim) {
2665 starti;
2666 // 109
2667 f(0b101, 31, 29);
2668 // 87654321098765
2669 f(0b00000000000000, 28, 15);
2670 f(type, 14, 0);
2671 }
2672 }
2673
2674 void blrt(Register Rn, int gpargs, int fpargs, int type) {
2675 if (UseBuiltinSim) {
2676 starti;
2677 f(0b110, 31 ,29);
2678 f(0b00, 28, 25);
2679 // 4321098765
2680 f(0b0000000000, 24, 15);
2681 f(gpargs, 14, 11);
2682 f(fpargs, 10, 7);
2683 f(type, 6, 5);
2684 rf(Rn, 0);
2685 } else {
2686 blr(Rn);
2687 }
2688 }
2689
2690 void blrt(Register Rn, Register Rm) {
2691 if (UseBuiltinSim) {
2692 starti;
2693 f(0b110, 31 ,29);
2694 f(0b00, 28, 25);
2695 // 4321098765
2696 f(0b0000000001, 24, 15);
2697 // 43210
2698 f(0b00000, 14, 10);
2699 rf(Rm, 5);
2700 rf(Rn, 0);
2701 } else {
2702 blr(Rn);
2703 }
2704 }
2705
2706 void haltsim() {
2707 starti;
2708 f(0b111, 31 ,29);
2709 f(0b00, 28, 27);
2710 // 654321098765432109876543210
2711 f(0b000000000000000000000000000, 26, 0);
2712 }
2713
2714 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2715 }
2716
2717 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2718 Register tmp,
2719 int offset) {
2720 ShouldNotCallThis();
2721 return RegisterOrConstant();
2722 }
2723
2724 // Stack overflow checking
2725 virtual void bang_stack_with_offset(int offset);
2726
2727 static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
2728 static bool operand_valid_for_add_sub_immediate(long imm);
2729 static bool operand_valid_for_float_immediate(double imm);
2730
2731 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
2732 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
2733 };
2734
2735 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
2736 Assembler::Membar_mask_bits b) {
2737 return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
2738 }
2739
2740 Instruction_aarch64::~Instruction_aarch64() {
2741 assem->emit();
2742 }
2743
2744 #undef starti
2745
2746 // Invert a condition
2747 inline const Assembler::Condition operator~(const Assembler::Condition cond) {
2748 return Assembler::Condition(int(cond) ^ 1);
2749 }
2750
2751 class BiasedLockingCounters;
2752
2753 extern "C" void das(uint64_t start, int len);
2754
2755 #endif // CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP