1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
1656 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1657 InstructionMark im(this);
1658 simd_prefix(dst, src, VEX_SIMD_66);
1659 emit_int8(0x6E);
1660 emit_operand(dst, src);
1661 }
1662
1663 void Assembler::movdl(Address dst, XMMRegister src) {
1664 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1665 InstructionMark im(this);
1666 simd_prefix(dst, src, VEX_SIMD_66);
1667 emit_int8(0x7E);
1668 emit_operand(src, dst);
1669 }
1670
1671 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1672 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1673 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1674 }
1675
1676 void Assembler::movdqu(XMMRegister dst, Address src) {
1677 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1678 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1679 }
1680
1681 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1682 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1683 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1684 }
1685
1686 void Assembler::movdqu(Address dst, XMMRegister src) {
1687 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1688 InstructionMark im(this);
1689 simd_prefix(dst, src, VEX_SIMD_F3);
1690 emit_int8(0x7F);
1691 emit_operand(src, dst);
1692 }
1693
1694 // Move Unaligned 256bit Vector
1695 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2269 emit_int8(imm8);
2270 }
2271
2272 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2273 assert(VM_Version::supports_sse4_2(), "");
2274 InstructionMark im(this);
2275 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2276 emit_int8(0x61);
2277 emit_operand(dst, src);
2278 emit_int8(imm8);
2279 }
2280
2281 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2282 assert(VM_Version::supports_sse4_2(), "");
2283 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2284 emit_int8(0x61);
2285 emit_int8((unsigned char)(0xC0 | encode));
2286 emit_int8(imm8);
2287 }
2288
2289 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2290 assert(VM_Version::supports_sse4_1(), "");
2291 InstructionMark im(this);
2292 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2293 emit_int8(0x30);
2294 emit_operand(dst, src);
2295 }
2296
2297 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2298 assert(VM_Version::supports_sse4_1(), "");
2299 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2300 emit_int8(0x30);
2301 emit_int8((unsigned char)(0xC0 | encode));
2302 }
2303
2304 // generic
2305 void Assembler::pop(Register dst) {
2306 int encode = prefix_and_encode(dst->encoding());
2307 emit_int8(0x58 | encode);
2308 }
3674 InstructionMark im(this);
3675 bool vector256 = true;
3676 assert(src != xnoreg, "sanity");
3677 int src_enc = src->encoding();
3678 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3679 emit_int8(0x39);
3680 emit_operand(src, dst);
3681 // 0x01 - extract from upper 128 bits
3682 emit_int8(0x01);
3683 }
3684
3685 // duplicate 4-bytes integer data from src into 8 locations in dest
3686 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
3687 assert(VM_Version::supports_avx2(), "");
3688 bool vector256 = true;
3689 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3690 emit_int8(0x58);
3691 emit_int8((unsigned char)(0xC0 | encode));
3692 }
3693
3694 void Assembler::vzeroupper() {
3695 assert(VM_Version::supports_avx(), "");
3696 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
3697 emit_int8(0x77);
3698 }
3699
3700
3701 #ifndef _LP64
3702 // 32bit only pieces of the assembler
3703
3704 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3705 // NO PREFIX AS NEVER 64BIT
3706 InstructionMark im(this);
3707 emit_int8((unsigned char)0x81);
3708 emit_int8((unsigned char)(0xF8 | src1->encoding()));
3709 emit_data(imm32, rspec, 0);
3710 }
3711
3712 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3713 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
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1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
1656 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1657 InstructionMark im(this);
1658 simd_prefix(dst, src, VEX_SIMD_66);
1659 emit_int8(0x6E);
1660 emit_operand(dst, src);
1661 }
1662
1663 void Assembler::movdl(Address dst, XMMRegister src) {
1664 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1665 InstructionMark im(this);
1666 simd_prefix(dst, src, VEX_SIMD_66);
1667 emit_int8(0x7E);
1668 emit_operand(src, dst);
1669 }
1670
1671 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1672 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1673 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1674 }
1675
1676 void Assembler::movdqa(XMMRegister dst, Address src) {
1677 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1678 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1679 }
1680
1681 void Assembler::movdqu(XMMRegister dst, Address src) {
1682 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1683 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1684 }
1685
1686 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1687 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1688 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1689 }
1690
1691 void Assembler::movdqu(Address dst, XMMRegister src) {
1692 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1693 InstructionMark im(this);
1694 simd_prefix(dst, src, VEX_SIMD_F3);
1695 emit_int8(0x7F);
1696 emit_operand(src, dst);
1697 }
1698
1699 // Move Unaligned 256bit Vector
1700 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2274 emit_int8(imm8);
2275 }
2276
2277 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2278 assert(VM_Version::supports_sse4_2(), "");
2279 InstructionMark im(this);
2280 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2281 emit_int8(0x61);
2282 emit_operand(dst, src);
2283 emit_int8(imm8);
2284 }
2285
2286 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2287 assert(VM_Version::supports_sse4_2(), "");
2288 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2289 emit_int8(0x61);
2290 emit_int8((unsigned char)(0xC0 | encode));
2291 emit_int8(imm8);
2292 }
2293
2294 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2295 assert(VM_Version::supports_sse4_1(), "");
2296 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2297 emit_int8(0x16);
2298 emit_int8((unsigned char)(0xC0 | encode));
2299 emit_int8(imm8);
2300 }
2301
2302 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
2303 assert(VM_Version::supports_sse4_1(), "");
2304 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2305 emit_int8(0x16);
2306 emit_int8((unsigned char)(0xC0 | encode));
2307 emit_int8(imm8);
2308 }
2309
2310 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
2311 assert(VM_Version::supports_sse4_1(), "");
2312 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2313 emit_int8(0x22);
2314 emit_int8((unsigned char)(0xC0 | encode));
2315 emit_int8(imm8);
2316 }
2317
2318 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
2319 assert(VM_Version::supports_sse4_1(), "");
2320 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2321 emit_int8(0x22);
2322 emit_int8((unsigned char)(0xC0 | encode));
2323 emit_int8(imm8);
2324 }
2325
2326 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2327 assert(VM_Version::supports_sse4_1(), "");
2328 InstructionMark im(this);
2329 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2330 emit_int8(0x30);
2331 emit_operand(dst, src);
2332 }
2333
2334 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2335 assert(VM_Version::supports_sse4_1(), "");
2336 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2337 emit_int8(0x30);
2338 emit_int8((unsigned char)(0xC0 | encode));
2339 }
2340
2341 // generic
2342 void Assembler::pop(Register dst) {
2343 int encode = prefix_and_encode(dst->encoding());
2344 emit_int8(0x58 | encode);
2345 }
3711 InstructionMark im(this);
3712 bool vector256 = true;
3713 assert(src != xnoreg, "sanity");
3714 int src_enc = src->encoding();
3715 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3716 emit_int8(0x39);
3717 emit_operand(src, dst);
3718 // 0x01 - extract from upper 128 bits
3719 emit_int8(0x01);
3720 }
3721
3722 // duplicate 4-bytes integer data from src into 8 locations in dest
3723 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
3724 assert(VM_Version::supports_avx2(), "");
3725 bool vector256 = true;
3726 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3727 emit_int8(0x58);
3728 emit_int8((unsigned char)(0xC0 | encode));
3729 }
3730
3731 // Carry-Less Multiplication Quadword
3732 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
3733 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
3734 bool vector256 = false;
3735 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3736 emit_int8(0x44);
3737 emit_int8((unsigned char)(0xC0 | encode));
3738 emit_int8((unsigned char)mask);
3739 }
3740
3741 void Assembler::vzeroupper() {
3742 assert(VM_Version::supports_avx(), "");
3743 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
3744 emit_int8(0x77);
3745 }
3746
3747
3748 #ifndef _LP64
3749 // 32bit only pieces of the assembler
3750
3751 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3752 // NO PREFIX AS NEVER 64BIT
3753 InstructionMark im(this);
3754 emit_int8((unsigned char)0x81);
3755 emit_int8((unsigned char)(0xF8 | src1->encoding()));
3756 emit_data(imm32, rspec, 0);
3757 }
3758
3759 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3760 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
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