src/cpu/x86/vm/vm_version_x86.hpp

*** 1,7 ****
  /*
!  * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
--- 1,7 ----
  /*
!  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
*** 59,69 ****
  
    union StdCpuid1Ecx {
      uint32_t value;
      struct {
        uint32_t sse3     : 1,
!                         : 2,
                 monitor  : 1,
                          : 1,
                 vmx      : 1,
                          : 1,
                 est      : 1,
--- 59,70 ----
  
    union StdCpuid1Ecx {
      uint32_t value;
      struct {
        uint32_t sse3     : 1,
!                clmul    : 1,
!                         : 1,
                 monitor  : 1,
                          : 1,
                 vmx      : 1,
                          : 1,
                 est      : 1,
*** 247,257 ****
      CPU_TSC    = (1 << 15),
      CPU_TSCINV = (1 << 16),
      CPU_AVX    = (1 << 17),
      CPU_AVX2   = (1 << 18),
      CPU_AES    = (1 << 19),
!     CPU_ERMS   = (1 << 20) // enhanced 'rep movsb/stosb' instructions
    } cpuFeatureFlags;
  
    enum {
      // AMD
      CPU_FAMILY_AMD_11H       = 0x11,
--- 248,259 ----
      CPU_TSC    = (1 << 15),
      CPU_TSCINV = (1 << 16),
      CPU_AVX    = (1 << 17),
      CPU_AVX2   = (1 << 18),
      CPU_AES    = (1 << 19),
!     CPU_ERMS   = (1 << 20), // enhanced 'rep movsb/stosb' instructions
!     CPU_CLMUL  = (1 << 21) // carryless multiply for CRC
    } cpuFeatureFlags;
  
    enum {
      // AMD
      CPU_FAMILY_AMD_11H       = 0x11,
*** 427,436 ****
--- 429,440 ----
        result |= CPU_TSCINV;
      if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
        result |= CPU_AES;
      if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
        result |= CPU_ERMS;
+     if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
+       result |= CPU_CLMUL;
  
      // AMD features.
      if (is_amd()) {
        if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
            (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
*** 553,562 ****
--- 557,567 ----
    static bool supports_avx()      { return (_cpuFeatures & CPU_AVX) != 0; }
    static bool supports_avx2()     { return (_cpuFeatures & CPU_AVX2) != 0; }
    static bool supports_tsc()      { return (_cpuFeatures & CPU_TSC)    != 0; }
    static bool supports_aes()      { return (_cpuFeatures & CPU_AES) != 0; }
    static bool supports_erms()     { return (_cpuFeatures & CPU_ERMS) != 0; }
+   static bool supports_clmul()    { return (_cpuFeatures & CPU_CLMUL) != 0; }
  
    // Intel features
    static bool is_intel_family_core() { return is_intel() &&
                                         extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }