1 /* 2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP 26 #define CPU_X86_VM_VM_VERSION_X86_HPP 27 28 #include "runtime/globals_extension.hpp" 29 #include "runtime/vm_version.hpp" 30 31 class VM_Version : public Abstract_VM_Version { 32 public: 33 // cpuid result register layouts. These are all unions of a uint32_t 34 // (in case anyone wants access to the register as a whole) and a bitfield. 35 36 union StdCpuid1Eax { 37 uint32_t value; 38 struct { 39 uint32_t stepping : 4, 40 model : 4, 41 family : 4, 42 proc_type : 2, 43 : 2, 44 ext_model : 4, 45 ext_family : 8, 46 : 4; 47 } bits; 48 }; 49 50 union StdCpuid1Ebx { // example, unused 51 uint32_t value; 52 struct { 53 uint32_t brand_id : 8, 54 clflush_size : 8, 55 threads_per_cpu : 8, 56 apic_id : 8; 57 } bits; 58 }; 59 60 union StdCpuid1Ecx { 61 uint32_t value; 62 struct { 63 uint32_t sse3 : 1, 64 : 2, 65 monitor : 1, 66 : 1, 67 vmx : 1, 68 : 1, 69 est : 1, 70 : 1, 71 ssse3 : 1, 72 cid : 1, 73 : 2, 74 cmpxchg16: 1, 75 : 4, 76 dca : 1, 77 sse4_1 : 1, 78 sse4_2 : 1, 79 : 2, 80 popcnt : 1, 81 : 1, 82 aes : 1, 83 : 1, 84 osxsave : 1, 85 avx : 1, 86 : 3; 87 } bits; 88 }; 89 90 union StdCpuid1Edx { 91 uint32_t value; 92 struct { 93 uint32_t : 4, 94 tsc : 1, 95 : 3, 96 cmpxchg8 : 1, 97 : 6, 98 cmov : 1, 99 : 3, 100 clflush : 1, 101 : 3, 102 mmx : 1, 103 fxsr : 1, 104 sse : 1, 105 sse2 : 1, 106 : 1, 107 ht : 1, 108 : 3; 109 } bits; 110 }; 111 112 union DcpCpuid4Eax { 113 uint32_t value; 114 struct { 115 uint32_t cache_type : 5, 116 : 21, 117 cores_per_cpu : 6; 118 } bits; 119 }; 120 121 union DcpCpuid4Ebx { 122 uint32_t value; 123 struct { 124 uint32_t L1_line_size : 12, 125 partitions : 10, 126 associativity : 10; 127 } bits; 128 }; 129 130 union TplCpuidBEbx { 131 uint32_t value; 132 struct { 133 uint32_t logical_cpus : 16, 134 : 16; 135 } bits; 136 }; 137 138 union ExtCpuid1Ecx { 139 uint32_t value; 140 struct { 141 uint32_t LahfSahf : 1, 142 CmpLegacy : 1, 143 : 4, 144 lzcnt : 1, 145 sse4a : 1, 146 misalignsse : 1, 147 prefetchw : 1, 148 : 22; 149 } bits; 150 }; 151 152 union ExtCpuid1Edx { 153 uint32_t value; 154 struct { 155 uint32_t : 22, 156 mmx_amd : 1, 157 mmx : 1, 158 fxsr : 1, 159 : 4, 160 long_mode : 1, 161 tdnow2 : 1, 162 tdnow : 1; 163 } bits; 164 }; 165 166 union ExtCpuid5Ex { 167 uint32_t value; 168 struct { 169 uint32_t L1_line_size : 8, 170 L1_tag_lines : 8, 171 L1_assoc : 8, 172 L1_size : 8; 173 } bits; 174 }; 175 176 union ExtCpuid7Edx { 177 uint32_t value; 178 struct { 179 uint32_t : 8, 180 tsc_invariance : 1, 181 : 23; 182 } bits; 183 }; 184 185 union ExtCpuid8Ecx { 186 uint32_t value; 187 struct { 188 uint32_t cores_per_cpu : 8, 189 : 24; 190 } bits; 191 }; 192 193 union SefCpuid7Eax { 194 uint32_t value; 195 }; 196 197 union SefCpuid7Ebx { 198 uint32_t value; 199 struct { 200 uint32_t fsgsbase : 1, 201 : 2, 202 bmi1 : 1, 203 : 1, 204 avx2 : 1, 205 : 2, 206 bmi2 : 1, 207 erms : 1, 208 : 22; 209 } bits; 210 }; 211 212 union XemXcr0Eax { 213 uint32_t value; 214 struct { 215 uint32_t x87 : 1, 216 sse : 1, 217 ymm : 1, 218 : 29; 219 } bits; 220 }; 221 222 protected: 223 static int _cpu; 224 static int _model; 225 static int _stepping; 226 static int _cpuFeatures; // features returned by the "cpuid" instruction 227 // 0 if this instruction is not available 228 static const char* _features_str; 229 230 enum { 231 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) 232 CPU_CMOV = (1 << 1), 233 CPU_FXSR = (1 << 2), 234 CPU_HT = (1 << 3), 235 CPU_MMX = (1 << 4), 236 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions 237 // may not necessarily support other 3dnow instructions 238 CPU_SSE = (1 << 6), 239 CPU_SSE2 = (1 << 7), 240 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) 241 CPU_SSSE3 = (1 << 9), 242 CPU_SSE4A = (1 << 10), 243 CPU_SSE4_1 = (1 << 11), 244 CPU_SSE4_2 = (1 << 12), 245 CPU_POPCNT = (1 << 13), 246 CPU_LZCNT = (1 << 14), 247 CPU_TSC = (1 << 15), 248 CPU_TSCINV = (1 << 16), 249 CPU_AVX = (1 << 17), 250 CPU_AVX2 = (1 << 18), 251 CPU_AES = (1 << 19), 252 CPU_ERMS = (1 << 20) // enhanced 'rep movsb/stosb' instructions 253 } cpuFeatureFlags; 254 255 enum { 256 // AMD 257 CPU_FAMILY_AMD_11H = 0x11, 258 // Intel 259 CPU_FAMILY_INTEL_CORE = 6, 260 CPU_MODEL_NEHALEM = 0x1e, 261 CPU_MODEL_NEHALEM_EP = 0x1a, 262 CPU_MODEL_NEHALEM_EX = 0x2e, 263 CPU_MODEL_WESTMERE = 0x25, 264 CPU_MODEL_WESTMERE_EP = 0x2c, 265 CPU_MODEL_WESTMERE_EX = 0x2f, 266 CPU_MODEL_SANDYBRIDGE = 0x2a, 267 CPU_MODEL_SANDYBRIDGE_EP = 0x2d, 268 CPU_MODEL_IVYBRIDGE_EP = 0x3a 269 } cpuExtendedFamily; 270 271 // cpuid information block. All info derived from executing cpuid with 272 // various function numbers is stored here. Intel and AMD info is 273 // merged in this block: accessor methods disentangle it. 274 // 275 // The info block is laid out in subblocks of 4 dwords corresponding to 276 // eax, ebx, ecx and edx, whether or not they contain anything useful. 277 struct CpuidInfo { 278 // cpuid function 0 279 uint32_t std_max_function; 280 uint32_t std_vendor_name_0; 281 uint32_t std_vendor_name_1; 282 uint32_t std_vendor_name_2; 283 284 // cpuid function 1 285 StdCpuid1Eax std_cpuid1_eax; 286 StdCpuid1Ebx std_cpuid1_ebx; 287 StdCpuid1Ecx std_cpuid1_ecx; 288 StdCpuid1Edx std_cpuid1_edx; 289 290 // cpuid function 4 (deterministic cache parameters) 291 DcpCpuid4Eax dcp_cpuid4_eax; 292 DcpCpuid4Ebx dcp_cpuid4_ebx; 293 uint32_t dcp_cpuid4_ecx; // unused currently 294 uint32_t dcp_cpuid4_edx; // unused currently 295 296 // cpuid function 7 (structured extended features) 297 SefCpuid7Eax sef_cpuid7_eax; 298 SefCpuid7Ebx sef_cpuid7_ebx; 299 uint32_t sef_cpuid7_ecx; // unused currently 300 uint32_t sef_cpuid7_edx; // unused currently 301 302 // cpuid function 0xB (processor topology) 303 // ecx = 0 304 uint32_t tpl_cpuidB0_eax; 305 TplCpuidBEbx tpl_cpuidB0_ebx; 306 uint32_t tpl_cpuidB0_ecx; // unused currently 307 uint32_t tpl_cpuidB0_edx; // unused currently 308 309 // ecx = 1 310 uint32_t tpl_cpuidB1_eax; 311 TplCpuidBEbx tpl_cpuidB1_ebx; 312 uint32_t tpl_cpuidB1_ecx; // unused currently 313 uint32_t tpl_cpuidB1_edx; // unused currently 314 315 // ecx = 2 316 uint32_t tpl_cpuidB2_eax; 317 TplCpuidBEbx tpl_cpuidB2_ebx; 318 uint32_t tpl_cpuidB2_ecx; // unused currently 319 uint32_t tpl_cpuidB2_edx; // unused currently 320 321 // cpuid function 0x80000000 // example, unused 322 uint32_t ext_max_function; 323 uint32_t ext_vendor_name_0; 324 uint32_t ext_vendor_name_1; 325 uint32_t ext_vendor_name_2; 326 327 // cpuid function 0x80000001 328 uint32_t ext_cpuid1_eax; // reserved 329 uint32_t ext_cpuid1_ebx; // reserved 330 ExtCpuid1Ecx ext_cpuid1_ecx; 331 ExtCpuid1Edx ext_cpuid1_edx; 332 333 // cpuid functions 0x80000002 thru 0x80000004: example, unused 334 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; 335 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; 336 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; 337 338 // cpuid function 0x80000005 // AMD L1, Intel reserved 339 uint32_t ext_cpuid5_eax; // unused currently 340 uint32_t ext_cpuid5_ebx; // reserved 341 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) 342 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) 343 344 // cpuid function 0x80000007 345 uint32_t ext_cpuid7_eax; // reserved 346 uint32_t ext_cpuid7_ebx; // reserved 347 uint32_t ext_cpuid7_ecx; // reserved 348 ExtCpuid7Edx ext_cpuid7_edx; // tscinv 349 350 // cpuid function 0x80000008 351 uint32_t ext_cpuid8_eax; // unused currently 352 uint32_t ext_cpuid8_ebx; // reserved 353 ExtCpuid8Ecx ext_cpuid8_ecx; 354 uint32_t ext_cpuid8_edx; // reserved 355 356 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) 357 XemXcr0Eax xem_xcr0_eax; 358 uint32_t xem_xcr0_edx; // reserved 359 }; 360 361 // The actual cpuid info block 362 static CpuidInfo _cpuid_info; 363 364 // Extractors and predicates 365 static uint32_t extended_cpu_family() { 366 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; 367 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; 368 return result; 369 } 370 371 static uint32_t extended_cpu_model() { 372 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; 373 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; 374 return result; 375 } 376 377 static uint32_t cpu_stepping() { 378 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; 379 return result; 380 } 381 382 static uint logical_processor_count() { 383 uint result = threads_per_core(); 384 return result; 385 } 386 387 static uint32_t feature_flags() { 388 uint32_t result = 0; 389 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) 390 result |= CPU_CX8; 391 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) 392 result |= CPU_CMOV; 393 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && 394 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) 395 result |= CPU_FXSR; 396 // HT flag is set for multi-core processors also. 397 if (threads_per_core() > 1) 398 result |= CPU_HT; 399 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && 400 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) 401 result |= CPU_MMX; 402 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) 403 result |= CPU_SSE; 404 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) 405 result |= CPU_SSE2; 406 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) 407 result |= CPU_SSE3; 408 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) 409 result |= CPU_SSSE3; 410 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) 411 result |= CPU_SSE4_1; 412 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) 413 result |= CPU_SSE4_2; 414 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) 415 result |= CPU_POPCNT; 416 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && 417 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && 418 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && 419 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { 420 result |= CPU_AVX; 421 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) 422 result |= CPU_AVX2; 423 } 424 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) 425 result |= CPU_TSC; 426 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) 427 result |= CPU_TSCINV; 428 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) 429 result |= CPU_AES; 430 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0) 431 result |= CPU_ERMS; 432 433 // AMD features. 434 if (is_amd()) { 435 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || 436 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) 437 result |= CPU_3DNOW_PREFETCH; 438 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) 439 result |= CPU_LZCNT; 440 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) 441 result |= CPU_SSE4A; 442 } 443 444 return result; 445 } 446 447 static void get_processor_features(); 448 449 public: 450 // Offsets for cpuid asm stub 451 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } 452 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } 453 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } 454 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } 455 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } 456 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } 457 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } 458 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } 459 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } 460 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } 461 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } 462 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } 463 464 // Initialization 465 static void initialize(); 466 467 // Asserts 468 static void assert_is_initialized() { 469 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); 470 } 471 472 // 473 // Processor family: 474 // 3 - 386 475 // 4 - 486 476 // 5 - Pentium 477 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, 478 // Pentium M, Core Solo, Core Duo, Core2 Duo 479 // family 6 model: 9, 13, 14, 15 480 // 0x0f - Pentium 4, Opteron 481 // 482 // Note: The cpu family should be used to select between 483 // instruction sequences which are valid on all Intel 484 // processors. Use the feature test functions below to 485 // determine whether a particular instruction is supported. 486 // 487 static int cpu_family() { return _cpu;} 488 static bool is_P6() { return cpu_family() >= 6; } 489 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' 490 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' 491 492 static bool supports_processor_topology() { 493 return (_cpuid_info.std_max_function >= 0xB) && 494 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. 495 // Some cpus have max cpuid >= 0xB but do not support processor topology. 496 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); 497 } 498 499 static uint cores_per_cpu() { 500 uint result = 1; 501 if (is_intel()) { 502 if (supports_processor_topology()) { 503 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / 504 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 505 } else { 506 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); 507 } 508 } else if (is_amd()) { 509 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); 510 } 511 return result; 512 } 513 514 static uint threads_per_core() { 515 uint result = 1; 516 if (is_intel() && supports_processor_topology()) { 517 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 518 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { 519 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / 520 cores_per_cpu(); 521 } 522 return result; 523 } 524 525 static intx prefetch_data_size() { 526 intx result = 0; 527 if (is_intel()) { 528 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); 529 } else if (is_amd()) { 530 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; 531 } 532 if (result < 32) // not defined ? 533 result = 32; // 32 bytes by default on x86 and other x64 534 return result; 535 } 536 537 // 538 // Feature identification 539 // 540 static bool supports_cpuid() { return _cpuFeatures != 0; } 541 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } 542 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } 543 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } 544 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } 545 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } 546 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } 547 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } 548 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } 549 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } 550 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } 551 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } 552 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } 553 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; } 554 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } 555 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } 556 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; } 557 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; } 558 559 // Intel features 560 static bool is_intel_family_core() { return is_intel() && 561 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } 562 563 static bool is_intel_tsc_synched_at_init() { 564 if (is_intel_family_core()) { 565 uint32_t ext_model = extended_cpu_model(); 566 if (ext_model == CPU_MODEL_NEHALEM_EP || 567 ext_model == CPU_MODEL_WESTMERE_EP || 568 ext_model == CPU_MODEL_SANDYBRIDGE_EP || 569 ext_model == CPU_MODEL_IVYBRIDGE_EP) { 570 // <= 2-socket invariant tsc support. EX versions are usually used 571 // in > 2-socket systems and likely don't synchronize tscs at 572 // initialization. 573 // Code that uses tsc values must be prepared for them to arbitrarily 574 // jump forward or backward. 575 return true; 576 } 577 } 578 return false; 579 } 580 581 // AMD features 582 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; } 583 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } 584 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } 585 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } 586 587 static bool is_amd_Barcelona() { return is_amd() && 588 extended_cpu_family() == CPU_FAMILY_AMD_11H; } 589 590 // Intel and AMD newer cores support fast timestamps well 591 static bool supports_tscinv_bit() { 592 return (_cpuFeatures & CPU_TSCINV) != 0; 593 } 594 static bool supports_tscinv() { 595 return supports_tscinv_bit() && 596 ( (is_amd() && !is_amd_Barcelona()) || 597 is_intel_tsc_synched_at_init() ); 598 } 599 600 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). 601 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && 602 supports_sse3() && _model != 0x1C; } 603 604 static bool supports_compare_and_exchange() { return true; } 605 606 static const char* cpu_features() { return _features_str; } 607 608 static intx allocate_prefetch_distance() { 609 // This method should be called before allocate_prefetch_style(). 610 // 611 // Hardware prefetching (distance/size in bytes): 612 // Pentium 3 - 64 / 32 613 // Pentium 4 - 256 / 128 614 // Athlon - 64 / 32 ???? 615 // Opteron - 128 / 64 only when 2 sequential cache lines accessed 616 // Core - 128 / 64 617 // 618 // Software prefetching (distance in bytes / instruction with best score): 619 // Pentium 3 - 128 / prefetchnta 620 // Pentium 4 - 512 / prefetchnta 621 // Athlon - 128 / prefetchnta 622 // Opteron - 256 / prefetchnta 623 // Core - 256 / prefetchnta 624 // It will be used only when AllocatePrefetchStyle > 0 625 626 intx count = AllocatePrefetchDistance; 627 if (count < 0) { // default ? 628 if (is_amd()) { // AMD 629 if (supports_sse2()) 630 count = 256; // Opteron 631 else 632 count = 128; // Athlon 633 } else { // Intel 634 if (supports_sse2()) 635 if (cpu_family() == 6) { 636 count = 256; // Pentium M, Core, Core2 637 } else { 638 count = 512; // Pentium 4 639 } 640 else 641 count = 128; // Pentium 3 (and all other old CPUs) 642 } 643 } 644 return count; 645 } 646 static intx allocate_prefetch_style() { 647 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 648 // Return 0 if AllocatePrefetchDistance was not defined. 649 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; 650 } 651 652 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from 653 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. 654 // Tested intervals from 128 to 2048 in increments of 64 == one cache line. 655 // 256 bytes (4 dcache lines) was the nearest runner-up to 576. 656 657 // gc copy/scan is disabled if prefetchw isn't supported, because 658 // Prefetch::write emits an inlined prefetchw on Linux. 659 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. 660 // The used prefetcht0 instruction works for both amd64 and em64t. 661 static intx prefetch_copy_interval_in_bytes() { 662 intx interval = PrefetchCopyIntervalInBytes; 663 return interval >= 0 ? interval : 576; 664 } 665 static intx prefetch_scan_interval_in_bytes() { 666 intx interval = PrefetchScanIntervalInBytes; 667 return interval >= 0 ? interval : 576; 668 } 669 static intx prefetch_fields_ahead() { 670 intx count = PrefetchFieldsAhead; 671 return count >= 0 ? count : 1; 672 } 673 }; 674 675 #endif // CPU_X86_VM_VM_VERSION_X86_HPP