1938
1939 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1940 MacroAssembler _masm(&cbuf);
1941
1942 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1943 int reg = ra_->get_encode(this);
1944
1945 if (Assembler::operand_valid_for_add_sub_immediate(offset)) {
1946 __ add(as_Register(reg), sp, offset);
1947 } else {
1948 ShouldNotReachHere();
1949 }
1950 }
1951
1952 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1953 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1954 return 4;
1955 }
1956
1957 //=============================================================================
1958
1959 #ifndef PRODUCT
1960 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1961 {
1962 st->print_cr("# MachUEPNode");
1963 if (UseCompressedClassPointers) {
1964 st->print_cr("\tldrw rscratch1, j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1965 if (Universe::narrow_klass_shift() != 0) {
1966 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1967 }
1968 } else {
1969 st->print_cr("\tldr rscratch1, j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1970 }
1971 st->print_cr("\tcmp r0, rscratch1\t # Inline cache check");
1972 st->print_cr("\tbne, SharedRuntime::_ic_miss_stub");
1973 }
1974 #endif
1975
1976 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1977 {
2350 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2351 return true;
2352 }
2353 return false;
2354 }
2355
2356 void Compile::reshape_address(AddPNode* addp) {
2357 }
2358
2359 // helper for encoding java_to_runtime calls on sim
2360 //
2361 // this is needed to compute the extra arguments required when
2362 // planting a call to the simulator blrt instruction. the TypeFunc
2363 // can be queried to identify the counts for integral, and floating
2364 // arguments and the return type
2365
2366 static void getCallInfo(const TypeFunc *tf, int &gpcnt, int &fpcnt, int &rtype)
2367 {
2368 int gps = 0;
2369 int fps = 0;
2370 const TypeTuple *domain = tf->domain();
2371 int max = domain->cnt();
2372 for (int i = TypeFunc::Parms; i < max; i++) {
2373 const Type *t = domain->field_at(i);
2374 switch(t->basic_type()) {
2375 case T_FLOAT:
2376 case T_DOUBLE:
2377 fps++;
2378 default:
2379 gps++;
2380 }
2381 }
2382 gpcnt = gps;
2383 fpcnt = fps;
2384 BasicType rt = tf->return_type();
2385 switch (rt) {
2386 case T_VOID:
2387 rtype = MacroAssembler::ret_type_void;
2388 break;
2389 default:
2390 rtype = MacroAssembler::ret_type_integral;
7868 %}
7869
7870 // ============================================================================
7871 // Cast/Convert Instructions
7872
7873 instruct castX2P(iRegPNoSp dst, iRegL src) %{
7874 match(Set dst (CastX2P src));
7875
7876 ins_cost(INSN_COST);
7877 format %{ "mov $dst, $src\t# long -> ptr" %}
7878
7879 ins_encode %{
7880 if ($dst$$reg != $src$$reg) {
7881 __ mov(as_Register($dst$$reg), as_Register($src$$reg));
7882 }
7883 %}
7884
7885 ins_pipe(ialu_reg);
7886 %}
7887
7888 instruct castP2X(iRegLNoSp dst, iRegP src) %{
7889 match(Set dst (CastP2X src));
7890
7891 ins_cost(INSN_COST);
7892 format %{ "mov $dst, $src\t# ptr -> long" %}
7893
7894 ins_encode %{
7895 if ($dst$$reg != $src$$reg) {
7896 __ mov(as_Register($dst$$reg), as_Register($src$$reg));
7897 }
7898 %}
7899
7900 ins_pipe(ialu_reg);
7901 %}
7902
7903 // Convert oop into int for vectors alignment masking
7904 instruct convP2I(iRegINoSp dst, iRegP src) %{
7905 match(Set dst (ConvL2I (CastP2X src)));
7906
7907 ins_cost(INSN_COST);
13381
13382 match(Set dst (MoveL2D src));
13383
13384 effect(DEF dst, USE src);
13385
13386 ins_cost(INSN_COST);
13387
13388 format %{ "fmovd $dst, $src\t# MoveL2D_reg_reg" %}
13389
13390 ins_encode %{
13391 __ fmovd(as_FloatRegister($dst$$reg), $src$$Register);
13392 %}
13393
13394 ins_pipe(fp_l2d);
13395
13396 %}
13397
13398 // ============================================================================
13399 // clearing of an array
13400
13401 instruct clearArray_reg_reg(iRegL_R11 cnt, iRegP_R10 base, Universe dummy, rFlagsReg cr)
13402 %{
13403 match(Set dummy (ClearArray cnt base));
13404 effect(USE_KILL cnt, USE_KILL base);
13405
13406 ins_cost(4 * INSN_COST);
13407 format %{ "ClearArray $cnt, $base" %}
13408
13409 ins_encode %{
13410 __ zero_words($base$$Register, $cnt$$Register);
13411 %}
13412
13413 ins_pipe(pipe_class_memory);
13414 %}
13415
13416 instruct clearArray_imm_reg(immL cnt, iRegP_R10 base, Universe dummy, rFlagsReg cr)
13417 %{
13418 predicate((u_int64_t)n->in(2)->get_long()
13419 < (u_int64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
13420 match(Set dummy (ClearArray cnt base));
13421 effect(USE_KILL base);
13422
13423 ins_cost(4 * INSN_COST);
13424 format %{ "ClearArray $cnt, $base" %}
13425
13426 ins_encode %{
13427 __ zero_words($base$$Register, (u_int64_t)$cnt$$constant);
13428 %}
13429
13430 ins_pipe(pipe_class_memory);
13431 %}
13432
13433 // ============================================================================
13434 // Overflow Math Instructions
13435
13436 instruct overflowAddI_reg_reg(rFlagsReg cr, iRegIorL2I op1, iRegIorL2I op2)
13437 %{
13438 match(Set cr (OverflowAddI op1 op2));
13439
13440 format %{ "cmnw $op1, $op2\t# overflow check int" %}
|
1938
1939 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1940 MacroAssembler _masm(&cbuf);
1941
1942 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1943 int reg = ra_->get_encode(this);
1944
1945 if (Assembler::operand_valid_for_add_sub_immediate(offset)) {
1946 __ add(as_Register(reg), sp, offset);
1947 } else {
1948 ShouldNotReachHere();
1949 }
1950 }
1951
1952 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1953 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1954 return 4;
1955 }
1956
1957 //=============================================================================
1958 #ifndef PRODUCT
1959 void MachVVEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1960 {
1961 st->print_cr("MachVVEPNode");
1962 }
1963 #endif
1964
1965 void MachVVEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1966 {
1967 // Unpack all value type args passed as oop and then jump to
1968 // the verified entry point (skipping the unverified entry).
1969 MacroAssembler _masm(&cbuf);
1970
1971 __ unpack_value_args(ra_->C);
1972 __ b(*_verified_entry);
1973 }
1974
1975 uint MachVVEPNode::size(PhaseRegAlloc* ra_) const
1976 {
1977 return MachNode::size(ra_); // too many variables; just compute it the hard way
1978 }
1979
1980
1981 //=============================================================================
1982
1983 #ifndef PRODUCT
1984 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1985 {
1986 st->print_cr("# MachUEPNode");
1987 if (UseCompressedClassPointers) {
1988 st->print_cr("\tldrw rscratch1, j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1989 if (Universe::narrow_klass_shift() != 0) {
1990 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1991 }
1992 } else {
1993 st->print_cr("\tldr rscratch1, j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1994 }
1995 st->print_cr("\tcmp r0, rscratch1\t # Inline cache check");
1996 st->print_cr("\tbne, SharedRuntime::_ic_miss_stub");
1997 }
1998 #endif
1999
2000 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
2001 {
2374 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2375 return true;
2376 }
2377 return false;
2378 }
2379
2380 void Compile::reshape_address(AddPNode* addp) {
2381 }
2382
2383 // helper for encoding java_to_runtime calls on sim
2384 //
2385 // this is needed to compute the extra arguments required when
2386 // planting a call to the simulator blrt instruction. the TypeFunc
2387 // can be queried to identify the counts for integral, and floating
2388 // arguments and the return type
2389
2390 static void getCallInfo(const TypeFunc *tf, int &gpcnt, int &fpcnt, int &rtype)
2391 {
2392 int gps = 0;
2393 int fps = 0;
2394 const TypeTuple *domain = tf->domain_cc();
2395 int max = domain->cnt();
2396 for (int i = TypeFunc::Parms; i < max; i++) {
2397 const Type *t = domain->field_at(i);
2398 switch(t->basic_type()) {
2399 case T_FLOAT:
2400 case T_DOUBLE:
2401 fps++;
2402 default:
2403 gps++;
2404 }
2405 }
2406 gpcnt = gps;
2407 fpcnt = fps;
2408 BasicType rt = tf->return_type();
2409 switch (rt) {
2410 case T_VOID:
2411 rtype = MacroAssembler::ret_type_void;
2412 break;
2413 default:
2414 rtype = MacroAssembler::ret_type_integral;
7892 %}
7893
7894 // ============================================================================
7895 // Cast/Convert Instructions
7896
7897 instruct castX2P(iRegPNoSp dst, iRegL src) %{
7898 match(Set dst (CastX2P src));
7899
7900 ins_cost(INSN_COST);
7901 format %{ "mov $dst, $src\t# long -> ptr" %}
7902
7903 ins_encode %{
7904 if ($dst$$reg != $src$$reg) {
7905 __ mov(as_Register($dst$$reg), as_Register($src$$reg));
7906 }
7907 %}
7908
7909 ins_pipe(ialu_reg);
7910 %}
7911
7912 instruct castN2X(iRegLNoSp dst, iRegN src) %{
7913 match(Set dst (CastP2X src));
7914
7915 ins_cost(INSN_COST);
7916 format %{ "mov $dst, $src\t# ptr -> long" %}
7917
7918 ins_encode %{
7919 if ($dst$$reg != $src$$reg) {
7920 __ mov(as_Register($dst$$reg), as_Register($src$$reg));
7921 }
7922 %}
7923
7924 ins_pipe(ialu_reg);
7925 %}
7926
7927 instruct castP2X(iRegLNoSp dst, iRegP src) %{
7928 match(Set dst (CastP2X src));
7929
7930 ins_cost(INSN_COST);
7931 format %{ "mov $dst, $src\t# ptr -> long" %}
7932
7933 ins_encode %{
7934 if ($dst$$reg != $src$$reg) {
7935 __ mov(as_Register($dst$$reg), as_Register($src$$reg));
7936 }
7937 %}
7938
7939 ins_pipe(ialu_reg);
7940 %}
7941
7942 // Convert oop into int for vectors alignment masking
7943 instruct convP2I(iRegINoSp dst, iRegP src) %{
7944 match(Set dst (ConvL2I (CastP2X src)));
7945
7946 ins_cost(INSN_COST);
13420
13421 match(Set dst (MoveL2D src));
13422
13423 effect(DEF dst, USE src);
13424
13425 ins_cost(INSN_COST);
13426
13427 format %{ "fmovd $dst, $src\t# MoveL2D_reg_reg" %}
13428
13429 ins_encode %{
13430 __ fmovd(as_FloatRegister($dst$$reg), $src$$Register);
13431 %}
13432
13433 ins_pipe(fp_l2d);
13434
13435 %}
13436
13437 // ============================================================================
13438 // clearing of an array
13439
13440 instruct clearArray_reg_reg(iRegL_R11 cnt, iRegP_R10 base, iRegL val, Universe dummy, rFlagsReg cr)
13441 %{
13442 match(Set dummy (ClearArray (Binary cnt base) val));
13443 effect(USE_KILL cnt, USE_KILL base);
13444
13445 ins_cost(4 * INSN_COST);
13446 format %{ "ClearArray $cnt, $base" %}
13447
13448 ins_encode %{
13449 __ zero_words($base$$Register, $cnt$$Register);
13450 %}
13451
13452 ins_pipe(pipe_class_memory);
13453 %}
13454
13455 instruct clearArray_imm_reg(immL cnt, iRegP_R10 base, iRegL val, Universe dummy, rFlagsReg cr)
13456 %{
13457 predicate((u_int64_t)n->in(3)->get_long()
13458 < (u_int64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
13459
13460 match(Set dummy (ClearArray (Binary cnt base) val));
13461 effect(USE_KILL base);
13462
13463 ins_cost(4 * INSN_COST);
13464 format %{ "ClearArray $cnt, $base" %}
13465
13466 ins_encode %{
13467 __ zero_words($base$$Register, (u_int64_t)$cnt$$constant);
13468 %}
13469
13470 ins_pipe(pipe_class_memory);
13471 %}
13472
13473 // ============================================================================
13474 // Overflow Math Instructions
13475
13476 instruct overflowAddI_reg_reg(rFlagsReg cr, iRegIorL2I op1, iRegIorL2I op2)
13477 %{
13478 match(Set cr (OverflowAddI op1 op2));
13479
13480 format %{ "cmnw $op1, $op2\t# overflow check int" %}
|