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src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp

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rev 53735 : AArch64 support for ValueTypes

*** 25,34 **** --- 25,36 ---- #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP #include "asm/assembler.hpp" + #include "runtime/signature.hpp" + // MacroAssembler extends Assembler by frequently used macros. // // Instructions for which a 'better' code sequence exists depending // on arguments should also go in here.
*** 582,591 **** --- 584,605 ---- virtual void null_check(Register reg, int offset = -1); static bool needs_explicit_null_check(intptr_t offset); static bool uses_implicit_null_check(void* address); + void test_klass_is_value(Register klass, Register temp_reg, Label& is_value); + + void test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable); + void test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable); + void test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened); + + // Check klass/oops is flat value type array (oop->_klass->_layout_helper & vt_bit) + void test_flat_array_klass(Register klass, Register temp_reg, Label& is_flat_array); + void test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array); + + + static address target_addr_for_insn(address insn_addr, unsigned insn); static address target_addr_for_insn(address insn_addr) { unsigned insn = *(unsigned*)insn_addr; return target_addr_for_insn(insn_addr, insn); }
*** 1139,1148 **** --- 1153,1165 ---- void sub(Register Rd, Register Rn, RegisterOrConstant decrement); void subw(Register Rd, Register Rn, RegisterOrConstant decrement); void adrp(Register reg1, const Address &dest, unsigned long &byte_offset); + // Support for MachVVEPNode + void unpack_value_args(Compile* C); + void tableswitch(Register index, jint lowbound, jint highbound, Label &jumptable, Label &jumptable_end, int stride = 1) { adr(rscratch1, jumptable); subsw(rscratch2, index, lowbound); subsw(zr, rscratch2, highbound - lowbound);
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