1 /*
2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "gc/shared/barrierSet.hpp"
38 #include "gc/shared/cardTableBarrierSet.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "nativeInst_aarch64.hpp"
41 #include "oops/objArrayKlass.hpp"
42 #include "runtime/frame.inline.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "vmreg_aarch64.inline.hpp"
45
46
47
48 #ifndef PRODUCT
49 #define COMMENT(x) do { __ block_comment(x); } while (0)
50 #else
51 #define COMMENT(x)
52 #endif
53
54 NEEDS_CLEANUP // remove this definitions ?
55 const Register IC_Klass = rscratch2; // where the IC klass is cached
56 const Register SYNC_header = r0; // synchronization header
57 const Register SHIFT_count = r0; // where count for shift operations must be
58
59 #define __ _masm->
60
61
62 static void select_different_registers(Register preserve,
63 Register extra,
64 Register &tmp1,
65 Register &tmp2) {
66 if (tmp1 == preserve) {
67 assert_different_registers(tmp1, tmp2, extra);
68 tmp1 = extra;
69 } else if (tmp2 == preserve) {
70 assert_different_registers(tmp1, tmp2, extra);
71 tmp2 = extra;
72 }
73 assert_different_registers(preserve, tmp1, tmp2);
74 }
75
76
77
78 static void select_different_registers(Register preserve,
79 Register extra,
80 Register &tmp1,
81 Register &tmp2,
82 Register &tmp3) {
83 if (tmp1 == preserve) {
84 assert_different_registers(tmp1, tmp2, tmp3, extra);
85 tmp1 = extra;
86 } else if (tmp2 == preserve) {
87 assert_different_registers(tmp1, tmp2, tmp3, extra);
88 tmp2 = extra;
89 } else if (tmp3 == preserve) {
90 assert_different_registers(tmp1, tmp2, tmp3, extra);
91 tmp3 = extra;
92 }
93 assert_different_registers(preserve, tmp1, tmp2, tmp3);
94 }
95
96
97 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
98
99
100 LIR_Opr LIR_Assembler::receiverOpr() {
101 return FrameMap::receiver_opr;
102 }
103
104 LIR_Opr LIR_Assembler::osrBufferPointer() {
105 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
106 }
107
108 //--------------fpu register translations-----------------------
109
110
111 address LIR_Assembler::float_constant(float f) {
112 address const_addr = __ float_constant(f);
113 if (const_addr == NULL) {
114 bailout("const section overflow");
115 return __ code()->consts()->start();
116 } else {
117 return const_addr;
118 }
119 }
120
121
122 address LIR_Assembler::double_constant(double d) {
123 address const_addr = __ double_constant(d);
124 if (const_addr == NULL) {
125 bailout("const section overflow");
126 return __ code()->consts()->start();
127 } else {
128 return const_addr;
129 }
130 }
131
132 address LIR_Assembler::int_constant(jlong n) {
133 address const_addr = __ long_constant(n);
134 if (const_addr == NULL) {
135 bailout("const section overflow");
136 return __ code()->consts()->start();
137 } else {
138 return const_addr;
139 }
140 }
141
142 void LIR_Assembler::set_24bit_FPU() { Unimplemented(); }
143
144 void LIR_Assembler::reset_FPU() { Unimplemented(); }
145
146 void LIR_Assembler::fpop() { Unimplemented(); }
147
148 void LIR_Assembler::fxch(int i) { Unimplemented(); }
149
150 void LIR_Assembler::fld(int i) { Unimplemented(); }
151
152 void LIR_Assembler::ffree(int i) { Unimplemented(); }
153
154 void LIR_Assembler::breakpoint() { Unimplemented(); }
155
156 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
157
158 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
159
160 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
161 //-------------------------------------------
162
163 static Register as_reg(LIR_Opr op) {
164 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
165 }
166
167 static jlong as_long(LIR_Opr data) {
168 jlong result;
169 switch (data->type()) {
170 case T_INT:
171 result = (data->as_jint());
172 break;
173 case T_LONG:
174 result = (data->as_jlong());
175 break;
176 default:
177 ShouldNotReachHere();
178 result = 0; // unreachable
179 }
180 return result;
181 }
182
183 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
184 Register base = addr->base()->as_pointer_register();
185 LIR_Opr opr = addr->index();
186 if (opr->is_cpu_register()) {
187 Register index;
188 if (opr->is_single_cpu())
189 index = opr->as_register();
190 else
191 index = opr->as_register_lo();
192 assert(addr->disp() == 0, "must be");
193 switch(opr->type()) {
194 case T_INT:
195 return Address(base, index, Address::sxtw(addr->scale()));
196 case T_LONG:
197 return Address(base, index, Address::lsl(addr->scale()));
198 default:
199 ShouldNotReachHere();
200 }
201 } else {
202 intptr_t addr_offset = intptr_t(addr->disp());
203 if (Address::offset_ok_for_immed(addr_offset, addr->scale()))
204 return Address(base, addr_offset, Address::lsl(addr->scale()));
205 else {
206 __ mov(tmp, addr_offset);
207 return Address(base, tmp, Address::lsl(addr->scale()));
208 }
209 }
210 return Address();
211 }
212
213 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
214 ShouldNotReachHere();
215 return Address();
216 }
217
218 Address LIR_Assembler::as_Address(LIR_Address* addr) {
219 return as_Address(addr, rscratch1);
220 }
221
222 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
223 return as_Address(addr, rscratch1); // Ouch
224 // FIXME: This needs to be much more clever. See x86.
225 }
226
227
228 void LIR_Assembler::osr_entry() {
229 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
230 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
231 ValueStack* entry_state = osr_entry->state();
232 int number_of_locks = entry_state->locks_size();
233
234 // we jump here if osr happens with the interpreter
235 // state set up to continue at the beginning of the
236 // loop that triggered osr - in particular, we have
237 // the following registers setup:
238 //
239 // r2: osr buffer
240 //
241
242 // build frame
243 ciMethod* m = compilation()->method();
244 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
245
246 // OSR buffer is
247 //
248 // locals[nlocals-1..0]
249 // monitors[0..number_of_locks]
250 //
251 // locals is a direct copy of the interpreter frame so in the osr buffer
252 // so first slot in the local array is the last local from the interpreter
253 // and last slot is local[0] (receiver) from the interpreter
254 //
255 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
256 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
257 // in the interpreter frame (the method lock if a sync method)
258
259 // Initialize monitors in the compiled activation.
260 // r2: pointer to osr buffer
261 //
262 // All other registers are dead at this point and the locals will be
263 // copied into place by code emitted in the IR.
264
265 Register OSR_buf = osrBufferPointer()->as_pointer_register();
266 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
267 int monitor_offset = BytesPerWord * method()->max_locals() +
268 (2 * BytesPerWord) * (number_of_locks - 1);
269 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
270 // the OSR buffer using 2 word entries: first the lock and then
271 // the oop.
272 for (int i = 0; i < number_of_locks; i++) {
273 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
274 #ifdef ASSERT
275 // verify the interpreter's monitor has a non-null object
276 {
277 Label L;
278 __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
279 __ cbnz(rscratch1, L);
280 __ stop("locked object is NULL");
281 __ bind(L);
282 }
283 #endif
284 __ ldr(r19, Address(OSR_buf, slot_offset + 0));
285 __ str(r19, frame_map()->address_for_monitor_lock(i));
286 __ ldr(r19, Address(OSR_buf, slot_offset + 1*BytesPerWord));
287 __ str(r19, frame_map()->address_for_monitor_object(i));
288 }
289 }
290 }
291
292
293 // inline cache check; done before the frame is built.
294 int LIR_Assembler::check_icache() {
295 Register receiver = FrameMap::receiver_opr->as_register();
296 Register ic_klass = IC_Klass;
297 int start_offset = __ offset();
298 __ inline_cache_check(receiver, ic_klass);
299
300 // if icache check fails, then jump to runtime routine
301 // Note: RECEIVER must still contain the receiver!
302 Label dont;
303 __ br(Assembler::EQ, dont);
304 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
305
306 // We align the verified entry point unless the method body
307 // (including its inline cache check) will fit in a single 64-byte
308 // icache line.
309 if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {
310 // force alignment after the cache check.
311 __ align(CodeEntryAlignment);
312 }
313
314 __ bind(dont);
315 return start_offset;
316 }
317
318
319 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
320 if (o == NULL) {
321 __ mov(reg, zr);
322 } else {
323 __ movoop(reg, o, /*immediate*/true);
324 }
325 }
326
327 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
328 address target = NULL;
329 relocInfo::relocType reloc_type = relocInfo::none;
330
331 switch (patching_id(info)) {
332 case PatchingStub::access_field_id:
333 target = Runtime1::entry_for(Runtime1::access_field_patching_id);
334 reloc_type = relocInfo::section_word_type;
335 break;
336 case PatchingStub::load_klass_id:
337 target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
338 reloc_type = relocInfo::metadata_type;
339 break;
340 case PatchingStub::load_mirror_id:
341 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
342 reloc_type = relocInfo::oop_type;
343 break;
344 case PatchingStub::load_appendix_id:
345 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
346 reloc_type = relocInfo::oop_type;
347 break;
348 default: ShouldNotReachHere();
349 }
350
351 __ far_call(RuntimeAddress(target));
352 add_call_info_here(info);
353 }
354
355 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
356 deoptimize_trap(info);
357 }
358
359
360 // This specifies the rsp decrement needed to build the frame
361 int LIR_Assembler::initial_frame_size_in_bytes() const {
362 // if rounding, must let FrameMap know!
363
364 // The frame_map records size in slots (32bit word)
365
366 // subtract two words to account for return address and link
367 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
368 }
369
370
371 int LIR_Assembler::emit_exception_handler() {
372 // if the last instruction is a call (typically to do a throw which
373 // is coming at the end after block reordering) the return address
374 // must still point into the code area in order to avoid assertion
375 // failures when searching for the corresponding bci => add a nop
376 // (was bug 5/14/1999 - gri)
377 __ nop();
378
379 // generate code for exception handler
380 address handler_base = __ start_a_stub(exception_handler_size());
381 if (handler_base == NULL) {
382 // not enough space left for the handler
383 bailout("exception handler overflow");
384 return -1;
385 }
386
387 int offset = code_offset();
388
389 // the exception oop and pc are in r0, and r3
390 // no other registers need to be preserved, so invalidate them
391 __ invalidate_registers(false, true, true, false, true, true);
392
393 // check that there is really an exception
394 __ verify_not_null_oop(r0);
395
396 // search an exception handler (r0: exception oop, r3: throwing pc)
397 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); __ should_not_reach_here();
398 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
399 __ end_a_stub();
400
401 return offset;
402 }
403
404
405 // Emit the code to remove the frame from the stack in the exception
406 // unwind path.
407 int LIR_Assembler::emit_unwind_handler() {
408 #ifndef PRODUCT
409 if (CommentedAssembly) {
410 _masm->block_comment("Unwind handler");
411 }
412 #endif
413
414 int offset = code_offset();
415
416 // Fetch the exception from TLS and clear out exception related thread state
417 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
418 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
419 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
420
421 __ bind(_unwind_handler_entry);
422 __ verify_not_null_oop(r0);
423 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
424 __ mov(r19, r0); // Preserve the exception
425 }
426
427 // Preform needed unlocking
428 MonitorExitStub* stub = NULL;
429 if (method()->is_synchronized()) {
430 monitor_address(0, FrameMap::r0_opr);
431 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
432 __ unlock_object(r5, r4, r0, *stub->entry());
433 __ bind(*stub->continuation());
434 }
435
436 if (compilation()->env()->dtrace_method_probes()) {
437 __ call_Unimplemented();
438 #if 0
439 __ movptr(Address(rsp, 0), rax);
440 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
441 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
442 #endif
443 }
444
445 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
446 __ mov(r0, r19); // Restore the exception
447 }
448
449 // remove the activation and dispatch to the unwind handler
450 __ block_comment("remove_frame and dispatch to the unwind handler");
451 __ remove_frame(initial_frame_size_in_bytes());
452 __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
453
454 // Emit the slow path assembly
455 if (stub != NULL) {
456 stub->emit_code(this);
457 }
458
459 return offset;
460 }
461
462
463 int LIR_Assembler::emit_deopt_handler() {
464 // if the last instruction is a call (typically to do a throw which
465 // is coming at the end after block reordering) the return address
466 // must still point into the code area in order to avoid assertion
467 // failures when searching for the corresponding bci => add a nop
468 // (was bug 5/14/1999 - gri)
469 __ nop();
470
471 // generate code for exception handler
472 address handler_base = __ start_a_stub(deopt_handler_size());
473 if (handler_base == NULL) {
474 // not enough space left for the handler
475 bailout("deopt handler overflow");
476 return -1;
477 }
478
479 int offset = code_offset();
480
481 __ adr(lr, pc());
482 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
483 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
484 __ end_a_stub();
485
486 return offset;
487 }
488
489 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
490 _masm->code_section()->relocate(adr, relocInfo::poll_type);
491 int pc_offset = code_offset();
492 flush_debug_info(pc_offset);
493 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
494 if (info->exception_handlers() != NULL) {
495 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
496 }
497 }
498
499 void LIR_Assembler::return_op(LIR_Opr result) {
500 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
501
502 // Pop the stack before the safepoint code
503 __ remove_frame(initial_frame_size_in_bytes());
504
505 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
506 __ reserved_stack_check();
507 }
508
509 address polling_page(os::get_polling_page());
510 __ read_polling_page(rscratch1, polling_page, relocInfo::poll_return_type);
511 __ ret(lr);
512 }
513
514 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
515 address polling_page(os::get_polling_page());
516 guarantee(info != NULL, "Shouldn't be NULL");
517 assert(os::is_poll_address(polling_page), "should be");
518 __ get_polling_page(rscratch1, polling_page, relocInfo::poll_type);
519 add_debug_info_for_branch(info); // This isn't just debug info:
520 // it's the oop map
521 __ read_polling_page(rscratch1, relocInfo::poll_type);
522 return __ offset();
523 }
524
525
526 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
527 if (from_reg == r31_sp)
528 from_reg = sp;
529 if (to_reg == r31_sp)
530 to_reg = sp;
531 __ mov(to_reg, from_reg);
532 }
533
534 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
535
536
537 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
538 assert(src->is_constant(), "should not call otherwise");
539 assert(dest->is_register(), "should not call otherwise");
540 LIR_Const* c = src->as_constant_ptr();
541
542 switch (c->type()) {
543 case T_INT: {
544 assert(patch_code == lir_patch_none, "no patching handled here");
545 __ movw(dest->as_register(), c->as_jint());
546 break;
547 }
548
549 case T_ADDRESS: {
550 assert(patch_code == lir_patch_none, "no patching handled here");
551 __ mov(dest->as_register(), c->as_jint());
552 break;
553 }
554
555 case T_LONG: {
556 assert(patch_code == lir_patch_none, "no patching handled here");
557 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
558 break;
559 }
560
561 case T_VALUETYPE:
562 case T_OBJECT: {
563 if (patch_code == lir_patch_none) {
564 jobject2reg(c->as_jobject(), dest->as_register());
565 } else {
566 jobject2reg_with_patching(dest->as_register(), info);
567 }
568 break;
569 }
570
571 case T_METADATA: {
572 if (patch_code != lir_patch_none) {
573 klass2reg_with_patching(dest->as_register(), info);
574 } else {
575 __ mov_metadata(dest->as_register(), c->as_metadata());
576 }
577 break;
578 }
579
580 case T_FLOAT: {
581 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
582 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
583 } else {
584 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
585 __ ldrs(dest->as_float_reg(), Address(rscratch1));
586 }
587 break;
588 }
589
590 case T_DOUBLE: {
591 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
592 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
593 } else {
594 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
595 __ ldrd(dest->as_double_reg(), Address(rscratch1));
596 }
597 break;
598 }
599
600 default:
601 ShouldNotReachHere();
602 }
603 }
604
605 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
606 LIR_Const* c = src->as_constant_ptr();
607 switch (c->type()) {
608 case T_VALUETYPE:
609 case T_OBJECT:
610 {
611 if (! c->as_jobject())
612 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
613 else {
614 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
615 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
616 }
617 }
618 break;
619 case T_ADDRESS:
620 {
621 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
622 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
623 }
624 case T_INT:
625 case T_FLOAT:
626 {
627 Register reg = zr;
628 if (c->as_jint_bits() == 0)
629 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
630 else {
631 __ movw(rscratch1, c->as_jint_bits());
632 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
633 }
634 }
635 break;
636 case T_LONG:
637 case T_DOUBLE:
638 {
639 Register reg = zr;
640 if (c->as_jlong_bits() == 0)
641 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
642 lo_word_offset_in_bytes));
643 else {
644 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
645 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
646 lo_word_offset_in_bytes));
647 }
648 }
649 break;
650 default:
651 ShouldNotReachHere();
652 }
653 }
654
655 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
656 assert(src->is_constant(), "should not call otherwise");
657 LIR_Const* c = src->as_constant_ptr();
658 LIR_Address* to_addr = dest->as_address_ptr();
659
660 void (Assembler::* insn)(Register Rt, const Address &adr);
661
662 switch (type) {
663 case T_ADDRESS:
664 assert(c->as_jint() == 0, "should be");
665 insn = &Assembler::str;
666 break;
667 case T_LONG:
668 assert(c->as_jlong() == 0, "should be");
669 insn = &Assembler::str;
670 break;
671 case T_INT:
672 assert(c->as_jint() == 0, "should be");
673 insn = &Assembler::strw;
674 break;
675 case T_VALUETYPE:
676 case T_OBJECT:
677 case T_ARRAY:
678 assert(c->as_jobject() == 0, "should be");
679 if (UseCompressedOops && !wide) {
680 insn = &Assembler::strw;
681 } else {
682 insn = &Assembler::str;
683 }
684 break;
685 case T_CHAR:
686 case T_SHORT:
687 assert(c->as_jint() == 0, "should be");
688 insn = &Assembler::strh;
689 break;
690 case T_BOOLEAN:
691 case T_BYTE:
692 assert(c->as_jint() == 0, "should be");
693 insn = &Assembler::strb;
694 break;
695 default:
696 ShouldNotReachHere();
697 insn = &Assembler::str; // unreachable
698 }
699
700 if (info) add_debug_info_for_null_check_here(info);
701 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
702 }
703
704 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
705 assert(src->is_register(), "should not call otherwise");
706 assert(dest->is_register(), "should not call otherwise");
707
708 // move between cpu-registers
709 if (dest->is_single_cpu()) {
710 if (src->type() == T_LONG) {
711 // Can do LONG -> OBJECT
712 move_regs(src->as_register_lo(), dest->as_register());
713 return;
714 }
715 assert(src->is_single_cpu(), "must match");
716 if (src->type() == T_OBJECT || src->type() == T_VALUETYPE) {
717 __ verify_oop(src->as_register());
718 }
719 move_regs(src->as_register(), dest->as_register());
720
721 } else if (dest->is_double_cpu()) {
722 if (src->type() == T_OBJECT || src->type() == T_ARRAY || src->type() == T_VALUETYPE) {
723 // Surprising to me but we can see move of a long to t_object
724 __ verify_oop(src->as_register());
725 move_regs(src->as_register(), dest->as_register_lo());
726 return;
727 }
728 assert(src->is_double_cpu(), "must match");
729 Register f_lo = src->as_register_lo();
730 Register f_hi = src->as_register_hi();
731 Register t_lo = dest->as_register_lo();
732 Register t_hi = dest->as_register_hi();
733 assert(f_hi == f_lo, "must be same");
734 assert(t_hi == t_lo, "must be same");
735 move_regs(f_lo, t_lo);
736
737 } else if (dest->is_single_fpu()) {
738 __ fmovs(dest->as_float_reg(), src->as_float_reg());
739
740 } else if (dest->is_double_fpu()) {
741 __ fmovd(dest->as_double_reg(), src->as_double_reg());
742
743 } else {
744 ShouldNotReachHere();
745 }
746 }
747
748 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
749 if (src->is_single_cpu()) {
750 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
751 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
752 __ verify_oop(src->as_register());
753 } else if (type == T_METADATA || type == T_DOUBLE) {
754 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
755 } else {
756 __ strw(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
757 }
758
759 } else if (src->is_double_cpu()) {
760 Address dest_addr_LO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
761 __ str(src->as_register_lo(), dest_addr_LO);
762
763 } else if (src->is_single_fpu()) {
764 Address dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
765 __ strs(src->as_float_reg(), dest_addr);
766
767 } else if (src->is_double_fpu()) {
768 Address dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
769 __ strd(src->as_double_reg(), dest_addr);
770
771 } else {
772 ShouldNotReachHere();
773 }
774
775 }
776
777
778 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
779 LIR_Address* to_addr = dest->as_address_ptr();
780 PatchingStub* patch = NULL;
781 Register compressed_src = rscratch1;
782
783 if (patch_code != lir_patch_none) {
784 deoptimize_trap(info);
785 return;
786 }
787
788 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
789 __ verify_oop(src->as_register());
790
791 if (UseCompressedOops && !wide) {
792 __ encode_heap_oop(compressed_src, src->as_register());
793 } else {
794 compressed_src = src->as_register();
795 }
796 }
797
798 int null_check_here = code_offset();
799 switch (type) {
800 case T_FLOAT: {
801 __ strs(src->as_float_reg(), as_Address(to_addr));
802 break;
803 }
804
805 case T_DOUBLE: {
806 __ strd(src->as_double_reg(), as_Address(to_addr));
807 break;
808 }
809
810 case T_VALUETYPE: // fall through
811 case T_ARRAY: // fall through
812 case T_OBJECT: // fall through
813 if (UseCompressedOops && !wide) {
814 __ strw(compressed_src, as_Address(to_addr, rscratch2));
815 } else {
816 __ str(compressed_src, as_Address(to_addr));
817 }
818 break;
819 case T_METADATA:
820 // We get here to store a method pointer to the stack to pass to
821 // a dtrace runtime call. This can't work on 64 bit with
822 // compressed klass ptrs: T_METADATA can be a compressed klass
823 // ptr or a 64 bit method pointer.
824 ShouldNotReachHere();
825 __ str(src->as_register(), as_Address(to_addr));
826 break;
827 case T_ADDRESS:
828 __ str(src->as_register(), as_Address(to_addr));
829 break;
830 case T_INT:
831 __ strw(src->as_register(), as_Address(to_addr));
832 break;
833
834 case T_LONG: {
835 __ str(src->as_register_lo(), as_Address_lo(to_addr));
836 break;
837 }
838
839 case T_BYTE: // fall through
840 case T_BOOLEAN: {
841 __ strb(src->as_register(), as_Address(to_addr));
842 break;
843 }
844
845 case T_CHAR: // fall through
846 case T_SHORT:
847 __ strh(src->as_register(), as_Address(to_addr));
848 break;
849
850 default:
851 ShouldNotReachHere();
852 }
853 if (info != NULL) {
854 add_debug_info_for_null_check(null_check_here, info);
855 }
856 }
857
858
859 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
860 assert(src->is_stack(), "should not call otherwise");
861 assert(dest->is_register(), "should not call otherwise");
862
863 if (dest->is_single_cpu()) {
864 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
865 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
866 __ verify_oop(dest->as_register());
867 } else if (type == T_METADATA) {
868 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
869 } else {
870 __ ldrw(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
871 }
872
873 } else if (dest->is_double_cpu()) {
874 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
875 __ ldr(dest->as_register_lo(), src_addr_LO);
876
877 } else if (dest->is_single_fpu()) {
878 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
879 __ ldrs(dest->as_float_reg(), src_addr);
880
881 } else if (dest->is_double_fpu()) {
882 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
883 __ ldrd(dest->as_double_reg(), src_addr);
884
885 } else {
886 ShouldNotReachHere();
887 }
888 }
889
890
891 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
892 address target = NULL;
893 relocInfo::relocType reloc_type = relocInfo::none;
894
895 switch (patching_id(info)) {
896 case PatchingStub::access_field_id:
897 target = Runtime1::entry_for(Runtime1::access_field_patching_id);
898 reloc_type = relocInfo::section_word_type;
899 break;
900 case PatchingStub::load_klass_id:
901 target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
902 reloc_type = relocInfo::metadata_type;
903 break;
904 case PatchingStub::load_mirror_id:
905 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
906 reloc_type = relocInfo::oop_type;
907 break;
908 case PatchingStub::load_appendix_id:
909 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
910 reloc_type = relocInfo::oop_type;
911 break;
912 default: ShouldNotReachHere();
913 }
914
915 __ far_call(RuntimeAddress(target));
916 add_call_info_here(info);
917 }
918
919 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
920
921 LIR_Opr temp;
922 if (type == T_LONG || type == T_DOUBLE)
923 temp = FrameMap::rscratch1_long_opr;
924 else
925 temp = FrameMap::rscratch1_opr;
926
927 stack2reg(src, temp, src->type());
928 reg2stack(temp, dest, dest->type(), false);
929 }
930
931
932 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
933 LIR_Address* addr = src->as_address_ptr();
934 LIR_Address* from_addr = src->as_address_ptr();
935
936 if (addr->base()->type() == T_OBJECT || addr->base()->type() == T_VALUETYPE) {
937 __ verify_oop(addr->base()->as_pointer_register());
938 }
939
940 if (patch_code != lir_patch_none) {
941 deoptimize_trap(info);
942 return;
943 }
944
945 if (info != NULL) {
946 add_debug_info_for_null_check_here(info);
947 }
948 int null_check_here = code_offset();
949 switch (type) {
950 case T_FLOAT: {
951 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
952 break;
953 }
954
955 case T_DOUBLE: {
956 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
957 break;
958 }
959
960 case T_VALUETYPE: // fall through
961 case T_ARRAY: // fall through
962 case T_OBJECT: // fall through
963 if (UseCompressedOops && !wide) {
964 __ ldrw(dest->as_register(), as_Address(from_addr));
965 } else {
966 __ ldr(dest->as_register(), as_Address(from_addr));
967 }
968 break;
969 case T_METADATA:
970 // We get here to store a method pointer to the stack to pass to
971 // a dtrace runtime call. This can't work on 64 bit with
972 // compressed klass ptrs: T_METADATA can be a compressed klass
973 // ptr or a 64 bit method pointer.
974 ShouldNotReachHere();
975 __ ldr(dest->as_register(), as_Address(from_addr));
976 break;
977 case T_ADDRESS:
978 // FIXME: OMG this is a horrible kludge. Any offset from an
979 // address that matches klass_offset_in_bytes() will be loaded
980 // as a word, not a long.
981 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
982 __ ldrw(dest->as_register(), as_Address(from_addr));
983 } else {
984 __ ldr(dest->as_register(), as_Address(from_addr));
985 }
986 break;
987 case T_INT:
988 __ ldrw(dest->as_register(), as_Address(from_addr));
989 break;
990
991 case T_LONG: {
992 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
993 break;
994 }
995
996 case T_BYTE:
997 __ ldrsb(dest->as_register(), as_Address(from_addr));
998 break;
999 case T_BOOLEAN: {
1000 __ ldrb(dest->as_register(), as_Address(from_addr));
1001 break;
1002 }
1003
1004 case T_CHAR:
1005 __ ldrh(dest->as_register(), as_Address(from_addr));
1006 break;
1007 case T_SHORT:
1008 __ ldrsh(dest->as_register(), as_Address(from_addr));
1009 break;
1010
1011 default:
1012 ShouldNotReachHere();
1013 }
1014
1015 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
1016 if (UseCompressedOops && !wide) {
1017 __ decode_heap_oop(dest->as_register());
1018 }
1019 __ verify_oop(dest->as_register());
1020 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1021 if (UseCompressedClassPointers) {
1022 __ decode_klass_not_null(dest->as_register());
1023 }
1024 }
1025 }
1026
1027
1028 int LIR_Assembler::array_element_size(BasicType type) const {
1029 int elem_size = type2aelembytes(type);
1030 return exact_log2(elem_size);
1031 }
1032
1033
1034 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1035 switch (op->code()) {
1036 case lir_idiv:
1037 case lir_irem:
1038 arithmetic_idiv(op->code(),
1039 op->in_opr1(),
1040 op->in_opr2(),
1041 op->in_opr3(),
1042 op->result_opr(),
1043 op->info());
1044 break;
1045 case lir_fmad:
1046 __ fmaddd(op->result_opr()->as_double_reg(),
1047 op->in_opr1()->as_double_reg(),
1048 op->in_opr2()->as_double_reg(),
1049 op->in_opr3()->as_double_reg());
1050 break;
1051 case lir_fmaf:
1052 __ fmadds(op->result_opr()->as_float_reg(),
1053 op->in_opr1()->as_float_reg(),
1054 op->in_opr2()->as_float_reg(),
1055 op->in_opr3()->as_float_reg());
1056 break;
1057 default: ShouldNotReachHere(); break;
1058 }
1059 }
1060
1061 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1062 #ifdef ASSERT
1063 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1064 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1065 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1066 #endif
1067
1068 if (op->cond() == lir_cond_always) {
1069 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1070 __ b(*(op->label()));
1071 } else {
1072 Assembler::Condition acond;
1073 if (op->code() == lir_cond_float_branch) {
1074 bool is_unordered = (op->ublock() == op->block());
1075 // Assembler::EQ does not permit unordered branches, so we add
1076 // another branch here. Likewise, Assembler::NE does not permit
1077 // ordered branches.
1078 if (is_unordered && op->cond() == lir_cond_equal
1079 || !is_unordered && op->cond() == lir_cond_notEqual)
1080 __ br(Assembler::VS, *(op->ublock()->label()));
1081 switch(op->cond()) {
1082 case lir_cond_equal: acond = Assembler::EQ; break;
1083 case lir_cond_notEqual: acond = Assembler::NE; break;
1084 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1085 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1086 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1087 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1088 default: ShouldNotReachHere();
1089 acond = Assembler::EQ; // unreachable
1090 }
1091 } else {
1092 switch (op->cond()) {
1093 case lir_cond_equal: acond = Assembler::EQ; break;
1094 case lir_cond_notEqual: acond = Assembler::NE; break;
1095 case lir_cond_less: acond = Assembler::LT; break;
1096 case lir_cond_lessEqual: acond = Assembler::LE; break;
1097 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1098 case lir_cond_greater: acond = Assembler::GT; break;
1099 case lir_cond_belowEqual: acond = Assembler::LS; break;
1100 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1101 default: ShouldNotReachHere();
1102 acond = Assembler::EQ; // unreachable
1103 }
1104 }
1105 __ br(acond,*(op->label()));
1106 }
1107 }
1108
1109
1110
1111 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1112 LIR_Opr src = op->in_opr();
1113 LIR_Opr dest = op->result_opr();
1114
1115 switch (op->bytecode()) {
1116 case Bytecodes::_i2f:
1117 {
1118 __ scvtfws(dest->as_float_reg(), src->as_register());
1119 break;
1120 }
1121 case Bytecodes::_i2d:
1122 {
1123 __ scvtfwd(dest->as_double_reg(), src->as_register());
1124 break;
1125 }
1126 case Bytecodes::_l2d:
1127 {
1128 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1129 break;
1130 }
1131 case Bytecodes::_l2f:
1132 {
1133 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1134 break;
1135 }
1136 case Bytecodes::_f2d:
1137 {
1138 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1139 break;
1140 }
1141 case Bytecodes::_d2f:
1142 {
1143 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1144 break;
1145 }
1146 case Bytecodes::_i2c:
1147 {
1148 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1149 break;
1150 }
1151 case Bytecodes::_i2l:
1152 {
1153 __ sxtw(dest->as_register_lo(), src->as_register());
1154 break;
1155 }
1156 case Bytecodes::_i2s:
1157 {
1158 __ sxth(dest->as_register(), src->as_register());
1159 break;
1160 }
1161 case Bytecodes::_i2b:
1162 {
1163 __ sxtb(dest->as_register(), src->as_register());
1164 break;
1165 }
1166 case Bytecodes::_l2i:
1167 {
1168 _masm->block_comment("FIXME: This could be a no-op");
1169 __ uxtw(dest->as_register(), src->as_register_lo());
1170 break;
1171 }
1172 case Bytecodes::_d2l:
1173 {
1174 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1175 break;
1176 }
1177 case Bytecodes::_f2i:
1178 {
1179 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1180 break;
1181 }
1182 case Bytecodes::_f2l:
1183 {
1184 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1185 break;
1186 }
1187 case Bytecodes::_d2i:
1188 {
1189 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1190 break;
1191 }
1192 default: ShouldNotReachHere();
1193 }
1194 }
1195
1196 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1197 if (op->init_check()) {
1198 __ ldrb(rscratch1, Address(op->klass()->as_register(),
1199 InstanceKlass::init_state_offset()));
1200 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1201 add_debug_info_for_null_check_here(op->stub()->info());
1202 __ br(Assembler::NE, *op->stub()->entry());
1203 }
1204 __ allocate_object(op->obj()->as_register(),
1205 op->tmp1()->as_register(),
1206 op->tmp2()->as_register(),
1207 op->header_size(),
1208 op->object_size(),
1209 op->klass()->as_register(),
1210 *op->stub()->entry());
1211 __ bind(*op->stub()->continuation());
1212 }
1213
1214 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1215 Register len = op->len()->as_register();
1216 __ uxtw(len, len);
1217
1218 if (UseSlowPath || op->type() == T_VALUETYPE ||
1219 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1220 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1221 __ b(*op->stub()->entry());
1222 } else {
1223 Register tmp1 = op->tmp1()->as_register();
1224 Register tmp2 = op->tmp2()->as_register();
1225 Register tmp3 = op->tmp3()->as_register();
1226 if (len == tmp1) {
1227 tmp1 = tmp3;
1228 } else if (len == tmp2) {
1229 tmp2 = tmp3;
1230 } else if (len == tmp3) {
1231 // everything is ok
1232 } else {
1233 __ mov(tmp3, len);
1234 }
1235 __ allocate_array(op->obj()->as_register(),
1236 len,
1237 tmp1,
1238 tmp2,
1239 arrayOopDesc::header_size(op->type()),
1240 array_element_size(op->type()),
1241 op->klass()->as_register(),
1242 *op->stub()->entry());
1243 }
1244 __ bind(*op->stub()->continuation());
1245 }
1246
1247 void LIR_Assembler::type_profile_helper(Register mdo,
1248 ciMethodData *md, ciProfileData *data,
1249 Register recv, Label* update_done) {
1250 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1251 Label next_test;
1252 // See if the receiver is receiver[n].
1253 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1254 __ ldr(rscratch1, Address(rscratch2));
1255 __ cmp(recv, rscratch1);
1256 __ br(Assembler::NE, next_test);
1257 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1258 __ addptr(data_addr, DataLayout::counter_increment);
1259 __ b(*update_done);
1260 __ bind(next_test);
1261 }
1262
1263 // Didn't find receiver; find next empty slot and fill it in
1264 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1265 Label next_test;
1266 __ lea(rscratch2,
1267 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1268 Address recv_addr(rscratch2);
1269 __ ldr(rscratch1, recv_addr);
1270 __ cbnz(rscratch1, next_test);
1271 __ str(recv, recv_addr);
1272 __ mov(rscratch1, DataLayout::counter_increment);
1273 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1274 __ str(rscratch1, Address(rscratch2));
1275 __ b(*update_done);
1276 __ bind(next_test);
1277 }
1278 }
1279
1280 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1281 // we always need a stub for the failure case.
1282 CodeStub* stub = op->stub();
1283 Register obj = op->object()->as_register();
1284 Register k_RInfo = op->tmp1()->as_register();
1285 Register klass_RInfo = op->tmp2()->as_register();
1286 Register dst = op->result_opr()->as_register();
1287 ciKlass* k = op->klass();
1288 Register Rtmp1 = noreg;
1289
1290 // check if it needs to be profiled
1291 ciMethodData* md;
1292 ciProfileData* data;
1293
1294 const bool should_profile = op->should_profile();
1295
1296 if (should_profile) {
1297 ciMethod* method = op->profiled_method();
1298 assert(method != NULL, "Should have method");
1299 int bci = op->profiled_bci();
1300 md = method->method_data_or_null();
1301 assert(md != NULL, "Sanity");
1302 data = md->bci_to_data(bci);
1303 assert(data != NULL, "need data for type check");
1304 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1305 }
1306 Label profile_cast_success, profile_cast_failure;
1307 Label *success_target = should_profile ? &profile_cast_success : success;
1308 Label *failure_target = should_profile ? &profile_cast_failure : failure;
1309
1310 if (obj == k_RInfo) {
1311 k_RInfo = dst;
1312 } else if (obj == klass_RInfo) {
1313 klass_RInfo = dst;
1314 }
1315 if (k->is_loaded() && !UseCompressedClassPointers) {
1316 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1317 } else {
1318 Rtmp1 = op->tmp3()->as_register();
1319 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1320 }
1321
1322 assert_different_registers(obj, k_RInfo, klass_RInfo);
1323
1324 if (should_profile) {
1325 Label not_null;
1326 __ cbnz(obj, not_null);
1327 // Object is null; update MDO and exit
1328 Register mdo = klass_RInfo;
1329 __ mov_metadata(mdo, md->constant_encoding());
1330 Address data_addr
1331 = __ form_address(rscratch2, mdo,
1332 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1333 0);
1334 __ ldrb(rscratch1, data_addr);
1335 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1336 __ strb(rscratch1, data_addr);
1337 __ b(*obj_is_null);
1338 __ bind(not_null);
1339 } else {
1340 __ cbz(obj, *obj_is_null);
1341 }
1342
1343 if (!k->is_loaded()) {
1344 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1345 } else {
1346 __ mov_metadata(k_RInfo, k->constant_encoding());
1347 }
1348 __ verify_oop(obj);
1349
1350 if (op->fast_check()) {
1351 // get object class
1352 // not a safepoint as obj null check happens earlier
1353 __ load_klass(rscratch1, obj);
1354 __ cmp( rscratch1, k_RInfo);
1355
1356 __ br(Assembler::NE, *failure_target);
1357 // successful cast, fall through to profile or jump
1358 } else {
1359 // get object class
1360 // not a safepoint as obj null check happens earlier
1361 __ load_klass(klass_RInfo, obj);
1362 if (k->is_loaded()) {
1363 // See if we get an immediate positive hit
1364 __ ldr(rscratch1, Address(klass_RInfo, long(k->super_check_offset())));
1365 __ cmp(k_RInfo, rscratch1);
1366 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1367 __ br(Assembler::NE, *failure_target);
1368 // successful cast, fall through to profile or jump
1369 } else {
1370 // See if we get an immediate positive hit
1371 __ br(Assembler::EQ, *success_target);
1372 // check for self
1373 __ cmp(klass_RInfo, k_RInfo);
1374 __ br(Assembler::EQ, *success_target);
1375
1376 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1377 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1378 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1379 // result is a boolean
1380 __ cbzw(klass_RInfo, *failure_target);
1381 // successful cast, fall through to profile or jump
1382 }
1383 } else {
1384 // perform the fast part of the checking logic
1385 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1386 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1387 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1388 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1389 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1390 // result is a boolean
1391 __ cbz(k_RInfo, *failure_target);
1392 // successful cast, fall through to profile or jump
1393 }
1394 }
1395 if (should_profile) {
1396 Register mdo = klass_RInfo, recv = k_RInfo;
1397 __ bind(profile_cast_success);
1398 __ mov_metadata(mdo, md->constant_encoding());
1399 __ load_klass(recv, obj);
1400 Label update_done;
1401 type_profile_helper(mdo, md, data, recv, success);
1402 __ b(*success);
1403
1404 __ bind(profile_cast_failure);
1405 __ mov_metadata(mdo, md->constant_encoding());
1406 Address counter_addr
1407 = __ form_address(rscratch2, mdo,
1408 md->byte_offset_of_slot(data, CounterData::count_offset()),
1409 0);
1410 __ ldr(rscratch1, counter_addr);
1411 __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1412 __ str(rscratch1, counter_addr);
1413 __ b(*failure);
1414 }
1415 __ b(*success);
1416 }
1417
1418
1419 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1420 const bool should_profile = op->should_profile();
1421
1422 LIR_Code code = op->code();
1423 if (code == lir_store_check) {
1424 Register value = op->object()->as_register();
1425 Register array = op->array()->as_register();
1426 Register k_RInfo = op->tmp1()->as_register();
1427 Register klass_RInfo = op->tmp2()->as_register();
1428 Register Rtmp1 = op->tmp3()->as_register();
1429
1430 CodeStub* stub = op->stub();
1431
1432 // check if it needs to be profiled
1433 ciMethodData* md;
1434 ciProfileData* data;
1435
1436 if (should_profile) {
1437 ciMethod* method = op->profiled_method();
1438 assert(method != NULL, "Should have method");
1439 int bci = op->profiled_bci();
1440 md = method->method_data_or_null();
1441 assert(md != NULL, "Sanity");
1442 data = md->bci_to_data(bci);
1443 assert(data != NULL, "need data for type check");
1444 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1445 }
1446 Label profile_cast_success, profile_cast_failure, done;
1447 Label *success_target = should_profile ? &profile_cast_success : &done;
1448 Label *failure_target = should_profile ? &profile_cast_failure : stub->entry();
1449
1450 if (should_profile) {
1451 Label not_null;
1452 __ cbnz(value, not_null);
1453 // Object is null; update MDO and exit
1454 Register mdo = klass_RInfo;
1455 __ mov_metadata(mdo, md->constant_encoding());
1456 Address data_addr
1457 = __ form_address(rscratch2, mdo,
1458 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1459 0);
1460 __ ldrb(rscratch1, data_addr);
1461 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1462 __ strb(rscratch1, data_addr);
1463 __ b(done);
1464 __ bind(not_null);
1465 } else {
1466 __ cbz(value, done);
1467 }
1468
1469 add_debug_info_for_null_check_here(op->info_for_exception());
1470 __ load_klass(k_RInfo, array);
1471 __ load_klass(klass_RInfo, value);
1472
1473 // get instance klass (it's already uncompressed)
1474 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1475 // perform the fast part of the checking logic
1476 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1477 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1478 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1479 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1480 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1481 // result is a boolean
1482 __ cbzw(k_RInfo, *failure_target);
1483 // fall through to the success case
1484
1485 if (should_profile) {
1486 Register mdo = klass_RInfo, recv = k_RInfo;
1487 __ bind(profile_cast_success);
1488 __ mov_metadata(mdo, md->constant_encoding());
1489 __ load_klass(recv, value);
1490 Label update_done;
1491 type_profile_helper(mdo, md, data, recv, &done);
1492 __ b(done);
1493
1494 __ bind(profile_cast_failure);
1495 __ mov_metadata(mdo, md->constant_encoding());
1496 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1497 __ lea(rscratch2, counter_addr);
1498 __ ldr(rscratch1, Address(rscratch2));
1499 __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1500 __ str(rscratch1, Address(rscratch2));
1501 __ b(*stub->entry());
1502 }
1503
1504 __ bind(done);
1505 } else if (code == lir_checkcast) {
1506 Register obj = op->object()->as_register();
1507 Register dst = op->result_opr()->as_register();
1508 Label success;
1509 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1510 __ bind(success);
1511 if (dst != obj) {
1512 __ mov(dst, obj);
1513 }
1514 } else if (code == lir_instanceof) {
1515 Register obj = op->object()->as_register();
1516 Register dst = op->result_opr()->as_register();
1517 Label success, failure, done;
1518 emit_typecheck_helper(op, &success, &failure, &failure);
1519 __ bind(failure);
1520 __ mov(dst, zr);
1521 __ b(done);
1522 __ bind(success);
1523 __ mov(dst, 1);
1524 __ bind(done);
1525 } else {
1526 ShouldNotReachHere();
1527 }
1528 }
1529
1530 void LIR_Assembler::emit_opFlattenedStoreCheck(LIR_OpFlattenedStoreCheck* op) {
1531 Klass* k = (Klass*)(op->element_klass()->constant_encoding());
1532 assert(k->is_klass(), "must be a loaded klass");
1533 add_debug_info_for_null_check_here(op->info_for_exception());
1534
1535 __ ldr(op->tmp1()->as_register(), Address(op->object()->as_register(), oopDesc::klass_offset_in_bytes()));
1536 __ cmp(op->tmp1()->as_register(), op->tmp2()->as_register());
1537 __ br(Assembler::NE, *op->stub()->entry());
1538 __ bind(*op->stub()->continuation());
1539 }
1540
1541 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1542 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1543 __ cset(rscratch1, Assembler::NE);
1544 __ membar(__ AnyAny);
1545 }
1546
1547 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1548 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1549 __ cset(rscratch1, Assembler::NE);
1550 __ membar(__ AnyAny);
1551 }
1552
1553
1554 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1555 assert(VM_Version::supports_cx8(), "wrong machine");
1556 Register addr;
1557 if (op->addr()->is_register()) {
1558 addr = as_reg(op->addr());
1559 } else {
1560 assert(op->addr()->is_address(), "what else?");
1561 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1562 assert(addr_ptr->disp() == 0, "need 0 disp");
1563 assert(addr_ptr->index() == LIR_OprDesc::illegalOpr(), "need 0 index");
1564 addr = as_reg(addr_ptr->base());
1565 }
1566 Register newval = as_reg(op->new_value());
1567 Register cmpval = as_reg(op->cmp_value());
1568
1569 if (op->code() == lir_cas_obj) {
1570 if (UseCompressedOops) {
1571 Register t1 = op->tmp1()->as_register();
1572 assert(op->tmp1()->is_valid(), "must be");
1573 __ encode_heap_oop(t1, cmpval);
1574 cmpval = t1;
1575 __ encode_heap_oop(rscratch2, newval);
1576 newval = rscratch2;
1577 casw(addr, newval, cmpval);
1578 } else {
1579 casl(addr, newval, cmpval);
1580 }
1581 } else if (op->code() == lir_cas_int) {
1582 casw(addr, newval, cmpval);
1583 } else {
1584 casl(addr, newval, cmpval);
1585 }
1586 }
1587
1588
1589 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1590
1591 Assembler::Condition acond, ncond;
1592 switch (condition) {
1593 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1594 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1595 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1596 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1597 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1598 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1599 case lir_cond_belowEqual:
1600 case lir_cond_aboveEqual:
1601 default: ShouldNotReachHere();
1602 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1603 }
1604
1605 assert(result->is_single_cpu() || result->is_double_cpu(),
1606 "expect single register for result");
1607 if (opr1->is_constant() && opr2->is_constant()
1608 && opr1->type() == T_INT && opr2->type() == T_INT) {
1609 jint val1 = opr1->as_jint();
1610 jint val2 = opr2->as_jint();
1611 if (val1 == 0 && val2 == 1) {
1612 __ cset(result->as_register(), ncond);
1613 return;
1614 } else if (val1 == 1 && val2 == 0) {
1615 __ cset(result->as_register(), acond);
1616 return;
1617 }
1618 }
1619
1620 if (opr1->is_constant() && opr2->is_constant()
1621 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1622 jlong val1 = opr1->as_jlong();
1623 jlong val2 = opr2->as_jlong();
1624 if (val1 == 0 && val2 == 1) {
1625 __ cset(result->as_register_lo(), ncond);
1626 return;
1627 } else if (val1 == 1 && val2 == 0) {
1628 __ cset(result->as_register_lo(), acond);
1629 return;
1630 }
1631 }
1632
1633 if (opr1->is_stack()) {
1634 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1635 opr1 = FrameMap::rscratch1_opr;
1636 } else if (opr1->is_constant()) {
1637 LIR_Opr tmp
1638 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1639 const2reg(opr1, tmp, lir_patch_none, NULL);
1640 opr1 = tmp;
1641 }
1642
1643 if (opr2->is_stack()) {
1644 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1645 opr2 = FrameMap::rscratch2_opr;
1646 } else if (opr2->is_constant()) {
1647 LIR_Opr tmp
1648 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1649 const2reg(opr2, tmp, lir_patch_none, NULL);
1650 opr2 = tmp;
1651 }
1652
1653 if (result->type() == T_LONG)
1654 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1655 else
1656 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1657 }
1658
1659 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1660 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1661
1662 if (left->is_single_cpu()) {
1663 Register lreg = left->as_register();
1664 Register dreg = as_reg(dest);
1665
1666 if (right->is_single_cpu()) {
1667 // cpu register - cpu register
1668
1669 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1670 "should be");
1671 Register rreg = right->as_register();
1672 switch (code) {
1673 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1674 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1675 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1676 default: ShouldNotReachHere();
1677 }
1678
1679 } else if (right->is_double_cpu()) {
1680 Register rreg = right->as_register_lo();
1681 // single_cpu + double_cpu: can happen with obj+long
1682 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1683 switch (code) {
1684 case lir_add: __ add(dreg, lreg, rreg); break;
1685 case lir_sub: __ sub(dreg, lreg, rreg); break;
1686 default: ShouldNotReachHere();
1687 }
1688 } else if (right->is_constant()) {
1689 // cpu register - constant
1690 jlong c;
1691
1692 // FIXME. This is fugly: we really need to factor all this logic.
1693 switch(right->type()) {
1694 case T_LONG:
1695 c = right->as_constant_ptr()->as_jlong();
1696 break;
1697 case T_INT:
1698 case T_ADDRESS:
1699 c = right->as_constant_ptr()->as_jint();
1700 break;
1701 default:
1702 ShouldNotReachHere();
1703 c = 0; // unreachable
1704 break;
1705 }
1706
1707 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1708 if (c == 0 && dreg == lreg) {
1709 COMMENT("effective nop elided");
1710 return;
1711 }
1712 switch(left->type()) {
1713 case T_INT:
1714 switch (code) {
1715 case lir_add: __ addw(dreg, lreg, c); break;
1716 case lir_sub: __ subw(dreg, lreg, c); break;
1717 default: ShouldNotReachHere();
1718 }
1719 break;
1720 case T_OBJECT:
1721 case T_ADDRESS:
1722 switch (code) {
1723 case lir_add: __ add(dreg, lreg, c); break;
1724 case lir_sub: __ sub(dreg, lreg, c); break;
1725 default: ShouldNotReachHere();
1726 }
1727 break;
1728 default:
1729 ShouldNotReachHere();
1730 }
1731 } else {
1732 ShouldNotReachHere();
1733 }
1734
1735 } else if (left->is_double_cpu()) {
1736 Register lreg_lo = left->as_register_lo();
1737
1738 if (right->is_double_cpu()) {
1739 // cpu register - cpu register
1740 Register rreg_lo = right->as_register_lo();
1741 switch (code) {
1742 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1743 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1744 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1745 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1746 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1747 default:
1748 ShouldNotReachHere();
1749 }
1750
1751 } else if (right->is_constant()) {
1752 jlong c = right->as_constant_ptr()->as_jlong();
1753 Register dreg = as_reg(dest);
1754 switch (code) {
1755 case lir_add:
1756 case lir_sub:
1757 if (c == 0 && dreg == lreg_lo) {
1758 COMMENT("effective nop elided");
1759 return;
1760 }
1761 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1762 break;
1763 case lir_div:
1764 assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1765 if (c == 1) {
1766 // move lreg_lo to dreg if divisor is 1
1767 __ mov(dreg, lreg_lo);
1768 } else {
1769 unsigned int shift = exact_log2_long(c);
1770 // use rscratch1 as intermediate result register
1771 __ asr(rscratch1, lreg_lo, 63);
1772 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1773 __ asr(dreg, rscratch1, shift);
1774 }
1775 break;
1776 case lir_rem:
1777 assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1778 if (c == 1) {
1779 // move 0 to dreg if divisor is 1
1780 __ mov(dreg, zr);
1781 } else {
1782 // use rscratch1 as intermediate result register
1783 __ negs(rscratch1, lreg_lo);
1784 __ andr(dreg, lreg_lo, c - 1);
1785 __ andr(rscratch1, rscratch1, c - 1);
1786 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1787 }
1788 break;
1789 default:
1790 ShouldNotReachHere();
1791 }
1792 } else {
1793 ShouldNotReachHere();
1794 }
1795 } else if (left->is_single_fpu()) {
1796 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1797 switch (code) {
1798 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1799 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1800 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1801 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1802 default:
1803 ShouldNotReachHere();
1804 }
1805 } else if (left->is_double_fpu()) {
1806 if (right->is_double_fpu()) {
1807 // cpu register - cpu register
1808 switch (code) {
1809 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1810 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1811 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1812 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1813 default:
1814 ShouldNotReachHere();
1815 }
1816 } else {
1817 if (right->is_constant()) {
1818 ShouldNotReachHere();
1819 }
1820 ShouldNotReachHere();
1821 }
1822 } else if (left->is_single_stack() || left->is_address()) {
1823 assert(left == dest, "left and dest must be equal");
1824 ShouldNotReachHere();
1825 } else {
1826 ShouldNotReachHere();
1827 }
1828 }
1829
1830 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1831
1832
1833 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1834 switch(code) {
1835 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1836 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1837 default : ShouldNotReachHere();
1838 }
1839 }
1840
1841 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1842
1843 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1844 Register Rleft = left->is_single_cpu() ? left->as_register() :
1845 left->as_register_lo();
1846 if (dst->is_single_cpu()) {
1847 Register Rdst = dst->as_register();
1848 if (right->is_constant()) {
1849 switch (code) {
1850 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1851 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1852 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1853 default: ShouldNotReachHere(); break;
1854 }
1855 } else {
1856 Register Rright = right->is_single_cpu() ? right->as_register() :
1857 right->as_register_lo();
1858 switch (code) {
1859 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1860 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1861 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1862 default: ShouldNotReachHere(); break;
1863 }
1864 }
1865 } else {
1866 Register Rdst = dst->as_register_lo();
1867 if (right->is_constant()) {
1868 switch (code) {
1869 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1870 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1871 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1872 default: ShouldNotReachHere(); break;
1873 }
1874 } else {
1875 Register Rright = right->is_single_cpu() ? right->as_register() :
1876 right->as_register_lo();
1877 switch (code) {
1878 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1879 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1880 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1881 default: ShouldNotReachHere(); break;
1882 }
1883 }
1884 }
1885 }
1886
1887
1888
1889 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1890
1891 // opcode check
1892 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1893 bool is_irem = (code == lir_irem);
1894
1895 // operand check
1896 assert(left->is_single_cpu(), "left must be register");
1897 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1898 assert(result->is_single_cpu(), "result must be register");
1899 Register lreg = left->as_register();
1900 Register dreg = result->as_register();
1901
1902 // power-of-2 constant check and codegen
1903 if (right->is_constant()) {
1904 int c = right->as_constant_ptr()->as_jint();
1905 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1906 if (is_irem) {
1907 if (c == 1) {
1908 // move 0 to dreg if divisor is 1
1909 __ movw(dreg, zr);
1910 } else {
1911 // use rscratch1 as intermediate result register
1912 __ negsw(rscratch1, lreg);
1913 __ andw(dreg, lreg, c - 1);
1914 __ andw(rscratch1, rscratch1, c - 1);
1915 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1916 }
1917 } else {
1918 if (c == 1) {
1919 // move lreg to dreg if divisor is 1
1920 __ movw(dreg, lreg);
1921 } else {
1922 unsigned int shift = exact_log2(c);
1923 // use rscratch1 as intermediate result register
1924 __ asrw(rscratch1, lreg, 31);
1925 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1926 __ asrw(dreg, rscratch1, shift);
1927 }
1928 }
1929 } else {
1930 Register rreg = right->as_register();
1931 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1932 }
1933 }
1934
1935
1936 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1937 if (opr1->is_constant() && opr2->is_single_cpu()) {
1938 // tableswitch
1939 Register reg = as_reg(opr2);
1940 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1941 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1942 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1943 Register reg1 = as_reg(opr1);
1944 if (opr2->is_single_cpu()) {
1945 // cpu register - cpu register
1946 Register reg2 = opr2->as_register();
1947 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY || opr1->type() == T_VALUETYPE) {
1948 __ cmpoop(reg1, reg2);
1949 } else {
1950 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_VALUETYPE, "cmp int, oop?");
1951 __ cmpw(reg1, reg2);
1952 }
1953 return;
1954 }
1955 if (opr2->is_double_cpu()) {
1956 // cpu register - cpu register
1957 Register reg2 = opr2->as_register_lo();
1958 __ cmp(reg1, reg2);
1959 return;
1960 }
1961
1962 if (opr2->is_constant()) {
1963 bool is_32bit = false; // width of register operand
1964 jlong imm;
1965
1966 switch(opr2->type()) {
1967 case T_INT:
1968 imm = opr2->as_constant_ptr()->as_jint();
1969 is_32bit = true;
1970 break;
1971 case T_LONG:
1972 imm = opr2->as_constant_ptr()->as_jlong();
1973 break;
1974 case T_ADDRESS:
1975 imm = opr2->as_constant_ptr()->as_jint();
1976 break;
1977 case T_VALUETYPE:
1978 case T_OBJECT:
1979 case T_ARRAY:
1980 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1981 __ cmpoop(reg1, rscratch1);
1982 return;
1983 default:
1984 ShouldNotReachHere();
1985 imm = 0; // unreachable
1986 break;
1987 }
1988
1989 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1990 if (is_32bit)
1991 __ cmpw(reg1, imm);
1992 else
1993 __ subs(zr, reg1, imm);
1994 return;
1995 } else {
1996 __ mov(rscratch1, imm);
1997 if (is_32bit)
1998 __ cmpw(reg1, rscratch1);
1999 else
2000 __ cmp(reg1, rscratch1);
2001 return;
2002 }
2003 } else
2004 ShouldNotReachHere();
2005 } else if (opr1->is_single_fpu()) {
2006 FloatRegister reg1 = opr1->as_float_reg();
2007 assert(opr2->is_single_fpu(), "expect single float register");
2008 FloatRegister reg2 = opr2->as_float_reg();
2009 __ fcmps(reg1, reg2);
2010 } else if (opr1->is_double_fpu()) {
2011 FloatRegister reg1 = opr1->as_double_reg();
2012 assert(opr2->is_double_fpu(), "expect double float register");
2013 FloatRegister reg2 = opr2->as_double_reg();
2014 __ fcmpd(reg1, reg2);
2015 } else {
2016 ShouldNotReachHere();
2017 }
2018 }
2019
2020 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2021 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2022 bool is_unordered_less = (code == lir_ucmp_fd2i);
2023 if (left->is_single_fpu()) {
2024 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2025 } else if (left->is_double_fpu()) {
2026 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2027 } else {
2028 ShouldNotReachHere();
2029 }
2030 } else if (code == lir_cmp_l2i) {
2031 Label done;
2032 __ cmp(left->as_register_lo(), right->as_register_lo());
2033 __ mov(dst->as_register(), (u_int64_t)-1L);
2034 __ br(Assembler::LT, done);
2035 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2036 __ bind(done);
2037 } else {
2038 ShouldNotReachHere();
2039 }
2040 }
2041
2042
2043 void LIR_Assembler::align_call(LIR_Code code) { }
2044
2045
2046 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2047 address call = __ trampoline_call(Address(op->addr(), rtype));
2048 if (call == NULL) {
2049 bailout("trampoline stub overflow");
2050 return;
2051 }
2052 add_call_info(code_offset(), op->info());
2053 }
2054
2055
2056 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2057 address call = __ ic_call(op->addr());
2058 if (call == NULL) {
2059 bailout("trampoline stub overflow");
2060 return;
2061 }
2062 add_call_info(code_offset(), op->info());
2063 }
2064
2065
2066 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2067 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2068 ShouldNotReachHere();
2069 }
2070
2071
2072 void LIR_Assembler::emit_static_call_stub() {
2073 address call_pc = __ pc();
2074 address stub = __ start_a_stub(call_stub_size());
2075 if (stub == NULL) {
2076 bailout("static call stub overflow");
2077 return;
2078 }
2079
2080 int start = __ offset();
2081
2082 __ relocate(static_stub_Relocation::spec(call_pc));
2083 __ mov_metadata(rmethod, (Metadata*)NULL);
2084 __ movptr(rscratch1, 0);
2085 __ br(rscratch1);
2086
2087 assert(__ offset() - start <= call_stub_size(), "stub too big");
2088 __ end_a_stub();
2089 }
2090
2091
2092 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2093 assert(exceptionOop->as_register() == r0, "must match");
2094 assert(exceptionPC->as_register() == r3, "must match");
2095
2096 // exception object is not added to oop map by LinearScan
2097 // (LinearScan assumes that no oops are in fixed registers)
2098 info->add_register_oop(exceptionOop);
2099 Runtime1::StubID unwind_id;
2100
2101 // get current pc information
2102 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2103 int pc_for_athrow_offset = __ offset();
2104 InternalAddress pc_for_athrow(__ pc());
2105 __ adr(exceptionPC->as_register(), pc_for_athrow);
2106 add_call_info(pc_for_athrow_offset, info); // for exception handler
2107
2108 __ verify_not_null_oop(r0);
2109 // search an exception handler (r0: exception oop, r3: throwing pc)
2110 if (compilation()->has_fpu_code()) {
2111 unwind_id = Runtime1::handle_exception_id;
2112 } else {
2113 unwind_id = Runtime1::handle_exception_nofpu_id;
2114 }
2115 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2116
2117 // FIXME: enough room for two byte trap ????
2118 __ nop();
2119 }
2120
2121
2122 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2123 assert(exceptionOop->as_register() == r0, "must match");
2124
2125 __ b(_unwind_handler_entry);
2126 }
2127
2128
2129 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2130 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2131 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2132
2133 switch (left->type()) {
2134 case T_INT: {
2135 switch (code) {
2136 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2137 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2138 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2139 default:
2140 ShouldNotReachHere();
2141 break;
2142 }
2143 break;
2144 case T_LONG:
2145 case T_VALUETYPE:
2146 case T_ADDRESS:
2147 case T_OBJECT:
2148 switch (code) {
2149 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2150 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2151 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2152 default:
2153 ShouldNotReachHere();
2154 break;
2155 }
2156 break;
2157 default:
2158 ShouldNotReachHere();
2159 break;
2160 }
2161 }
2162 }
2163
2164
2165 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2166 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2167 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2168
2169 switch (left->type()) {
2170 case T_INT: {
2171 switch (code) {
2172 case lir_shl: __ lslw (dreg, lreg, count); break;
2173 case lir_shr: __ asrw (dreg, lreg, count); break;
2174 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2175 default:
2176 ShouldNotReachHere();
2177 break;
2178 }
2179 break;
2180 case T_LONG:
2181 case T_ADDRESS:
2182 case T_VALUETYPE:
2183 case T_OBJECT:
2184 switch (code) {
2185 case lir_shl: __ lsl (dreg, lreg, count); break;
2186 case lir_shr: __ asr (dreg, lreg, count); break;
2187 case lir_ushr: __ lsr (dreg, lreg, count); break;
2188 default:
2189 ShouldNotReachHere();
2190 break;
2191 }
2192 break;
2193 default:
2194 ShouldNotReachHere();
2195 break;
2196 }
2197 }
2198 }
2199
2200
2201 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2202 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2203 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2204 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2205 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2206 }
2207
2208
2209 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2210 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2211 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2212 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2213 __ mov (rscratch1, c);
2214 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2215 }
2216
2217
2218 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2219 ShouldNotReachHere();
2220 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2221 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2222 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2223 __ lea(rscratch1, __ constant_oop_address(o));
2224 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2225 }
2226
2227
2228 // This code replaces a call to arraycopy; no exception may
2229 // be thrown in this code, they must be thrown in the System.arraycopy
2230 // activation frame; we could save some checks if this would not be the case
2231 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2232 ciArrayKlass* default_type = op->expected_type();
2233 Register src = op->src()->as_register();
2234 Register dst = op->dst()->as_register();
2235 Register src_pos = op->src_pos()->as_register();
2236 Register dst_pos = op->dst_pos()->as_register();
2237 Register length = op->length()->as_register();
2238 Register tmp = op->tmp()->as_register();
2239
2240 __ resolve(ACCESS_READ, src);
2241 __ resolve(ACCESS_WRITE, dst);
2242
2243 CodeStub* stub = op->stub();
2244 int flags = op->flags();
2245 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2246 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2247
2248 // if we don't know anything, just go through the generic arraycopy
2249 if (default_type == NULL // || basic_type == T_OBJECT
2250 ) {
2251 Label done;
2252 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2253
2254 // Save the arguments in case the generic arraycopy fails and we
2255 // have to fall back to the JNI stub
2256 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2257 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2258 __ str(src, Address(sp, 4*BytesPerWord));
2259
2260 address copyfunc_addr = StubRoutines::generic_arraycopy();
2261 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2262
2263 // The arguments are in java calling convention so we shift them
2264 // to C convention
2265 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2266 __ mov(c_rarg0, j_rarg0);
2267 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2268 __ mov(c_rarg1, j_rarg1);
2269 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2270 __ mov(c_rarg2, j_rarg2);
2271 assert_different_registers(c_rarg3, j_rarg4);
2272 __ mov(c_rarg3, j_rarg3);
2273 __ mov(c_rarg4, j_rarg4);
2274 #ifndef PRODUCT
2275 if (PrintC1Statistics) {
2276 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2277 }
2278 #endif
2279 __ far_call(RuntimeAddress(copyfunc_addr));
2280
2281 __ cbz(r0, *stub->continuation());
2282
2283 // Reload values from the stack so they are where the stub
2284 // expects them.
2285 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2286 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2287 __ ldr(src, Address(sp, 4*BytesPerWord));
2288
2289 // r0 is -1^K where K == partial copied count
2290 __ eonw(rscratch1, r0, 0);
2291 // adjust length down and src/end pos up by partial copied count
2292 __ subw(length, length, rscratch1);
2293 __ addw(src_pos, src_pos, rscratch1);
2294 __ addw(dst_pos, dst_pos, rscratch1);
2295 __ b(*stub->entry());
2296
2297 __ bind(*stub->continuation());
2298 return;
2299 }
2300
2301 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2302
2303 int elem_size = type2aelembytes(basic_type);
2304 int shift_amount;
2305 int scale = exact_log2(elem_size);
2306
2307 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2308 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2309 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2310 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2311
2312 // test for NULL
2313 if (flags & LIR_OpArrayCopy::src_null_check) {
2314 __ cbz(src, *stub->entry());
2315 }
2316 if (flags & LIR_OpArrayCopy::dst_null_check) {
2317 __ cbz(dst, *stub->entry());
2318 }
2319
2320 // If the compiler was not able to prove that exact type of the source or the destination
2321 // of the arraycopy is an array type, check at runtime if the source or the destination is
2322 // an instance type.
2323 if (flags & LIR_OpArrayCopy::type_check) {
2324 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2325 __ load_klass(tmp, dst);
2326 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2327 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2328 __ br(Assembler::GE, *stub->entry());
2329 }
2330
2331 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2332 __ load_klass(tmp, src);
2333 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2334 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2335 __ br(Assembler::GE, *stub->entry());
2336 }
2337 }
2338
2339 // check if negative
2340 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2341 __ cmpw(src_pos, 0);
2342 __ br(Assembler::LT, *stub->entry());
2343 }
2344 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2345 __ cmpw(dst_pos, 0);
2346 __ br(Assembler::LT, *stub->entry());
2347 }
2348
2349 if (flags & LIR_OpArrayCopy::length_positive_check) {
2350 __ cmpw(length, 0);
2351 __ br(Assembler::LT, *stub->entry());
2352 }
2353
2354 if (flags & LIR_OpArrayCopy::src_range_check) {
2355 __ addw(tmp, src_pos, length);
2356 __ ldrw(rscratch1, src_length_addr);
2357 __ cmpw(tmp, rscratch1);
2358 __ br(Assembler::HI, *stub->entry());
2359 }
2360 if (flags & LIR_OpArrayCopy::dst_range_check) {
2361 __ addw(tmp, dst_pos, length);
2362 __ ldrw(rscratch1, dst_length_addr);
2363 __ cmpw(tmp, rscratch1);
2364 __ br(Assembler::HI, *stub->entry());
2365 }
2366
2367 if (flags & LIR_OpArrayCopy::type_check) {
2368 // We don't know the array types are compatible
2369 if (basic_type != T_OBJECT) {
2370 // Simple test for basic type arrays
2371 if (UseCompressedClassPointers) {
2372 __ ldrw(tmp, src_klass_addr);
2373 __ ldrw(rscratch1, dst_klass_addr);
2374 __ cmpw(tmp, rscratch1);
2375 } else {
2376 __ ldr(tmp, src_klass_addr);
2377 __ ldr(rscratch1, dst_klass_addr);
2378 __ cmp(tmp, rscratch1);
2379 }
2380 __ br(Assembler::NE, *stub->entry());
2381 } else {
2382 // For object arrays, if src is a sub class of dst then we can
2383 // safely do the copy.
2384 Label cont, slow;
2385
2386 #define PUSH(r1, r2) \
2387 stp(r1, r2, __ pre(sp, -2 * wordSize));
2388
2389 #define POP(r1, r2) \
2390 ldp(r1, r2, __ post(sp, 2 * wordSize));
2391
2392 __ PUSH(src, dst);
2393
2394 __ load_klass(src, src);
2395 __ load_klass(dst, dst);
2396
2397 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
2398
2399 __ PUSH(src, dst);
2400 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
2401 __ POP(src, dst);
2402
2403 __ cbnz(src, cont);
2404
2405 __ bind(slow);
2406 __ POP(src, dst);
2407
2408 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2409 if (copyfunc_addr != NULL) { // use stub if available
2410 // src is not a sub class of dst so we have to do a
2411 // per-element check.
2412
2413 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2414 if ((flags & mask) != mask) {
2415 // Check that at least both of them object arrays.
2416 assert(flags & mask, "one of the two should be known to be an object array");
2417
2418 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2419 __ load_klass(tmp, src);
2420 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2421 __ load_klass(tmp, dst);
2422 }
2423 int lh_offset = in_bytes(Klass::layout_helper_offset());
2424 Address klass_lh_addr(tmp, lh_offset);
2425 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2426 __ ldrw(rscratch1, klass_lh_addr);
2427 __ mov(rscratch2, objArray_lh);
2428 __ eorw(rscratch1, rscratch1, rscratch2);
2429 __ cbnzw(rscratch1, *stub->entry());
2430 }
2431
2432 // Spill because stubs can use any register they like and it's
2433 // easier to restore just those that we care about.
2434 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2435 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2436 __ str(src, Address(sp, 4*BytesPerWord));
2437
2438 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2439 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2440 assert_different_registers(c_rarg0, dst, dst_pos, length);
2441 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2442 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2443 assert_different_registers(c_rarg1, dst, length);
2444 __ uxtw(c_rarg2, length);
2445 assert_different_registers(c_rarg2, dst);
2446
2447 __ load_klass(c_rarg4, dst);
2448 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2449 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2450 __ far_call(RuntimeAddress(copyfunc_addr));
2451
2452 #ifndef PRODUCT
2453 if (PrintC1Statistics) {
2454 Label failed;
2455 __ cbnz(r0, failed);
2456 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2457 __ bind(failed);
2458 }
2459 #endif
2460
2461 __ cbz(r0, *stub->continuation());
2462
2463 #ifndef PRODUCT
2464 if (PrintC1Statistics) {
2465 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2466 }
2467 #endif
2468 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2469
2470 // Restore previously spilled arguments
2471 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2472 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2473 __ ldr(src, Address(sp, 4*BytesPerWord));
2474
2475 // return value is -1^K where K is partial copied count
2476 __ eonw(rscratch1, r0, zr);
2477 // adjust length down and src/end pos up by partial copied count
2478 __ subw(length, length, rscratch1);
2479 __ addw(src_pos, src_pos, rscratch1);
2480 __ addw(dst_pos, dst_pos, rscratch1);
2481 }
2482
2483 __ b(*stub->entry());
2484
2485 __ bind(cont);
2486 __ POP(src, dst);
2487 }
2488 }
2489
2490 #ifdef ASSERT
2491 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2492 // Sanity check the known type with the incoming class. For the
2493 // primitive case the types must match exactly with src.klass and
2494 // dst.klass each exactly matching the default type. For the
2495 // object array case, if no type check is needed then either the
2496 // dst type is exactly the expected type and the src type is a
2497 // subtype which we can't check or src is the same array as dst
2498 // but not necessarily exactly of type default_type.
2499 Label known_ok, halt;
2500 __ mov_metadata(tmp, default_type->constant_encoding());
2501 if (UseCompressedClassPointers) {
2502 __ encode_klass_not_null(tmp);
2503 }
2504
2505 if (basic_type != T_OBJECT) {
2506
2507 if (UseCompressedClassPointers) {
2508 __ ldrw(rscratch1, dst_klass_addr);
2509 __ cmpw(tmp, rscratch1);
2510 } else {
2511 __ ldr(rscratch1, dst_klass_addr);
2512 __ cmp(tmp, rscratch1);
2513 }
2514 __ br(Assembler::NE, halt);
2515 if (UseCompressedClassPointers) {
2516 __ ldrw(rscratch1, src_klass_addr);
2517 __ cmpw(tmp, rscratch1);
2518 } else {
2519 __ ldr(rscratch1, src_klass_addr);
2520 __ cmp(tmp, rscratch1);
2521 }
2522 __ br(Assembler::EQ, known_ok);
2523 } else {
2524 if (UseCompressedClassPointers) {
2525 __ ldrw(rscratch1, dst_klass_addr);
2526 __ cmpw(tmp, rscratch1);
2527 } else {
2528 __ ldr(rscratch1, dst_klass_addr);
2529 __ cmp(tmp, rscratch1);
2530 }
2531 __ br(Assembler::EQ, known_ok);
2532 __ cmp(src, dst);
2533 __ br(Assembler::EQ, known_ok);
2534 }
2535 __ bind(halt);
2536 __ stop("incorrect type information in arraycopy");
2537 __ bind(known_ok);
2538 }
2539 #endif
2540
2541 #ifndef PRODUCT
2542 if (PrintC1Statistics) {
2543 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2544 }
2545 #endif
2546
2547 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2548 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2549 assert_different_registers(c_rarg0, dst, dst_pos, length);
2550 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2551 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2552 assert_different_registers(c_rarg1, dst, length);
2553 __ uxtw(c_rarg2, length);
2554 assert_different_registers(c_rarg2, dst);
2555
2556 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2557 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2558 const char *name;
2559 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2560
2561 CodeBlob *cb = CodeCache::find_blob(entry);
2562 if (cb) {
2563 __ far_call(RuntimeAddress(entry));
2564 } else {
2565 __ call_VM_leaf(entry, 3);
2566 }
2567
2568 __ bind(*stub->continuation());
2569 }
2570
2571
2572
2573
2574 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2575 Register obj = op->obj_opr()->as_register(); // may not be an oop
2576 Register hdr = op->hdr_opr()->as_register();
2577 Register lock = op->lock_opr()->as_register();
2578 if (!UseFastLocking) {
2579 __ b(*op->stub()->entry());
2580 } else if (op->code() == lir_lock) {
2581 Register scratch = noreg;
2582 if (UseBiasedLocking) {
2583 scratch = op->scratch_opr()->as_register();
2584 }
2585 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2586 __ resolve(ACCESS_READ | ACCESS_WRITE, obj);
2587 // add debug info for NullPointerException only if one is possible
2588 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
2589 if (op->info() != NULL) {
2590 add_debug_info_for_null_check(null_check_offset, op->info());
2591 }
2592 // done
2593 } else if (op->code() == lir_unlock) {
2594 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2595 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2596 } else {
2597 Unimplemented();
2598 }
2599 __ bind(*op->stub()->continuation());
2600 }
2601
2602
2603 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2604 ciMethod* method = op->profiled_method();
2605 int bci = op->profiled_bci();
2606 ciMethod* callee = op->profiled_callee();
2607
2608 // Update counter for all call types
2609 ciMethodData* md = method->method_data_or_null();
2610 assert(md != NULL, "Sanity");
2611 ciProfileData* data = md->bci_to_data(bci);
2612 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2613 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2614 Register mdo = op->mdo()->as_register();
2615 __ mov_metadata(mdo, md->constant_encoding());
2616 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2617 // Perform additional virtual call profiling for invokevirtual and
2618 // invokeinterface bytecodes
2619 if (op->should_profile_receiver_type()) {
2620 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2621 Register recv = op->recv()->as_register();
2622 assert_different_registers(mdo, recv);
2623 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2624 ciKlass* known_klass = op->known_holder();
2625 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2626 // We know the type that will be seen at this call site; we can
2627 // statically update the MethodData* rather than needing to do
2628 // dynamic tests on the receiver type
2629
2630 // NOTE: we should probably put a lock around this search to
2631 // avoid collisions by concurrent compilations
2632 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2633 uint i;
2634 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2635 ciKlass* receiver = vc_data->receiver(i);
2636 if (known_klass->equals(receiver)) {
2637 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2638 __ addptr(data_addr, DataLayout::counter_increment);
2639 return;
2640 }
2641 }
2642
2643 // Receiver type not found in profile data; select an empty slot
2644
2645 // Note that this is less efficient than it should be because it
2646 // always does a write to the receiver part of the
2647 // VirtualCallData rather than just the first time
2648 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2649 ciKlass* receiver = vc_data->receiver(i);
2650 if (receiver == NULL) {
2651 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2652 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2653 __ lea(rscratch2, recv_addr);
2654 __ str(rscratch1, Address(rscratch2));
2655 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2656 __ addptr(data_addr, DataLayout::counter_increment);
2657 return;
2658 }
2659 }
2660 } else {
2661 __ load_klass(recv, recv);
2662 Label update_done;
2663 type_profile_helper(mdo, md, data, recv, &update_done);
2664 // Receiver did not match any saved receiver and there is no empty row for it.
2665 // Increment total counter to indicate polymorphic case.
2666 __ addptr(counter_addr, DataLayout::counter_increment);
2667
2668 __ bind(update_done);
2669 }
2670 } else {
2671 // Static call
2672 __ addptr(counter_addr, DataLayout::counter_increment);
2673 }
2674 }
2675
2676
2677 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2678 Unimplemented();
2679 }
2680
2681
2682 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2683 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2684 }
2685
2686 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2687 assert(op->crc()->is_single_cpu(), "crc must be register");
2688 assert(op->val()->is_single_cpu(), "byte value must be register");
2689 assert(op->result_opr()->is_single_cpu(), "result must be register");
2690 Register crc = op->crc()->as_register();
2691 Register val = op->val()->as_register();
2692 Register res = op->result_opr()->as_register();
2693
2694 assert_different_registers(val, crc, res);
2695 unsigned long offset;
2696 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2697 if (offset) __ add(res, res, offset);
2698
2699 __ mvnw(crc, crc); // ~crc
2700 __ update_byte_crc32(crc, val, res);
2701 __ mvnw(res, crc); // ~crc
2702 }
2703
2704 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2705 COMMENT("emit_profile_type {");
2706 Register obj = op->obj()->as_register();
2707 Register tmp = op->tmp()->as_pointer_register();
2708 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2709 ciKlass* exact_klass = op->exact_klass();
2710 intptr_t current_klass = op->current_klass();
2711 bool not_null = op->not_null();
2712 bool no_conflict = op->no_conflict();
2713
2714 Label update, next, none;
2715
2716 bool do_null = !not_null;
2717 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2718 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2719
2720 assert(do_null || do_update, "why are we here?");
2721 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2722 assert(mdo_addr.base() != rscratch1, "wrong register");
2723
2724 __ verify_oop(obj);
2725
2726 if (tmp != obj) {
2727 __ mov(tmp, obj);
2728 }
2729 if (do_null) {
2730 __ cbnz(tmp, update);
2731 if (!TypeEntries::was_null_seen(current_klass)) {
2732 __ ldr(rscratch2, mdo_addr);
2733 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2734 __ str(rscratch2, mdo_addr);
2735 }
2736 if (do_update) {
2737 #ifndef ASSERT
2738 __ b(next);
2739 }
2740 #else
2741 __ b(next);
2742 }
2743 } else {
2744 __ cbnz(tmp, update);
2745 __ stop("unexpected null obj");
2746 #endif
2747 }
2748
2749 __ bind(update);
2750
2751 if (do_update) {
2752 #ifdef ASSERT
2753 if (exact_klass != NULL) {
2754 Label ok;
2755 __ load_klass(tmp, tmp);
2756 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2757 __ eor(rscratch1, tmp, rscratch1);
2758 __ cbz(rscratch1, ok);
2759 __ stop("exact klass and actual klass differ");
2760 __ bind(ok);
2761 }
2762 #endif
2763 if (!no_conflict) {
2764 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2765 if (exact_klass != NULL) {
2766 __ mov_metadata(tmp, exact_klass->constant_encoding());
2767 } else {
2768 __ load_klass(tmp, tmp);
2769 }
2770
2771 __ ldr(rscratch2, mdo_addr);
2772 __ eor(tmp, tmp, rscratch2);
2773 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2774 // klass seen before, nothing to do. The unknown bit may have been
2775 // set already but no need to check.
2776 __ cbz(rscratch1, next);
2777
2778 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2779
2780 if (TypeEntries::is_type_none(current_klass)) {
2781 __ cbz(rscratch2, none);
2782 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2783 __ br(Assembler::EQ, none);
2784 // There is a chance that the checks above (re-reading profiling
2785 // data from memory) fail if another thread has just set the
2786 // profiling to this obj's klass
2787 __ dmb(Assembler::ISHLD);
2788 __ ldr(rscratch2, mdo_addr);
2789 __ eor(tmp, tmp, rscratch2);
2790 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2791 __ cbz(rscratch1, next);
2792 }
2793 } else {
2794 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2795 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2796
2797 __ ldr(tmp, mdo_addr);
2798 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2799 }
2800
2801 // different than before. Cannot keep accurate profile.
2802 __ ldr(rscratch2, mdo_addr);
2803 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2804 __ str(rscratch2, mdo_addr);
2805
2806 if (TypeEntries::is_type_none(current_klass)) {
2807 __ b(next);
2808
2809 __ bind(none);
2810 // first time here. Set profile type.
2811 __ str(tmp, mdo_addr);
2812 }
2813 } else {
2814 // There's a single possible klass at this profile point
2815 assert(exact_klass != NULL, "should be");
2816 if (TypeEntries::is_type_none(current_klass)) {
2817 __ mov_metadata(tmp, exact_klass->constant_encoding());
2818 __ ldr(rscratch2, mdo_addr);
2819 __ eor(tmp, tmp, rscratch2);
2820 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2821 __ cbz(rscratch1, next);
2822 #ifdef ASSERT
2823 {
2824 Label ok;
2825 __ ldr(rscratch1, mdo_addr);
2826 __ cbz(rscratch1, ok);
2827 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2828 __ br(Assembler::EQ, ok);
2829 // may have been set by another thread
2830 __ dmb(Assembler::ISHLD);
2831 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2832 __ ldr(rscratch2, mdo_addr);
2833 __ eor(rscratch2, rscratch1, rscratch2);
2834 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2835 __ cbz(rscratch2, ok);
2836
2837 __ stop("unexpected profiling mismatch");
2838 __ bind(ok);
2839 }
2840 #endif
2841 // first time here. Set profile type.
2842 __ ldr(tmp, mdo_addr);
2843 } else {
2844 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2845 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2846
2847 __ ldr(tmp, mdo_addr);
2848 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2849
2850 __ orr(tmp, tmp, TypeEntries::type_unknown);
2851 __ str(tmp, mdo_addr);
2852 // FIXME: Write barrier needed here?
2853 }
2854 }
2855
2856 __ bind(next);
2857 }
2858 COMMENT("} emit_profile_type");
2859 }
2860
2861
2862 void LIR_Assembler::align_backward_branch_target() {
2863 }
2864
2865
2866 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2867 // tmp must be unused
2868 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2869
2870 if (left->is_single_cpu()) {
2871 assert(dest->is_single_cpu(), "expect single result reg");
2872 __ negw(dest->as_register(), left->as_register());
2873 } else if (left->is_double_cpu()) {
2874 assert(dest->is_double_cpu(), "expect double result reg");
2875 __ neg(dest->as_register_lo(), left->as_register_lo());
2876 } else if (left->is_single_fpu()) {
2877 assert(dest->is_single_fpu(), "expect single float result reg");
2878 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2879 } else {
2880 assert(left->is_double_fpu(), "expect double float operand reg");
2881 assert(dest->is_double_fpu(), "expect double float result reg");
2882 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2883 }
2884 }
2885
2886
2887 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2888 assert(patch_code == lir_patch_none, "Patch code not supported");
2889 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2890 }
2891
2892
2893 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2894 assert(!tmp->is_valid(), "don't need temporary");
2895
2896 CodeBlob *cb = CodeCache::find_blob(dest);
2897 if (cb) {
2898 __ far_call(RuntimeAddress(dest));
2899 } else {
2900 __ mov(rscratch1, RuntimeAddress(dest));
2901 int len = args->length();
2902 int type = 0;
2903 if (! result->is_illegal()) {
2904 switch (result->type()) {
2905 case T_VOID:
2906 type = 0;
2907 break;
2908 case T_INT:
2909 case T_LONG:
2910 case T_OBJECT:
2911 case T_VALUETYPE:
2912 type = 1;
2913 break;
2914 case T_FLOAT:
2915 type = 2;
2916 break;
2917 case T_DOUBLE:
2918 type = 3;
2919 break;
2920 default:
2921 ShouldNotReachHere();
2922 break;
2923 }
2924 }
2925 int num_gpargs = 0;
2926 int num_fpargs = 0;
2927 for (int i = 0; i < args->length(); i++) {
2928 LIR_Opr arg = args->at(i);
2929 if (arg->type() == T_FLOAT || arg->type() == T_DOUBLE) {
2930 num_fpargs++;
2931 } else {
2932 num_gpargs++;
2933 }
2934 }
2935 __ blrt(rscratch1, num_gpargs, num_fpargs, type);
2936 }
2937
2938 if (info != NULL) {
2939 add_call_info_here(info);
2940 }
2941 __ maybe_isb();
2942 }
2943
2944 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2945 if (dest->is_address() || src->is_address()) {
2946 move_op(src, dest, type, lir_patch_none, info,
2947 /*pop_fpu_stack*/false, /*unaligned*/false, /*wide*/false);
2948 } else {
2949 ShouldNotReachHere();
2950 }
2951 }
2952
2953 #ifdef ASSERT
2954 // emit run-time assertion
2955 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2956 assert(op->code() == lir_assert, "must be");
2957
2958 if (op->in_opr1()->is_valid()) {
2959 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2960 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2961 } else {
2962 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2963 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2964 }
2965
2966 Label ok;
2967 if (op->condition() != lir_cond_always) {
2968 Assembler::Condition acond = Assembler::AL;
2969 switch (op->condition()) {
2970 case lir_cond_equal: acond = Assembler::EQ; break;
2971 case lir_cond_notEqual: acond = Assembler::NE; break;
2972 case lir_cond_less: acond = Assembler::LT; break;
2973 case lir_cond_lessEqual: acond = Assembler::LE; break;
2974 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2975 case lir_cond_greater: acond = Assembler::GT; break;
2976 case lir_cond_belowEqual: acond = Assembler::LS; break;
2977 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2978 default: ShouldNotReachHere();
2979 }
2980 __ br(acond, ok);
2981 }
2982 if (op->halt()) {
2983 const char* str = __ code_string(op->msg());
2984 __ stop(str);
2985 } else {
2986 breakpoint();
2987 }
2988 __ bind(ok);
2989 }
2990 #endif
2991
2992 #ifndef PRODUCT
2993 #define COMMENT(x) do { __ block_comment(x); } while (0)
2994 #else
2995 #define COMMENT(x)
2996 #endif
2997
2998 void LIR_Assembler::membar() {
2999 COMMENT("membar");
3000 __ membar(MacroAssembler::AnyAny);
3001 }
3002
3003 void LIR_Assembler::membar_acquire() {
3004 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
3005 }
3006
3007 void LIR_Assembler::membar_release() {
3008 __ membar(Assembler::LoadStore|Assembler::StoreStore);
3009 }
3010
3011 void LIR_Assembler::membar_loadload() {
3012 __ membar(Assembler::LoadLoad);
3013 }
3014
3015 void LIR_Assembler::membar_storestore() {
3016 __ membar(MacroAssembler::StoreStore);
3017 }
3018
3019 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3020
3021 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3022
3023 void LIR_Assembler::on_spin_wait() {
3024 Unimplemented();
3025 }
3026
3027 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3028 __ mov(result_reg->as_register(), rthread);
3029 }
3030
3031
3032 void LIR_Assembler::peephole(LIR_List *lir) {
3033 #if 0
3034 if (tableswitch_count >= max_tableswitches)
3035 return;
3036
3037 /*
3038 This finite-state automaton recognizes sequences of compare-and-
3039 branch instructions. We will turn them into a tableswitch. You
3040 could argue that C1 really shouldn't be doing this sort of
3041 optimization, but without it the code is really horrible.
3042 */
3043
3044 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3045 int first_key, last_key = -2147483648;
3046 int next_key = 0;
3047 int start_insn = -1;
3048 int last_insn = -1;
3049 Register reg = noreg;
3050 LIR_Opr reg_opr;
3051 state = start_s;
3052
3053 LIR_OpList* inst = lir->instructions_list();
3054 for (int i = 0; i < inst->length(); i++) {
3055 LIR_Op* op = inst->at(i);
3056 switch (state) {
3057 case start_s:
3058 first_key = -1;
3059 start_insn = i;
3060 switch (op->code()) {
3061 case lir_cmp:
3062 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3063 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3064 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3065 && opr2->is_constant()
3066 && opr2->type() == T_INT) {
3067 reg_opr = opr1;
3068 reg = opr1->as_register();
3069 first_key = opr2->as_constant_ptr()->as_jint();
3070 next_key = first_key + 1;
3071 state = cmp_s;
3072 goto next_state;
3073 }
3074 break;
3075 }
3076 break;
3077 case cmp_s:
3078 switch (op->code()) {
3079 case lir_branch:
3080 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3081 state = beq_s;
3082 last_insn = i;
3083 goto next_state;
3084 }
3085 }
3086 state = start_s;
3087 break;
3088 case beq_s:
3089 switch (op->code()) {
3090 case lir_cmp: {
3091 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3092 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3093 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3094 && opr1->as_register() == reg
3095 && opr2->is_constant()
3096 && opr2->type() == T_INT
3097 && opr2->as_constant_ptr()->as_jint() == next_key) {
3098 last_key = next_key;
3099 next_key++;
3100 state = cmp_s;
3101 goto next_state;
3102 }
3103 }
3104 }
3105 last_key = next_key;
3106 state = start_s;
3107 break;
3108 default:
3109 assert(false, "impossible state");
3110 }
3111 if (state == start_s) {
3112 if (first_key < last_key - 5L && reg != noreg) {
3113 {
3114 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3115 // reg->encoding(),
3116 // start_insn, first_key, last_key);
3117 // for (int i = 0; i < inst->length(); i++) {
3118 // inst->at(i)->print();
3119 // tty->print("\n");
3120 // }
3121 // tty->print("\n");
3122 }
3123
3124 struct tableswitch *sw = &switches[tableswitch_count];
3125 sw->_insn_index = start_insn, sw->_first_key = first_key,
3126 sw->_last_key = last_key, sw->_reg = reg;
3127 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3128 {
3129 // Insert the new table of branches
3130 int offset = last_insn;
3131 for (int n = first_key; n < last_key; n++) {
3132 inst->insert_before
3133 (last_insn + 1,
3134 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3135 inst->at(offset)->as_OpBranch()->label()));
3136 offset -= 2, i++;
3137 }
3138 }
3139 // Delete all the old compare-and-branch instructions
3140 for (int n = first_key; n < last_key; n++) {
3141 inst->remove_at(start_insn);
3142 inst->remove_at(start_insn);
3143 }
3144 // Insert the tableswitch instruction
3145 inst->insert_before(start_insn,
3146 new LIR_Op2(lir_cmp, lir_cond_always,
3147 LIR_OprFact::intConst(tableswitch_count),
3148 reg_opr));
3149 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3150 tableswitch_count++;
3151 }
3152 reg = noreg;
3153 last_key = -2147483648;
3154 }
3155 next_state:
3156 ;
3157 }
3158 #endif
3159 }
3160
3161 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3162 Address addr = as_Address(src->as_address_ptr());
3163 BasicType type = src->type();
3164 bool is_oop = type == T_OBJECT || type == T_ARRAY;
3165
3166 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3167 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3168
3169 switch(type) {
3170 case T_INT:
3171 xchg = &MacroAssembler::atomic_xchgalw;
3172 add = &MacroAssembler::atomic_addalw;
3173 break;
3174 case T_LONG:
3175 xchg = &MacroAssembler::atomic_xchgal;
3176 add = &MacroAssembler::atomic_addal;
3177 break;
3178 case T_VALUETYPE:
3179 case T_OBJECT:
3180 case T_ARRAY:
3181 if (UseCompressedOops) {
3182 xchg = &MacroAssembler::atomic_xchgalw;
3183 add = &MacroAssembler::atomic_addalw;
3184 } else {
3185 xchg = &MacroAssembler::atomic_xchgal;
3186 add = &MacroAssembler::atomic_addal;
3187 }
3188 break;
3189 default:
3190 ShouldNotReachHere();
3191 xchg = &MacroAssembler::atomic_xchgal;
3192 add = &MacroAssembler::atomic_addal; // unreachable
3193 }
3194
3195 switch (code) {
3196 case lir_xadd:
3197 {
3198 RegisterOrConstant inc;
3199 Register tmp = as_reg(tmp_op);
3200 Register dst = as_reg(dest);
3201 if (data->is_constant()) {
3202 inc = RegisterOrConstant(as_long(data));
3203 assert_different_registers(dst, addr.base(), tmp,
3204 rscratch1, rscratch2);
3205 } else {
3206 inc = RegisterOrConstant(as_reg(data));
3207 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3208 rscratch1, rscratch2);
3209 }
3210 __ lea(tmp, addr);
3211 (_masm->*add)(dst, inc, tmp);
3212 break;
3213 }
3214 case lir_xchg:
3215 {
3216 Register tmp = tmp_op->as_register();
3217 Register obj = as_reg(data);
3218 Register dst = as_reg(dest);
3219 if (is_oop && UseCompressedOops) {
3220 __ encode_heap_oop(rscratch2, obj);
3221 obj = rscratch2;
3222 }
3223 assert_different_registers(obj, addr.base(), tmp, rscratch1, dst);
3224 __ lea(tmp, addr);
3225 (_masm->*xchg)(dst, obj, tmp);
3226 if (is_oop && UseCompressedOops) {
3227 __ decode_heap_oop(dst);
3228 }
3229 }
3230 break;
3231 default:
3232 ShouldNotReachHere();
3233 }
3234 __ membar(__ AnyAny);
3235 }
3236
3237 #undef __