rev 54670 : Port of valuetypes to aarch64

   1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.hpp"
  30 #include "runtime/signature.hpp"
  31 
  32 
  33 // MacroAssembler extends Assembler by frequently used macros.
  34 //
  35 // Instructions for which a 'better' code sequence exists depending
  36 // on arguments should also go in here.
  37 
  38 class MacroAssembler: public Assembler {
  39   friend class LIR_Assembler;
  40 
  41  public:
  42   using Assembler::mov;
  43   using Assembler::movi;
  44 
  45  protected:
  46 
  47   // Support for VM calls
  48   //
  49   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  50   // may customize this version by overriding it for its purposes (e.g., to save/restore
  51   // additional registers when doing a VM call).
  52   virtual void call_VM_leaf_base(
  53     address entry_point,               // the entry point
  54     int     number_of_arguments,        // the number of arguments to pop after the call
  55     Label *retaddr = NULL
  56   );
  57 
  58   virtual void call_VM_leaf_base(
  59     address entry_point,               // the entry point
  60     int     number_of_arguments,        // the number of arguments to pop after the call
  61     Label &retaddr) {
  62     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  63   }
  64 
  65   // This is the base routine called by the different versions of call_VM. The interpreter
  66   // may customize this version by overriding it for its purposes (e.g., to save/restore
  67   // additional registers when doing a VM call).
  68   //
  69   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  70   // returns the register which contains the thread upon return. If a thread register has been
  71   // specified, the return value will correspond to that register. If no last_java_sp is specified
  72   // (noreg) than rsp will be used instead.
  73   virtual void call_VM_base(           // returns the register containing the thread upon return
  74     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  75     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  76     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  77     address  entry_point,              // the entry point
  78     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  79     bool     check_exceptions          // whether to check for pending exceptions after return
  80   );
  81 
  82   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  83 
  84   // True if an XOR can be used to expand narrow klass references.
  85   bool use_XOR_for_compressed_class_base;
  86 
  87  public:
  88   MacroAssembler(CodeBuffer* code) : Assembler(code) {
  89     use_XOR_for_compressed_class_base
  90       = (operand_valid_for_logical_immediate(false /*is32*/,
  91                                              (uint64_t)Universe::narrow_klass_base())
  92          && ((uint64_t)Universe::narrow_klass_base()
  93              > (1UL << log2_intptr(Universe::narrow_klass_range()))));
  94   }
  95 
  96  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  97  // The implementation is only non-empty for the InterpreterMacroAssembler,
  98  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  99  virtual void check_and_handle_popframe(Register java_thread);
 100  virtual void check_and_handle_earlyret(Register java_thread);
 101 
 102   void safepoint_poll(Label& slow_path);
 103   void safepoint_poll_acquire(Label& slow_path);
 104 
 105   // Biased locking support
 106   // lock_reg and obj_reg must be loaded up with the appropriate values.
 107   // swap_reg is killed.
 108   // tmp_reg must be supplied and must not be rscratch1 or rscratch2
 109   // Optional slow case is for implementations (interpreter and C1) which branch to
 110   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 111   // Returns offset of first potentially-faulting instruction for null
 112   // check info (currently consumed only by C1). If
 113   // swap_reg_contains_mark is true then returns -1 as it is assumed
 114   // the calling code has already passed any potential faults.
 115   int biased_locking_enter(Register lock_reg, Register obj_reg,
 116                            Register swap_reg, Register tmp_reg,
 117                            bool swap_reg_contains_mark,
 118                            Label& done, Label* slow_case = NULL,
 119                            BiasedLockingCounters* counters = NULL);
 120   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 121 
 122 
 123   // Helper functions for statistics gathering.
 124   // Unconditional atomic increment.
 125   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 126   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 127     lea(tmp1, counter_addr);
 128     atomic_incw(tmp1, tmp2, tmp3);
 129   }
 130   // Load Effective Address
 131   void lea(Register r, const Address &a) {
 132     InstructionMark im(this);
 133     code_section()->relocate(inst_mark(), a.rspec());
 134     a.lea(this, r);
 135   }
 136 
 137   void addmw(Address a, Register incr, Register scratch) {
 138     ldrw(scratch, a);
 139     addw(scratch, scratch, incr);
 140     strw(scratch, a);
 141   }
 142 
 143   // Add constant to memory word
 144   void addmw(Address a, int imm, Register scratch) {
 145     ldrw(scratch, a);
 146     if (imm > 0)
 147       addw(scratch, scratch, (unsigned)imm);
 148     else
 149       subw(scratch, scratch, (unsigned)-imm);
 150     strw(scratch, a);
 151   }
 152 
 153   void bind(Label& L) {
 154     Assembler::bind(L);
 155     code()->clear_last_insn();
 156   }
 157 
 158   void membar(Membar_mask_bits order_constraint);
 159 
 160   using Assembler::ldr;
 161   using Assembler::str;
 162 
 163   void ldr(Register Rx, const Address &adr);
 164   void ldrw(Register Rw, const Address &adr);
 165   void str(Register Rx, const Address &adr);
 166   void strw(Register Rx, const Address &adr);
 167 
 168   // Frame creation and destruction shared between JITs.
 169   void build_frame(int framesize);
 170   void remove_frame(int framesize);
 171 
 172   virtual void _call_Unimplemented(address call_site) {
 173     mov(rscratch2, call_site);
 174     haltsim();
 175   }
 176 
 177 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 178 
 179   virtual void notify(int type);
 180 
 181   // aliases defined in AARCH64 spec
 182 
 183   template<class T>
 184   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 185 
 186   inline void cmp(Register Rd, unsigned char imm8)  { subs(zr, Rd, imm8); }
 187   inline void cmp(Register Rd, unsigned imm) __attribute__ ((deprecated));
 188 
 189   inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
 190   inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
 191 
 192   void cset(Register Rd, Assembler::Condition cond) {
 193     csinc(Rd, zr, zr, ~cond);
 194   }
 195   void csetw(Register Rd, Assembler::Condition cond) {
 196     csincw(Rd, zr, zr, ~cond);
 197   }
 198 
 199   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 200     csneg(Rd, Rn, Rn, ~cond);
 201   }
 202   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 203     csnegw(Rd, Rn, Rn, ~cond);
 204   }
 205 
 206   inline void movw(Register Rd, Register Rn) {
 207     if (Rd == sp || Rn == sp) {
 208       addw(Rd, Rn, 0U);
 209     } else {
 210       orrw(Rd, zr, Rn);
 211     }
 212   }
 213   inline void mov(Register Rd, Register Rn) {
 214     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 215     if (Rd == Rn) {
 216     } else if (Rd == sp || Rn == sp) {
 217       add(Rd, Rn, 0U);
 218     } else {
 219       orr(Rd, zr, Rn);
 220     }
 221   }
 222 
 223   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 224   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 225 
 226   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 227   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 228 
 229   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 230   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 231 
 232   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 233     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 234   }
 235   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 236     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 237   }
 238 
 239   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 240     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 241   }
 242   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 243     bfm(Rd, Rn, lsb , (lsb + width - 1));
 244   }
 245 
 246   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 247     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 248   }
 249   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 250     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 251   }
 252 
 253   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 254     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 255   }
 256   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 257     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 258   }
 259 
 260   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 261     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 262   }
 263   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 264     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 265   }
 266 
 267   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 268     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 269   }
 270   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 271     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 272   }
 273 
 274   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 275     sbfmw(Rd, Rn, imm, 31);
 276   }
 277 
 278   inline void asr(Register Rd, Register Rn, unsigned imm) {
 279     sbfm(Rd, Rn, imm, 63);
 280   }
 281 
 282   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 283     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 284   }
 285 
 286   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 287     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 288   }
 289 
 290   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 291     ubfmw(Rd, Rn, imm, 31);
 292   }
 293 
 294   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 295     ubfm(Rd, Rn, imm, 63);
 296   }
 297 
 298   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 299     extrw(Rd, Rn, Rn, imm);
 300   }
 301 
 302   inline void ror(Register Rd, Register Rn, unsigned imm) {
 303     extr(Rd, Rn, Rn, imm);
 304   }
 305 
 306   inline void sxtbw(Register Rd, Register Rn) {
 307     sbfmw(Rd, Rn, 0, 7);
 308   }
 309   inline void sxthw(Register Rd, Register Rn) {
 310     sbfmw(Rd, Rn, 0, 15);
 311   }
 312   inline void sxtb(Register Rd, Register Rn) {
 313     sbfm(Rd, Rn, 0, 7);
 314   }
 315   inline void sxth(Register Rd, Register Rn) {
 316     sbfm(Rd, Rn, 0, 15);
 317   }
 318   inline void sxtw(Register Rd, Register Rn) {
 319     sbfm(Rd, Rn, 0, 31);
 320   }
 321 
 322   inline void uxtbw(Register Rd, Register Rn) {
 323     ubfmw(Rd, Rn, 0, 7);
 324   }
 325   inline void uxthw(Register Rd, Register Rn) {
 326     ubfmw(Rd, Rn, 0, 15);
 327   }
 328   inline void uxtb(Register Rd, Register Rn) {
 329     ubfm(Rd, Rn, 0, 7);
 330   }
 331   inline void uxth(Register Rd, Register Rn) {
 332     ubfm(Rd, Rn, 0, 15);
 333   }
 334   inline void uxtw(Register Rd, Register Rn) {
 335     ubfm(Rd, Rn, 0, 31);
 336   }
 337 
 338   inline void cmnw(Register Rn, Register Rm) {
 339     addsw(zr, Rn, Rm);
 340   }
 341   inline void cmn(Register Rn, Register Rm) {
 342     adds(zr, Rn, Rm);
 343   }
 344 
 345   inline void cmpw(Register Rn, Register Rm) {
 346     subsw(zr, Rn, Rm);
 347   }
 348   inline void cmp(Register Rn, Register Rm) {
 349     subs(zr, Rn, Rm);
 350   }
 351 
 352   inline void negw(Register Rd, Register Rn) {
 353     subw(Rd, zr, Rn);
 354   }
 355 
 356   inline void neg(Register Rd, Register Rn) {
 357     sub(Rd, zr, Rn);
 358   }
 359 
 360   inline void negsw(Register Rd, Register Rn) {
 361     subsw(Rd, zr, Rn);
 362   }
 363 
 364   inline void negs(Register Rd, Register Rn) {
 365     subs(Rd, zr, Rn);
 366   }
 367 
 368   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 369     addsw(zr, Rn, Rm, kind, shift);
 370   }
 371   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 372     adds(zr, Rn, Rm, kind, shift);
 373   }
 374 
 375   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 376     subsw(zr, Rn, Rm, kind, shift);
 377   }
 378   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 379     subs(zr, Rn, Rm, kind, shift);
 380   }
 381 
 382   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 383     subw(Rd, zr, Rn, kind, shift);
 384   }
 385 
 386   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 387     sub(Rd, zr, Rn, kind, shift);
 388   }
 389 
 390   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 391     subsw(Rd, zr, Rn, kind, shift);
 392   }
 393 
 394   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 395     subs(Rd, zr, Rn, kind, shift);
 396   }
 397 
 398   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 399     msubw(Rd, Rn, Rm, zr);
 400   }
 401   inline void mneg(Register Rd, Register Rn, Register Rm) {
 402     msub(Rd, Rn, Rm, zr);
 403   }
 404 
 405   inline void mulw(Register Rd, Register Rn, Register Rm) {
 406     maddw(Rd, Rn, Rm, zr);
 407   }
 408   inline void mul(Register Rd, Register Rn, Register Rm) {
 409     madd(Rd, Rn, Rm, zr);
 410   }
 411 
 412   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 413     smsubl(Rd, Rn, Rm, zr);
 414   }
 415   inline void smull(Register Rd, Register Rn, Register Rm) {
 416     smaddl(Rd, Rn, Rm, zr);
 417   }
 418 
 419   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 420     umsubl(Rd, Rn, Rm, zr);
 421   }
 422   inline void umull(Register Rd, Register Rn, Register Rm) {
 423     umaddl(Rd, Rn, Rm, zr);
 424   }
 425 
 426 #define WRAP(INSN)                                                            \
 427   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 428     if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr)        \
 429       nop();                                                                  \
 430     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 431   }
 432 
 433   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 434   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 435 #undef WRAP
 436 
 437 
 438   // macro assembly operations needed for aarch64
 439 
 440   // first two private routines for loading 32 bit or 64 bit constants
 441 private:
 442 
 443   void mov_immediate64(Register dst, u_int64_t imm64);
 444   void mov_immediate32(Register dst, u_int32_t imm32);
 445 
 446   int push(unsigned int bitset, Register stack);
 447   int pop(unsigned int bitset, Register stack);
 448 
 449   void mov(Register dst, Address a);
 450 
 451 public:
 452   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 453   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 454 
 455   // Push and pop everything that might be clobbered by a native
 456   // runtime call except rscratch1 and rscratch2.  (They are always
 457   // scratch, so we don't have to protect them.)  Only save the lower
 458   // 64 bits of each vector register.
 459   void push_call_clobbered_registers();
 460   void pop_call_clobbered_registers();
 461 
 462   // now mov instructions for loading absolute addresses and 32 or
 463   // 64 bit integers
 464 
 465   inline void mov(Register dst, address addr)
 466   {
 467     mov_immediate64(dst, (u_int64_t)addr);
 468   }
 469 
 470   inline void mov(Register dst, u_int64_t imm64)
 471   {
 472     mov_immediate64(dst, imm64);
 473   }
 474 
 475   inline void movw(Register dst, u_int32_t imm32)
 476   {
 477     mov_immediate32(dst, imm32);
 478   }
 479 
 480   inline void mov(Register dst, long l)
 481   {
 482     mov(dst, (u_int64_t)l);
 483   }
 484 
 485   inline void mov(Register dst, int i)
 486   {
 487     mov(dst, (long)i);
 488   }
 489 
 490   void mov(Register dst, RegisterOrConstant src) {
 491     if (src.is_register())
 492       mov(dst, src.as_register());
 493     else
 494       mov(dst, src.as_constant());
 495   }
 496 
 497   void movptr(Register r, uintptr_t imm64);
 498 
 499   void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
 500 
 501   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 502     orr(Vd, T, Vn, Vn);
 503   }
 504 
 505 public:
 506 
 507   // Generalized Test Bit And Branch, including a "far" variety which
 508   // spans more than 32KiB.
 509   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
 510     assert(cond == EQ || cond == NE, "must be");
 511 
 512     if (far)
 513       cond = ~cond;
 514 
 515     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 516     if (cond == Assembler::EQ)
 517       branch = &Assembler::tbz;
 518     else
 519       branch = &Assembler::tbnz;
 520 
 521     if (far) {
 522       Label L;
 523       (this->*branch)(Rt, bitpos, L);
 524       b(dest);
 525       bind(L);
 526     } else {
 527       (this->*branch)(Rt, bitpos, dest);
 528     }
 529   }
 530 
 531   // macro instructions for accessing and updating floating point
 532   // status register
 533   //
 534   // FPSR : op1 == 011
 535   //        CRn == 0100
 536   //        CRm == 0100
 537   //        op2 == 001
 538 
 539   inline void get_fpsr(Register reg)
 540   {
 541     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 542   }
 543 
 544   inline void set_fpsr(Register reg)
 545   {
 546     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 547   }
 548 
 549   inline void clear_fpsr()
 550   {
 551     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 552   }
 553 
 554   // DCZID_EL0: op1 == 011
 555   //            CRn == 0000
 556   //            CRm == 0000
 557   //            op2 == 111
 558   inline void get_dczid_el0(Register reg)
 559   {
 560     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 561   }
 562 
 563   // CTR_EL0:   op1 == 011
 564   //            CRn == 0000
 565   //            CRm == 0000
 566   //            op2 == 001
 567   inline void get_ctr_el0(Register reg)
 568   {
 569     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 570   }
 571 
 572   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 573   int corrected_idivl(Register result, Register ra, Register rb,
 574                       bool want_remainder, Register tmp = rscratch1);
 575   int corrected_idivq(Register result, Register ra, Register rb,
 576                       bool want_remainder, Register tmp = rscratch1);
 577 
 578   // Support for NULL-checks
 579   //
 580   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 581   // If the accessed location is M[reg + offset] and the offset is known, provide the
 582   // offset. No explicit code generation is needed if the offset is within a certain
 583   // range (0 <= offset <= page_size).
 584 
 585   virtual void null_check(Register reg, int offset = -1);
 586   static bool needs_explicit_null_check(intptr_t offset);
 587   static bool uses_implicit_null_check(void* address);
 588 
 589   void test_klass_is_value(Register klass, Register temp_reg, Label& is_value);
 590 
 591   void test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable);
 592   void test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable);
 593   void test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened);
 594 
 595   // Check klass/oops is flat value type array (oop->_klass->_layout_helper & vt_bit)
 596   void test_flat_array_klass(Register klass, Register temp_reg, Label& is_flat_array);
 597   void test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array);
 598 
 599 
 600 
 601   static address target_addr_for_insn(address insn_addr, unsigned insn);
 602   static address target_addr_for_insn(address insn_addr) {
 603     unsigned insn = *(unsigned*)insn_addr;
 604     return target_addr_for_insn(insn_addr, insn);
 605   }
 606 
 607   // Required platform-specific helpers for Label::patch_instructions.
 608   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 609   static int pd_patch_instruction_size(address branch, address target);
 610   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 611     pd_patch_instruction_size(branch, target);
 612   }
 613   static address pd_call_destination(address branch) {
 614     return target_addr_for_insn(branch);
 615   }
 616 #ifndef PRODUCT
 617   static void pd_print_patched_instruction(address branch);
 618 #endif
 619 
 620   static int patch_oop(address insn_addr, address o);
 621   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 622 
 623   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 624 
 625   // The following 4 methods return the offset of the appropriate move instruction
 626 
 627   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 628   int load_unsigned_byte(Register dst, Address src);
 629   int load_unsigned_short(Register dst, Address src);
 630 
 631   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 632   int load_signed_byte(Register dst, Address src);
 633   int load_signed_short(Register dst, Address src);
 634 
 635   int load_signed_byte32(Register dst, Address src);
 636   int load_signed_short32(Register dst, Address src);
 637 
 638   // Support for sign-extension (hi:lo = extend_sign(lo))
 639   void extend_sign(Register hi, Register lo);
 640 
 641   // Load and store values by size and signed-ness
 642   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 643   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 644 
 645   // Support for inc/dec with optimal instruction selection depending on value
 646 
 647   // x86_64 aliases an unqualified register/address increment and
 648   // decrement to call incrementq and decrementq but also supports
 649   // explicitly sized calls to incrementq/decrementq or
 650   // incrementl/decrementl
 651 
 652   // for aarch64 the proper convention would be to use
 653   // increment/decrement for 64 bit operatons and
 654   // incrementw/decrementw for 32 bit operations. so when porting
 655   // x86_64 code we can leave calls to increment/decrement as is,
 656   // replace incrementq/decrementq with increment/decrement and
 657   // replace incrementl/decrementl with incrementw/decrementw.
 658 
 659   // n.b. increment/decrement calls with an Address destination will
 660   // need to use a scratch register to load the value to be
 661   // incremented. increment/decrement calls which add or subtract a
 662   // constant value greater than 2^12 will need to use a 2nd scratch
 663   // register to hold the constant. so, a register increment/decrement
 664   // may trash rscratch2 and an address increment/decrement trash
 665   // rscratch and rscratch2
 666 
 667   void decrementw(Address dst, int value = 1);
 668   void decrementw(Register reg, int value = 1);
 669 
 670   void decrement(Register reg, int value = 1);
 671   void decrement(Address dst, int value = 1);
 672 
 673   void incrementw(Address dst, int value = 1);
 674   void incrementw(Register reg, int value = 1);
 675 
 676   void increment(Register reg, int value = 1);
 677   void increment(Address dst, int value = 1);
 678 
 679 
 680   // Alignment
 681   void align(int modulus);
 682 
 683   // Stack frame creation/removal
 684   void enter()
 685   {
 686     stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
 687     mov(rfp, sp);
 688   }
 689   void leave()
 690   {
 691     mov(sp, rfp);
 692     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
 693   }
 694 
 695   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 696   // The pointer will be loaded into the thread register.
 697   void get_thread(Register thread);
 698 
 699 
 700   // Support for VM calls
 701   //
 702   // It is imperative that all calls into the VM are handled via the call_VM macros.
 703   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 704   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 705 
 706 
 707   void call_VM(Register oop_result,
 708                address entry_point,
 709                bool check_exceptions = true);
 710   void call_VM(Register oop_result,
 711                address entry_point,
 712                Register arg_1,
 713                bool check_exceptions = true);
 714   void call_VM(Register oop_result,
 715                address entry_point,
 716                Register arg_1, Register arg_2,
 717                bool check_exceptions = true);
 718   void call_VM(Register oop_result,
 719                address entry_point,
 720                Register arg_1, Register arg_2, Register arg_3,
 721                bool check_exceptions = true);
 722 
 723   // Overloadings with last_Java_sp
 724   void call_VM(Register oop_result,
 725                Register last_java_sp,
 726                address entry_point,
 727                int number_of_arguments = 0,
 728                bool check_exceptions = true);
 729   void call_VM(Register oop_result,
 730                Register last_java_sp,
 731                address entry_point,
 732                Register arg_1, bool
 733                check_exceptions = true);
 734   void call_VM(Register oop_result,
 735                Register last_java_sp,
 736                address entry_point,
 737                Register arg_1, Register arg_2,
 738                bool check_exceptions = true);
 739   void call_VM(Register oop_result,
 740                Register last_java_sp,
 741                address entry_point,
 742                Register arg_1, Register arg_2, Register arg_3,
 743                bool check_exceptions = true);
 744 
 745   void get_vm_result  (Register oop_result, Register thread);
 746   void get_vm_result_2(Register metadata_result, Register thread);
 747 
 748   // These always tightly bind to MacroAssembler::call_VM_base
 749   // bypassing the virtual implementation
 750   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 751   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 752   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 753   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 754   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 755 
 756   void call_VM_leaf(address entry_point,
 757                     int number_of_arguments = 0);
 758   void call_VM_leaf(address entry_point,
 759                     Register arg_1);
 760   void call_VM_leaf(address entry_point,
 761                     Register arg_1, Register arg_2);
 762   void call_VM_leaf(address entry_point,
 763                     Register arg_1, Register arg_2, Register arg_3);
 764 
 765   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 766   // bypassing the virtual implementation
 767   void super_call_VM_leaf(address entry_point);
 768   void super_call_VM_leaf(address entry_point, Register arg_1);
 769   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 770   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 771   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 772 
 773   // last Java Frame (fills frame anchor)
 774   void set_last_Java_frame(Register last_java_sp,
 775                            Register last_java_fp,
 776                            address last_java_pc,
 777                            Register scratch);
 778 
 779   void set_last_Java_frame(Register last_java_sp,
 780                            Register last_java_fp,
 781                            Label &last_java_pc,
 782                            Register scratch);
 783 
 784   void set_last_Java_frame(Register last_java_sp,
 785                            Register last_java_fp,
 786                            Register last_java_pc,
 787                            Register scratch);
 788 
 789   void reset_last_Java_frame(Register thread);
 790 
 791   // thread in the default location (rthread)
 792   void reset_last_Java_frame(bool clear_fp);
 793 
 794   // Stores
 795   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 796   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 797 
 798   void resolve_jobject(Register value, Register thread, Register tmp);
 799 
 800   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 801   void c2bool(Register x);
 802 
 803   // oop manipulations
 804   void load_klass(Register dst, Register src);
 805   void store_klass(Register dst, Register src);
 806   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 807 
 808   void resolve_oop_handle(Register result, Register tmp = r5);
 809   void load_mirror(Register dst, Register method, Register tmp = r5);
 810 
 811   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 812                       Register tmp1, Register tmp_thread);
 813 
 814   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 815                        Register tmp1, Register tmp_thread);
 816 
 817   // Resolves obj for access. Result is placed in the same register.
 818   // All other registers are preserved.
 819   void resolve(DecoratorSet decorators, Register obj);
 820 
 821   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 822                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 823 
 824   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 825                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 826   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 827                       Register tmp_thread = noreg, DecoratorSet decorators = 0);
 828 
 829   // currently unimplemented
 830   // Used for storing NULL. All other oop constants should be
 831   // stored using routines that take a jobject.
 832   void store_heap_oop_null(Address dst);
 833 
 834   void load_prototype_header(Register dst, Register src);
 835 
 836   void store_klass_gap(Register dst, Register src);
 837 
 838   // This dummy is to prevent a call to store_heap_oop from
 839   // converting a zero (like NULL) into a Register by giving
 840   // the compiler two choices it can't resolve
 841 
 842   void store_heap_oop(Address dst, void* dummy);
 843 
 844   void encode_heap_oop(Register d, Register s);
 845   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 846   void decode_heap_oop(Register d, Register s);
 847   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 848   void encode_heap_oop_not_null(Register r);
 849   void decode_heap_oop_not_null(Register r);
 850   void encode_heap_oop_not_null(Register dst, Register src);
 851   void decode_heap_oop_not_null(Register dst, Register src);
 852 
 853   void set_narrow_oop(Register dst, jobject obj);
 854 
 855   void encode_klass_not_null(Register r);
 856   void decode_klass_not_null(Register r);
 857   void encode_klass_not_null(Register dst, Register src);
 858   void decode_klass_not_null(Register dst, Register src);
 859 
 860   void set_narrow_klass(Register dst, Klass* k);
 861 
 862   // if heap base register is used - reinit it with the correct value
 863   void reinit_heapbase();
 864 
 865   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 866 
 867   void push_CPU_state(bool save_vectors = false);
 868   void pop_CPU_state(bool restore_vectors = false) ;
 869 
 870   // Round up to a power of two
 871   void round_to(Register reg, int modulus);
 872 
 873   // allocation
 874   void eden_allocate(
 875     Register obj,                      // result: pointer to object after successful allocation
 876     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 877     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 878     Register t1,                       // temp register
 879     Label&   slow_case                 // continuation point if fast allocation fails
 880   );
 881   void tlab_allocate(
 882     Register obj,                      // result: pointer to object after successful allocation
 883     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 884     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 885     Register t1,                       // temp register
 886     Register t2,                       // temp register
 887     Label&   slow_case                 // continuation point if fast allocation fails
 888   );
 889   void zero_memory(Register addr, Register len, Register t1);
 890   void verify_tlab();
 891 
 892   // interface method calling
 893   void lookup_interface_method(Register recv_klass,
 894                                Register intf_klass,
 895                                RegisterOrConstant itable_index,
 896                                Register method_result,
 897                                Register scan_temp,
 898                                Label& no_such_interface,
 899                    bool return_method = true);
 900 
 901   // virtual method calling
 902   // n.b. x86 allows RegisterOrConstant for vtable_index
 903   void lookup_virtual_method(Register recv_klass,
 904                              RegisterOrConstant vtable_index,
 905                              Register method_result);
 906 
 907   // Test sub_klass against super_klass, with fast and slow paths.
 908 
 909   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 910   // One of the three labels can be NULL, meaning take the fall-through.
 911   // If super_check_offset is -1, the value is loaded up from super_klass.
 912   // No registers are killed, except temp_reg.
 913   void check_klass_subtype_fast_path(Register sub_klass,
 914                                      Register super_klass,
 915                                      Register temp_reg,
 916                                      Label* L_success,
 917                                      Label* L_failure,
 918                                      Label* L_slow_path,
 919                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 920 
 921   // The rest of the type check; must be wired to a corresponding fast path.
 922   // It does not repeat the fast path logic, so don't use it standalone.
 923   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 924   // Updates the sub's secondary super cache as necessary.
 925   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 926   void check_klass_subtype_slow_path(Register sub_klass,
 927                                      Register super_klass,
 928                                      Register temp_reg,
 929                                      Register temp2_reg,
 930                                      Label* L_success,
 931                                      Label* L_failure,
 932                                      bool set_cond_codes = false);
 933 
 934   // Simplified, combined version, good for typical uses.
 935   // Falls through on failure.
 936   void check_klass_subtype(Register sub_klass,
 937                            Register super_klass,
 938                            Register temp_reg,
 939                            Label& L_success);
 940 
 941   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 942 
 943 
 944   // Debugging
 945 
 946   // only if +VerifyOops
 947   void verify_oop(Register reg, const char* s = "broken oop");
 948   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 949 
 950 // TODO: verify method and klass metadata (compare against vptr?)
 951   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 952   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 953 
 954 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 955 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 956 
 957   // only if +VerifyFPU
 958   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 959 
 960   // prints msg, dumps registers and stops execution
 961   void stop(const char* msg);
 962 
 963   // prints msg and continues
 964   void warn(const char* msg);
 965 
 966   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 967 
 968   void untested()                                { stop("untested"); }
 969 
 970   void unimplemented(const char* what = "");
 971 
 972   void should_not_reach_here()                   { stop("should not reach here"); }
 973 
 974   // Stack overflow checking
 975   void bang_stack_with_offset(int offset) {
 976     // stack grows down, caller passes positive offset
 977     assert(offset > 0, "must bang with negative offset");
 978     sub(rscratch2, sp, offset);
 979     str(zr, Address(rscratch2));
 980   }
 981 
 982   // Writes to stack successive pages until offset reached to check for
 983   // stack overflow + shadow pages.  Also, clobbers tmp
 984   void bang_stack_size(Register size, Register tmp);
 985 
 986   // Check for reserved stack access in method being exited (for JIT)
 987   void reserved_stack_check();
 988 
 989   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 990                                                 Register tmp,
 991                                                 int offset);
 992 
 993   // Arithmetics
 994 
 995   void addptr(const Address &dst, int32_t src);
 996   void cmpptr(Register src1, Address src2);
 997 
 998   void cmpoop(Register obj1, Register obj2);
 999 
1000   // Various forms of CAS
1001 
1002   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1003                           Label &suceed, Label *fail);
1004   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1005                   Label &suceed, Label *fail);
1006 
1007   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1008                   Label &suceed, Label *fail);
1009 
1010   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1011   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1012   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1013   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1014 
1015   void atomic_xchg(Register prev, Register newv, Register addr);
1016   void atomic_xchgw(Register prev, Register newv, Register addr);
1017   void atomic_xchgal(Register prev, Register newv, Register addr);
1018   void atomic_xchgalw(Register prev, Register newv, Register addr);
1019 
1020   void orptr(Address adr, RegisterOrConstant src) {
1021     ldr(rscratch1, adr);
1022     if (src.is_register())
1023       orr(rscratch1, rscratch1, src.as_register());
1024     else
1025       orr(rscratch1, rscratch1, src.as_constant());
1026     str(rscratch1, adr);
1027   }
1028 
1029   // A generic CAS; success or failure is in the EQ flag.
1030   // Clobbers rscratch1
1031   void cmpxchg(Register addr, Register expected, Register new_val,
1032                enum operand_size size,
1033                bool acquire, bool release, bool weak,
1034                Register result);
1035 private:
1036   void compare_eq(Register rn, Register rm, enum operand_size size);
1037 
1038 public:
1039   // Calls
1040 
1041   address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1042 
1043   static bool far_branches() {
1044     return ReservedCodeCacheSize > branch_range || UseAOT;
1045   }
1046 
1047   // Jumps that can reach anywhere in the code cache.
1048   // Trashes tmp.
1049   void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1050   void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1051 
1052   static int far_branch_size() {
1053     if (far_branches()) {
1054       return 3 * 4;  // adrp, add, br
1055     } else {
1056       return 4;
1057     }
1058   }
1059 
1060   // Emit the CompiledIC call idiom
1061   address ic_call(address entry, jint method_index = 0);
1062 
1063 public:
1064 
1065   // Data
1066 
1067   void mov_metadata(Register dst, Metadata* obj);
1068   Address allocate_metadata_address(Metadata* obj);
1069   Address constant_oop_address(jobject obj);
1070 
1071   void movoop(Register dst, jobject obj, bool immediate = false);
1072 
1073   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1074   void kernel_crc32(Register crc, Register buf, Register len,
1075         Register table0, Register table1, Register table2, Register table3,
1076         Register tmp, Register tmp2, Register tmp3);
1077   // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1078   void kernel_crc32c(Register crc, Register buf, Register len,
1079         Register table0, Register table1, Register table2, Register table3,
1080         Register tmp, Register tmp2, Register tmp3);
1081 
1082   // Stack push and pop individual 64 bit registers
1083   void push(Register src);
1084   void pop(Register dst);
1085 
1086   // push all registers onto the stack
1087   void pusha();
1088   void popa();
1089 
1090   void repne_scan(Register addr, Register value, Register count,
1091                   Register scratch);
1092   void repne_scanw(Register addr, Register value, Register count,
1093                    Register scratch);
1094 
1095   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1096   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1097 
1098   // If a constant does not fit in an immediate field, generate some
1099   // number of MOV instructions and then perform the operation
1100   void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1101                              add_sub_imm_insn insn1,
1102                              add_sub_reg_insn insn2);
1103   // Seperate vsn which sets the flags
1104   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1105                              add_sub_imm_insn insn1,
1106                              add_sub_reg_insn insn2);
1107 
1108 #define WRAP(INSN)                                                      \
1109   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1110     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1111   }                                                                     \
1112                                                                         \
1113   void INSN(Register Rd, Register Rn, Register Rm,                      \
1114              enum shift_kind kind, unsigned shift = 0) {                \
1115     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1116   }                                                                     \
1117                                                                         \
1118   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1119     Assembler::INSN(Rd, Rn, Rm);                                        \
1120   }                                                                     \
1121                                                                         \
1122   void INSN(Register Rd, Register Rn, Register Rm,                      \
1123            ext::operation option, int amount = 0) {                     \
1124     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1125   }
1126 
1127   WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1128 
1129 #undef WRAP
1130 #define WRAP(INSN)                                                      \
1131   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1132     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1133   }                                                                     \
1134                                                                         \
1135   void INSN(Register Rd, Register Rn, Register Rm,                      \
1136              enum shift_kind kind, unsigned shift = 0) {                \
1137     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1138   }                                                                     \
1139                                                                         \
1140   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1141     Assembler::INSN(Rd, Rn, Rm);                                        \
1142   }                                                                     \
1143                                                                         \
1144   void INSN(Register Rd, Register Rn, Register Rm,                      \
1145            ext::operation option, int amount = 0) {                     \
1146     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1147   }
1148 
1149   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1150 
1151   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1152   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1153   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1154   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1155 
1156   void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1157 
1158 
1159   enum RegState {
1160      reg_readonly,
1161      reg_writable,
1162      reg_written
1163   };
1164 
1165 // Unpack all value type arguments passed as oops 
1166   void unpack_value_args(Compile* C, bool receiver_only);
1167   bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[], int ret_off);
1168   bool unpack_value_helper(const GrowableArray<SigEntry>* sig, int& sig_index, VMReg from, VMRegPair* regs_to, int& to_index, RegState reg_state[], int ret_off);
1169   void verified_entry(Compile* C, int sp_inc);
1170 
1171   void tableswitch(Register index, jint lowbound, jint highbound,
1172                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1173     adr(rscratch1, jumptable);
1174     subsw(rscratch2, index, lowbound);
1175     subsw(zr, rscratch2, highbound - lowbound);
1176     br(Assembler::HS, jumptable_end);
1177     add(rscratch1, rscratch1, rscratch2,
1178         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1179     br(rscratch1);
1180   }
1181 
1182   // Form an address from base + offset in Rd.  Rd may or may not
1183   // actually be used: you must use the Address that is returned.  It
1184   // is up to you to ensure that the shift provided matches the size
1185   // of your data.
1186   Address form_address(Register Rd, Register base, long byte_offset, int shift);
1187 
1188   // Return true iff an address is within the 48-bit AArch64 address
1189   // space.
1190   bool is_valid_AArch64_address(address a) {
1191     return ((uint64_t)a >> 48) == 0;
1192   }
1193 
1194   // Load the base of the cardtable byte map into reg.
1195   void load_byte_map_base(Register reg);
1196 
1197   // Prolog generator routines to support switch between x86 code and
1198   // generated ARM code
1199 
1200   // routine to generate an x86 prolog for a stub function which
1201   // bootstraps into the generated ARM code which directly follows the
1202   // stub
1203   //
1204 
1205   public:
1206   // enum used for aarch64--x86 linkage to define return type of x86 function
1207   enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1208 
1209 #ifdef BUILTIN_SIM
1210   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1211 #else
1212   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1213 #endif
1214 
1215   // special version of call_VM_leaf_base needed for aarch64 simulator
1216   // where we need to specify both the gp and fp arg counts and the
1217   // return type so that the linkage routine from aarch64 to x86 and
1218   // back knows which aarch64 registers to copy to x86 registers and
1219   // which x86 result register to copy back to an aarch64 register
1220 
1221   void call_VM_leaf_base1(
1222     address  entry_point,             // the entry point
1223     int      number_of_gp_arguments,  // the number of gp reg arguments to pass
1224     int      number_of_fp_arguments,  // the number of fp reg arguments to pass
1225     ret_type type,                    // the return type for the call
1226     Label*   retaddr = NULL
1227   );
1228 
1229   void ldr_constant(Register dest, const Address &const_addr) {
1230     if (NearCpool) {
1231       ldr(dest, const_addr);
1232     } else {
1233       unsigned long offset;
1234       adrp(dest, InternalAddress(const_addr.target()), offset);
1235       ldr(dest, Address(dest, offset));
1236     }
1237   }
1238 
1239   address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1240   address read_polling_page(Register r, relocInfo::relocType rtype);
1241   void get_polling_page(Register dest, address page, relocInfo::relocType rtype);
1242 
1243   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1244   void update_byte_crc32(Register crc, Register val, Register table);
1245   void update_word_crc32(Register crc, Register v, Register tmp,
1246         Register table0, Register table1, Register table2, Register table3,
1247         bool upper = false);
1248 
1249   void string_compare(Register str1, Register str2,
1250                       Register cnt1, Register cnt2, Register result,
1251                       Register tmp1, Register tmp2, FloatRegister vtmp1,
1252                       FloatRegister vtmp2, FloatRegister vtmp3, int ae);
1253 
1254   void has_negatives(Register ary1, Register len, Register result);
1255 
1256   void arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1257                      Register tmp1, Register tmp2, Register tmp3, int elem_size);
1258 
1259   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1260                      int elem_size);
1261 
1262   void fill_words(Register base, Register cnt, Register value);
1263   void fill_words(Register base, u_int64_t cnt, Register value);
1264 
1265   void zero_words(Register base, u_int64_t cnt);
1266   void zero_words(Register ptr, Register cnt);
1267   void zero_dcache_blocks(Register base, Register cnt);
1268 
1269   static const int zero_words_block_size;
1270 
1271   void byte_array_inflate(Register src, Register dst, Register len,
1272                           FloatRegister vtmp1, FloatRegister vtmp2,
1273                           FloatRegister vtmp3, Register tmp4);
1274 
1275   void char_array_compress(Register src, Register dst, Register len,
1276                            FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1277                            FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1278                            Register result);
1279 
1280   void encode_iso_array(Register src, Register dst,
1281                         Register len, Register result,
1282                         FloatRegister Vtmp1, FloatRegister Vtmp2,
1283                         FloatRegister Vtmp3, FloatRegister Vtmp4);
1284   void string_indexof(Register str1, Register str2,
1285                       Register cnt1, Register cnt2,
1286                       Register tmp1, Register tmp2,
1287                       Register tmp3, Register tmp4,
1288                       Register tmp5, Register tmp6,
1289                       int int_cnt1, Register result, int ae);
1290   void string_indexof_char(Register str1, Register cnt1,
1291                            Register ch, Register result,
1292                            Register tmp1, Register tmp2, Register tmp3);
1293   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1294                 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1295                 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1296                 FloatRegister tmpC4, Register tmp1, Register tmp2,
1297                 Register tmp3, Register tmp4, Register tmp5);
1298   void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1299       address pio2, address dsin_coef, address dcos_coef);
1300  private:
1301   // begin trigonometric functions support block
1302   void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1303   void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1304   void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1305   void generate_kernel_cos(FloatRegister x, address dcos_coef);
1306   // end trigonometric functions support block
1307   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1308                        Register src1, Register src2);
1309   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1310     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1311   }
1312   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1313                              Register y, Register y_idx, Register z,
1314                              Register carry, Register product,
1315                              Register idx, Register kdx);
1316   void multiply_128_x_128_loop(Register y, Register z,
1317                                Register carry, Register carry2,
1318                                Register idx, Register jdx,
1319                                Register yz_idx1, Register yz_idx2,
1320                                Register tmp, Register tmp3, Register tmp4,
1321                                Register tmp7, Register product_hi);
1322   void kernel_crc32_using_crc32(Register crc, Register buf,
1323         Register len, Register tmp0, Register tmp1, Register tmp2,
1324         Register tmp3);
1325   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1326         Register len, Register tmp0, Register tmp1, Register tmp2,
1327         Register tmp3);
1328 public:
1329   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1330                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1331                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1332   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1333   // ISB may be needed because of a safepoint
1334   void maybe_isb() { isb(); }
1335 
1336 private:
1337   // Return the effective address r + (r1 << ext) + offset.
1338   // Uses rscratch2.
1339   Address offsetted_address(Register r, Register r1, Address::extend ext,
1340                             int offset, int size);
1341 
1342 private:
1343   // Returns an address on the stack which is reachable with a ldr/str of size
1344   // Uses rscratch2 if the address is not directly reachable
1345   Address spill_address(int size, int offset, Register tmp=rscratch2);
1346 
1347   bool merge_alignment_check(Register base, size_t size, long cur_offset, long prev_offset) const;
1348 
1349   // Check whether two loads/stores can be merged into ldp/stp.
1350   bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1351 
1352   // Merge current load/store with previous load/store into ldp/stp.
1353   void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1354 
1355   // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1356   bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1357 
1358 public:
1359   void spill(Register Rx, bool is64, int offset) {
1360     if (is64) {
1361       str(Rx, spill_address(8, offset));
1362     } else {
1363       strw(Rx, spill_address(4, offset));
1364     }
1365   }
1366   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1367     str(Vx, T, spill_address(1 << (int)T, offset));
1368   }
1369   void unspill(Register Rx, bool is64, int offset) {
1370     if (is64) {
1371       ldr(Rx, spill_address(8, offset));
1372     } else {
1373       ldrw(Rx, spill_address(4, offset));
1374     }
1375   }
1376   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1377     ldr(Vx, T, spill_address(1 << (int)T, offset));
1378   }
1379   void spill_copy128(int src_offset, int dst_offset,
1380                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1381     if (src_offset < 512 && (src_offset & 7) == 0 &&
1382         dst_offset < 512 && (dst_offset & 7) == 0) {
1383       ldp(tmp1, tmp2, Address(sp, src_offset));
1384       stp(tmp1, tmp2, Address(sp, dst_offset));
1385     } else {
1386       unspill(tmp1, true, src_offset);
1387       spill(tmp1, true, dst_offset);
1388       unspill(tmp1, true, src_offset+8);
1389       spill(tmp1, true, dst_offset+8);
1390     }
1391   }
1392 };
1393 
1394 #ifdef ASSERT
1395 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1396 #endif
1397 
1398 /**
1399  * class SkipIfEqual:
1400  *
1401  * Instantiating this class will result in assembly code being output that will
1402  * jump around any code emitted between the creation of the instance and it's
1403  * automatic destruction at the end of a scope block, depending on the value of
1404  * the flag passed to the constructor, which will be checked at run-time.
1405  */
1406 class SkipIfEqual {
1407  private:
1408   MacroAssembler* _masm;
1409   Label _label;
1410 
1411  public:
1412    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1413    ~SkipIfEqual();
1414 };
1415 
1416 struct tableswitch {
1417   Register _reg;
1418   int _insn_index; jint _first_key; jint _last_key;
1419   Label _after;
1420   Label _branches;
1421 };
1422 
1423 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
--- EOF ---