1 /*
2 * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "code/compiledIC.hpp"
38 #include "gc/shared/barrierSet.hpp"
39 #include "gc/shared/cardTableBarrierSet.hpp"
40 #include "gc/shared/collectedHeap.hpp"
41 #include "nativeInst_aarch64.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "oops/oop.inline.hpp"
44 #include "runtime/frame.inline.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "vmreg_aarch64.inline.hpp"
47
48
49
50 #ifndef PRODUCT
51 #define COMMENT(x) do { __ block_comment(x); } while (0)
52 #else
53 #define COMMENT(x)
54 #endif
55
56 NEEDS_CLEANUP // remove this definitions ?
57 const Register IC_Klass = rscratch2; // where the IC klass is cached
58 const Register SYNC_header = r0; // synchronization header
59 const Register SHIFT_count = r0; // where count for shift operations must be
60
61 #define __ _masm->
62
63
64 static void select_different_registers(Register preserve,
65 Register extra,
66 Register &tmp1,
67 Register &tmp2) {
68 if (tmp1 == preserve) {
69 assert_different_registers(tmp1, tmp2, extra);
70 tmp1 = extra;
71 } else if (tmp2 == preserve) {
72 assert_different_registers(tmp1, tmp2, extra);
73 tmp2 = extra;
74 }
75 assert_different_registers(preserve, tmp1, tmp2);
76 }
77
78
79
80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2,
84 Register &tmp3) {
85 if (tmp1 == preserve) {
86 assert_different_registers(tmp1, tmp2, tmp3, extra);
87 tmp1 = extra;
88 } else if (tmp2 == preserve) {
89 assert_different_registers(tmp1, tmp2, tmp3, extra);
90 tmp2 = extra;
91 } else if (tmp3 == preserve) {
92 assert_different_registers(tmp1, tmp2, tmp3, extra);
93 tmp3 = extra;
94 }
95 assert_different_registers(preserve, tmp1, tmp2, tmp3);
96 }
97
98
99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
100
101
102 LIR_Opr LIR_Assembler::receiverOpr() {
103 return FrameMap::receiver_opr;
104 }
105
106 LIR_Opr LIR_Assembler::osrBufferPointer() {
107 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
108 }
109
110 //--------------fpu register translations-----------------------
111
112
113 address LIR_Assembler::float_constant(float f) {
114 address const_addr = __ float_constant(f);
115 if (const_addr == NULL) {
116 bailout("const section overflow");
117 return __ code()->consts()->start();
118 } else {
119 return const_addr;
120 }
121 }
122
123
124 address LIR_Assembler::double_constant(double d) {
125 address const_addr = __ double_constant(d);
126 if (const_addr == NULL) {
127 bailout("const section overflow");
128 return __ code()->consts()->start();
129 } else {
130 return const_addr;
131 }
132 }
133
134 address LIR_Assembler::int_constant(jlong n) {
135 address const_addr = __ long_constant(n);
136 if (const_addr == NULL) {
137 bailout("const section overflow");
138 return __ code()->consts()->start();
139 } else {
140 return const_addr;
141 }
142 }
143
144 void LIR_Assembler::set_24bit_FPU() { Unimplemented(); }
145
146 void LIR_Assembler::reset_FPU() { Unimplemented(); }
147
148 void LIR_Assembler::fpop() { Unimplemented(); }
149
150 void LIR_Assembler::fxch(int i) { Unimplemented(); }
151
152 void LIR_Assembler::fld(int i) { Unimplemented(); }
153
154 void LIR_Assembler::ffree(int i) { Unimplemented(); }
155
156 void LIR_Assembler::breakpoint() { Unimplemented(); }
157
158 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
159
160 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
161
162 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
163 //-------------------------------------------
164
165 static Register as_reg(LIR_Opr op) {
166 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
167 }
168
169 static jlong as_long(LIR_Opr data) {
170 jlong result;
171 switch (data->type()) {
172 case T_INT:
173 result = (data->as_jint());
174 break;
175 case T_LONG:
176 result = (data->as_jlong());
177 break;
178 default:
179 ShouldNotReachHere();
180 result = 0; // unreachable
181 }
182 return result;
183 }
184
185 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
186 Register base = addr->base()->as_pointer_register();
187 LIR_Opr opr = addr->index();
188 if (opr->is_cpu_register()) {
189 Register index;
190 if (opr->is_single_cpu())
191 index = opr->as_register();
192 else
193 index = opr->as_register_lo();
194 assert(addr->disp() == 0, "must be");
195 switch(opr->type()) {
196 case T_INT:
197 return Address(base, index, Address::sxtw(addr->scale()));
198 case T_LONG:
199 return Address(base, index, Address::lsl(addr->scale()));
200 default:
201 ShouldNotReachHere();
202 }
203 } else {
204 intptr_t addr_offset = intptr_t(addr->disp());
205 if (Address::offset_ok_for_immed(addr_offset, addr->scale()))
206 return Address(base, addr_offset, Address::lsl(addr->scale()));
207 else {
208 __ mov(tmp, addr_offset);
209 return Address(base, tmp, Address::lsl(addr->scale()));
210 }
211 }
212 return Address();
213 }
214
215 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
216 ShouldNotReachHere();
217 return Address();
218 }
219
220 Address LIR_Assembler::as_Address(LIR_Address* addr) {
221 return as_Address(addr, rscratch1);
222 }
223
224 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
225 return as_Address(addr, rscratch1); // Ouch
226 // FIXME: This needs to be much more clever. See x86.
227 }
228
229
230 void LIR_Assembler::osr_entry() {
231 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
232 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
233 ValueStack* entry_state = osr_entry->state();
234 int number_of_locks = entry_state->locks_size();
235
236 // we jump here if osr happens with the interpreter
237 // state set up to continue at the beginning of the
238 // loop that triggered osr - in particular, we have
239 // the following registers setup:
240 //
241 // r2: osr buffer
242 //
243
244 // build frame
245 ciMethod* m = compilation()->method();
246 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes(), needs_stack_repair(), NULL);
247
248 // OSR buffer is
249 //
250 // locals[nlocals-1..0]
251 // monitors[0..number_of_locks]
252 //
253 // locals is a direct copy of the interpreter frame so in the osr buffer
254 // so first slot in the local array is the last local from the interpreter
255 // and last slot is local[0] (receiver) from the interpreter
256 //
257 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
258 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
259 // in the interpreter frame (the method lock if a sync method)
260
261 // Initialize monitors in the compiled activation.
262 // r2: pointer to osr buffer
263 //
264 // All other registers are dead at this point and the locals will be
265 // copied into place by code emitted in the IR.
266
267 Register OSR_buf = osrBufferPointer()->as_pointer_register();
268 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
269 int monitor_offset = BytesPerWord * method()->max_locals() +
270 (2 * BytesPerWord) * (number_of_locks - 1);
271 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
272 // the OSR buffer using 2 word entries: first the lock and then
273 // the oop.
274 for (int i = 0; i < number_of_locks; i++) {
275 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
276 #ifdef ASSERT
277 // verify the interpreter's monitor has a non-null object
278 {
279 Label L;
280 __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
281 __ cbnz(rscratch1, L);
282 __ stop("locked object is NULL");
283 __ bind(L);
284 }
285 #endif
286 __ ldr(r19, Address(OSR_buf, slot_offset + 0));
287 __ str(r19, frame_map()->address_for_monitor_lock(i));
288 __ ldr(r19, Address(OSR_buf, slot_offset + 1*BytesPerWord));
289 __ str(r19, frame_map()->address_for_monitor_object(i));
290 }
291 }
292 }
293
294
295 // inline cache check; done before the frame is built.
296 int LIR_Assembler::check_icache() {
297 Register receiver = FrameMap::receiver_opr->as_register();
298 Register ic_klass = IC_Klass;
299 int start_offset = __ offset();
300 __ inline_cache_check(receiver, ic_klass);
301
302 // if icache check fails, then jump to runtime routine
303 // Note: RECEIVER must still contain the receiver!
304 Label dont;
305 __ br(Assembler::EQ, dont);
306 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
307
308 // We align the verified entry point unless the method body
309 // (including its inline cache check) will fit in a single 64-byte
310 // icache line.
311 if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {
312 // force alignment after the cache check.
313 __ align(CodeEntryAlignment);
314 }
315
316 __ bind(dont);
317 return start_offset;
318 }
319
320 void LIR_Assembler::clinit_barrier(ciMethod* method) {
321 ShouldNotReachHere(); // not implemented
322 }
323
324 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
325 if (o == NULL) {
326 __ mov(reg, zr);
327 } else {
328 __ movoop(reg, o, /*immediate*/true);
329 }
330 }
331
332 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
333 address target = NULL;
334 relocInfo::relocType reloc_type = relocInfo::none;
335
336 switch (patching_id(info)) {
337 case PatchingStub::access_field_id:
338 target = Runtime1::entry_for(Runtime1::access_field_patching_id);
339 reloc_type = relocInfo::section_word_type;
340 break;
341 case PatchingStub::load_klass_id:
342 target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
343 reloc_type = relocInfo::metadata_type;
344 break;
345 case PatchingStub::load_mirror_id:
346 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
347 reloc_type = relocInfo::oop_type;
348 break;
349 case PatchingStub::load_appendix_id:
350 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
351 reloc_type = relocInfo::oop_type;
352 break;
353 default: ShouldNotReachHere();
354 }
355
356 __ far_call(RuntimeAddress(target));
357 add_call_info_here(info);
358 }
359
360 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
361 deoptimize_trap(info);
362 }
363
364
365 // This specifies the rsp decrement needed to build the frame
366 int LIR_Assembler::initial_frame_size_in_bytes() const {
367 // if rounding, must let FrameMap know!
368
369 // The frame_map records size in slots (32bit word)
370
371 // subtract two words to account for return address and link
372 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
373 }
374
375
376 int LIR_Assembler::emit_exception_handler() {
377 // if the last instruction is a call (typically to do a throw which
378 // is coming at the end after block reordering) the return address
379 // must still point into the code area in order to avoid assertion
380 // failures when searching for the corresponding bci => add a nop
381 // (was bug 5/14/1999 - gri)
382 __ nop();
383
384 // generate code for exception handler
385 address handler_base = __ start_a_stub(exception_handler_size());
386 if (handler_base == NULL) {
387 // not enough space left for the handler
388 bailout("exception handler overflow");
389 return -1;
390 }
391
392 int offset = code_offset();
393
394 // the exception oop and pc are in r0, and r3
395 // no other registers need to be preserved, so invalidate them
396 __ invalidate_registers(false, true, true, false, true, true);
397
398 // check that there is really an exception
399 __ verify_not_null_oop(r0);
400
401 // search an exception handler (r0: exception oop, r3: throwing pc)
402 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); __ should_not_reach_here();
403 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
404 __ end_a_stub();
405
406 return offset;
407 }
408
409
410 // Emit the code to remove the frame from the stack in the exception
411 // unwind path.
412 int LIR_Assembler::emit_unwind_handler() {
413 #ifndef PRODUCT
414 if (CommentedAssembly) {
415 _masm->block_comment("Unwind handler");
416 }
417 #endif
418
419 int offset = code_offset();
420
421 // Fetch the exception from TLS and clear out exception related thread state
422 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
423 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
424 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
425
426 __ bind(_unwind_handler_entry);
427 __ verify_not_null_oop(r0);
428 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
429 __ mov(r19, r0); // Preserve the exception
430 }
431
432 // Preform needed unlocking
433 MonitorExitStub* stub = NULL;
434 if (method()->is_synchronized()) {
435 monitor_address(0, FrameMap::r0_opr);
436 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
437 __ unlock_object(r5, r4, r0, *stub->entry());
438 __ bind(*stub->continuation());
439 }
440
441 if (compilation()->env()->dtrace_method_probes()) {
442 __ call_Unimplemented();
443 #if 0
444 __ movptr(Address(rsp, 0), rax);
445 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
446 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
447 #endif
448 }
449
450 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
451 __ mov(r0, r19); // Restore the exception
452 }
453
454 // remove the activation and dispatch to the unwind handler
455 __ block_comment("remove_frame and dispatch to the unwind handler");
456 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
457 __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
458
459 // Emit the slow path assembly
460 if (stub != NULL) {
461 stub->emit_code(this);
462 }
463
464 return offset;
465 }
466
467
468 int LIR_Assembler::emit_deopt_handler() {
469 // if the last instruction is a call (typically to do a throw which
470 // is coming at the end after block reordering) the return address
471 // must still point into the code area in order to avoid assertion
472 // failures when searching for the corresponding bci => add a nop
473 // (was bug 5/14/1999 - gri)
474 __ nop();
475
476 // generate code for exception handler
477 address handler_base = __ start_a_stub(deopt_handler_size());
478 if (handler_base == NULL) {
479 // not enough space left for the handler
480 bailout("deopt handler overflow");
481 return -1;
482 }
483
484 int offset = code_offset();
485
486 __ adr(lr, pc());
487 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
488 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
489 __ end_a_stub();
490
491 return offset;
492 }
493
494 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
495 _masm->code_section()->relocate(adr, relocInfo::poll_type);
496 int pc_offset = code_offset();
497 flush_debug_info(pc_offset);
498 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
499 if (info->exception_handlers() != NULL) {
500 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
501 }
502 }
503
504 void LIR_Assembler::return_op(LIR_Opr result) {
505 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
506
507 ciMethod* method = compilation()->method();
508 // Pop the stack before the safepoint code
509 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
510
511 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
512 __ reserved_stack_check();
513 }
514
515 address polling_page(os::get_polling_page());
516 __ read_polling_page(rscratch1, polling_page, relocInfo::poll_return_type);
517 __ ret(lr);
518 }
519
520 void LIR_Assembler::store_value_type_fields_to_buf(ciValueKlass* vk) {
521 __ store_value_type_fields_to_buf(vk);
522 }
523
524 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
525 address polling_page(os::get_polling_page());
526 guarantee(info != NULL, "Shouldn't be NULL");
527 assert(os::is_poll_address(polling_page), "should be");
528 __ get_polling_page(rscratch1, polling_page, relocInfo::poll_type);
529 add_debug_info_for_branch(info); // This isn't just debug info:
530 // it's the oop map
531 __ read_polling_page(rscratch1, relocInfo::poll_type);
532 return __ offset();
533 }
534
535
536 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
537 if (from_reg == r31_sp)
538 from_reg = sp;
539 if (to_reg == r31_sp)
540 to_reg = sp;
541 __ mov(to_reg, from_reg);
542 }
543
544 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
545
546
547 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
548 assert(src->is_constant(), "should not call otherwise");
549 assert(dest->is_register(), "should not call otherwise");
550 LIR_Const* c = src->as_constant_ptr();
551
552 switch (c->type()) {
553 case T_INT: {
554 assert(patch_code == lir_patch_none, "no patching handled here");
555 __ movw(dest->as_register(), c->as_jint());
556 break;
557 }
558
559 case T_ADDRESS: {
560 assert(patch_code == lir_patch_none, "no patching handled here");
561 __ mov(dest->as_register(), c->as_jint());
562 break;
563 }
564
565 case T_LONG: {
566 assert(patch_code == lir_patch_none, "no patching handled here");
567 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
568 break;
569 }
570
571 case T_VALUETYPE:
572 case T_OBJECT: {
573 if (patch_code != lir_patch_none) {
574 jobject2reg_with_patching(dest->as_register(), info);
575 } else {
576 jobject2reg(c->as_jobject(), dest->as_register());
577 }
578 break;
579 }
580
581 case T_METADATA: {
582 if (patch_code != lir_patch_none) {
583 klass2reg_with_patching(dest->as_register(), info);
584 } else {
585 __ mov_metadata(dest->as_register(), c->as_metadata());
586 }
587 break;
588 }
589
590 case T_FLOAT: {
591 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
592 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
593 } else {
594 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
595 __ ldrs(dest->as_float_reg(), Address(rscratch1));
596 }
597 break;
598 }
599
600 case T_DOUBLE: {
601 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
602 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
603 } else {
604 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
605 __ ldrd(dest->as_double_reg(), Address(rscratch1));
606 }
607 break;
608 }
609
610 default:
611 ShouldNotReachHere();
612 }
613 }
614
615 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
616 LIR_Const* c = src->as_constant_ptr();
617 switch (c->type()) {
618 case T_VALUETYPE:
619 case T_OBJECT:
620 {
621 if (! c->as_jobject())
622 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
623 else {
624 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
625 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
626 }
627 }
628 break;
629 case T_ADDRESS:
630 {
631 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
632 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
633 }
634 case T_INT:
635 case T_FLOAT:
636 {
637 Register reg = zr;
638 if (c->as_jint_bits() == 0)
639 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
640 else {
641 __ movw(rscratch1, c->as_jint_bits());
642 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
643 }
644 }
645 break;
646 case T_LONG:
647 case T_DOUBLE:
648 {
649 Register reg = zr;
650 if (c->as_jlong_bits() == 0)
651 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
652 lo_word_offset_in_bytes));
653 else {
654 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
655 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
656 lo_word_offset_in_bytes));
657 }
658 }
659 break;
660 default:
661 ShouldNotReachHere();
662 }
663 }
664
665 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
666 assert(src->is_constant(), "should not call otherwise");
667 LIR_Const* c = src->as_constant_ptr();
668 LIR_Address* to_addr = dest->as_address_ptr();
669
670 void (Assembler::* insn)(Register Rt, const Address &adr);
671
672 switch (type) {
673 case T_ADDRESS:
674 assert(c->as_jint() == 0, "should be");
675 insn = &Assembler::str;
676 break;
677 case T_LONG:
678 assert(c->as_jlong() == 0, "should be");
679 insn = &Assembler::str;
680 break;
681 case T_INT:
682 assert(c->as_jint() == 0, "should be");
683 insn = &Assembler::strw;
684 break;
685 case T_VALUETYPE: // DMS CHECK: the code is significantly differ from x86
686 case T_OBJECT:
687 case T_ARRAY:
688 assert(c->as_jobject() == 0, "should be");
689 if (UseCompressedOops && !wide) {
690 insn = &Assembler::strw;
691 } else {
692 insn = &Assembler::str;
693 }
694 break;
695 case T_CHAR:
696 case T_SHORT:
697 assert(c->as_jint() == 0, "should be");
698 insn = &Assembler::strh;
699 break;
700 case T_BOOLEAN:
701 case T_BYTE:
702 assert(c->as_jint() == 0, "should be");
703 insn = &Assembler::strb;
704 break;
705 default:
706 ShouldNotReachHere();
707 insn = &Assembler::str; // unreachable
708 }
709
710 if (info) add_debug_info_for_null_check_here(info);
711 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
712 }
713
714 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
715 assert(src->is_register(), "should not call otherwise");
716 assert(dest->is_register(), "should not call otherwise");
717
718 // move between cpu-registers
719 if (dest->is_single_cpu()) {
720 if (src->type() == T_LONG) {
721 // Can do LONG -> OBJECT
722 move_regs(src->as_register_lo(), dest->as_register());
723 return;
724 }
725 assert(src->is_single_cpu(), "must match");
726 if (src->type() == T_OBJECT || src->type() == T_VALUETYPE) {
727 __ verify_oop(src->as_register());
728 }
729 move_regs(src->as_register(), dest->as_register());
730
731 } else if (dest->is_double_cpu()) {
732 if (src->type() == T_OBJECT || src->type() == T_ARRAY || src->type() == T_VALUETYPE) {
733 // Surprising to me but we can see move of a long to t_object
734 __ verify_oop(src->as_register());
735 move_regs(src->as_register(), dest->as_register_lo());
736 return;
737 }
738 assert(src->is_double_cpu(), "must match");
739 Register f_lo = src->as_register_lo();
740 Register f_hi = src->as_register_hi();
741 Register t_lo = dest->as_register_lo();
742 Register t_hi = dest->as_register_hi();
743 assert(f_hi == f_lo, "must be same");
744 assert(t_hi == t_lo, "must be same");
745 move_regs(f_lo, t_lo);
746
747 } else if (dest->is_single_fpu()) {
748 __ fmovs(dest->as_float_reg(), src->as_float_reg());
749
750 } else if (dest->is_double_fpu()) {
751 __ fmovd(dest->as_double_reg(), src->as_double_reg());
752
753 } else {
754 ShouldNotReachHere();
755 }
756 }
757
758 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
759 if (src->is_single_cpu()) {
760 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
761 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
762 __ verify_oop(src->as_register());
763 } else if (type == T_METADATA || type == T_DOUBLE) {
764 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
765 } else {
766 __ strw(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
767 }
768
769 } else if (src->is_double_cpu()) {
770 Address dest_addr_LO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
771 __ str(src->as_register_lo(), dest_addr_LO);
772
773 } else if (src->is_single_fpu()) {
774 Address dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
775 __ strs(src->as_float_reg(), dest_addr);
776
777 } else if (src->is_double_fpu()) {
778 Address dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
779 __ strd(src->as_double_reg(), dest_addr);
780
781 } else {
782 ShouldNotReachHere();
783 }
784
785 }
786
787
788 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
789 LIR_Address* to_addr = dest->as_address_ptr();
790 PatchingStub* patch = NULL;
791 Register compressed_src = rscratch1;
792
793 if (patch_code != lir_patch_none) {
794 deoptimize_trap(info);
795 return;
796 }
797
798 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
799 __ verify_oop(src->as_register());
800
801 if (UseCompressedOops && !wide) {
802 __ encode_heap_oop(compressed_src, src->as_register());
803 } else {
804 compressed_src = src->as_register();
805 }
806 }
807
808 int null_check_here = code_offset();
809 switch (type) {
810 case T_FLOAT: {
811 __ strs(src->as_float_reg(), as_Address(to_addr));
812 break;
813 }
814
815 case T_DOUBLE: {
816 __ strd(src->as_double_reg(), as_Address(to_addr));
817 break;
818 }
819
820 case T_VALUETYPE: // fall through
821 case T_ARRAY: // fall through
822 case T_OBJECT: // fall through
823 if (UseCompressedOops && !wide) {
824 __ strw(compressed_src, as_Address(to_addr, rscratch2));
825 } else {
826 __ str(compressed_src, as_Address(to_addr));
827 }
828 break;
829 case T_METADATA:
830 // We get here to store a method pointer to the stack to pass to
831 // a dtrace runtime call. This can't work on 64 bit with
832 // compressed klass ptrs: T_METADATA can be a compressed klass
833 // ptr or a 64 bit method pointer.
834 ShouldNotReachHere();
835 __ str(src->as_register(), as_Address(to_addr));
836 break;
837 case T_ADDRESS:
838 __ str(src->as_register(), as_Address(to_addr));
839 break;
840 case T_INT:
841 __ strw(src->as_register(), as_Address(to_addr));
842 break;
843
844 case T_LONG: {
845 __ str(src->as_register_lo(), as_Address_lo(to_addr));
846 break;
847 }
848
849 case T_BYTE: // fall through
850 case T_BOOLEAN: {
851 __ strb(src->as_register(), as_Address(to_addr));
852 break;
853 }
854
855 case T_CHAR: // fall through
856 case T_SHORT:
857 __ strh(src->as_register(), as_Address(to_addr));
858 break;
859
860 default:
861 ShouldNotReachHere();
862 }
863 if (info != NULL) {
864 add_debug_info_for_null_check(null_check_here, info);
865 }
866 }
867
868
869 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
870 assert(src->is_stack(), "should not call otherwise");
871 assert(dest->is_register(), "should not call otherwise");
872
873 if (dest->is_single_cpu()) {
874 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
875 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
876 __ verify_oop(dest->as_register());
877 } else if (type == T_METADATA) {
878 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
879 } else {
880 __ ldrw(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
881 }
882
883 } else if (dest->is_double_cpu()) {
884 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
885 __ ldr(dest->as_register_lo(), src_addr_LO);
886
887 } else if (dest->is_single_fpu()) {
888 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
889 __ ldrs(dest->as_float_reg(), src_addr);
890
891 } else if (dest->is_double_fpu()) {
892 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
893 __ ldrd(dest->as_double_reg(), src_addr);
894
895 } else {
896 ShouldNotReachHere();
897 }
898 }
899
900
901 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
902 address target = NULL;
903 relocInfo::relocType reloc_type = relocInfo::none;
904
905 switch (patching_id(info)) {
906 case PatchingStub::access_field_id:
907 target = Runtime1::entry_for(Runtime1::access_field_patching_id);
908 reloc_type = relocInfo::section_word_type;
909 break;
910 case PatchingStub::load_klass_id:
911 target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
912 reloc_type = relocInfo::metadata_type;
913 break;
914 case PatchingStub::load_mirror_id:
915 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
916 reloc_type = relocInfo::oop_type;
917 break;
918 case PatchingStub::load_appendix_id:
919 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
920 reloc_type = relocInfo::oop_type;
921 break;
922 default: ShouldNotReachHere();
923 }
924
925 __ far_call(RuntimeAddress(target));
926 add_call_info_here(info);
927 }
928
929 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
930
931 LIR_Opr temp;
932 if (type == T_LONG || type == T_DOUBLE)
933 temp = FrameMap::rscratch1_long_opr;
934 else
935 temp = FrameMap::rscratch1_opr;
936
937 stack2reg(src, temp, src->type());
938 reg2stack(temp, dest, dest->type(), false);
939 }
940
941
942 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
943 LIR_Address* addr = src->as_address_ptr();
944 LIR_Address* from_addr = src->as_address_ptr();
945
946 if (addr->base()->type() == T_OBJECT || addr->base()->type() == T_VALUETYPE) {
947 __ verify_oop(addr->base()->as_pointer_register());
948 }
949
950 if (patch_code != lir_patch_none) {
951 deoptimize_trap(info);
952 return;
953 }
954
955 if (info != NULL) {
956 add_debug_info_for_null_check_here(info);
957 }
958 int null_check_here = code_offset();
959 switch (type) {
960 case T_FLOAT: {
961 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
962 break;
963 }
964
965 case T_DOUBLE: {
966 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
967 break;
968 }
969
970 case T_VALUETYPE: // fall through
971 case T_ARRAY: // fall through
972 case T_OBJECT: // fall through
973 if (UseCompressedOops && !wide) {
974 __ ldrw(dest->as_register(), as_Address(from_addr));
975 } else {
976 __ ldr(dest->as_register(), as_Address(from_addr));
977 }
978 break;
979 case T_METADATA:
980 // We get here to store a method pointer to the stack to pass to
981 // a dtrace runtime call. This can't work on 64 bit with
982 // compressed klass ptrs: T_METADATA can be a compressed klass
983 // ptr or a 64 bit method pointer.
984 ShouldNotReachHere();
985 __ ldr(dest->as_register(), as_Address(from_addr));
986 break;
987 case T_ADDRESS:
988 // FIXME: OMG this is a horrible kludge. Any offset from an
989 // address that matches klass_offset_in_bytes() will be loaded
990 // as a word, not a long.
991 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
992 __ ldrw(dest->as_register(), as_Address(from_addr));
993 } else {
994 __ ldr(dest->as_register(), as_Address(from_addr));
995 }
996 break;
997 case T_INT:
998 __ ldrw(dest->as_register(), as_Address(from_addr));
999 break;
1000
1001 case T_LONG: {
1002 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1003 break;
1004 }
1005
1006 case T_BYTE:
1007 __ ldrsb(dest->as_register(), as_Address(from_addr));
1008 break;
1009 case T_BOOLEAN: {
1010 __ ldrb(dest->as_register(), as_Address(from_addr));
1011 break;
1012 }
1013
1014 case T_CHAR:
1015 __ ldrh(dest->as_register(), as_Address(from_addr));
1016 break;
1017 case T_SHORT:
1018 __ ldrsh(dest->as_register(), as_Address(from_addr));
1019 break;
1020
1021 default:
1022 ShouldNotReachHere();
1023 }
1024
1025 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
1026 if (UseCompressedOops && !wide) {
1027 __ decode_heap_oop(dest->as_register());
1028 }
1029
1030 if (!UseZGC) {
1031 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1032 __ verify_oop(dest->as_register());
1033 }
1034 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1035 if (UseCompressedClassPointers) {
1036 __ andr(dest->as_register(), dest->as_register(), oopDesc::compressed_klass_mask());
1037 __ decode_klass_not_null(dest->as_register());
1038 } else {
1039 __ ubfm(dest->as_register(), dest->as_register(), 0, 63 - oopDesc::storage_props_nof_bits);
1040 }
1041 }
1042 }
1043
1044 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
1045 assert(dst->is_cpu_register(), "must be");
1046 assert(dst->type() == src->type(), "must be");
1047
1048 if (src->is_cpu_register()) {
1049 reg2reg(src, dst);
1050 } else if (src->is_stack()) {
1051 stack2reg(src, dst, dst->type());
1052 } else if (src->is_constant()) {
1053 const2reg(src, dst, lir_patch_none, NULL);
1054 } else {
1055 ShouldNotReachHere();
1056 }
1057 }
1058
1059 int LIR_Assembler::array_element_size(BasicType type) const {
1060 int elem_size = type2aelembytes(type);
1061 return exact_log2(elem_size);
1062 }
1063
1064
1065 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1066 switch (op->code()) {
1067 case lir_idiv:
1068 case lir_irem:
1069 arithmetic_idiv(op->code(),
1070 op->in_opr1(),
1071 op->in_opr2(),
1072 op->in_opr3(),
1073 op->result_opr(),
1074 op->info());
1075 break;
1076 case lir_fmad:
1077 __ fmaddd(op->result_opr()->as_double_reg(),
1078 op->in_opr1()->as_double_reg(),
1079 op->in_opr2()->as_double_reg(),
1080 op->in_opr3()->as_double_reg());
1081 break;
1082 case lir_fmaf:
1083 __ fmadds(op->result_opr()->as_float_reg(),
1084 op->in_opr1()->as_float_reg(),
1085 op->in_opr2()->as_float_reg(),
1086 op->in_opr3()->as_float_reg());
1087 break;
1088 default: ShouldNotReachHere(); break;
1089 }
1090 }
1091
1092 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1093 #ifdef ASSERT
1094 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1095 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1096 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1097 #endif
1098
1099 if (op->cond() == lir_cond_always) {
1100 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1101 __ b(*(op->label()));
1102 } else {
1103 Assembler::Condition acond;
1104 if (op->code() == lir_cond_float_branch) {
1105 bool is_unordered = (op->ublock() == op->block());
1106 // Assembler::EQ does not permit unordered branches, so we add
1107 // another branch here. Likewise, Assembler::NE does not permit
1108 // ordered branches.
1109 if ((is_unordered && op->cond() == lir_cond_equal)
1110 || (!is_unordered && op->cond() == lir_cond_notEqual))
1111 __ br(Assembler::VS, *(op->ublock()->label()));
1112 switch(op->cond()) {
1113 case lir_cond_equal: acond = Assembler::EQ; break;
1114 case lir_cond_notEqual: acond = Assembler::NE; break;
1115 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1116 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1117 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1118 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1119 default: ShouldNotReachHere();
1120 acond = Assembler::EQ; // unreachable
1121 }
1122 } else {
1123 switch (op->cond()) {
1124 case lir_cond_equal: acond = Assembler::EQ; break;
1125 case lir_cond_notEqual: acond = Assembler::NE; break;
1126 case lir_cond_less: acond = Assembler::LT; break;
1127 case lir_cond_lessEqual: acond = Assembler::LE; break;
1128 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1129 case lir_cond_greater: acond = Assembler::GT; break;
1130 case lir_cond_belowEqual: acond = Assembler::LS; break;
1131 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1132 default: ShouldNotReachHere();
1133 acond = Assembler::EQ; // unreachable
1134 }
1135 }
1136 __ br(acond,*(op->label()));
1137 }
1138 }
1139
1140
1141
1142 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1143 LIR_Opr src = op->in_opr();
1144 LIR_Opr dest = op->result_opr();
1145
1146 switch (op->bytecode()) {
1147 case Bytecodes::_i2f:
1148 {
1149 __ scvtfws(dest->as_float_reg(), src->as_register());
1150 break;
1151 }
1152 case Bytecodes::_i2d:
1153 {
1154 __ scvtfwd(dest->as_double_reg(), src->as_register());
1155 break;
1156 }
1157 case Bytecodes::_l2d:
1158 {
1159 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1160 break;
1161 }
1162 case Bytecodes::_l2f:
1163 {
1164 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1165 break;
1166 }
1167 case Bytecodes::_f2d:
1168 {
1169 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1170 break;
1171 }
1172 case Bytecodes::_d2f:
1173 {
1174 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1175 break;
1176 }
1177 case Bytecodes::_i2c:
1178 {
1179 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1180 break;
1181 }
1182 case Bytecodes::_i2l:
1183 {
1184 __ sxtw(dest->as_register_lo(), src->as_register());
1185 break;
1186 }
1187 case Bytecodes::_i2s:
1188 {
1189 __ sxth(dest->as_register(), src->as_register());
1190 break;
1191 }
1192 case Bytecodes::_i2b:
1193 {
1194 __ sxtb(dest->as_register(), src->as_register());
1195 break;
1196 }
1197 case Bytecodes::_l2i:
1198 {
1199 _masm->block_comment("FIXME: This could be a no-op");
1200 __ uxtw(dest->as_register(), src->as_register_lo());
1201 break;
1202 }
1203 case Bytecodes::_d2l:
1204 {
1205 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1206 break;
1207 }
1208 case Bytecodes::_f2i:
1209 {
1210 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1211 break;
1212 }
1213 case Bytecodes::_f2l:
1214 {
1215 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1216 break;
1217 }
1218 case Bytecodes::_d2i:
1219 {
1220 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1221 break;
1222 }
1223 default: ShouldNotReachHere();
1224 }
1225 }
1226
1227 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1228 if (op->init_check()) {
1229 __ ldrb(rscratch1, Address(op->klass()->as_register(),
1230 InstanceKlass::init_state_offset()));
1231 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1232 add_debug_info_for_null_check_here(op->stub()->info());
1233 __ br(Assembler::NE, *op->stub()->entry());
1234 }
1235 __ allocate_object(op->obj()->as_register(),
1236 op->tmp1()->as_register(),
1237 op->tmp2()->as_register(),
1238 op->header_size(),
1239 op->object_size(),
1240 op->klass()->as_register(),
1241 *op->stub()->entry());
1242 __ bind(*op->stub()->continuation());
1243 }
1244
1245 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1246 Register len = op->len()->as_register();
1247 __ uxtw(len, len);
1248
1249 if (UseSlowPath || op->type() == T_VALUETYPE ||
1250 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1251 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1252 __ b(*op->stub()->entry());
1253 } else {
1254 Register tmp1 = op->tmp1()->as_register();
1255 Register tmp2 = op->tmp2()->as_register();
1256 Register tmp3 = op->tmp3()->as_register();
1257 if (len == tmp1) {
1258 tmp1 = tmp3;
1259 } else if (len == tmp2) {
1260 tmp2 = tmp3;
1261 } else if (len == tmp3) {
1262 // everything is ok
1263 } else {
1264 __ mov(tmp3, len);
1265 }
1266 __ allocate_array(op->obj()->as_register(),
1267 len,
1268 tmp1,
1269 tmp2,
1270 arrayOopDesc::header_size(op->type()),
1271 array_element_size(op->type()),
1272 op->klass()->as_register(),
1273 *op->stub()->entry());
1274 }
1275 __ bind(*op->stub()->continuation());
1276 }
1277
1278 void LIR_Assembler::type_profile_helper(Register mdo,
1279 ciMethodData *md, ciProfileData *data,
1280 Register recv, Label* update_done) {
1281 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1282 Label next_test;
1283 // See if the receiver is receiver[n].
1284 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1285 __ ldr(rscratch1, Address(rscratch2));
1286 __ cmp(recv, rscratch1);
1287 __ br(Assembler::NE, next_test);
1288 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1289 __ addptr(data_addr, DataLayout::counter_increment);
1290 __ b(*update_done);
1291 __ bind(next_test);
1292 }
1293
1294 // Didn't find receiver; find next empty slot and fill it in
1295 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1296 Label next_test;
1297 __ lea(rscratch2,
1298 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1299 Address recv_addr(rscratch2);
1300 __ ldr(rscratch1, recv_addr);
1301 __ cbnz(rscratch1, next_test);
1302 __ str(recv, recv_addr);
1303 __ mov(rscratch1, DataLayout::counter_increment);
1304 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1305 __ str(rscratch1, Address(rscratch2));
1306 __ b(*update_done);
1307 __ bind(next_test);
1308 }
1309 }
1310
1311 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1312 // we always need a stub for the failure case.
1313 CodeStub* stub = op->stub();
1314 Register obj = op->object()->as_register();
1315 Register k_RInfo = op->tmp1()->as_register();
1316 Register klass_RInfo = op->tmp2()->as_register();
1317 Register dst = op->result_opr()->as_register();
1318 ciKlass* k = op->klass();
1319 Register Rtmp1 = noreg;
1320
1321 // check if it needs to be profiled
1322 ciMethodData* md;
1323 ciProfileData* data;
1324
1325 const bool should_profile = op->should_profile();
1326
1327 if (should_profile) {
1328 ciMethod* method = op->profiled_method();
1329 assert(method != NULL, "Should have method");
1330 int bci = op->profiled_bci();
1331 md = method->method_data_or_null();
1332 assert(md != NULL, "Sanity");
1333 data = md->bci_to_data(bci);
1334 assert(data != NULL, "need data for type check");
1335 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1336 }
1337 Label profile_cast_success, profile_cast_failure;
1338 Label *success_target = should_profile ? &profile_cast_success : success;
1339 Label *failure_target = should_profile ? &profile_cast_failure : failure;
1340
1341 if (obj == k_RInfo) {
1342 k_RInfo = dst;
1343 } else if (obj == klass_RInfo) {
1344 klass_RInfo = dst;
1345 }
1346 if (k->is_loaded() && !UseCompressedClassPointers) {
1347 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1348 } else {
1349 Rtmp1 = op->tmp3()->as_register();
1350 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1351 }
1352
1353 assert_different_registers(obj, k_RInfo, klass_RInfo);
1354
1355 if (should_profile) {
1356 Label not_null;
1357 __ cbnz(obj, not_null);
1358 // Object is null; update MDO and exit
1359 Register mdo = klass_RInfo;
1360 __ mov_metadata(mdo, md->constant_encoding());
1361 Address data_addr
1362 = __ form_address(rscratch2, mdo,
1363 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1364 0);
1365 __ ldrb(rscratch1, data_addr);
1366 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1367 __ strb(rscratch1, data_addr);
1368 __ b(*obj_is_null);
1369 __ bind(not_null);
1370 } else {
1371 __ cbz(obj, *obj_is_null);
1372 }
1373
1374 if (!k->is_loaded()) {
1375 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1376 } else {
1377 __ mov_metadata(k_RInfo, k->constant_encoding());
1378 }
1379 __ verify_oop(obj);
1380
1381 if (op->fast_check()) {
1382 // get object class
1383 // not a safepoint as obj null check happens earlier
1384 __ load_klass(rscratch1, obj);
1385 __ cmp( rscratch1, k_RInfo);
1386
1387 __ br(Assembler::NE, *failure_target);
1388 // successful cast, fall through to profile or jump
1389 } else {
1390 // get object class
1391 // not a safepoint as obj null check happens earlier
1392 __ load_klass(klass_RInfo, obj);
1393 if (k->is_loaded()) {
1394 // See if we get an immediate positive hit
1395 __ ldr(rscratch1, Address(klass_RInfo, long(k->super_check_offset())));
1396 __ cmp(k_RInfo, rscratch1);
1397 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1398 __ br(Assembler::NE, *failure_target);
1399 // successful cast, fall through to profile or jump
1400 } else {
1401 // See if we get an immediate positive hit
1402 __ br(Assembler::EQ, *success_target);
1403 // check for self
1404 __ cmp(klass_RInfo, k_RInfo);
1405 __ br(Assembler::EQ, *success_target);
1406
1407 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1408 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1409 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1410 // result is a boolean
1411 __ cbzw(klass_RInfo, *failure_target);
1412 // successful cast, fall through to profile or jump
1413 }
1414 } else {
1415 // perform the fast part of the checking logic
1416 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1417 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1418 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1419 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1420 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1421 // result is a boolean
1422 __ cbz(k_RInfo, *failure_target);
1423 // successful cast, fall through to profile or jump
1424 }
1425 }
1426 if (should_profile) {
1427 Register mdo = klass_RInfo, recv = k_RInfo;
1428 __ bind(profile_cast_success);
1429 __ mov_metadata(mdo, md->constant_encoding());
1430 __ load_klass(recv, obj);
1431 Label update_done;
1432 type_profile_helper(mdo, md, data, recv, success);
1433 __ b(*success);
1434
1435 __ bind(profile_cast_failure);
1436 __ mov_metadata(mdo, md->constant_encoding());
1437 Address counter_addr
1438 = __ form_address(rscratch2, mdo,
1439 md->byte_offset_of_slot(data, CounterData::count_offset()),
1440 0);
1441 __ ldr(rscratch1, counter_addr);
1442 __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1443 __ str(rscratch1, counter_addr);
1444 __ b(*failure);
1445 }
1446 __ b(*success);
1447 }
1448
1449
1450 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1451 const bool should_profile = op->should_profile();
1452
1453 LIR_Code code = op->code();
1454 if (code == lir_store_check) {
1455 Register value = op->object()->as_register();
1456 Register array = op->array()->as_register();
1457 Register k_RInfo = op->tmp1()->as_register();
1458 Register klass_RInfo = op->tmp2()->as_register();
1459 Register Rtmp1 = op->tmp3()->as_register();
1460
1461 CodeStub* stub = op->stub();
1462
1463 // check if it needs to be profiled
1464 ciMethodData* md;
1465 ciProfileData* data;
1466
1467 if (should_profile) {
1468 ciMethod* method = op->profiled_method();
1469 assert(method != NULL, "Should have method");
1470 int bci = op->profiled_bci();
1471 md = method->method_data_or_null();
1472 assert(md != NULL, "Sanity");
1473 data = md->bci_to_data(bci);
1474 assert(data != NULL, "need data for type check");
1475 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1476 }
1477 Label profile_cast_success, profile_cast_failure, done;
1478 Label *success_target = should_profile ? &profile_cast_success : &done;
1479 Label *failure_target = should_profile ? &profile_cast_failure : stub->entry();
1480
1481 if (should_profile) {
1482 Label not_null;
1483 __ cbnz(value, not_null);
1484 // Object is null; update MDO and exit
1485 Register mdo = klass_RInfo;
1486 __ mov_metadata(mdo, md->constant_encoding());
1487 Address data_addr
1488 = __ form_address(rscratch2, mdo,
1489 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1490 0);
1491 __ ldrb(rscratch1, data_addr);
1492 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1493 __ strb(rscratch1, data_addr);
1494 __ b(done);
1495 __ bind(not_null);
1496 } else {
1497 __ cbz(value, done);
1498 }
1499
1500 add_debug_info_for_null_check_here(op->info_for_exception());
1501 __ load_klass(k_RInfo, array);
1502 __ load_klass(klass_RInfo, value);
1503
1504 // get instance klass (it's already uncompressed)
1505 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1506 // perform the fast part of the checking logic
1507 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1508 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1509 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1510 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1511 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1512 // result is a boolean
1513 __ cbzw(k_RInfo, *failure_target);
1514 // fall through to the success case
1515
1516 if (should_profile) {
1517 Register mdo = klass_RInfo, recv = k_RInfo;
1518 __ bind(profile_cast_success);
1519 __ mov_metadata(mdo, md->constant_encoding());
1520 __ load_klass(recv, value);
1521 Label update_done;
1522 type_profile_helper(mdo, md, data, recv, &done);
1523 __ b(done);
1524
1525 __ bind(profile_cast_failure);
1526 __ mov_metadata(mdo, md->constant_encoding());
1527 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1528 __ lea(rscratch2, counter_addr);
1529 __ ldr(rscratch1, Address(rscratch2));
1530 __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1531 __ str(rscratch1, Address(rscratch2));
1532 __ b(*stub->entry());
1533 }
1534
1535 __ bind(done);
1536 } else if (code == lir_checkcast) {
1537 Register obj = op->object()->as_register();
1538 Register dst = op->result_opr()->as_register();
1539 Label success;
1540 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1541 __ bind(success);
1542 if (dst != obj) {
1543 __ mov(dst, obj);
1544 }
1545 } else if (code == lir_instanceof) {
1546 Register obj = op->object()->as_register();
1547 Register dst = op->result_opr()->as_register();
1548 Label success, failure, done;
1549 emit_typecheck_helper(op, &success, &failure, &failure);
1550 __ bind(failure);
1551 __ mov(dst, zr);
1552 __ b(done);
1553 __ bind(success);
1554 __ mov(dst, 1);
1555 __ bind(done);
1556 } else {
1557 ShouldNotReachHere();
1558 }
1559 }
1560
1561 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1562 // We are loading/storing an array that *may* be a flattened array (the declared type
1563 // Object[], interface[], or VT?[]). If this array is flattened, take slow path.
1564
1565 __ load_storage_props(op->tmp()->as_register(), op->array()->as_register());
1566 __ tst(op->tmp()->as_register(), ArrayStorageProperties::flattened_value);
1567 __ br(Assembler::NE, *op->stub()->entry());
1568 if (!op->value()->is_illegal()) {
1569 // We are storing into the array.
1570 Label skip;
1571 __ tst(op->tmp()->as_register(), ArrayStorageProperties::null_free_value);
1572 __ br(Assembler::EQ, skip);
1573 // The array is not flattened, but it is null_free. If we are storing
1574 // a null, take the slow path (which will throw NPE).
1575 __ cbz(op->value()->as_register(), *op->stub()->entry());
1576 __ bind(skip);
1577 }
1578
1579 }
1580
1581 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
1582 // This is called when we use aastore into a an array declared as "[LVT;",
1583 // where we know VT is not flattenable (due to ValueArrayElemMaxFlatOops, etc).
1584 // However, we need to do a NULL check if the actual array is a "[QVT;".
1585
1586 __ load_storage_props(op->tmp()->as_register(), op->array()->as_register());
1587 __ mov(rscratch1, (uint64_t) ArrayStorageProperties::null_free_value);
1588 __ cmp(op->tmp()->as_register(), rscratch1);
1589 }
1590
1591 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
1592 Label L_oops_equal;
1593 Label L_oops_not_equal;
1594 Label L_end;
1595
1596 Register left = op->left()->as_register();
1597 Register right = op->right()->as_register();
1598
1599 __ cmp(left, right);
1600 __ br(Assembler::EQ, L_oops_equal);
1601
1602 // (1) Null check -- if one of the operands is null, the other must not be null (because
1603 // the two references are not equal), so they are not substitutable,
1604 // FIXME: do null check only if the operand is nullable
1605 {
1606 __ cbz(left, L_oops_not_equal);
1607 __ cbz(right, L_oops_not_equal);
1608 }
1609
1610
1611 ciKlass* left_klass = op->left_klass();
1612 ciKlass* right_klass = op->right_klass();
1613
1614 // (2) Value object check -- if either of the operands is not a value object,
1615 // they are not substitutable. We do this only if we are not sure that the
1616 // operands are value objects
1617 if ((left_klass == NULL || right_klass == NULL) ||// The klass is still unloaded, or came from a Phi node.
1618 !left_klass->is_valuetype() || !right_klass->is_valuetype()) {
1619 Register tmp1 = rscratch1; /* op->tmp1()->as_register(); */
1620 Register tmp2 = rscratch2; /* op->tmp2()->as_register(); */
1621
1622 __ mov(tmp1, (intptr_t)markOopDesc::always_locked_pattern);
1623
1624 __ ldr(tmp2, Address(left, oopDesc::mark_offset_in_bytes()));
1625 __ andr(tmp1, tmp1, tmp2);
1626
1627 __ ldr(tmp2, Address(right, oopDesc::mark_offset_in_bytes()));
1628 __ andr(tmp1, tmp1, tmp2);
1629
1630 __ mov(tmp2, (intptr_t)markOopDesc::always_locked_pattern);
1631 __ cmp(tmp1, tmp2);
1632 __ br(Assembler::NE, L_oops_not_equal);
1633 }
1634
1635 // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
1636 if (left_klass != NULL && left_klass->is_valuetype() && left_klass == right_klass) {
1637 // No need to load klass -- the operands are statically known to be the same value klass.
1638 __ b(*op->stub()->entry());
1639 } else {
1640 Register left_klass_op = op->left_klass_op()->as_register();
1641 Register right_klass_op = op->right_klass_op()->as_register();
1642
1643 // DMS CHECK, likely x86 bug, make aarch64 implementation correct
1644 __ load_klass(left_klass_op, left);
1645 __ load_klass(right_klass_op, right);
1646 __ cmp(left_klass_op, right_klass_op);
1647 __ br(Assembler::EQ, *op->stub()->entry()); // same klass -> do slow check
1648 // fall through to L_oops_not_equal
1649 }
1650
1651 __ bind(L_oops_not_equal);
1652 move(op->not_equal_result(), op->result_opr());
1653 __ b(L_end);
1654
1655 __ bind(L_oops_equal);
1656 move(op->equal_result(), op->result_opr());
1657 __ b(L_end);
1658
1659 // We've returned from the stub. op->result_opr() contains 0x0 IFF the two
1660 // operands are not substitutable. (Don't compare against 0x1 in case the
1661 // C compiler is naughty)
1662 __ bind(*op->stub()->continuation());
1663
1664 if (op->result_opr()->type() == T_LONG) {
1665 __ cbzw(op->result_opr()->as_register(), L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
1666 } else {
1667 __ cbz(op->result_opr()->as_register(), L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
1668 }
1669
1670 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
1671 // fall-through
1672 __ bind(L_end);
1673
1674 }
1675
1676
1677 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1678 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1679 __ cset(rscratch1, Assembler::NE);
1680 __ membar(__ AnyAny);
1681 }
1682
1683 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1684 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1685 __ cset(rscratch1, Assembler::NE);
1686 __ membar(__ AnyAny);
1687 }
1688
1689
1690 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1691 assert(VM_Version::supports_cx8(), "wrong machine");
1692 Register addr;
1693 if (op->addr()->is_register()) {
1694 addr = as_reg(op->addr());
1695 } else {
1696 assert(op->addr()->is_address(), "what else?");
1697 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1698 assert(addr_ptr->disp() == 0, "need 0 disp");
1699 assert(addr_ptr->index() == LIR_OprDesc::illegalOpr(), "need 0 index");
1700 addr = as_reg(addr_ptr->base());
1701 }
1702 Register newval = as_reg(op->new_value());
1703 Register cmpval = as_reg(op->cmp_value());
1704
1705 if (op->code() == lir_cas_obj) {
1706 if (UseCompressedOops) {
1707 Register t1 = op->tmp1()->as_register();
1708 assert(op->tmp1()->is_valid(), "must be");
1709 __ encode_heap_oop(t1, cmpval);
1710 cmpval = t1;
1711 __ encode_heap_oop(rscratch2, newval);
1712 newval = rscratch2;
1713 casw(addr, newval, cmpval);
1714 } else {
1715 casl(addr, newval, cmpval);
1716 }
1717 } else if (op->code() == lir_cas_int) {
1718 casw(addr, newval, cmpval);
1719 } else {
1720 casl(addr, newval, cmpval);
1721 }
1722 }
1723
1724
1725 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1726
1727 Assembler::Condition acond, ncond;
1728 switch (condition) {
1729 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1730 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1731 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1732 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1733 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1734 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1735 case lir_cond_belowEqual:
1736 case lir_cond_aboveEqual:
1737 default: ShouldNotReachHere();
1738 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1739 }
1740
1741 assert(result->is_single_cpu() || result->is_double_cpu(),
1742 "expect single register for result");
1743 if (opr1->is_constant() && opr2->is_constant()
1744 && opr1->type() == T_INT && opr2->type() == T_INT) {
1745 jint val1 = opr1->as_jint();
1746 jint val2 = opr2->as_jint();
1747 if (val1 == 0 && val2 == 1) {
1748 __ cset(result->as_register(), ncond);
1749 return;
1750 } else if (val1 == 1 && val2 == 0) {
1751 __ cset(result->as_register(), acond);
1752 return;
1753 }
1754 }
1755
1756 if (opr1->is_constant() && opr2->is_constant()
1757 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1758 jlong val1 = opr1->as_jlong();
1759 jlong val2 = opr2->as_jlong();
1760 if (val1 == 0 && val2 == 1) {
1761 __ cset(result->as_register_lo(), ncond);
1762 return;
1763 } else if (val1 == 1 && val2 == 0) {
1764 __ cset(result->as_register_lo(), acond);
1765 return;
1766 }
1767 }
1768
1769 if (opr1->is_stack()) {
1770 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1771 opr1 = FrameMap::rscratch1_opr;
1772 } else if (opr1->is_constant()) {
1773 LIR_Opr tmp
1774 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1775 const2reg(opr1, tmp, lir_patch_none, NULL);
1776 opr1 = tmp;
1777 }
1778
1779 if (opr2->is_stack()) {
1780 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1781 opr2 = FrameMap::rscratch2_opr;
1782 } else if (opr2->is_constant()) {
1783 LIR_Opr tmp
1784 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1785 const2reg(opr2, tmp, lir_patch_none, NULL);
1786 opr2 = tmp;
1787 }
1788
1789 if (result->type() == T_LONG)
1790 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1791 else
1792 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1793 }
1794
1795 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1796 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1797
1798 if (left->is_single_cpu()) {
1799 Register lreg = left->as_register();
1800 Register dreg = as_reg(dest);
1801
1802 if (right->is_single_cpu()) {
1803 // cpu register - cpu register
1804
1805 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1806 "should be");
1807 Register rreg = right->as_register();
1808 switch (code) {
1809 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1810 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1811 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1812 default: ShouldNotReachHere();
1813 }
1814
1815 } else if (right->is_double_cpu()) {
1816 Register rreg = right->as_register_lo();
1817 // single_cpu + double_cpu: can happen with obj+long
1818 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1819 switch (code) {
1820 case lir_add: __ add(dreg, lreg, rreg); break;
1821 case lir_sub: __ sub(dreg, lreg, rreg); break;
1822 default: ShouldNotReachHere();
1823 }
1824 } else if (right->is_constant()) {
1825 // cpu register - constant
1826 jlong c;
1827
1828 // FIXME. This is fugly: we really need to factor all this logic.
1829 switch(right->type()) {
1830 case T_LONG:
1831 c = right->as_constant_ptr()->as_jlong();
1832 break;
1833 case T_INT:
1834 case T_ADDRESS:
1835 c = right->as_constant_ptr()->as_jint();
1836 break;
1837 default:
1838 ShouldNotReachHere();
1839 c = 0; // unreachable
1840 break;
1841 }
1842
1843 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1844 if (c == 0 && dreg == lreg) {
1845 COMMENT("effective nop elided");
1846 return;
1847 }
1848 switch(left->type()) {
1849 case T_INT:
1850 switch (code) {
1851 case lir_add: __ addw(dreg, lreg, c); break;
1852 case lir_sub: __ subw(dreg, lreg, c); break;
1853 default: ShouldNotReachHere();
1854 }
1855 break;
1856 case T_OBJECT:
1857 case T_ADDRESS:
1858 switch (code) {
1859 case lir_add: __ add(dreg, lreg, c); break;
1860 case lir_sub: __ sub(dreg, lreg, c); break;
1861 default: ShouldNotReachHere();
1862 }
1863 break;
1864 default:
1865 ShouldNotReachHere();
1866 }
1867 } else {
1868 ShouldNotReachHere();
1869 }
1870
1871 } else if (left->is_double_cpu()) {
1872 Register lreg_lo = left->as_register_lo();
1873
1874 if (right->is_double_cpu()) {
1875 // cpu register - cpu register
1876 Register rreg_lo = right->as_register_lo();
1877 switch (code) {
1878 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1879 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1880 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1881 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1882 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1883 default:
1884 ShouldNotReachHere();
1885 }
1886
1887 } else if (right->is_constant()) {
1888 jlong c = right->as_constant_ptr()->as_jlong();
1889 Register dreg = as_reg(dest);
1890 switch (code) {
1891 case lir_add:
1892 case lir_sub:
1893 if (c == 0 && dreg == lreg_lo) {
1894 COMMENT("effective nop elided");
1895 return;
1896 }
1897 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1898 break;
1899 case lir_div:
1900 assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1901 if (c == 1) {
1902 // move lreg_lo to dreg if divisor is 1
1903 __ mov(dreg, lreg_lo);
1904 } else {
1905 unsigned int shift = exact_log2_long(c);
1906 // use rscratch1 as intermediate result register
1907 __ asr(rscratch1, lreg_lo, 63);
1908 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1909 __ asr(dreg, rscratch1, shift);
1910 }
1911 break;
1912 case lir_rem:
1913 assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1914 if (c == 1) {
1915 // move 0 to dreg if divisor is 1
1916 __ mov(dreg, zr);
1917 } else {
1918 // use rscratch1 as intermediate result register
1919 __ negs(rscratch1, lreg_lo);
1920 __ andr(dreg, lreg_lo, c - 1);
1921 __ andr(rscratch1, rscratch1, c - 1);
1922 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1923 }
1924 break;
1925 default:
1926 ShouldNotReachHere();
1927 }
1928 } else {
1929 ShouldNotReachHere();
1930 }
1931 } else if (left->is_single_fpu()) {
1932 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1933 switch (code) {
1934 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1935 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1936 case lir_mul_strictfp: // fall through
1937 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1938 case lir_div_strictfp: // fall through
1939 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1940 default:
1941 ShouldNotReachHere();
1942 }
1943 } else if (left->is_double_fpu()) {
1944 if (right->is_double_fpu()) {
1945 // fpu register - fpu register
1946 switch (code) {
1947 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1948 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1949 case lir_mul_strictfp: // fall through
1950 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1951 case lir_div_strictfp: // fall through
1952 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1953 default:
1954 ShouldNotReachHere();
1955 }
1956 } else {
1957 if (right->is_constant()) {
1958 ShouldNotReachHere();
1959 }
1960 ShouldNotReachHere();
1961 }
1962 } else if (left->is_single_stack() || left->is_address()) {
1963 assert(left == dest, "left and dest must be equal");
1964 ShouldNotReachHere();
1965 } else {
1966 ShouldNotReachHere();
1967 }
1968 }
1969
1970 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1971
1972
1973 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1974 switch(code) {
1975 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1976 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1977 default : ShouldNotReachHere();
1978 }
1979 }
1980
1981 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1982
1983 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1984 Register Rleft = left->is_single_cpu() ? left->as_register() :
1985 left->as_register_lo();
1986 if (dst->is_single_cpu()) {
1987 Register Rdst = dst->as_register();
1988 if (right->is_constant()) {
1989 switch (code) {
1990 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1991 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1992 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1993 default: ShouldNotReachHere(); break;
1994 }
1995 } else {
1996 Register Rright = right->is_single_cpu() ? right->as_register() :
1997 right->as_register_lo();
1998 switch (code) {
1999 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
2000 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
2001 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
2002 default: ShouldNotReachHere(); break;
2003 }
2004 }
2005 } else {
2006 Register Rdst = dst->as_register_lo();
2007 if (right->is_constant()) {
2008 switch (code) {
2009 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
2010 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
2011 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
2012 default: ShouldNotReachHere(); break;
2013 }
2014 } else {
2015 Register Rright = right->is_single_cpu() ? right->as_register() :
2016 right->as_register_lo();
2017 switch (code) {
2018 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
2019 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
2020 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
2021 default: ShouldNotReachHere(); break;
2022 }
2023 }
2024 }
2025 }
2026
2027
2028
2029 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
2030
2031 // opcode check
2032 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
2033 bool is_irem = (code == lir_irem);
2034
2035 // operand check
2036 assert(left->is_single_cpu(), "left must be register");
2037 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2038 assert(result->is_single_cpu(), "result must be register");
2039 Register lreg = left->as_register();
2040 Register dreg = result->as_register();
2041
2042 // power-of-2 constant check and codegen
2043 if (right->is_constant()) {
2044 int c = right->as_constant_ptr()->as_jint();
2045 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
2046 if (is_irem) {
2047 if (c == 1) {
2048 // move 0 to dreg if divisor is 1
2049 __ movw(dreg, zr);
2050 } else {
2051 // use rscratch1 as intermediate result register
2052 __ negsw(rscratch1, lreg);
2053 __ andw(dreg, lreg, c - 1);
2054 __ andw(rscratch1, rscratch1, c - 1);
2055 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
2056 }
2057 } else {
2058 if (c == 1) {
2059 // move lreg to dreg if divisor is 1
2060 __ movw(dreg, lreg);
2061 } else {
2062 unsigned int shift = exact_log2(c);
2063 // use rscratch1 as intermediate result register
2064 __ asrw(rscratch1, lreg, 31);
2065 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
2066 __ asrw(dreg, rscratch1, shift);
2067 }
2068 }
2069 } else {
2070 Register rreg = right->as_register();
2071 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
2072 }
2073 }
2074
2075
2076 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2077 if (opr1->is_constant() && opr2->is_single_cpu()) {
2078 // tableswitch
2079 Register reg = as_reg(opr2);
2080 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
2081 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
2082 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
2083 Register reg1 = as_reg(opr1);
2084 if (opr2->is_single_cpu()) {
2085 // cpu register - cpu register
2086 Register reg2 = opr2->as_register();
2087 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY || opr1->type() == T_VALUETYPE) {
2088 __ cmpoop(reg1, reg2);
2089 } else {
2090 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_VALUETYPE, "cmp int, oop?");
2091 __ cmpw(reg1, reg2);
2092 }
2093 return;
2094 }
2095 if (opr2->is_double_cpu()) {
2096 // cpu register - cpu register
2097 Register reg2 = opr2->as_register_lo();
2098 __ cmp(reg1, reg2);
2099 return;
2100 }
2101
2102 if (opr2->is_constant()) {
2103 bool is_32bit = false; // width of register operand
2104 jlong imm;
2105
2106 switch(opr2->type()) {
2107 case T_INT:
2108 imm = opr2->as_constant_ptr()->as_jint();
2109 is_32bit = true;
2110 break;
2111 case T_LONG:
2112 imm = opr2->as_constant_ptr()->as_jlong();
2113 break;
2114 case T_ADDRESS:
2115 imm = opr2->as_constant_ptr()->as_jint();
2116 break;
2117 case T_VALUETYPE:
2118 case T_OBJECT:
2119 case T_ARRAY:
2120 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
2121 __ cmpoop(reg1, rscratch1);
2122 return;
2123 default:
2124 ShouldNotReachHere();
2125 imm = 0; // unreachable
2126 break;
2127 }
2128
2129 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
2130 if (is_32bit)
2131 __ cmpw(reg1, imm);
2132 else
2133 __ subs(zr, reg1, imm);
2134 return;
2135 } else {
2136 __ mov(rscratch1, imm);
2137 if (is_32bit)
2138 __ cmpw(reg1, rscratch1);
2139 else
2140 __ cmp(reg1, rscratch1);
2141 return;
2142 }
2143 } else
2144 ShouldNotReachHere();
2145 } else if (opr1->is_single_fpu()) {
2146 FloatRegister reg1 = opr1->as_float_reg();
2147 assert(opr2->is_single_fpu(), "expect single float register");
2148 FloatRegister reg2 = opr2->as_float_reg();
2149 __ fcmps(reg1, reg2);
2150 } else if (opr1->is_double_fpu()) {
2151 FloatRegister reg1 = opr1->as_double_reg();
2152 assert(opr2->is_double_fpu(), "expect double float register");
2153 FloatRegister reg2 = opr2->as_double_reg();
2154 __ fcmpd(reg1, reg2);
2155 } else {
2156 ShouldNotReachHere();
2157 }
2158 }
2159
2160 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2161 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2162 bool is_unordered_less = (code == lir_ucmp_fd2i);
2163 if (left->is_single_fpu()) {
2164 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2165 } else if (left->is_double_fpu()) {
2166 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2167 } else {
2168 ShouldNotReachHere();
2169 }
2170 } else if (code == lir_cmp_l2i) {
2171 Label done;
2172 __ cmp(left->as_register_lo(), right->as_register_lo());
2173 __ mov(dst->as_register(), (u_int64_t)-1L);
2174 __ br(Assembler::LT, done);
2175 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2176 __ bind(done);
2177 } else {
2178 ShouldNotReachHere();
2179 }
2180 }
2181
2182
2183 void LIR_Assembler::align_call(LIR_Code code) { }
2184
2185
2186 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2187 address call = __ trampoline_call(Address(op->addr(), rtype));
2188 if (call == NULL) {
2189 bailout("trampoline stub overflow");
2190 return;
2191 }
2192 add_call_info(code_offset(), op->info());
2193 }
2194
2195
2196 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2197 address call = __ ic_call(op->addr());
2198 if (call == NULL) {
2199 bailout("trampoline stub overflow");
2200 return;
2201 }
2202 add_call_info(code_offset(), op->info());
2203 }
2204
2205
2206 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2207 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2208 ShouldNotReachHere();
2209 }
2210
2211
2212 void LIR_Assembler::emit_static_call_stub() {
2213 address call_pc = __ pc();
2214 address stub = __ start_a_stub(call_stub_size());
2215 if (stub == NULL) {
2216 bailout("static call stub overflow");
2217 return;
2218 }
2219
2220 int start = __ offset();
2221
2222 __ relocate(static_stub_Relocation::spec(call_pc));
2223 __ emit_static_call_stub();
2224
2225 assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size()
2226 <= call_stub_size(), "stub too big");
2227 __ end_a_stub();
2228 }
2229
2230
2231 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2232 assert(exceptionOop->as_register() == r0, "must match");
2233 assert(exceptionPC->as_register() == r3, "must match");
2234
2235 // exception object is not added to oop map by LinearScan
2236 // (LinearScan assumes that no oops are in fixed registers)
2237 info->add_register_oop(exceptionOop);
2238 Runtime1::StubID unwind_id;
2239
2240 // get current pc information
2241 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2242 int pc_for_athrow_offset = __ offset();
2243 InternalAddress pc_for_athrow(__ pc());
2244 __ adr(exceptionPC->as_register(), pc_for_athrow);
2245 add_call_info(pc_for_athrow_offset, info); // for exception handler
2246
2247 __ verify_not_null_oop(r0);
2248 // search an exception handler (r0: exception oop, r3: throwing pc)
2249 if (compilation()->has_fpu_code()) {
2250 unwind_id = Runtime1::handle_exception_id;
2251 } else {
2252 unwind_id = Runtime1::handle_exception_nofpu_id;
2253 }
2254 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2255
2256 // FIXME: enough room for two byte trap ????
2257 __ nop();
2258 }
2259
2260
2261 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2262 assert(exceptionOop->as_register() == r0, "must match");
2263
2264 __ b(_unwind_handler_entry);
2265 }
2266
2267
2268 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2269 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2270 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2271
2272 switch (left->type()) {
2273 case T_INT: {
2274 switch (code) {
2275 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2276 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2277 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2278 default:
2279 ShouldNotReachHere();
2280 break;
2281 }
2282 break;
2283 case T_LONG:
2284 case T_VALUETYPE:
2285 case T_ADDRESS:
2286 case T_OBJECT:
2287 switch (code) {
2288 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2289 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2290 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2291 default:
2292 ShouldNotReachHere();
2293 break;
2294 }
2295 break;
2296 default:
2297 ShouldNotReachHere();
2298 break;
2299 }
2300 }
2301 }
2302
2303
2304 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2305 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2306 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2307
2308 switch (left->type()) {
2309 case T_INT: {
2310 switch (code) {
2311 case lir_shl: __ lslw (dreg, lreg, count); break;
2312 case lir_shr: __ asrw (dreg, lreg, count); break;
2313 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2314 default:
2315 ShouldNotReachHere();
2316 break;
2317 }
2318 break;
2319 case T_LONG:
2320 case T_ADDRESS:
2321 case T_VALUETYPE:
2322 case T_OBJECT:
2323 switch (code) {
2324 case lir_shl: __ lsl (dreg, lreg, count); break;
2325 case lir_shr: __ asr (dreg, lreg, count); break;
2326 case lir_ushr: __ lsr (dreg, lreg, count); break;
2327 default:
2328 ShouldNotReachHere();
2329 break;
2330 }
2331 break;
2332 default:
2333 ShouldNotReachHere();
2334 break;
2335 }
2336 }
2337 }
2338
2339
2340 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2341 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2342 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2343 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2344 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2345 }
2346
2347
2348 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2349 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2350 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2351 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2352 __ mov (rscratch1, c);
2353 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2354 }
2355
2356
2357 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2358 ShouldNotReachHere();
2359 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2360 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2361 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2362 __ lea(rscratch1, __ constant_oop_address(o));
2363 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2364 }
2365
2366 void LIR_Assembler::arraycopy_valuetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest) {
2367 __ load_storage_props(tmp, obj);
2368 if (is_dest) {
2369 // We also take slow path if it's a null_free destination array, just in case the source array
2370 // contains NULLs.
2371 __ tst(tmp, ArrayStorageProperties::flattened_value | ArrayStorageProperties::null_free_value);
2372 } else {
2373 __ tst(tmp, ArrayStorageProperties::flattened_value);
2374 }
2375 __ br(Assembler::NE, *slow_path->entry());
2376 }
2377
2378
2379
2380 // This code replaces a call to arraycopy; no exception may
2381 // be thrown in this code, they must be thrown in the System.arraycopy
2382 // activation frame; we could save some checks if this would not be the case
2383 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2384 ciArrayKlass* default_type = op->expected_type();
2385 Register src = op->src()->as_register();
2386 Register dst = op->dst()->as_register();
2387 Register src_pos = op->src_pos()->as_register();
2388 Register dst_pos = op->dst_pos()->as_register();
2389 Register length = op->length()->as_register();
2390 Register tmp = op->tmp()->as_register();
2391
2392 __ resolve(ACCESS_READ, src);
2393 __ resolve(ACCESS_WRITE, dst);
2394
2395 CodeStub* stub = op->stub();
2396 int flags = op->flags();
2397 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2398 if (basic_type == T_ARRAY || basic_type == T_VALUETYPE) basic_type = T_OBJECT;
2399
2400 if (flags & LIR_OpArrayCopy::always_slow_path) {
2401 __ b(*stub->entry());
2402 __ bind(*stub->continuation());
2403 return;
2404 }
2405
2406 if (flags & LIR_OpArrayCopy::src_valuetype_check) {
2407 arraycopy_valuetype_check(src, tmp, stub, false);
2408 }
2409
2410 if (flags & LIR_OpArrayCopy::dst_valuetype_check) {
2411 arraycopy_valuetype_check(dst, tmp, stub, true);
2412 }
2413
2414
2415
2416 // if we don't know anything, just go through the generic arraycopy
2417 if (default_type == NULL // || basic_type == T_OBJECT
2418 ) {
2419 Label done;
2420 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2421
2422 // Save the arguments in case the generic arraycopy fails and we
2423 // have to fall back to the JNI stub
2424 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2425 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2426 __ str(src, Address(sp, 4*BytesPerWord));
2427
2428 address copyfunc_addr = StubRoutines::generic_arraycopy();
2429 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2430
2431 // The arguments are in java calling convention so we shift them
2432 // to C convention
2433 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2434 __ mov(c_rarg0, j_rarg0);
2435 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2436 __ mov(c_rarg1, j_rarg1);
2437 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2438 __ mov(c_rarg2, j_rarg2);
2439 assert_different_registers(c_rarg3, j_rarg4);
2440 __ mov(c_rarg3, j_rarg3);
2441 __ mov(c_rarg4, j_rarg4);
2442 #ifndef PRODUCT
2443 if (PrintC1Statistics) {
2444 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2445 }
2446 #endif
2447 __ far_call(RuntimeAddress(copyfunc_addr));
2448
2449 __ cbz(r0, *stub->continuation());
2450
2451 // Reload values from the stack so they are where the stub
2452 // expects them.
2453 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2454 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2455 __ ldr(src, Address(sp, 4*BytesPerWord));
2456
2457 // r0 is -1^K where K == partial copied count
2458 __ eonw(rscratch1, r0, zr);
2459 // adjust length down and src/end pos up by partial copied count
2460 __ subw(length, length, rscratch1);
2461 __ addw(src_pos, src_pos, rscratch1);
2462 __ addw(dst_pos, dst_pos, rscratch1);
2463 __ b(*stub->entry());
2464
2465 __ bind(*stub->continuation());
2466 return;
2467 }
2468
2469 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2470
2471 int elem_size = type2aelembytes(basic_type);
2472 int shift_amount;
2473 int scale = exact_log2(elem_size);
2474
2475 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2476 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2477 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2478 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2479
2480 // test for NULL
2481 if (flags & LIR_OpArrayCopy::src_null_check) {
2482 __ cbz(src, *stub->entry());
2483 }
2484 if (flags & LIR_OpArrayCopy::dst_null_check) {
2485 __ cbz(dst, *stub->entry());
2486 }
2487
2488 // If the compiler was not able to prove that exact type of the source or the destination
2489 // of the arraycopy is an array type, check at runtime if the source or the destination is
2490 // an instance type.
2491 if (flags & LIR_OpArrayCopy::type_check) {
2492 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2493 __ load_klass(tmp, dst);
2494 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2495 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2496 __ br(Assembler::GE, *stub->entry());
2497 }
2498
2499 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2500 __ load_klass(tmp, src);
2501 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2502 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2503 __ br(Assembler::GE, *stub->entry());
2504 }
2505 }
2506
2507 // check if negative
2508 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2509 __ cmpw(src_pos, 0);
2510 __ br(Assembler::LT, *stub->entry());
2511 }
2512 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2513 __ cmpw(dst_pos, 0);
2514 __ br(Assembler::LT, *stub->entry());
2515 }
2516
2517 if (flags & LIR_OpArrayCopy::length_positive_check) {
2518 __ cmpw(length, 0);
2519 __ br(Assembler::LT, *stub->entry());
2520 }
2521
2522 if (flags & LIR_OpArrayCopy::src_range_check) {
2523 __ addw(tmp, src_pos, length);
2524 __ ldrw(rscratch1, src_length_addr);
2525 __ cmpw(tmp, rscratch1);
2526 __ br(Assembler::HI, *stub->entry());
2527 }
2528 if (flags & LIR_OpArrayCopy::dst_range_check) {
2529 __ addw(tmp, dst_pos, length);
2530 __ ldrw(rscratch1, dst_length_addr);
2531 __ cmpw(tmp, rscratch1);
2532 __ br(Assembler::HI, *stub->entry());
2533 }
2534
2535 if (flags & LIR_OpArrayCopy::type_check) {
2536 // We don't know the array types are compatible
2537 if (basic_type != T_OBJECT) {
2538 // Simple test for basic type arrays
2539 if (UseCompressedClassPointers) {
2540 __ ldrw(tmp, src_klass_addr);
2541 __ ldrw(rscratch1, dst_klass_addr);
2542 __ cmpw(tmp, rscratch1);
2543 } else {
2544 __ ldr(tmp, src_klass_addr);
2545 __ ldr(rscratch1, dst_klass_addr);
2546 __ cmp(tmp, rscratch1);
2547 }
2548 __ br(Assembler::NE, *stub->entry());
2549 } else {
2550 // For object arrays, if src is a sub class of dst then we can
2551 // safely do the copy.
2552 Label cont, slow;
2553
2554 #define PUSH(r1, r2) \
2555 stp(r1, r2, __ pre(sp, -2 * wordSize));
2556
2557 #define POP(r1, r2) \
2558 ldp(r1, r2, __ post(sp, 2 * wordSize));
2559
2560 __ PUSH(src, dst);
2561
2562 __ load_klass(src, src);
2563 __ load_klass(dst, dst);
2564
2565 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
2566
2567 __ PUSH(src, dst);
2568 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
2569 __ POP(src, dst);
2570
2571 __ cbnz(src, cont);
2572
2573 __ bind(slow);
2574 __ POP(src, dst);
2575
2576 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2577 if (copyfunc_addr != NULL) { // use stub if available
2578 // src is not a sub class of dst so we have to do a
2579 // per-element check.
2580
2581 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2582 if ((flags & mask) != mask) {
2583 // Check that at least both of them object arrays.
2584 assert(flags & mask, "one of the two should be known to be an object array");
2585
2586 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2587 __ load_klass(tmp, src);
2588 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2589 __ load_klass(tmp, dst);
2590 }
2591 int lh_offset = in_bytes(Klass::layout_helper_offset());
2592 Address klass_lh_addr(tmp, lh_offset);
2593 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2594 __ ldrw(rscratch1, klass_lh_addr);
2595 __ mov(rscratch2, objArray_lh);
2596 __ eorw(rscratch1, rscratch1, rscratch2);
2597 __ cbnzw(rscratch1, *stub->entry());
2598 }
2599
2600 // Spill because stubs can use any register they like and it's
2601 // easier to restore just those that we care about.
2602 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2603 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2604 __ str(src, Address(sp, 4*BytesPerWord));
2605
2606 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2607 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2608 assert_different_registers(c_rarg0, dst, dst_pos, length);
2609 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2610 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2611 assert_different_registers(c_rarg1, dst, length);
2612 __ uxtw(c_rarg2, length);
2613 assert_different_registers(c_rarg2, dst);
2614
2615 __ load_klass(c_rarg4, dst);
2616 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2617 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2618 __ far_call(RuntimeAddress(copyfunc_addr));
2619
2620 #ifndef PRODUCT
2621 if (PrintC1Statistics) {
2622 Label failed;
2623 __ cbnz(r0, failed);
2624 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2625 __ bind(failed);
2626 }
2627 #endif
2628
2629 __ cbz(r0, *stub->continuation());
2630
2631 #ifndef PRODUCT
2632 if (PrintC1Statistics) {
2633 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2634 }
2635 #endif
2636 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2637
2638 // Restore previously spilled arguments
2639 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2640 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2641 __ ldr(src, Address(sp, 4*BytesPerWord));
2642
2643 // return value is -1^K where K is partial copied count
2644 __ eonw(rscratch1, r0, zr);
2645 // adjust length down and src/end pos up by partial copied count
2646 __ subw(length, length, rscratch1);
2647 __ addw(src_pos, src_pos, rscratch1);
2648 __ addw(dst_pos, dst_pos, rscratch1);
2649 }
2650
2651 __ b(*stub->entry());
2652
2653 __ bind(cont);
2654 __ POP(src, dst);
2655 }
2656 }
2657
2658 #ifdef ASSERT
2659 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2660 // Sanity check the known type with the incoming class. For the
2661 // primitive case the types must match exactly with src.klass and
2662 // dst.klass each exactly matching the default type. For the
2663 // object array case, if no type check is needed then either the
2664 // dst type is exactly the expected type and the src type is a
2665 // subtype which we can't check or src is the same array as dst
2666 // but not necessarily exactly of type default_type.
2667 Label known_ok, halt;
2668 __ mov_metadata(tmp, default_type->constant_encoding());
2669 if (UseCompressedClassPointers) {
2670 __ encode_klass_not_null(tmp);
2671 }
2672
2673 if (basic_type != T_OBJECT) {
2674
2675 if (UseCompressedClassPointers) {
2676 __ ldrw(rscratch1, dst_klass_addr);
2677 __ cmpw(tmp, rscratch1);
2678 } else {
2679 __ ldr(rscratch1, dst_klass_addr);
2680 __ cmp(tmp, rscratch1);
2681 }
2682 __ br(Assembler::NE, halt);
2683 if (UseCompressedClassPointers) {
2684 __ ldrw(rscratch1, src_klass_addr);
2685 __ cmpw(tmp, rscratch1);
2686 } else {
2687 __ ldr(rscratch1, src_klass_addr);
2688 __ cmp(tmp, rscratch1);
2689 }
2690 __ br(Assembler::EQ, known_ok);
2691 } else {
2692 if (UseCompressedClassPointers) {
2693 __ ldrw(rscratch1, dst_klass_addr);
2694 __ cmpw(tmp, rscratch1);
2695 } else {
2696 __ ldr(rscratch1, dst_klass_addr);
2697 __ cmp(tmp, rscratch1);
2698 }
2699 __ br(Assembler::EQ, known_ok);
2700 __ cmp(src, dst);
2701 __ br(Assembler::EQ, known_ok);
2702 }
2703 __ bind(halt);
2704 __ stop("incorrect type information in arraycopy");
2705 __ bind(known_ok);
2706 }
2707 #endif
2708
2709 #ifndef PRODUCT
2710 if (PrintC1Statistics) {
2711 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2712 }
2713 #endif
2714
2715 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2716 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2717 assert_different_registers(c_rarg0, dst, dst_pos, length);
2718 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2719 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2720 assert_different_registers(c_rarg1, dst, length);
2721 __ uxtw(c_rarg2, length);
2722 assert_different_registers(c_rarg2, dst);
2723
2724 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2725 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2726 const char *name;
2727 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2728
2729 CodeBlob *cb = CodeCache::find_blob(entry);
2730 if (cb) {
2731 __ far_call(RuntimeAddress(entry));
2732 } else {
2733 __ call_VM_leaf(entry, 3);
2734 }
2735
2736 __ bind(*stub->continuation());
2737 }
2738
2739
2740
2741
2742 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2743 Register obj = op->obj_opr()->as_register(); // may not be an oop
2744 Register hdr = op->hdr_opr()->as_register();
2745 Register lock = op->lock_opr()->as_register();
2746 if (!UseFastLocking) {
2747 __ b(*op->stub()->entry());
2748 } else if (op->code() == lir_lock) {
2749 Register scratch = noreg;
2750 if (UseBiasedLocking) {
2751 scratch = op->scratch_opr()->as_register();
2752 }
2753 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2754 __ resolve(ACCESS_READ | ACCESS_WRITE, obj);
2755 // add debug info for NullPointerException only if one is possible
2756 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
2757 if (op->info() != NULL) {
2758 add_debug_info_for_null_check(null_check_offset, op->info());
2759 }
2760 // done
2761 } else if (op->code() == lir_unlock) {
2762 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2763 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2764 } else {
2765 Unimplemented();
2766 }
2767 __ bind(*op->stub()->continuation());
2768 }
2769
2770
2771 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2772 ciMethod* method = op->profiled_method();
2773 int bci = op->profiled_bci();
2774 ciMethod* callee = op->profiled_callee();
2775
2776 // Update counter for all call types
2777 ciMethodData* md = method->method_data_or_null();
2778 assert(md != NULL, "Sanity");
2779 ciProfileData* data = md->bci_to_data(bci);
2780 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2781 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2782 Register mdo = op->mdo()->as_register();
2783 __ mov_metadata(mdo, md->constant_encoding());
2784 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2785 // Perform additional virtual call profiling for invokevirtual and
2786 // invokeinterface bytecodes
2787 if (op->should_profile_receiver_type()) {
2788 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2789 Register recv = op->recv()->as_register();
2790 assert_different_registers(mdo, recv);
2791 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2792 ciKlass* known_klass = op->known_holder();
2793 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2794 // We know the type that will be seen at this call site; we can
2795 // statically update the MethodData* rather than needing to do
2796 // dynamic tests on the receiver type
2797
2798 // NOTE: we should probably put a lock around this search to
2799 // avoid collisions by concurrent compilations
2800 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2801 uint i;
2802 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2803 ciKlass* receiver = vc_data->receiver(i);
2804 if (known_klass->equals(receiver)) {
2805 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2806 __ addptr(data_addr, DataLayout::counter_increment);
2807 return;
2808 }
2809 }
2810
2811 // Receiver type not found in profile data; select an empty slot
2812
2813 // Note that this is less efficient than it should be because it
2814 // always does a write to the receiver part of the
2815 // VirtualCallData rather than just the first time
2816 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2817 ciKlass* receiver = vc_data->receiver(i);
2818 if (receiver == NULL) {
2819 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2820 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2821 __ lea(rscratch2, recv_addr);
2822 __ str(rscratch1, Address(rscratch2));
2823 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2824 __ addptr(data_addr, DataLayout::counter_increment);
2825 return;
2826 }
2827 }
2828 } else {
2829 __ load_klass(recv, recv);
2830 Label update_done;
2831 type_profile_helper(mdo, md, data, recv, &update_done);
2832 // Receiver did not match any saved receiver and there is no empty row for it.
2833 // Increment total counter to indicate polymorphic case.
2834 __ addptr(counter_addr, DataLayout::counter_increment);
2835
2836 __ bind(update_done);
2837 }
2838 } else {
2839 // Static call
2840 __ addptr(counter_addr, DataLayout::counter_increment);
2841 }
2842 }
2843
2844
2845 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2846 Unimplemented();
2847 }
2848
2849
2850 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2851 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2852 }
2853
2854 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2855 assert(op->crc()->is_single_cpu(), "crc must be register");
2856 assert(op->val()->is_single_cpu(), "byte value must be register");
2857 assert(op->result_opr()->is_single_cpu(), "result must be register");
2858 Register crc = op->crc()->as_register();
2859 Register val = op->val()->as_register();
2860 Register res = op->result_opr()->as_register();
2861
2862 assert_different_registers(val, crc, res);
2863 unsigned long offset;
2864 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2865 if (offset) __ add(res, res, offset);
2866
2867 __ mvnw(crc, crc); // ~crc
2868 __ update_byte_crc32(crc, val, res);
2869 __ mvnw(res, crc); // ~crc
2870 }
2871
2872 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2873 COMMENT("emit_profile_type {");
2874 Register obj = op->obj()->as_register();
2875 Register tmp = op->tmp()->as_pointer_register();
2876 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2877 ciKlass* exact_klass = op->exact_klass();
2878 intptr_t current_klass = op->current_klass();
2879 bool not_null = op->not_null();
2880 bool no_conflict = op->no_conflict();
2881
2882 Label update, next, none;
2883
2884 bool do_null = !not_null;
2885 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2886 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2887
2888 assert(do_null || do_update, "why are we here?");
2889 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2890 assert(mdo_addr.base() != rscratch1, "wrong register");
2891
2892 __ verify_oop(obj);
2893
2894 if (tmp != obj) {
2895 __ mov(tmp, obj);
2896 }
2897 if (do_null) {
2898 __ cbnz(tmp, update);
2899 if (!TypeEntries::was_null_seen(current_klass)) {
2900 __ ldr(rscratch2, mdo_addr);
2901 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2902 __ str(rscratch2, mdo_addr);
2903 }
2904 if (do_update) {
2905 #ifndef ASSERT
2906 __ b(next);
2907 }
2908 #else
2909 __ b(next);
2910 }
2911 } else {
2912 __ cbnz(tmp, update);
2913 __ stop("unexpected null obj");
2914 #endif
2915 }
2916
2917 __ bind(update);
2918
2919 if (do_update) {
2920 #ifdef ASSERT
2921 if (exact_klass != NULL) {
2922 Label ok;
2923 __ load_klass(tmp, tmp);
2924 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2925 __ eor(rscratch1, tmp, rscratch1);
2926 __ cbz(rscratch1, ok);
2927 __ stop("exact klass and actual klass differ");
2928 __ bind(ok);
2929 }
2930 #endif
2931 if (!no_conflict) {
2932 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2933 if (exact_klass != NULL) {
2934 __ mov_metadata(tmp, exact_klass->constant_encoding());
2935 } else {
2936 __ load_klass(tmp, tmp);
2937 }
2938
2939 __ ldr(rscratch2, mdo_addr);
2940 __ eor(tmp, tmp, rscratch2);
2941 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2942 // klass seen before, nothing to do. The unknown bit may have been
2943 // set already but no need to check.
2944 __ cbz(rscratch1, next);
2945
2946 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2947
2948 if (TypeEntries::is_type_none(current_klass)) {
2949 __ cbz(rscratch2, none);
2950 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2951 __ br(Assembler::EQ, none);
2952 // There is a chance that the checks above (re-reading profiling
2953 // data from memory) fail if another thread has just set the
2954 // profiling to this obj's klass
2955 __ dmb(Assembler::ISHLD);
2956 __ ldr(rscratch2, mdo_addr);
2957 __ eor(tmp, tmp, rscratch2);
2958 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2959 __ cbz(rscratch1, next);
2960 }
2961 } else {
2962 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2963 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2964
2965 __ ldr(tmp, mdo_addr);
2966 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2967 }
2968
2969 // different than before. Cannot keep accurate profile.
2970 __ ldr(rscratch2, mdo_addr);
2971 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2972 __ str(rscratch2, mdo_addr);
2973
2974 if (TypeEntries::is_type_none(current_klass)) {
2975 __ b(next);
2976
2977 __ bind(none);
2978 // first time here. Set profile type.
2979 __ str(tmp, mdo_addr);
2980 }
2981 } else {
2982 // There's a single possible klass at this profile point
2983 assert(exact_klass != NULL, "should be");
2984 if (TypeEntries::is_type_none(current_klass)) {
2985 __ mov_metadata(tmp, exact_klass->constant_encoding());
2986 __ ldr(rscratch2, mdo_addr);
2987 __ eor(tmp, tmp, rscratch2);
2988 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2989 __ cbz(rscratch1, next);
2990 #ifdef ASSERT
2991 {
2992 Label ok;
2993 __ ldr(rscratch1, mdo_addr);
2994 __ cbz(rscratch1, ok);
2995 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2996 __ br(Assembler::EQ, ok);
2997 // may have been set by another thread
2998 __ dmb(Assembler::ISHLD);
2999 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
3000 __ ldr(rscratch2, mdo_addr);
3001 __ eor(rscratch2, rscratch1, rscratch2);
3002 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
3003 __ cbz(rscratch2, ok);
3004
3005 __ stop("unexpected profiling mismatch");
3006 __ bind(ok);
3007 }
3008 #endif
3009 // first time here. Set profile type.
3010 __ ldr(tmp, mdo_addr);
3011 } else {
3012 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3013 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3014
3015 __ ldr(tmp, mdo_addr);
3016 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
3017
3018 __ orr(tmp, tmp, TypeEntries::type_unknown);
3019 __ str(tmp, mdo_addr);
3020 // FIXME: Write barrier needed here?
3021 }
3022 }
3023
3024 __ bind(next);
3025 }
3026 COMMENT("} emit_profile_type");
3027 }
3028
3029
3030 void LIR_Assembler::align_backward_branch_target() {
3031 }
3032
3033
3034 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3035 // tmp must be unused
3036 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3037
3038 if (left->is_single_cpu()) {
3039 assert(dest->is_single_cpu(), "expect single result reg");
3040 __ negw(dest->as_register(), left->as_register());
3041 } else if (left->is_double_cpu()) {
3042 assert(dest->is_double_cpu(), "expect double result reg");
3043 __ neg(dest->as_register_lo(), left->as_register_lo());
3044 } else if (left->is_single_fpu()) {
3045 assert(dest->is_single_fpu(), "expect single float result reg");
3046 __ fnegs(dest->as_float_reg(), left->as_float_reg());
3047 } else {
3048 assert(left->is_double_fpu(), "expect double float operand reg");
3049 assert(dest->is_double_fpu(), "expect double float result reg");
3050 __ fnegd(dest->as_double_reg(), left->as_double_reg());
3051 }
3052 }
3053
3054
3055 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3056 if (patch_code != lir_patch_none) {
3057 deoptimize_trap(info);
3058 return;
3059 }
3060
3061 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
3062 }
3063
3064
3065 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3066 assert(!tmp->is_valid(), "don't need temporary");
3067
3068 CodeBlob *cb = CodeCache::find_blob(dest);
3069 if (cb) {
3070 __ far_call(RuntimeAddress(dest));
3071 } else {
3072 __ mov(rscratch1, RuntimeAddress(dest));
3073 int len = args->length();
3074 int type = 0;
3075 if (! result->is_illegal()) {
3076 switch (result->type()) {
3077 case T_VOID:
3078 type = 0;
3079 break;
3080 case T_INT:
3081 case T_LONG:
3082 case T_OBJECT:
3083 case T_VALUETYPE:
3084 type = 1;
3085 break;
3086 case T_FLOAT:
3087 type = 2;
3088 break;
3089 case T_DOUBLE:
3090 type = 3;
3091 break;
3092 default:
3093 ShouldNotReachHere();
3094 break;
3095 }
3096 }
3097 int num_gpargs = 0;
3098 int num_fpargs = 0;
3099 for (int i = 0; i < args->length(); i++) {
3100 LIR_Opr arg = args->at(i);
3101 if (arg->type() == T_FLOAT || arg->type() == T_DOUBLE) {
3102 num_fpargs++;
3103 } else {
3104 num_gpargs++;
3105 }
3106 }
3107 __ blrt(rscratch1, num_gpargs, num_fpargs, type);
3108 }
3109
3110 if (info != NULL) {
3111 add_call_info_here(info);
3112 }
3113 __ maybe_isb();
3114 }
3115
3116 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3117 if (dest->is_address() || src->is_address()) {
3118 move_op(src, dest, type, lir_patch_none, info,
3119 /*pop_fpu_stack*/false, /*unaligned*/false, /*wide*/false);
3120 } else {
3121 ShouldNotReachHere();
3122 }
3123 }
3124
3125 #ifdef ASSERT
3126 // emit run-time assertion
3127 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3128 assert(op->code() == lir_assert, "must be");
3129
3130 if (op->in_opr1()->is_valid()) {
3131 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3132 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3133 } else {
3134 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3135 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3136 }
3137
3138 Label ok;
3139 if (op->condition() != lir_cond_always) {
3140 Assembler::Condition acond = Assembler::AL;
3141 switch (op->condition()) {
3142 case lir_cond_equal: acond = Assembler::EQ; break;
3143 case lir_cond_notEqual: acond = Assembler::NE; break;
3144 case lir_cond_less: acond = Assembler::LT; break;
3145 case lir_cond_lessEqual: acond = Assembler::LE; break;
3146 case lir_cond_greaterEqual: acond = Assembler::GE; break;
3147 case lir_cond_greater: acond = Assembler::GT; break;
3148 case lir_cond_belowEqual: acond = Assembler::LS; break;
3149 case lir_cond_aboveEqual: acond = Assembler::HS; break;
3150 default: ShouldNotReachHere();
3151 }
3152 __ br(acond, ok);
3153 }
3154 if (op->halt()) {
3155 const char* str = __ code_string(op->msg());
3156 __ stop(str);
3157 } else {
3158 breakpoint();
3159 }
3160 __ bind(ok);
3161 }
3162 #endif
3163
3164 #ifndef PRODUCT
3165 #define COMMENT(x) do { __ block_comment(x); } while (0)
3166 #else
3167 #define COMMENT(x)
3168 #endif
3169
3170 void LIR_Assembler::membar() {
3171 COMMENT("membar");
3172 __ membar(MacroAssembler::AnyAny);
3173 }
3174
3175 void LIR_Assembler::membar_acquire() {
3176 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
3177 }
3178
3179 void LIR_Assembler::membar_release() {
3180 __ membar(Assembler::LoadStore|Assembler::StoreStore);
3181 }
3182
3183 void LIR_Assembler::membar_loadload() {
3184 __ membar(Assembler::LoadLoad);
3185 }
3186
3187 void LIR_Assembler::membar_storestore() {
3188 __ membar(MacroAssembler::StoreStore);
3189 }
3190
3191 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3192
3193 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3194
3195 void LIR_Assembler::on_spin_wait() {
3196 Unimplemented();
3197 }
3198
3199 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3200 __ mov(result_reg->as_register(), rthread);
3201 }
3202
3203
3204 void LIR_Assembler::peephole(LIR_List *lir) {
3205 #if 0
3206 if (tableswitch_count >= max_tableswitches)
3207 return;
3208
3209 /*
3210 This finite-state automaton recognizes sequences of compare-and-
3211 branch instructions. We will turn them into a tableswitch. You
3212 could argue that C1 really shouldn't be doing this sort of
3213 optimization, but without it the code is really horrible.
3214 */
3215
3216 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3217 int first_key, last_key = -2147483648;
3218 int next_key = 0;
3219 int start_insn = -1;
3220 int last_insn = -1;
3221 Register reg = noreg;
3222 LIR_Opr reg_opr;
3223 state = start_s;
3224
3225 LIR_OpList* inst = lir->instructions_list();
3226 for (int i = 0; i < inst->length(); i++) {
3227 LIR_Op* op = inst->at(i);
3228 switch (state) {
3229 case start_s:
3230 first_key = -1;
3231 start_insn = i;
3232 switch (op->code()) {
3233 case lir_cmp:
3234 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3235 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3236 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3237 && opr2->is_constant()
3238 && opr2->type() == T_INT) {
3239 reg_opr = opr1;
3240 reg = opr1->as_register();
3241 first_key = opr2->as_constant_ptr()->as_jint();
3242 next_key = first_key + 1;
3243 state = cmp_s;
3244 goto next_state;
3245 }
3246 break;
3247 }
3248 break;
3249 case cmp_s:
3250 switch (op->code()) {
3251 case lir_branch:
3252 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3253 state = beq_s;
3254 last_insn = i;
3255 goto next_state;
3256 }
3257 }
3258 state = start_s;
3259 break;
3260 case beq_s:
3261 switch (op->code()) {
3262 case lir_cmp: {
3263 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3264 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3265 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3266 && opr1->as_register() == reg
3267 && opr2->is_constant()
3268 && opr2->type() == T_INT
3269 && opr2->as_constant_ptr()->as_jint() == next_key) {
3270 last_key = next_key;
3271 next_key++;
3272 state = cmp_s;
3273 goto next_state;
3274 }
3275 }
3276 }
3277 last_key = next_key;
3278 state = start_s;
3279 break;
3280 default:
3281 assert(false, "impossible state");
3282 }
3283 if (state == start_s) {
3284 if (first_key < last_key - 5L && reg != noreg) {
3285 {
3286 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3287 // reg->encoding(),
3288 // start_insn, first_key, last_key);
3289 // for (int i = 0; i < inst->length(); i++) {
3290 // inst->at(i)->print();
3291 // tty->print("\n");
3292 // }
3293 // tty->print("\n");
3294 }
3295
3296 struct tableswitch *sw = &switches[tableswitch_count];
3297 sw->_insn_index = start_insn, sw->_first_key = first_key,
3298 sw->_last_key = last_key, sw->_reg = reg;
3299 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3300 {
3301 // Insert the new table of branches
3302 int offset = last_insn;
3303 for (int n = first_key; n < last_key; n++) {
3304 inst->insert_before
3305 (last_insn + 1,
3306 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3307 inst->at(offset)->as_OpBranch()->label()));
3308 offset -= 2, i++;
3309 }
3310 }
3311 // Delete all the old compare-and-branch instructions
3312 for (int n = first_key; n < last_key; n++) {
3313 inst->remove_at(start_insn);
3314 inst->remove_at(start_insn);
3315 }
3316 // Insert the tableswitch instruction
3317 inst->insert_before(start_insn,
3318 new LIR_Op2(lir_cmp, lir_cond_always,
3319 LIR_OprFact::intConst(tableswitch_count),
3320 reg_opr));
3321 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3322 tableswitch_count++;
3323 }
3324 reg = noreg;
3325 last_key = -2147483648;
3326 }
3327 next_state:
3328 ;
3329 }
3330 #endif
3331 }
3332
3333 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3334 Address addr = as_Address(src->as_address_ptr());
3335 BasicType type = src->type();
3336 bool is_oop = type == T_OBJECT || type == T_ARRAY;
3337
3338 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3339 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3340
3341 switch(type) {
3342 case T_INT:
3343 xchg = &MacroAssembler::atomic_xchgalw;
3344 add = &MacroAssembler::atomic_addalw;
3345 break;
3346 case T_LONG:
3347 xchg = &MacroAssembler::atomic_xchgal;
3348 add = &MacroAssembler::atomic_addal;
3349 break;
3350 case T_VALUETYPE:
3351 case T_OBJECT:
3352 case T_ARRAY:
3353 if (UseCompressedOops) {
3354 xchg = &MacroAssembler::atomic_xchgalw;
3355 add = &MacroAssembler::atomic_addalw;
3356 } else {
3357 xchg = &MacroAssembler::atomic_xchgal;
3358 add = &MacroAssembler::atomic_addal;
3359 }
3360 break;
3361 default:
3362 ShouldNotReachHere();
3363 xchg = &MacroAssembler::atomic_xchgal;
3364 add = &MacroAssembler::atomic_addal; // unreachable
3365 }
3366
3367 switch (code) {
3368 case lir_xadd:
3369 {
3370 RegisterOrConstant inc;
3371 Register tmp = as_reg(tmp_op);
3372 Register dst = as_reg(dest);
3373 if (data->is_constant()) {
3374 inc = RegisterOrConstant(as_long(data));
3375 assert_different_registers(dst, addr.base(), tmp,
3376 rscratch1, rscratch2);
3377 } else {
3378 inc = RegisterOrConstant(as_reg(data));
3379 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3380 rscratch1, rscratch2);
3381 }
3382 __ lea(tmp, addr);
3383 (_masm->*add)(dst, inc, tmp);
3384 break;
3385 }
3386 case lir_xchg:
3387 {
3388 Register tmp = tmp_op->as_register();
3389 Register obj = as_reg(data);
3390 Register dst = as_reg(dest);
3391 if (is_oop && UseCompressedOops) {
3392 __ encode_heap_oop(rscratch2, obj);
3393 obj = rscratch2;
3394 }
3395 assert_different_registers(obj, addr.base(), tmp, rscratch1, dst);
3396 __ lea(tmp, addr);
3397 (_masm->*xchg)(dst, obj, tmp);
3398 if (is_oop && UseCompressedOops) {
3399 __ decode_heap_oop(dst);
3400 }
3401 }
3402 break;
3403 default:
3404 ShouldNotReachHere();
3405 }
3406 __ membar(__ AnyAny);
3407 }
3408
3409 #undef __