1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31 #include "runtime/signature.hpp"
32
33 class ciValueKlass;
34
35 // MacroAssembler extends Assembler by frequently used macros.
36 //
37 // Instructions for which a 'better' code sequence exists depending
38 // on arguments should also go in here.
39
40 class MacroAssembler: public Assembler {
41 friend class LIR_Assembler;
42 friend class Runtime1; // as_Address()
43
44 public:
45 // Support for VM calls
46 //
47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
48 // may customize this version by overriding it for its purposes (e.g., to save/restore
49 // additional registers when doing a VM call).
50
51 virtual void call_VM_leaf_base(
52 address entry_point, // the entry point
53 int number_of_arguments // the number of arguments to pop after the call
54 );
55
56 protected:
57 // This is the base routine called by the different versions of call_VM. The interpreter
58 // may customize this version by overriding it for its purposes (e.g., to save/restore
59 // additional registers when doing a VM call).
60 //
61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
62 // returns the register which contains the thread upon return. If a thread register has been
63 // specified, the return value will correspond to that register. If no last_java_sp is specified
64 // (noreg) than rsp will be used instead.
65 virtual void call_VM_base( // returns the register containing the thread upon return
66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
67 Register java_thread, // the thread if computed before ; use noreg otherwise
68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
69 address entry_point, // the entry point
70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
71 bool check_exceptions // whether to check for pending exceptions after return
72 );
73
74 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
75
76 // helpers for FPU flag access
77 // tmp is a temporary register, if none is available use noreg
78 void save_rax (Register tmp);
79 void restore_rax(Register tmp);
80
81 public:
82 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
83
84 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
85 // The implementation is only non-empty for the InterpreterMacroAssembler,
86 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
87 virtual void check_and_handle_popframe(Register java_thread);
88 virtual void check_and_handle_earlyret(Register java_thread);
89
90 Address as_Address(AddressLiteral adr);
91 Address as_Address(ArrayAddress adr);
92
93 // Support for NULL-checks
94 //
95 // Generates code that causes a NULL OS exception if the content of reg is NULL.
96 // If the accessed location is M[reg + offset] and the offset is known, provide the
97 // offset. No explicit code generation is needed if the offset is within a certain
98 // range (0 <= offset <= page_size).
99
100 void null_check(Register reg, int offset = -1);
101 static bool needs_explicit_null_check(intptr_t offset);
102 static bool uses_implicit_null_check(void* address);
103
104 void test_klass_is_value(Register klass, Register temp_reg, Label& is_value);
105
106 void test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable);
107 void test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable);
108 void test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened);
109
110 // Check oops array storage properties, i.e. flattened and/or null-free
111 void test_flattened_array_oop(Register oop, Register temp_reg, Label&is_flattened_array);
112 void test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array);
113
114 // Required platform-specific helpers for Label::patch_instructions.
115 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
116 void pd_patch_instruction(address branch, address target, const char* file, int line) {
117 unsigned char op = branch[0];
118 assert(op == 0xE8 /* call */ ||
119 op == 0xE9 /* jmp */ ||
120 op == 0xEB /* short jmp */ ||
121 (op & 0xF0) == 0x70 /* short jcc */ ||
122 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
123 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
124 "Invalid opcode at patch point");
125
126 if (op == 0xEB || (op & 0xF0) == 0x70) {
127 // short offset operators (jmp and jcc)
128 char* disp = (char*) &branch[1];
129 int imm8 = target - (address) &disp[1];
130 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d",
131 file == NULL ? "<NULL>" : file, line);
132 *disp = imm8;
133 } else {
134 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
135 int imm32 = target - (address) &disp[1];
136 *disp = imm32;
137 }
138 }
139
140 // The following 4 methods return the offset of the appropriate move instruction
141
142 // Support for fast byte/short loading with zero extension (depending on particular CPU)
143 int load_unsigned_byte(Register dst, Address src);
144 int load_unsigned_short(Register dst, Address src);
145
146 // Support for fast byte/short loading with sign extension (depending on particular CPU)
147 int load_signed_byte(Register dst, Address src);
148 int load_signed_short(Register dst, Address src);
149
150 // Support for sign-extension (hi:lo = extend_sign(lo))
151 void extend_sign(Register hi, Register lo);
152
153 // Load and store values by size and signed-ness
154 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
155 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
156
157 // Support for inc/dec with optimal instruction selection depending on value
158
159 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
160 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
161
162 void decrementl(Address dst, int value = 1);
163 void decrementl(Register reg, int value = 1);
164
165 void decrementq(Register reg, int value = 1);
166 void decrementq(Address dst, int value = 1);
167
168 void incrementl(Address dst, int value = 1);
169 void incrementl(Register reg, int value = 1);
170
171 void incrementq(Register reg, int value = 1);
172 void incrementq(Address dst, int value = 1);
173
174 #ifdef COMPILER2
175 // special instructions for EVEX
176 void setvectmask(Register dst, Register src);
177 void restorevectmask();
178 #endif
179
180 // Support optimal SSE move instructions.
181 void movflt(XMMRegister dst, XMMRegister src) {
182 if (dst-> encoding() == src->encoding()) return;
183 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
184 else { movss (dst, src); return; }
185 }
186 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
187 void movflt(XMMRegister dst, AddressLiteral src);
188 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
189
190 void movdbl(XMMRegister dst, XMMRegister src) {
191 if (dst-> encoding() == src->encoding()) return;
192 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
193 else { movsd (dst, src); return; }
194 }
195
196 void movdbl(XMMRegister dst, AddressLiteral src);
197
198 void movdbl(XMMRegister dst, Address src) {
199 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
200 else { movlpd(dst, src); return; }
201 }
202 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
203
204 void incrementl(AddressLiteral dst);
205 void incrementl(ArrayAddress dst);
206
207 void incrementq(AddressLiteral dst);
208
209 // Alignment
210 void align(int modulus);
211 void align(int modulus, int target);
212
213 // A 5 byte nop that is safe for patching (see patch_verified_entry)
214 void fat_nop();
215
216 // Stack frame creation/removal
217 void enter();
218 void leave();
219
220 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
221 // The pointer will be loaded into the thread register.
222 void get_thread(Register thread);
223
224
225 // Support for VM calls
226 //
227 // It is imperative that all calls into the VM are handled via the call_VM macros.
228 // They make sure that the stack linkage is setup correctly. call_VM's correspond
229 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
230
231
232 void call_VM(Register oop_result,
233 address entry_point,
234 bool check_exceptions = true);
235 void call_VM(Register oop_result,
236 address entry_point,
237 Register arg_1,
238 bool check_exceptions = true);
239 void call_VM(Register oop_result,
240 address entry_point,
241 Register arg_1, Register arg_2,
242 bool check_exceptions = true);
243 void call_VM(Register oop_result,
244 address entry_point,
245 Register arg_1, Register arg_2, Register arg_3,
246 bool check_exceptions = true);
247
248 // Overloadings with last_Java_sp
249 void call_VM(Register oop_result,
250 Register last_java_sp,
251 address entry_point,
252 int number_of_arguments = 0,
253 bool check_exceptions = true);
254 void call_VM(Register oop_result,
255 Register last_java_sp,
256 address entry_point,
257 Register arg_1, bool
258 check_exceptions = true);
259 void call_VM(Register oop_result,
260 Register last_java_sp,
261 address entry_point,
262 Register arg_1, Register arg_2,
263 bool check_exceptions = true);
264 void call_VM(Register oop_result,
265 Register last_java_sp,
266 address entry_point,
267 Register arg_1, Register arg_2, Register arg_3,
268 bool check_exceptions = true);
269
270 void get_vm_result (Register oop_result, Register thread);
271 void get_vm_result_2(Register metadata_result, Register thread);
272
273 // These always tightly bind to MacroAssembler::call_VM_base
274 // bypassing the virtual implementation
275 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
276 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
277 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
278 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
279 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
280
281 void call_VM_leaf0(address entry_point);
282 void call_VM_leaf(address entry_point,
283 int number_of_arguments = 0);
284 void call_VM_leaf(address entry_point,
285 Register arg_1);
286 void call_VM_leaf(address entry_point,
287 Register arg_1, Register arg_2);
288 void call_VM_leaf(address entry_point,
289 Register arg_1, Register arg_2, Register arg_3);
290
291 // These always tightly bind to MacroAssembler::call_VM_leaf_base
292 // bypassing the virtual implementation
293 void super_call_VM_leaf(address entry_point);
294 void super_call_VM_leaf(address entry_point, Register arg_1);
295 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
296 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
297 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
298
299 // last Java Frame (fills frame anchor)
300 void set_last_Java_frame(Register thread,
301 Register last_java_sp,
302 Register last_java_fp,
303 address last_java_pc);
304
305 // thread in the default location (r15_thread on 64bit)
306 void set_last_Java_frame(Register last_java_sp,
307 Register last_java_fp,
308 address last_java_pc);
309
310 void reset_last_Java_frame(Register thread, bool clear_fp);
311
312 // thread in the default location (r15_thread on 64bit)
313 void reset_last_Java_frame(bool clear_fp);
314
315 // jobjects
316 void clear_jweak_tag(Register possibly_jweak);
317 void resolve_jobject(Register value, Register thread, Register tmp);
318
319 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
320 void c2bool(Register x);
321
322 // C++ bool manipulation
323
324 void movbool(Register dst, Address src);
325 void movbool(Address dst, bool boolconst);
326 void movbool(Address dst, Register src);
327 void testbool(Register dst);
328
329 void resolve_oop_handle(Register result, Register tmp = rscratch2);
330 void resolve_weak_handle(Register result, Register tmp);
331 void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
332 void load_method_holder_cld(Register rresult, Register rmethod);
333
334 void load_method_holder(Register holder, Register method);
335
336 // oop manipulations
337 void load_metadata(Register dst, Register src);
338 void load_storage_props(Register dst, Register src);
339 void load_klass(Register dst, Register src);
340 void store_klass(Register dst, Register src);
341
342 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
343 Register tmp1, Register thread_tmp);
344 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
345 Register tmp1, Register tmp2, Register tmp3 = noreg);
346
347 // Resolves obj access. Result is placed in the same register.
348 // All other registers are preserved.
349 void resolve(DecoratorSet decorators, Register obj);
350
351 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
352 Register thread_tmp = noreg, DecoratorSet decorators = 0);
353 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
354 Register thread_tmp = noreg, DecoratorSet decorators = 0);
355 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
356 Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
357
358 // Used for storing NULL. All other oop constants should be
359 // stored using routines that take a jobject.
360 void store_heap_oop_null(Address dst);
361
362 void load_prototype_header(Register dst, Register src);
363
364 #ifdef _LP64
365 void store_klass_gap(Register dst, Register src);
366
367 // This dummy is to prevent a call to store_heap_oop from
368 // converting a zero (like NULL) into a Register by giving
369 // the compiler two choices it can't resolve
370
371 void store_heap_oop(Address dst, void* dummy);
372
373 void encode_heap_oop(Register r);
374 void decode_heap_oop(Register r);
375 void encode_heap_oop_not_null(Register r);
376 void decode_heap_oop_not_null(Register r);
377 void encode_heap_oop_not_null(Register dst, Register src);
378 void decode_heap_oop_not_null(Register dst, Register src);
379
380 void set_narrow_oop(Register dst, jobject obj);
381 void set_narrow_oop(Address dst, jobject obj);
382 void cmp_narrow_oop(Register dst, jobject obj);
383 void cmp_narrow_oop(Address dst, jobject obj);
384
385 void encode_klass_not_null(Register r);
386 void decode_klass_not_null(Register r);
387 void encode_klass_not_null(Register dst, Register src);
388 void decode_klass_not_null(Register dst, Register src);
389 void set_narrow_klass(Register dst, Klass* k);
390 void set_narrow_klass(Address dst, Klass* k);
391 void cmp_narrow_klass(Register dst, Klass* k);
392 void cmp_narrow_klass(Address dst, Klass* k);
393
394 // Returns the byte size of the instructions generated by decode_klass_not_null()
395 // when compressed klass pointers are being used.
396 static int instr_size_for_decode_klass_not_null();
397
398 // if heap base register is used - reinit it with the correct value
399 void reinit_heapbase();
400
401 DEBUG_ONLY(void verify_heapbase(const char* msg);)
402
403 #endif // _LP64
404
405 // Int division/remainder for Java
406 // (as idivl, but checks for special case as described in JVM spec.)
407 // returns idivl instruction offset for implicit exception handling
408 int corrected_idivl(Register reg);
409
410 // Long division/remainder for Java
411 // (as idivq, but checks for special case as described in JVM spec.)
412 // returns idivq instruction offset for implicit exception handling
413 int corrected_idivq(Register reg);
414
415 void int3();
416
417 // Long operation macros for a 32bit cpu
418 // Long negation for Java
419 void lneg(Register hi, Register lo);
420
421 // Long multiplication for Java
422 // (destroys contents of eax, ebx, ecx and edx)
423 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
424
425 // Long shifts for Java
426 // (semantics as described in JVM spec.)
427 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
428 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
429
430 // Long compare for Java
431 // (semantics as described in JVM spec.)
432 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
433
434
435 // misc
436
437 // Sign extension
438 void sign_extend_short(Register reg);
439 void sign_extend_byte(Register reg);
440
441 // Division by power of 2, rounding towards 0
442 void division_with_shift(Register reg, int shift_value);
443
444 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
445 //
446 // CF (corresponds to C0) if x < y
447 // PF (corresponds to C2) if unordered
448 // ZF (corresponds to C3) if x = y
449 //
450 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
451 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
452 void fcmp(Register tmp);
453 // Variant of the above which allows y to be further down the stack
454 // and which only pops x and y if specified. If pop_right is
455 // specified then pop_left must also be specified.
456 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
457
458 // Floating-point comparison for Java
459 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
460 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
461 // (semantics as described in JVM spec.)
462 void fcmp2int(Register dst, bool unordered_is_less);
463 // Variant of the above which allows y to be further down the stack
464 // and which only pops x and y if specified. If pop_right is
465 // specified then pop_left must also be specified.
466 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
467
468 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
469 // tmp is a temporary register, if none is available use noreg
470 void fremr(Register tmp);
471
472 // dst = c = a * b + c
473 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
474 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
475
476 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
477 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
478 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
479 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
480
481
482 // same as fcmp2int, but using SSE2
483 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
484 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
485
486 // branch to L if FPU flag C2 is set/not set
487 // tmp is a temporary register, if none is available use noreg
488 void jC2 (Register tmp, Label& L);
489 void jnC2(Register tmp, Label& L);
490
491 // Pop ST (ffree & fincstp combined)
492 void fpop();
493
494 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
495 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
496 void load_float(Address src);
497
498 // Store float value to 'address'. If UseSSE >= 1, the value is stored
499 // from register xmm0. Otherwise, the value is stored from the FPU stack.
500 void store_float(Address dst);
501
502 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
503 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
504 void load_double(Address src);
505
506 // Store double value to 'address'. If UseSSE >= 2, the value is stored
507 // from register xmm0. Otherwise, the value is stored from the FPU stack.
508 void store_double(Address dst);
509
510 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
511 void push_fTOS();
512
513 // pops double TOS element from CPU stack and pushes on FPU stack
514 void pop_fTOS();
515
516 void empty_FPU_stack();
517
518 void push_IU_state();
519 void pop_IU_state();
520
521 void push_FPU_state();
522 void pop_FPU_state();
523
524 void push_CPU_state();
525 void pop_CPU_state();
526
527 // Round up to a power of two
528 void round_to(Register reg, int modulus);
529
530 // Callee saved registers handling
531 void push_callee_saved_registers();
532 void pop_callee_saved_registers();
533
534 // allocation
535 void eden_allocate(
536 Register thread, // Current thread
537 Register obj, // result: pointer to object after successful allocation
538 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
539 int con_size_in_bytes, // object size in bytes if known at compile time
540 Register t1, // temp register
541 Label& slow_case // continuation point if fast allocation fails
542 );
543 void tlab_allocate(
544 Register thread, // Current thread
545 Register obj, // result: pointer to object after successful allocation
546 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
547 int con_size_in_bytes, // object size in bytes if known at compile time
548 Register t1, // temp register
549 Register t2, // temp register
550 Label& slow_case // continuation point if fast allocation fails
551 );
552 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
553
554 // interface method calling
555 void lookup_interface_method(Register recv_klass,
556 Register intf_klass,
557 RegisterOrConstant itable_index,
558 Register method_result,
559 Register scan_temp,
560 Label& no_such_interface,
561 bool return_method = true);
562
563 // virtual method calling
564 void lookup_virtual_method(Register recv_klass,
565 RegisterOrConstant vtable_index,
566 Register method_result);
567
568 // Test sub_klass against super_klass, with fast and slow paths.
569
570 // The fast path produces a tri-state answer: yes / no / maybe-slow.
571 // One of the three labels can be NULL, meaning take the fall-through.
572 // If super_check_offset is -1, the value is loaded up from super_klass.
573 // No registers are killed, except temp_reg.
574 void check_klass_subtype_fast_path(Register sub_klass,
575 Register super_klass,
576 Register temp_reg,
577 Label* L_success,
578 Label* L_failure,
579 Label* L_slow_path,
580 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
581
582 // The rest of the type check; must be wired to a corresponding fast path.
583 // It does not repeat the fast path logic, so don't use it standalone.
584 // The temp_reg and temp2_reg can be noreg, if no temps are available.
585 // Updates the sub's secondary super cache as necessary.
586 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
587 void check_klass_subtype_slow_path(Register sub_klass,
588 Register super_klass,
589 Register temp_reg,
590 Register temp2_reg,
591 Label* L_success,
592 Label* L_failure,
593 bool set_cond_codes = false);
594
595 // Simplified, combined version, good for typical uses.
596 // Falls through on failure.
597 void check_klass_subtype(Register sub_klass,
598 Register super_klass,
599 Register temp_reg,
600 Label& L_success);
601
602 void clinit_barrier(Register klass,
603 Register thread,
604 Label* L_fast_path = NULL,
605 Label* L_slow_path = NULL);
606
607 // method handles (JSR 292)
608 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
609
610 //----
611 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
612
613 // Debugging
614
615 // only if +VerifyOops
616 // TODO: Make these macros with file and line like sparc version!
617 void verify_oop(Register reg, const char* s = "broken oop");
618 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
619
620 // TODO: verify method and klass metadata (compare against vptr?)
621 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
622 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
623
624 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
625 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
626
627 // only if +VerifyFPU
628 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
629
630 // Verify or restore cpu control state after JNI call
631 void restore_cpu_control_state_after_jni();
632
633 // prints msg, dumps registers and stops execution
634 void stop(const char* msg);
635
636 // prints msg and continues
637 void warn(const char* msg);
638
639 // dumps registers and other state
640 void print_state();
641
642 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
643 static void debug64(char* msg, int64_t pc, int64_t regs[]);
644 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
645 static void print_state64(int64_t pc, int64_t regs[]);
646
647 void os_breakpoint();
648
649 void untested() { stop("untested"); }
650
651 void unimplemented(const char* what = "");
652
653 void should_not_reach_here() { stop("should not reach here"); }
654
655 void print_CPU_state();
656
657 // Stack overflow checking
658 void bang_stack_with_offset(int offset) {
659 // stack grows down, caller passes positive offset
660 assert(offset > 0, "must bang with negative offset");
661 movl(Address(rsp, (-offset)), rax);
662 }
663
664 // Writes to stack successive pages until offset reached to check for
665 // stack overflow + shadow pages. Also, clobbers tmp
666 void bang_stack_size(Register size, Register tmp);
667
668 // Check for reserved stack access in method being exited (for JIT)
669 void reserved_stack_check();
670
671 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
672 Register tmp,
673 int offset);
674
675 // If thread_reg is != noreg the code assumes the register passed contains
676 // the thread (required on 64 bit).
677 void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
678
679 void verify_tlab();
680
681 // Biased locking support
682 // lock_reg and obj_reg must be loaded up with the appropriate values.
683 // swap_reg must be rax, and is killed.
684 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
685 // be killed; if not supplied, push/pop will be used internally to
686 // allocate a temporary (inefficient, avoid if possible).
687 // Optional slow case is for implementations (interpreter and C1) which branch to
688 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
689 // Returns offset of first potentially-faulting instruction for null
690 // check info (currently consumed only by C1). If
691 // swap_reg_contains_mark is true then returns -1 as it is assumed
692 // the calling code has already passed any potential faults.
693 int biased_locking_enter(Register lock_reg, Register obj_reg,
694 Register swap_reg, Register tmp_reg,
695 bool swap_reg_contains_mark,
696 Label& done, Label* slow_case = NULL,
697 BiasedLockingCounters* counters = NULL);
698 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
699 #ifdef COMPILER2
700 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
701 // See full desription in macroAssembler_x86.cpp.
702 void fast_lock(Register obj, Register box, Register tmp,
703 Register scr, Register cx1, Register cx2,
704 BiasedLockingCounters* counters,
705 RTMLockingCounters* rtm_counters,
706 RTMLockingCounters* stack_rtm_counters,
707 Metadata* method_data,
708 bool use_rtm, bool profile_rtm);
709 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
710 #if INCLUDE_RTM_OPT
711 void rtm_counters_update(Register abort_status, Register rtm_counters);
712 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
713 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
714 RTMLockingCounters* rtm_counters,
715 Metadata* method_data);
716 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
717 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
718 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
719 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
720 void rtm_stack_locking(Register obj, Register tmp, Register scr,
721 Register retry_on_abort_count,
722 RTMLockingCounters* stack_rtm_counters,
723 Metadata* method_data, bool profile_rtm,
724 Label& DONE_LABEL, Label& IsInflated);
725 void rtm_inflated_locking(Register obj, Register box, Register tmp,
726 Register scr, Register retry_on_busy_count,
727 Register retry_on_abort_count,
728 RTMLockingCounters* rtm_counters,
729 Metadata* method_data, bool profile_rtm,
730 Label& DONE_LABEL);
731 #endif
732 #endif
733
734 Condition negate_condition(Condition cond);
735
736 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
737 // operands. In general the names are modified to avoid hiding the instruction in Assembler
738 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
739 // here in MacroAssembler. The major exception to this rule is call
740
741 // Arithmetics
742
743
744 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
745 void addptr(Address dst, Register src);
746
747 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
748 void addptr(Register dst, int32_t src);
749 void addptr(Register dst, Register src);
750 void addptr(Register dst, RegisterOrConstant src) {
751 if (src.is_constant()) addptr(dst, (int) src.as_constant());
752 else addptr(dst, src.as_register());
753 }
754
755 void andptr(Register dst, int32_t src);
756 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
757
758 void cmp8(AddressLiteral src1, int imm);
759
760 // renamed to drag out the casting of address to int32_t/intptr_t
761 void cmp32(Register src1, int32_t imm);
762
763 void cmp32(AddressLiteral src1, int32_t imm);
764 // compare reg - mem, or reg - &mem
765 void cmp32(Register src1, AddressLiteral src2);
766
767 void cmp32(Register src1, Address src2);
768
769 #ifndef _LP64
770 void cmpklass(Address dst, Metadata* obj);
771 void cmpklass(Register dst, Metadata* obj);
772 void cmpoop(Address dst, jobject obj);
773 void cmpoop_raw(Address dst, jobject obj);
774 #endif // _LP64
775
776 void cmpoop(Register src1, Register src2);
777 void cmpoop(Register src1, Address src2);
778 void cmpoop(Register dst, jobject obj);
779 void cmpoop_raw(Register dst, jobject obj);
780
781 // NOTE src2 must be the lval. This is NOT an mem-mem compare
782 void cmpptr(Address src1, AddressLiteral src2);
783
784 void cmpptr(Register src1, AddressLiteral src2);
785
786 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
787 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
788 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
789
790 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
791 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
792
793 // cmp64 to avoild hiding cmpq
794 void cmp64(Register src1, AddressLiteral src);
795
796 void cmpxchgptr(Register reg, Address adr);
797
798 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
799
800
801 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
802 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
803
804
805 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
806
807 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
808
809 void shlptr(Register dst, int32_t shift);
810 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
811
812 void shrptr(Register dst, int32_t shift);
813 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
814
815 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
816 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
817
818 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
819
820 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
821 void subptr(Register dst, int32_t src);
822 // Force generation of a 4 byte immediate value even if it fits into 8bit
823 void subptr_imm32(Register dst, int32_t src);
824 void subptr(Register dst, Register src);
825 void subptr(Register dst, RegisterOrConstant src) {
826 if (src.is_constant()) subptr(dst, (int) src.as_constant());
827 else subptr(dst, src.as_register());
828 }
829
830 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
831 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
832
833 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
834 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
835
836 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
837
838
839
840 // Helper functions for statistics gathering.
841 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
842 void cond_inc32(Condition cond, AddressLiteral counter_addr);
843 // Unconditional atomic increment.
844 void atomic_incl(Address counter_addr);
845 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
846 #ifdef _LP64
847 void atomic_incq(Address counter_addr);
848 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
849 #endif
850 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
851 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
852
853 void lea(Register dst, AddressLiteral adr);
854 void lea(Address dst, AddressLiteral adr);
855 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
856
857 void leal32(Register dst, Address src) { leal(dst, src); }
858
859 // Import other testl() methods from the parent class or else
860 // they will be hidden by the following overriding declaration.
861 using Assembler::testl;
862 void testl(Register dst, AddressLiteral src);
863
864 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
865 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
866 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
867 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
868
869 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
870 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
871 void testptr(Register src1, Register src2);
872
873 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
874 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
875
876 // Calls
877
878 void call(Label& L, relocInfo::relocType rtype);
879 void call(Register entry);
880
881 // NOTE: this call transfers to the effective address of entry NOT
882 // the address contained by entry. This is because this is more natural
883 // for jumps/calls.
884 void call(AddressLiteral entry);
885
886 // Emit the CompiledIC call idiom
887 void ic_call(address entry, jint method_index = 0);
888
889 // Jumps
890
891 // NOTE: these jumps tranfer to the effective address of dst NOT
892 // the address contained by dst. This is because this is more natural
893 // for jumps/calls.
894 void jump(AddressLiteral dst);
895 void jump_cc(Condition cc, AddressLiteral dst);
896
897 // 32bit can do a case table jump in one instruction but we no longer allow the base
898 // to be installed in the Address class. This jump will tranfers to the address
899 // contained in the location described by entry (not the address of entry)
900 void jump(ArrayAddress entry);
901
902 // Floating
903
904 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
905 void andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
906 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
907
908 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
909 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
910 void andps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
911
912 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
913 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
914 void comiss(XMMRegister dst, AddressLiteral src);
915
916 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
917 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
918 void comisd(XMMRegister dst, AddressLiteral src);
919
920 void fadd_s(Address src) { Assembler::fadd_s(src); }
921 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
922
923 void fldcw(Address src) { Assembler::fldcw(src); }
924 void fldcw(AddressLiteral src);
925
926 void fld_s(int index) { Assembler::fld_s(index); }
927 void fld_s(Address src) { Assembler::fld_s(src); }
928 void fld_s(AddressLiteral src);
929
930 void fld_d(Address src) { Assembler::fld_d(src); }
931 void fld_d(AddressLiteral src);
932
933 void fld_x(Address src) { Assembler::fld_x(src); }
934 void fld_x(AddressLiteral src);
935
936 void fmul_s(Address src) { Assembler::fmul_s(src); }
937 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
938
939 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
940 void ldmxcsr(AddressLiteral src);
941
942 #ifdef _LP64
943 private:
944 void sha256_AVX2_one_round_compute(
945 Register reg_old_h,
946 Register reg_a,
947 Register reg_b,
948 Register reg_c,
949 Register reg_d,
950 Register reg_e,
951 Register reg_f,
952 Register reg_g,
953 Register reg_h,
954 int iter);
955 void sha256_AVX2_four_rounds_compute_first(int start);
956 void sha256_AVX2_four_rounds_compute_last(int start);
957 void sha256_AVX2_one_round_and_sched(
958 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
959 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
960 XMMRegister xmm_2, /* ymm6 */
961 XMMRegister xmm_3, /* ymm7 */
962 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
963 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
964 Register reg_c, /* edi */
965 Register reg_d, /* esi */
966 Register reg_e, /* r8d */
967 Register reg_f, /* r9d */
968 Register reg_g, /* r10d */
969 Register reg_h, /* r11d */
970 int iter);
971
972 void addm(int disp, Register r1, Register r2);
973 void gfmul(XMMRegister tmp0, XMMRegister t);
974 void schoolbookAAD(int i, Register subkeyH, XMMRegister data, XMMRegister tmp0,
975 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3);
976 void generateHtbl_one_block(Register htbl);
977 void generateHtbl_eight_blocks(Register htbl);
978 public:
979 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
980 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
981 Register buf, Register state, Register ofs, Register limit, Register rsp,
982 bool multi_block, XMMRegister shuf_mask);
983 void avx_ghash(Register state, Register htbl, Register data, Register blocks);
984 #endif
985
986 #ifdef _LP64
987 private:
988 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
989 Register e, Register f, Register g, Register h, int iteration);
990
991 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
992 Register a, Register b, Register c, Register d, Register e, Register f,
993 Register g, Register h, int iteration);
994
995 void addmq(int disp, Register r1, Register r2);
996 public:
997 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
998 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
999 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
1000 XMMRegister shuf_mask);
1001 private:
1002 void roundEnc(XMMRegister key, int rnum);
1003 void lastroundEnc(XMMRegister key, int rnum);
1004 void roundDec(XMMRegister key, int rnum);
1005 void lastroundDec(XMMRegister key, int rnum);
1006 void ev_load_key(XMMRegister xmmdst, Register key, int offset, XMMRegister xmm_shuf_mask);
1007
1008 public:
1009 void aesecb_encrypt(Register source_addr, Register dest_addr, Register key, Register len);
1010 void aesecb_decrypt(Register source_addr, Register dest_addr, Register key, Register len);
1011
1012 #endif
1013
1014 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
1015 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
1016 Register buf, Register state, Register ofs, Register limit, Register rsp,
1017 bool multi_block);
1018
1019 #ifdef _LP64
1020 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1021 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1022 Register buf, Register state, Register ofs, Register limit, Register rsp,
1023 bool multi_block, XMMRegister shuf_mask);
1024 #else
1025 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1026 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1027 Register buf, Register state, Register ofs, Register limit, Register rsp,
1028 bool multi_block);
1029 #endif
1030
1031 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1032 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1033 Register rax, Register rcx, Register rdx, Register tmp);
1034
1035 #ifdef _LP64
1036 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1037 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1038 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
1039
1040 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1041 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1042 Register rax, Register rcx, Register rdx, Register r11);
1043
1044 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1045 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1046 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1047
1048 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1049 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1050 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1051 Register tmp3, Register tmp4);
1052
1053 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1054 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1055 Register rax, Register rcx, Register rdx, Register tmp1,
1056 Register tmp2, Register tmp3, Register tmp4);
1057 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1058 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1059 Register rax, Register rcx, Register rdx, Register tmp1,
1060 Register tmp2, Register tmp3, Register tmp4);
1061 #else
1062 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1063 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1064 Register rax, Register rcx, Register rdx, Register tmp1);
1065
1066 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1067 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1068 Register rax, Register rcx, Register rdx, Register tmp);
1069
1070 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1071 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1072 Register rdx, Register tmp);
1073
1074 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1075 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1076 Register rax, Register rbx, Register rdx);
1077
1078 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1079 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1080 Register rax, Register rcx, Register rdx, Register tmp);
1081
1082 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1083 Register edx, Register ebx, Register esi, Register edi,
1084 Register ebp, Register esp);
1085
1086 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1087 Register esi, Register edi, Register ebp, Register esp);
1088
1089 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1090 Register edx, Register ebx, Register esi, Register edi,
1091 Register ebp, Register esp);
1092
1093 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1094 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1095 Register rax, Register rcx, Register rdx, Register tmp);
1096 #endif
1097
1098 void increase_precision();
1099 void restore_precision();
1100
1101 private:
1102
1103 // these are private because users should be doing movflt/movdbl
1104
1105 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1106 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1107 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1108 void movss(XMMRegister dst, AddressLiteral src);
1109
1110 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1111 void movlpd(XMMRegister dst, AddressLiteral src);
1112
1113 public:
1114
1115 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1116 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1117 void addsd(XMMRegister dst, AddressLiteral src);
1118
1119 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1120 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1121 void addss(XMMRegister dst, AddressLiteral src);
1122
1123 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1124 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1125 void addpd(XMMRegister dst, AddressLiteral src);
1126
1127 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1128 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1129 void divsd(XMMRegister dst, AddressLiteral src);
1130
1131 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1132 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1133 void divss(XMMRegister dst, AddressLiteral src);
1134
1135 // Move Unaligned Double Quadword
1136 void movdqu(Address dst, XMMRegister src);
1137 void movdqu(XMMRegister dst, Address src);
1138 void movdqu(XMMRegister dst, XMMRegister src);
1139 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1140 // AVX Unaligned forms
1141 void vmovdqu(Address dst, XMMRegister src);
1142 void vmovdqu(XMMRegister dst, Address src);
1143 void vmovdqu(XMMRegister dst, XMMRegister src);
1144 void vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1145 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1146 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1147 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1148 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1149
1150 // Move Aligned Double Quadword
1151 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1152 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1153 void movdqa(XMMRegister dst, AddressLiteral src);
1154
1155 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1156 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1157 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1158 void movsd(XMMRegister dst, AddressLiteral src);
1159
1160 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1161 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1162 void mulpd(XMMRegister dst, AddressLiteral src);
1163
1164 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1165 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1166 void mulsd(XMMRegister dst, AddressLiteral src);
1167
1168 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1169 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1170 void mulss(XMMRegister dst, AddressLiteral src);
1171
1172 // Carry-Less Multiplication Quadword
1173 void pclmulldq(XMMRegister dst, XMMRegister src) {
1174 // 0x00 - multiply lower 64 bits [0:63]
1175 Assembler::pclmulqdq(dst, src, 0x00);
1176 }
1177 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1178 // 0x11 - multiply upper 64 bits [64:127]
1179 Assembler::pclmulqdq(dst, src, 0x11);
1180 }
1181
1182 void pcmpeqb(XMMRegister dst, XMMRegister src);
1183 void pcmpeqw(XMMRegister dst, XMMRegister src);
1184
1185 void pcmpestri(XMMRegister dst, Address src, int imm8);
1186 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1187
1188 void pmovzxbw(XMMRegister dst, XMMRegister src);
1189 void pmovzxbw(XMMRegister dst, Address src);
1190
1191 void pmovmskb(Register dst, XMMRegister src);
1192
1193 void ptest(XMMRegister dst, XMMRegister src);
1194
1195 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1196 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1197 void sqrtsd(XMMRegister dst, AddressLiteral src);
1198
1199 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1200 void roundsd(XMMRegister dst, Address src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1201 void roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg);
1202
1203 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1204 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1205 void sqrtss(XMMRegister dst, AddressLiteral src);
1206
1207 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1208 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1209 void subsd(XMMRegister dst, AddressLiteral src);
1210
1211 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1212 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1213 void subss(XMMRegister dst, AddressLiteral src);
1214
1215 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1216 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1217 void ucomiss(XMMRegister dst, AddressLiteral src);
1218
1219 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1220 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1221 void ucomisd(XMMRegister dst, AddressLiteral src);
1222
1223 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1224 void xorpd(XMMRegister dst, XMMRegister src);
1225 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1226 void xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1227
1228 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1229 void xorps(XMMRegister dst, XMMRegister src);
1230 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1231 void xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1232
1233 // Shuffle Bytes
1234 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1235 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1236 void pshufb(XMMRegister dst, AddressLiteral src);
1237 // AVX 3-operands instructions
1238
1239 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1240 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1241 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1242
1243 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1244 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1245 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1246
1247 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1248 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1249
1250 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1251 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1252
1253 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1254 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1255
1256 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1257 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1258 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1259
1260 void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1261 void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); }
1262
1263 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1264
1265 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1266
1267 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1268 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1269
1270 void vpmovmskb(Register dst, XMMRegister src);
1271
1272 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1273 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1274
1275 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1276 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1277
1278 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1279 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1280
1281 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1282 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1283
1284 void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1285 void evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1286
1287 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1288 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1289
1290 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1291 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1292
1293 void vptest(XMMRegister dst, XMMRegister src);
1294
1295 void punpcklbw(XMMRegister dst, XMMRegister src);
1296 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1297
1298 void pshufd(XMMRegister dst, Address src, int mode);
1299 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1300
1301 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1302 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1303
1304 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1305 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1306 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1307
1308 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1309 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1310 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1311
1312 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1313 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1314 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1315
1316 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1317 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1318 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1319
1320 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1321 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1322 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1323
1324 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1325 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1326 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1327
1328 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1329 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1330 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1331
1332 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1333 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1334 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1335
1336 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1337 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1338
1339 // AVX Vector instructions
1340
1341 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1342 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1343 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1344
1345 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1346 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1347 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1348
1349 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1350 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1351 Assembler::vpxor(dst, nds, src, vector_len);
1352 else
1353 Assembler::vxorpd(dst, nds, src, vector_len);
1354 }
1355 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1356 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1357 Assembler::vpxor(dst, nds, src, vector_len);
1358 else
1359 Assembler::vxorpd(dst, nds, src, vector_len);
1360 }
1361 void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1362
1363 // Simple version for AVX2 256bit vectors
1364 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1365 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1366
1367 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1368 if (UseAVX > 2) {
1369 Assembler::vinserti32x4(dst, dst, src, imm8);
1370 } else if (UseAVX > 1) {
1371 // vinserti128 is available only in AVX2
1372 Assembler::vinserti128(dst, nds, src, imm8);
1373 } else {
1374 Assembler::vinsertf128(dst, nds, src, imm8);
1375 }
1376 }
1377
1378 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1379 if (UseAVX > 2) {
1380 Assembler::vinserti32x4(dst, dst, src, imm8);
1381 } else if (UseAVX > 1) {
1382 // vinserti128 is available only in AVX2
1383 Assembler::vinserti128(dst, nds, src, imm8);
1384 } else {
1385 Assembler::vinsertf128(dst, nds, src, imm8);
1386 }
1387 }
1388
1389 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1390 if (UseAVX > 2) {
1391 Assembler::vextracti32x4(dst, src, imm8);
1392 } else if (UseAVX > 1) {
1393 // vextracti128 is available only in AVX2
1394 Assembler::vextracti128(dst, src, imm8);
1395 } else {
1396 Assembler::vextractf128(dst, src, imm8);
1397 }
1398 }
1399
1400 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1401 if (UseAVX > 2) {
1402 Assembler::vextracti32x4(dst, src, imm8);
1403 } else if (UseAVX > 1) {
1404 // vextracti128 is available only in AVX2
1405 Assembler::vextracti128(dst, src, imm8);
1406 } else {
1407 Assembler::vextractf128(dst, src, imm8);
1408 }
1409 }
1410
1411 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1412 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1413 vinserti128(dst, dst, src, 1);
1414 }
1415 void vinserti128_high(XMMRegister dst, Address src) {
1416 vinserti128(dst, dst, src, 1);
1417 }
1418 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1419 vextracti128(dst, src, 1);
1420 }
1421 void vextracti128_high(Address dst, XMMRegister src) {
1422 vextracti128(dst, src, 1);
1423 }
1424
1425 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1426 if (UseAVX > 2) {
1427 Assembler::vinsertf32x4(dst, dst, src, 1);
1428 } else {
1429 Assembler::vinsertf128(dst, dst, src, 1);
1430 }
1431 }
1432
1433 void vinsertf128_high(XMMRegister dst, Address src) {
1434 if (UseAVX > 2) {
1435 Assembler::vinsertf32x4(dst, dst, src, 1);
1436 } else {
1437 Assembler::vinsertf128(dst, dst, src, 1);
1438 }
1439 }
1440
1441 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1442 if (UseAVX > 2) {
1443 Assembler::vextractf32x4(dst, src, 1);
1444 } else {
1445 Assembler::vextractf128(dst, src, 1);
1446 }
1447 }
1448
1449 void vextractf128_high(Address dst, XMMRegister src) {
1450 if (UseAVX > 2) {
1451 Assembler::vextractf32x4(dst, src, 1);
1452 } else {
1453 Assembler::vextractf128(dst, src, 1);
1454 }
1455 }
1456
1457 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1458 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1459 Assembler::vinserti64x4(dst, dst, src, 1);
1460 }
1461 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1462 Assembler::vinsertf64x4(dst, dst, src, 1);
1463 }
1464 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1465 Assembler::vextracti64x4(dst, src, 1);
1466 }
1467 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1468 Assembler::vextractf64x4(dst, src, 1);
1469 }
1470 void vextractf64x4_high(Address dst, XMMRegister src) {
1471 Assembler::vextractf64x4(dst, src, 1);
1472 }
1473 void vinsertf64x4_high(XMMRegister dst, Address src) {
1474 Assembler::vinsertf64x4(dst, dst, src, 1);
1475 }
1476
1477 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1478 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1479 vinserti128(dst, dst, src, 0);
1480 }
1481 void vinserti128_low(XMMRegister dst, Address src) {
1482 vinserti128(dst, dst, src, 0);
1483 }
1484 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1485 vextracti128(dst, src, 0);
1486 }
1487 void vextracti128_low(Address dst, XMMRegister src) {
1488 vextracti128(dst, src, 0);
1489 }
1490
1491 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1492 if (UseAVX > 2) {
1493 Assembler::vinsertf32x4(dst, dst, src, 0);
1494 } else {
1495 Assembler::vinsertf128(dst, dst, src, 0);
1496 }
1497 }
1498
1499 void vinsertf128_low(XMMRegister dst, Address src) {
1500 if (UseAVX > 2) {
1501 Assembler::vinsertf32x4(dst, dst, src, 0);
1502 } else {
1503 Assembler::vinsertf128(dst, dst, src, 0);
1504 }
1505 }
1506
1507 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1508 if (UseAVX > 2) {
1509 Assembler::vextractf32x4(dst, src, 0);
1510 } else {
1511 Assembler::vextractf128(dst, src, 0);
1512 }
1513 }
1514
1515 void vextractf128_low(Address dst, XMMRegister src) {
1516 if (UseAVX > 2) {
1517 Assembler::vextractf32x4(dst, src, 0);
1518 } else {
1519 Assembler::vextractf128(dst, src, 0);
1520 }
1521 }
1522
1523 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1524 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1525 Assembler::vinserti64x4(dst, dst, src, 0);
1526 }
1527 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1528 Assembler::vinsertf64x4(dst, dst, src, 0);
1529 }
1530 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1531 Assembler::vextracti64x4(dst, src, 0);
1532 }
1533 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1534 Assembler::vextractf64x4(dst, src, 0);
1535 }
1536 void vextractf64x4_low(Address dst, XMMRegister src) {
1537 Assembler::vextractf64x4(dst, src, 0);
1538 }
1539 void vinsertf64x4_low(XMMRegister dst, Address src) {
1540 Assembler::vinsertf64x4(dst, dst, src, 0);
1541 }
1542
1543 // Carry-Less Multiplication Quadword
1544 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1545 // 0x00 - multiply lower 64 bits [0:63]
1546 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1547 }
1548 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1549 // 0x11 - multiply upper 64 bits [64:127]
1550 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1551 }
1552 void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1553 // 0x10 - multiply nds[0:63] and src[64:127]
1554 Assembler::vpclmulqdq(dst, nds, src, 0x10);
1555 }
1556 void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1557 //0x01 - multiply nds[64:127] and src[0:63]
1558 Assembler::vpclmulqdq(dst, nds, src, 0x01);
1559 }
1560
1561 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1562 // 0x00 - multiply lower 64 bits [0:63]
1563 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1564 }
1565 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1566 // 0x11 - multiply upper 64 bits [64:127]
1567 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1568 }
1569
1570 // Data
1571
1572 void cmov32( Condition cc, Register dst, Address src);
1573 void cmov32( Condition cc, Register dst, Register src);
1574
1575 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1576
1577 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1578 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1579
1580 void movoop(Register dst, jobject obj);
1581 void movoop(Address dst, jobject obj);
1582
1583 void mov_metadata(Register dst, Metadata* obj);
1584 void mov_metadata(Address dst, Metadata* obj);
1585
1586 void movptr(ArrayAddress dst, Register src);
1587 // can this do an lea?
1588 void movptr(Register dst, ArrayAddress src);
1589
1590 void movptr(Register dst, Address src);
1591
1592 #ifdef _LP64
1593 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1594 #else
1595 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1596 #endif
1597
1598 void movptr(Register dst, intptr_t src);
1599 void movptr(Register dst, Register src);
1600 void movptr(Address dst, intptr_t src);
1601
1602 void movptr(Address dst, Register src);
1603
1604 void movptr(Register dst, RegisterOrConstant src) {
1605 if (src.is_constant()) movptr(dst, src.as_constant());
1606 else movptr(dst, src.as_register());
1607 }
1608
1609 #ifdef _LP64
1610 // Generally the next two are only used for moving NULL
1611 // Although there are situations in initializing the mark word where
1612 // they could be used. They are dangerous.
1613
1614 // They only exist on LP64 so that int32_t and intptr_t are not the same
1615 // and we have ambiguous declarations.
1616
1617 void movptr(Address dst, int32_t imm32);
1618 void movptr(Register dst, int32_t imm32);
1619 #endif // _LP64
1620
1621 // to avoid hiding movl
1622 void mov32(AddressLiteral dst, Register src);
1623 void mov32(Register dst, AddressLiteral src);
1624
1625 // to avoid hiding movb
1626 void movbyte(ArrayAddress dst, int src);
1627
1628 // Import other mov() methods from the parent class or else
1629 // they will be hidden by the following overriding declaration.
1630 using Assembler::movdl;
1631 using Assembler::movq;
1632 void movdl(XMMRegister dst, AddressLiteral src);
1633 void movq(XMMRegister dst, AddressLiteral src);
1634
1635 // Can push value or effective address
1636 void pushptr(AddressLiteral src);
1637
1638 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1639 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1640
1641 void pushoop(jobject obj);
1642 void pushklass(Metadata* obj);
1643
1644 // sign extend as need a l to ptr sized element
1645 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1646 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1647
1648 #ifdef COMPILER2
1649 // Generic instructions support for use in .ad files C2 code generation
1650 void vabsnegd(int opcode, XMMRegister dst, Register scr);
1651 void vabsnegd(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr);
1652 void vabsnegf(int opcode, XMMRegister dst, Register scr);
1653 void vabsnegf(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr);
1654 void vextendbw(bool sign, XMMRegister dst, XMMRegister src, int vector_len);
1655 void vextendbw(bool sign, XMMRegister dst, XMMRegister src);
1656 void vshiftd(int opcode, XMMRegister dst, XMMRegister src);
1657 void vshiftd(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1658 void vshiftw(int opcode, XMMRegister dst, XMMRegister src);
1659 void vshiftw(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1660 void vshiftq(int opcode, XMMRegister dst, XMMRegister src);
1661 void vshiftq(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1662 #endif
1663
1664 // C2 compiled method's prolog code.
1665 void verified_entry(Compile* C, int sp_inc = 0);
1666
1667 enum RegState {
1668 reg_readonly,
1669 reg_writable,
1670 reg_written
1671 };
1672
1673 int store_value_type_fields_to_buf(ciValueKlass* vk, bool from_interpreter = true);
1674
1675 // Unpack all value type arguments passed as oops
1676 void unpack_value_args(Compile* C, bool receiver_only);
1677 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[], int ret_off, int extra_stack_offset);
1678 bool unpack_value_helper(const GrowableArray<SigEntry>* sig, int& sig_index, VMReg from, VMRegPair* regs_to, int& to_index,
1679 RegState reg_state[], int ret_off, int extra_stack_offset);
1680 bool pack_value_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1681 VMReg to, VMRegPair* regs_from, int regs_from_count, int& from_index, RegState reg_state[],
1682 int ret_off, int extra_stack_offset);
1683 void restore_stack(Compile* C);
1684
1685 int shuffle_value_args(bool is_packing, bool receiver_only, int extra_stack_offset,
1686 BasicType* sig_bt, const GrowableArray<SigEntry>* sig_cc,
1687 int args_passed, int args_on_stack, VMRegPair* regs,
1688 int args_passed_to, int args_on_stack_to, VMRegPair* regs_to);
1689 bool shuffle_value_args_spill(bool is_packing, const GrowableArray<SigEntry>* sig_cc, int sig_cc_index,
1690 VMRegPair* regs_from, int from_index, int regs_from_count,
1691 RegState* reg_state, int sp_inc, int extra_stack_offset);
1692 VMReg spill_reg_for(VMReg reg);
1693
1694 // clear memory of size 'cnt' qwords, starting at 'base';
1695 // if 'is_large' is set, do not try to produce short loop
1696 void clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, bool is_large, bool word_copy_only);
1697
1698 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1699 void xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp);
1700
1701 #ifdef COMPILER2
1702 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1703 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1704
1705 // IndexOf strings.
1706 // Small strings are loaded through stack if they cross page boundary.
1707 void string_indexof(Register str1, Register str2,
1708 Register cnt1, Register cnt2,
1709 int int_cnt2, Register result,
1710 XMMRegister vec, Register tmp,
1711 int ae);
1712
1713 // IndexOf for constant substrings with size >= 8 elements
1714 // which don't need to be loaded through stack.
1715 void string_indexofC8(Register str1, Register str2,
1716 Register cnt1, Register cnt2,
1717 int int_cnt2, Register result,
1718 XMMRegister vec, Register tmp,
1719 int ae);
1720
1721 // Smallest code: we don't need to load through stack,
1722 // check string tail.
1723
1724 // helper function for string_compare
1725 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1726 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1727 Address::ScaleFactor scale2, Register index, int ae);
1728 // Compare strings.
1729 void string_compare(Register str1, Register str2,
1730 Register cnt1, Register cnt2, Register result,
1731 XMMRegister vec1, int ae);
1732
1733 // Search for Non-ASCII character (Negative byte value) in a byte array,
1734 // return true if it has any and false otherwise.
1735 void has_negatives(Register ary1, Register len,
1736 Register result, Register tmp1,
1737 XMMRegister vec1, XMMRegister vec2);
1738
1739 // Compare char[] or byte[] arrays.
1740 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1741 Register limit, Register result, Register chr,
1742 XMMRegister vec1, XMMRegister vec2, bool is_char);
1743
1744 #endif
1745
1746 // Fill primitive arrays
1747 void generate_fill(BasicType t, bool aligned,
1748 Register to, Register value, Register count,
1749 Register rtmp, XMMRegister xtmp);
1750
1751 void encode_iso_array(Register src, Register dst, Register len,
1752 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1753 XMMRegister tmp4, Register tmp5, Register result);
1754
1755 #ifdef _LP64
1756 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1757 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1758 Register y, Register y_idx, Register z,
1759 Register carry, Register product,
1760 Register idx, Register kdx);
1761 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1762 Register yz_idx, Register idx,
1763 Register carry, Register product, int offset);
1764 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1765 Register carry, Register carry2,
1766 Register idx, Register jdx,
1767 Register yz_idx1, Register yz_idx2,
1768 Register tmp, Register tmp3, Register tmp4);
1769 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1770 Register yz_idx, Register idx, Register jdx,
1771 Register carry, Register product,
1772 Register carry2);
1773 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1774 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1775 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1776 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1777 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1778 Register tmp2);
1779 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1780 Register rdxReg, Register raxReg);
1781 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1782 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1783 Register tmp3, Register tmp4);
1784 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1785 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1786
1787 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1788 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1789 Register raxReg);
1790 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1791 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1792 Register raxReg);
1793 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1794 Register result, Register tmp1, Register tmp2,
1795 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1796 #endif
1797
1798 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1799 void update_byte_crc32(Register crc, Register val, Register table);
1800 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1801 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1802 // Note on a naming convention:
1803 // Prefix w = register only used on a Westmere+ architecture
1804 // Prefix n = register only used on a Nehalem architecture
1805 #ifdef _LP64
1806 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1807 Register tmp1, Register tmp2, Register tmp3);
1808 #else
1809 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1810 Register tmp1, Register tmp2, Register tmp3,
1811 XMMRegister xtmp1, XMMRegister xtmp2);
1812 #endif
1813 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1814 Register in_out,
1815 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1816 XMMRegister w_xtmp2,
1817 Register tmp1,
1818 Register n_tmp2, Register n_tmp3);
1819 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1820 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1821 Register tmp1, Register tmp2,
1822 Register n_tmp3);
1823 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1824 Register in_out1, Register in_out2, Register in_out3,
1825 Register tmp1, Register tmp2, Register tmp3,
1826 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1827 Register tmp4, Register tmp5,
1828 Register n_tmp6);
1829 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1830 Register tmp1, Register tmp2, Register tmp3,
1831 Register tmp4, Register tmp5, Register tmp6,
1832 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1833 bool is_pclmulqdq_supported);
1834 // Fold 128-bit data chunk
1835 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1836 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1837 // Fold 8-bit data
1838 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1839 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1840 void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1841
1842 // Compress char[] array to byte[].
1843 void char_array_compress(Register src, Register dst, Register len,
1844 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1845 XMMRegister tmp4, Register tmp5, Register result);
1846
1847 // Inflate byte[] array to char[].
1848 void byte_array_inflate(Register src, Register dst, Register len,
1849 XMMRegister tmp1, Register tmp2);
1850
1851 #ifdef _LP64
1852 void cache_wb(Address line);
1853 void cache_wbsync(bool is_pre);
1854 #endif // _LP64
1855
1856 #include "asm/macroAssembler_common.hpp"
1857
1858 };
1859
1860 /**
1861 * class SkipIfEqual:
1862 *
1863 * Instantiating this class will result in assembly code being output that will
1864 * jump around any code emitted between the creation of the instance and it's
1865 * automatic destruction at the end of a scope block, depending on the value of
1866 * the flag passed to the constructor, which will be checked at run-time.
1867 */
1868 class SkipIfEqual {
1869 private:
1870 MacroAssembler* _masm;
1871 Label _label;
1872
1873 public:
1874 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1875 ~SkipIfEqual();
1876 };
1877
1878 #endif // CPU_X86_MACROASSEMBLER_X86_HPP