1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31 #include "runtime/signature.hpp"
32
33 class ciValueKlass;
34
35 // MacroAssembler extends Assembler by frequently used macros.
36 //
37 // Instructions for which a 'better' code sequence exists depending
38 // on arguments should also go in here.
39
40 class MacroAssembler: public Assembler {
41 friend class LIR_Assembler;
42 friend class Runtime1; // as_Address()
43
44 public:
45 // Support for VM calls
46 //
47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
48 // may customize this version by overriding it for its purposes (e.g., to save/restore
49 // additional registers when doing a VM call).
50
51 virtual void call_VM_leaf_base(
52 address entry_point, // the entry point
53 int number_of_arguments // the number of arguments to pop after the call
54 );
55
56 protected:
57 // This is the base routine called by the different versions of call_VM. The interpreter
58 // may customize this version by overriding it for its purposes (e.g., to save/restore
59 // additional registers when doing a VM call).
60 //
61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
62 // returns the register which contains the thread upon return. If a thread register has been
63 // specified, the return value will correspond to that register. If no last_java_sp is specified
64 // (noreg) than rsp will be used instead.
65 virtual void call_VM_base( // returns the register containing the thread upon return
66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
67 Register java_thread, // the thread if computed before ; use noreg otherwise
68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
69 address entry_point, // the entry point
70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
71 bool check_exceptions // whether to check for pending exceptions after return
72 );
73
74 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
75
76 // helpers for FPU flag access
77 // tmp is a temporary register, if none is available use noreg
78 void save_rax (Register tmp);
79 void restore_rax(Register tmp);
80
81 public:
82 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
83
84 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
85 // The implementation is only non-empty for the InterpreterMacroAssembler,
86 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
87 virtual void check_and_handle_popframe(Register java_thread);
88 virtual void check_and_handle_earlyret(Register java_thread);
89
90 Address as_Address(AddressLiteral adr);
91 Address as_Address(ArrayAddress adr);
92
93 // Support for NULL-checks
94 //
95 // Generates code that causes a NULL OS exception if the content of reg is NULL.
96 // If the accessed location is M[reg + offset] and the offset is known, provide the
97 // offset. No explicit code generation is needed if the offset is within a certain
98 // range (0 <= offset <= page_size).
99
100 void null_check(Register reg, int offset = -1);
101 static bool needs_explicit_null_check(intptr_t offset);
102 static bool uses_implicit_null_check(void* address);
103
104 // valueKlass queries, kills temp_reg
105 void test_klass_is_value(Register klass, Register temp_reg, Label& is_value);
106 void test_klass_is_empty_value(Register klass, Register temp_reg, Label& is_empty_value);
107 // For field "index" within "klass", return value_klass ...
108 void get_empty_value_oop(Register klass, Register temp_reg, Register obj);
109
110 void test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable);
111 void test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable);
112 void test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened);
113
114 // Check oops array storage properties, i.e. flattened and/or null-free
115 void test_flattened_array_oop(Register oop, Register temp_reg, Label&is_flattened_array);
116 void test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array);
117
118 // Required platform-specific helpers for Label::patch_instructions.
119 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
120 void pd_patch_instruction(address branch, address target, const char* file, int line) {
121 unsigned char op = branch[0];
122 assert(op == 0xE8 /* call */ ||
123 op == 0xE9 /* jmp */ ||
124 op == 0xEB /* short jmp */ ||
125 (op & 0xF0) == 0x70 /* short jcc */ ||
126 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
127 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
128 "Invalid opcode at patch point");
129
130 if (op == 0xEB || (op & 0xF0) == 0x70) {
131 // short offset operators (jmp and jcc)
132 char* disp = (char*) &branch[1];
133 int imm8 = target - (address) &disp[1];
134 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d",
135 file == NULL ? "<NULL>" : file, line);
136 *disp = imm8;
137 } else {
138 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
139 int imm32 = target - (address) &disp[1];
140 *disp = imm32;
141 }
142 }
143
144 // The following 4 methods return the offset of the appropriate move instruction
145
146 // Support for fast byte/short loading with zero extension (depending on particular CPU)
147 int load_unsigned_byte(Register dst, Address src);
148 int load_unsigned_short(Register dst, Address src);
149
150 // Support for fast byte/short loading with sign extension (depending on particular CPU)
151 int load_signed_byte(Register dst, Address src);
152 int load_signed_short(Register dst, Address src);
153
154 // Support for sign-extension (hi:lo = extend_sign(lo))
155 void extend_sign(Register hi, Register lo);
156
157 // Load and store values by size and signed-ness
158 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
159 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
160
161 // Support for inc/dec with optimal instruction selection depending on value
162
163 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
164 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
165
166 void decrementl(Address dst, int value = 1);
167 void decrementl(Register reg, int value = 1);
168
169 void decrementq(Register reg, int value = 1);
170 void decrementq(Address dst, int value = 1);
171
172 void incrementl(Address dst, int value = 1);
173 void incrementl(Register reg, int value = 1);
174
175 void incrementq(Register reg, int value = 1);
176 void incrementq(Address dst, int value = 1);
177
178 #ifdef COMPILER2
179 // special instructions for EVEX
180 void setvectmask(Register dst, Register src);
181 void restorevectmask();
182 #endif
183
184 // Support optimal SSE move instructions.
185 void movflt(XMMRegister dst, XMMRegister src) {
186 if (dst-> encoding() == src->encoding()) return;
187 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
188 else { movss (dst, src); return; }
189 }
190 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
191 void movflt(XMMRegister dst, AddressLiteral src);
192 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
193
194 void movdbl(XMMRegister dst, XMMRegister src) {
195 if (dst-> encoding() == src->encoding()) return;
196 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
197 else { movsd (dst, src); return; }
198 }
199
200 void movdbl(XMMRegister dst, AddressLiteral src);
201
202 void movdbl(XMMRegister dst, Address src) {
203 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
204 else { movlpd(dst, src); return; }
205 }
206 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
207
208 void incrementl(AddressLiteral dst);
209 void incrementl(ArrayAddress dst);
210
211 void incrementq(AddressLiteral dst);
212
213 // Alignment
214 void align(int modulus);
215 void align(int modulus, int target);
216
217 // A 5 byte nop that is safe for patching (see patch_verified_entry)
218 void fat_nop();
219
220 // Stack frame creation/removal
221 void enter();
222 void leave();
223
224 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
225 // The pointer will be loaded into the thread register.
226 void get_thread(Register thread);
227
228
229 // Support for VM calls
230 //
231 // It is imperative that all calls into the VM are handled via the call_VM macros.
232 // They make sure that the stack linkage is setup correctly. call_VM's correspond
233 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
234
235
236 void call_VM(Register oop_result,
237 address entry_point,
238 bool check_exceptions = true);
239 void call_VM(Register oop_result,
240 address entry_point,
241 Register arg_1,
242 bool check_exceptions = true);
243 void call_VM(Register oop_result,
244 address entry_point,
245 Register arg_1, Register arg_2,
246 bool check_exceptions = true);
247 void call_VM(Register oop_result,
248 address entry_point,
249 Register arg_1, Register arg_2, Register arg_3,
250 bool check_exceptions = true);
251
252 // Overloadings with last_Java_sp
253 void call_VM(Register oop_result,
254 Register last_java_sp,
255 address entry_point,
256 int number_of_arguments = 0,
257 bool check_exceptions = true);
258 void call_VM(Register oop_result,
259 Register last_java_sp,
260 address entry_point,
261 Register arg_1, bool
262 check_exceptions = true);
263 void call_VM(Register oop_result,
264 Register last_java_sp,
265 address entry_point,
266 Register arg_1, Register arg_2,
267 bool check_exceptions = true);
268 void call_VM(Register oop_result,
269 Register last_java_sp,
270 address entry_point,
271 Register arg_1, Register arg_2, Register arg_3,
272 bool check_exceptions = true);
273
274 void get_vm_result (Register oop_result, Register thread);
275 void get_vm_result_2(Register metadata_result, Register thread);
276
277 // These always tightly bind to MacroAssembler::call_VM_base
278 // bypassing the virtual implementation
279 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
280 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
281 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
282 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
283 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
284
285 void call_VM_leaf0(address entry_point);
286 void call_VM_leaf(address entry_point,
287 int number_of_arguments = 0);
288 void call_VM_leaf(address entry_point,
289 Register arg_1);
290 void call_VM_leaf(address entry_point,
291 Register arg_1, Register arg_2);
292 void call_VM_leaf(address entry_point,
293 Register arg_1, Register arg_2, Register arg_3);
294
295 // These always tightly bind to MacroAssembler::call_VM_leaf_base
296 // bypassing the virtual implementation
297 void super_call_VM_leaf(address entry_point);
298 void super_call_VM_leaf(address entry_point, Register arg_1);
299 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
300 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
301 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
302
303 // last Java Frame (fills frame anchor)
304 void set_last_Java_frame(Register thread,
305 Register last_java_sp,
306 Register last_java_fp,
307 address last_java_pc);
308
309 // thread in the default location (r15_thread on 64bit)
310 void set_last_Java_frame(Register last_java_sp,
311 Register last_java_fp,
312 address last_java_pc);
313
314 void reset_last_Java_frame(Register thread, bool clear_fp);
315
316 // thread in the default location (r15_thread on 64bit)
317 void reset_last_Java_frame(bool clear_fp);
318
319 // jobjects
320 void clear_jweak_tag(Register possibly_jweak);
321 void resolve_jobject(Register value, Register thread, Register tmp);
322
323 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
324 void c2bool(Register x);
325
326 // C++ bool manipulation
327
328 void movbool(Register dst, Address src);
329 void movbool(Address dst, bool boolconst);
330 void movbool(Address dst, Register src);
331 void testbool(Register dst);
332
333 void resolve_oop_handle(Register result, Register tmp = rscratch2);
334 void resolve_weak_handle(Register result, Register tmp);
335 void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
336 void load_method_holder_cld(Register rresult, Register rmethod);
337
338 void load_method_holder(Register holder, Register method);
339
340 // oop manipulations
341 void load_metadata(Register dst, Register src);
342 void load_storage_props(Register dst, Register src);
343 void load_klass(Register dst, Register src);
344 void store_klass(Register dst, Register src);
345
346 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
347 Register tmp1, Register thread_tmp);
348 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
349 Register tmp1, Register tmp2, Register tmp3 = noreg);
350
351 void access_value_copy(DecoratorSet decorators, Register src, Register dst, Register value_klass);
352
353 // value type data payload offsets...
354 void first_field_offset(Register value_klass, Register offset);
355 void data_for_oop(Register oop, Register data, Register value_klass);
356
357
358 // Resolves obj access. Result is placed in the same register.
359 // All other registers are preserved.
360 void resolve(DecoratorSet decorators, Register obj);
361
362 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
363 Register thread_tmp = noreg, DecoratorSet decorators = 0);
364 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
365 Register thread_tmp = noreg, DecoratorSet decorators = 0);
366 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
367 Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
368
369 // Used for storing NULL. All other oop constants should be
370 // stored using routines that take a jobject.
371 void store_heap_oop_null(Address dst);
372
373 void load_prototype_header(Register dst, Register src);
374
375 #ifdef _LP64
376 void store_klass_gap(Register dst, Register src);
377
378 // This dummy is to prevent a call to store_heap_oop from
379 // converting a zero (like NULL) into a Register by giving
380 // the compiler two choices it can't resolve
381
382 void store_heap_oop(Address dst, void* dummy);
383
384 void encode_heap_oop(Register r);
385 void decode_heap_oop(Register r);
386 void encode_heap_oop_not_null(Register r);
387 void decode_heap_oop_not_null(Register r);
388 void encode_heap_oop_not_null(Register dst, Register src);
389 void decode_heap_oop_not_null(Register dst, Register src);
390
391 void set_narrow_oop(Register dst, jobject obj);
392 void set_narrow_oop(Address dst, jobject obj);
393 void cmp_narrow_oop(Register dst, jobject obj);
394 void cmp_narrow_oop(Address dst, jobject obj);
395
396 void encode_klass_not_null(Register r);
397 void decode_klass_not_null(Register r);
398 void encode_klass_not_null(Register dst, Register src);
399 void decode_klass_not_null(Register dst, Register src);
400 void set_narrow_klass(Register dst, Klass* k);
401 void set_narrow_klass(Address dst, Klass* k);
402 void cmp_narrow_klass(Register dst, Klass* k);
403 void cmp_narrow_klass(Address dst, Klass* k);
404
405 // Returns the byte size of the instructions generated by decode_klass_not_null()
406 // when compressed klass pointers are being used.
407 static int instr_size_for_decode_klass_not_null();
408
409 // if heap base register is used - reinit it with the correct value
410 void reinit_heapbase();
411
412 DEBUG_ONLY(void verify_heapbase(const char* msg);)
413
414 #endif // _LP64
415
416 // Int division/remainder for Java
417 // (as idivl, but checks for special case as described in JVM spec.)
418 // returns idivl instruction offset for implicit exception handling
419 int corrected_idivl(Register reg);
420
421 // Long division/remainder for Java
422 // (as idivq, but checks for special case as described in JVM spec.)
423 // returns idivq instruction offset for implicit exception handling
424 int corrected_idivq(Register reg);
425
426 void int3();
427
428 // Long operation macros for a 32bit cpu
429 // Long negation for Java
430 void lneg(Register hi, Register lo);
431
432 // Long multiplication for Java
433 // (destroys contents of eax, ebx, ecx and edx)
434 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
435
436 // Long shifts for Java
437 // (semantics as described in JVM spec.)
438 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
439 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
440
441 // Long compare for Java
442 // (semantics as described in JVM spec.)
443 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
444
445
446 // misc
447
448 // Sign extension
449 void sign_extend_short(Register reg);
450 void sign_extend_byte(Register reg);
451
452 // Division by power of 2, rounding towards 0
453 void division_with_shift(Register reg, int shift_value);
454
455 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
456 //
457 // CF (corresponds to C0) if x < y
458 // PF (corresponds to C2) if unordered
459 // ZF (corresponds to C3) if x = y
460 //
461 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
462 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
463 void fcmp(Register tmp);
464 // Variant of the above which allows y to be further down the stack
465 // and which only pops x and y if specified. If pop_right is
466 // specified then pop_left must also be specified.
467 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
468
469 // Floating-point comparison for Java
470 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
471 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
472 // (semantics as described in JVM spec.)
473 void fcmp2int(Register dst, bool unordered_is_less);
474 // Variant of the above which allows y to be further down the stack
475 // and which only pops x and y if specified. If pop_right is
476 // specified then pop_left must also be specified.
477 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
478
479 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
480 // tmp is a temporary register, if none is available use noreg
481 void fremr(Register tmp);
482
483 // dst = c = a * b + c
484 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
485 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
486
487 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
488 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
489 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
490 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
491
492
493 // same as fcmp2int, but using SSE2
494 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
495 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
496
497 // branch to L if FPU flag C2 is set/not set
498 // tmp is a temporary register, if none is available use noreg
499 void jC2 (Register tmp, Label& L);
500 void jnC2(Register tmp, Label& L);
501
502 // Pop ST (ffree & fincstp combined)
503 void fpop();
504
505 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
506 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
507 void load_float(Address src);
508
509 // Store float value to 'address'. If UseSSE >= 1, the value is stored
510 // from register xmm0. Otherwise, the value is stored from the FPU stack.
511 void store_float(Address dst);
512
513 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
514 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
515 void load_double(Address src);
516
517 // Store double value to 'address'. If UseSSE >= 2, the value is stored
518 // from register xmm0. Otherwise, the value is stored from the FPU stack.
519 void store_double(Address dst);
520
521 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
522 void push_fTOS();
523
524 // pops double TOS element from CPU stack and pushes on FPU stack
525 void pop_fTOS();
526
527 void empty_FPU_stack();
528
529 void push_IU_state();
530 void pop_IU_state();
531
532 void push_FPU_state();
533 void pop_FPU_state();
534
535 void push_CPU_state();
536 void pop_CPU_state();
537
538 // Round up to a power of two
539 void round_to(Register reg, int modulus);
540
541 // Callee saved registers handling
542 void push_callee_saved_registers();
543 void pop_callee_saved_registers();
544
545 // allocation
546
547 // Object / value buffer allocation...
548 // Allocate instance of klass, assumes klass initialized by caller
549 // new_obj prefers to be rax
550 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
551 virtual void allocate_instance(Register klass, Register new_obj,
552 Register t1, Register t2,
553 bool clear_fields, Label& alloc_failed);
554
555 void eden_allocate(
556 Register thread, // Current thread
557 Register obj, // result: pointer to object after successful allocation
558 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
559 int con_size_in_bytes, // object size in bytes if known at compile time
560 Register t1, // temp register
561 Label& slow_case // continuation point if fast allocation fails
562 );
563 void tlab_allocate(
564 Register thread, // Current thread
565 Register obj, // result: pointer to object after successful allocation
566 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
567 int con_size_in_bytes, // object size in bytes if known at compile time
568 Register t1, // temp register
569 Register t2, // temp register
570 Label& slow_case // continuation point if fast allocation fails
571 );
572 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
573
574 // For field "index" within "klass", return value_klass ...
575 void get_value_field_klass(Register klass, Register index, Register value_klass);
576
577 // interface method calling
578 void lookup_interface_method(Register recv_klass,
579 Register intf_klass,
580 RegisterOrConstant itable_index,
581 Register method_result,
582 Register scan_temp,
583 Label& no_such_interface,
584 bool return_method = true);
585
586 // virtual method calling
587 void lookup_virtual_method(Register recv_klass,
588 RegisterOrConstant vtable_index,
589 Register method_result);
590
591 // Test sub_klass against super_klass, with fast and slow paths.
592
593 // The fast path produces a tri-state answer: yes / no / maybe-slow.
594 // One of the three labels can be NULL, meaning take the fall-through.
595 // If super_check_offset is -1, the value is loaded up from super_klass.
596 // No registers are killed, except temp_reg.
597 void check_klass_subtype_fast_path(Register sub_klass,
598 Register super_klass,
599 Register temp_reg,
600 Label* L_success,
601 Label* L_failure,
602 Label* L_slow_path,
603 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
604
605 // The rest of the type check; must be wired to a corresponding fast path.
606 // It does not repeat the fast path logic, so don't use it standalone.
607 // The temp_reg and temp2_reg can be noreg, if no temps are available.
608 // Updates the sub's secondary super cache as necessary.
609 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
610 void check_klass_subtype_slow_path(Register sub_klass,
611 Register super_klass,
612 Register temp_reg,
613 Register temp2_reg,
614 Label* L_success,
615 Label* L_failure,
616 bool set_cond_codes = false);
617
618 // Simplified, combined version, good for typical uses.
619 // Falls through on failure.
620 void check_klass_subtype(Register sub_klass,
621 Register super_klass,
622 Register temp_reg,
623 Label& L_success);
624
625 void clinit_barrier(Register klass,
626 Register thread,
627 Label* L_fast_path = NULL,
628 Label* L_slow_path = NULL);
629
630 // method handles (JSR 292)
631 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
632
633 //----
634 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
635
636 // Debugging
637
638 // only if +VerifyOops
639 // TODO: Make these macros with file and line like sparc version!
640 void verify_oop(Register reg, const char* s = "broken oop");
641 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
642
643 // TODO: verify method and klass metadata (compare against vptr?)
644 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
645 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
646
647 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
648 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
649
650 // only if +VerifyFPU
651 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
652
653 // Verify or restore cpu control state after JNI call
654 void restore_cpu_control_state_after_jni();
655
656 // prints msg, dumps registers and stops execution
657 void stop(const char* msg);
658
659 // prints msg and continues
660 void warn(const char* msg);
661
662 // dumps registers and other state
663 void print_state();
664
665 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
666 static void debug64(char* msg, int64_t pc, int64_t regs[]);
667 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
668 static void print_state64(int64_t pc, int64_t regs[]);
669
670 void os_breakpoint();
671
672 void untested() { stop("untested"); }
673
674 void unimplemented(const char* what = "");
675
676 void should_not_reach_here() { stop("should not reach here"); }
677
678 void print_CPU_state();
679
680 // Stack overflow checking
681 void bang_stack_with_offset(int offset) {
682 // stack grows down, caller passes positive offset
683 assert(offset > 0, "must bang with negative offset");
684 movl(Address(rsp, (-offset)), rax);
685 }
686
687 // Writes to stack successive pages until offset reached to check for
688 // stack overflow + shadow pages. Also, clobbers tmp
689 void bang_stack_size(Register size, Register tmp);
690
691 // Check for reserved stack access in method being exited (for JIT)
692 void reserved_stack_check();
693
694 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
695 Register tmp,
696 int offset);
697
698 // If thread_reg is != noreg the code assumes the register passed contains
699 // the thread (required on 64 bit).
700 void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
701
702 void verify_tlab();
703
704 // Biased locking support
705 // lock_reg and obj_reg must be loaded up with the appropriate values.
706 // swap_reg must be rax, and is killed.
707 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
708 // be killed; if not supplied, push/pop will be used internally to
709 // allocate a temporary (inefficient, avoid if possible).
710 // Optional slow case is for implementations (interpreter and C1) which branch to
711 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
712 // Returns offset of first potentially-faulting instruction for null
713 // check info (currently consumed only by C1). If
714 // swap_reg_contains_mark is true then returns -1 as it is assumed
715 // the calling code has already passed any potential faults.
716 int biased_locking_enter(Register lock_reg, Register obj_reg,
717 Register swap_reg, Register tmp_reg,
718 bool swap_reg_contains_mark,
719 Label& done, Label* slow_case = NULL,
720 BiasedLockingCounters* counters = NULL);
721 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
722 #ifdef COMPILER2
723 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
724 // See full desription in macroAssembler_x86.cpp.
725 void fast_lock(Register obj, Register box, Register tmp,
726 Register scr, Register cx1, Register cx2,
727 BiasedLockingCounters* counters,
728 RTMLockingCounters* rtm_counters,
729 RTMLockingCounters* stack_rtm_counters,
730 Metadata* method_data,
731 bool use_rtm, bool profile_rtm);
732 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
733 #if INCLUDE_RTM_OPT
734 void rtm_counters_update(Register abort_status, Register rtm_counters);
735 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
736 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
737 RTMLockingCounters* rtm_counters,
738 Metadata* method_data);
739 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
740 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
741 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
742 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
743 void rtm_stack_locking(Register obj, Register tmp, Register scr,
744 Register retry_on_abort_count,
745 RTMLockingCounters* stack_rtm_counters,
746 Metadata* method_data, bool profile_rtm,
747 Label& DONE_LABEL, Label& IsInflated);
748 void rtm_inflated_locking(Register obj, Register box, Register tmp,
749 Register scr, Register retry_on_busy_count,
750 Register retry_on_abort_count,
751 RTMLockingCounters* rtm_counters,
752 Metadata* method_data, bool profile_rtm,
753 Label& DONE_LABEL);
754 #endif
755 #endif
756
757 Condition negate_condition(Condition cond);
758
759 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
760 // operands. In general the names are modified to avoid hiding the instruction in Assembler
761 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
762 // here in MacroAssembler. The major exception to this rule is call
763
764 // Arithmetics
765
766
767 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
768 void addptr(Address dst, Register src);
769
770 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
771 void addptr(Register dst, int32_t src);
772 void addptr(Register dst, Register src);
773 void addptr(Register dst, RegisterOrConstant src) {
774 if (src.is_constant()) addptr(dst, (int) src.as_constant());
775 else addptr(dst, src.as_register());
776 }
777
778 void andptr(Register dst, int32_t src);
779 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
780
781 void cmp8(AddressLiteral src1, int imm);
782
783 // renamed to drag out the casting of address to int32_t/intptr_t
784 void cmp32(Register src1, int32_t imm);
785
786 void cmp32(AddressLiteral src1, int32_t imm);
787 // compare reg - mem, or reg - &mem
788 void cmp32(Register src1, AddressLiteral src2);
789
790 void cmp32(Register src1, Address src2);
791
792 #ifndef _LP64
793 void cmpklass(Address dst, Metadata* obj);
794 void cmpklass(Register dst, Metadata* obj);
795 void cmpoop(Address dst, jobject obj);
796 void cmpoop_raw(Address dst, jobject obj);
797 #endif // _LP64
798
799 void cmpoop(Register src1, Register src2);
800 void cmpoop(Register src1, Address src2);
801 void cmpoop(Register dst, jobject obj);
802 void cmpoop_raw(Register dst, jobject obj);
803
804 // NOTE src2 must be the lval. This is NOT an mem-mem compare
805 void cmpptr(Address src1, AddressLiteral src2);
806
807 void cmpptr(Register src1, AddressLiteral src2);
808
809 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
810 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
811 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
812
813 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
814 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
815
816 // cmp64 to avoild hiding cmpq
817 void cmp64(Register src1, AddressLiteral src);
818
819 void cmpxchgptr(Register reg, Address adr);
820
821 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
822
823
824 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
825 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
826
827
828 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
829
830 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
831
832 void shlptr(Register dst, int32_t shift);
833 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
834
835 void shrptr(Register dst, int32_t shift);
836 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
837
838 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
839 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
840
841 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
842
843 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
844 void subptr(Register dst, int32_t src);
845 // Force generation of a 4 byte immediate value even if it fits into 8bit
846 void subptr_imm32(Register dst, int32_t src);
847 void subptr(Register dst, Register src);
848 void subptr(Register dst, RegisterOrConstant src) {
849 if (src.is_constant()) subptr(dst, (int) src.as_constant());
850 else subptr(dst, src.as_register());
851 }
852
853 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
854 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
855
856 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
857 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
858
859 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
860
861
862
863 // Helper functions for statistics gathering.
864 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
865 void cond_inc32(Condition cond, AddressLiteral counter_addr);
866 // Unconditional atomic increment.
867 void atomic_incl(Address counter_addr);
868 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
869 #ifdef _LP64
870 void atomic_incq(Address counter_addr);
871 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
872 #endif
873 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
874 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
875
876 void lea(Register dst, AddressLiteral adr);
877 void lea(Address dst, AddressLiteral adr);
878 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
879
880 void leal32(Register dst, Address src) { leal(dst, src); }
881
882 // Import other testl() methods from the parent class or else
883 // they will be hidden by the following overriding declaration.
884 using Assembler::testl;
885 void testl(Register dst, AddressLiteral src);
886
887 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
888 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
889 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
890 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
891
892 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
893 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
894 void testptr(Register src1, Register src2);
895
896 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
897 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
898
899 // Calls
900
901 void call(Label& L, relocInfo::relocType rtype);
902 void call(Register entry);
903
904 // NOTE: this call transfers to the effective address of entry NOT
905 // the address contained by entry. This is because this is more natural
906 // for jumps/calls.
907 void call(AddressLiteral entry);
908
909 // Emit the CompiledIC call idiom
910 void ic_call(address entry, jint method_index = 0);
911
912 // Jumps
913
914 // NOTE: these jumps tranfer to the effective address of dst NOT
915 // the address contained by dst. This is because this is more natural
916 // for jumps/calls.
917 void jump(AddressLiteral dst);
918 void jump_cc(Condition cc, AddressLiteral dst);
919
920 // 32bit can do a case table jump in one instruction but we no longer allow the base
921 // to be installed in the Address class. This jump will tranfers to the address
922 // contained in the location described by entry (not the address of entry)
923 void jump(ArrayAddress entry);
924
925 // Floating
926
927 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
928 void andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
929 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
930
931 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
932 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
933 void andps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
934
935 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
936 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
937 void comiss(XMMRegister dst, AddressLiteral src);
938
939 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
940 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
941 void comisd(XMMRegister dst, AddressLiteral src);
942
943 void fadd_s(Address src) { Assembler::fadd_s(src); }
944 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
945
946 void fldcw(Address src) { Assembler::fldcw(src); }
947 void fldcw(AddressLiteral src);
948
949 void fld_s(int index) { Assembler::fld_s(index); }
950 void fld_s(Address src) { Assembler::fld_s(src); }
951 void fld_s(AddressLiteral src);
952
953 void fld_d(Address src) { Assembler::fld_d(src); }
954 void fld_d(AddressLiteral src);
955
956 void fld_x(Address src) { Assembler::fld_x(src); }
957 void fld_x(AddressLiteral src);
958
959 void fmul_s(Address src) { Assembler::fmul_s(src); }
960 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
961
962 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
963 void ldmxcsr(AddressLiteral src);
964
965 #ifdef _LP64
966 private:
967 void sha256_AVX2_one_round_compute(
968 Register reg_old_h,
969 Register reg_a,
970 Register reg_b,
971 Register reg_c,
972 Register reg_d,
973 Register reg_e,
974 Register reg_f,
975 Register reg_g,
976 Register reg_h,
977 int iter);
978 void sha256_AVX2_four_rounds_compute_first(int start);
979 void sha256_AVX2_four_rounds_compute_last(int start);
980 void sha256_AVX2_one_round_and_sched(
981 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
982 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
983 XMMRegister xmm_2, /* ymm6 */
984 XMMRegister xmm_3, /* ymm7 */
985 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
986 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
987 Register reg_c, /* edi */
988 Register reg_d, /* esi */
989 Register reg_e, /* r8d */
990 Register reg_f, /* r9d */
991 Register reg_g, /* r10d */
992 Register reg_h, /* r11d */
993 int iter);
994
995 void addm(int disp, Register r1, Register r2);
996 void gfmul(XMMRegister tmp0, XMMRegister t);
997 void schoolbookAAD(int i, Register subkeyH, XMMRegister data, XMMRegister tmp0,
998 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3);
999 void generateHtbl_one_block(Register htbl);
1000 void generateHtbl_eight_blocks(Register htbl);
1001 public:
1002 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1003 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1004 Register buf, Register state, Register ofs, Register limit, Register rsp,
1005 bool multi_block, XMMRegister shuf_mask);
1006 void avx_ghash(Register state, Register htbl, Register data, Register blocks);
1007 #endif
1008
1009 #ifdef _LP64
1010 private:
1011 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
1012 Register e, Register f, Register g, Register h, int iteration);
1013
1014 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1015 Register a, Register b, Register c, Register d, Register e, Register f,
1016 Register g, Register h, int iteration);
1017
1018 void addmq(int disp, Register r1, Register r2);
1019 public:
1020 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1021 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1022 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
1023 XMMRegister shuf_mask);
1024 private:
1025 void roundEnc(XMMRegister key, int rnum);
1026 void lastroundEnc(XMMRegister key, int rnum);
1027 void roundDec(XMMRegister key, int rnum);
1028 void lastroundDec(XMMRegister key, int rnum);
1029 void ev_load_key(XMMRegister xmmdst, Register key, int offset, XMMRegister xmm_shuf_mask);
1030
1031 public:
1032 void aesecb_encrypt(Register source_addr, Register dest_addr, Register key, Register len);
1033 void aesecb_decrypt(Register source_addr, Register dest_addr, Register key, Register len);
1034
1035 #endif
1036
1037 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
1038 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
1039 Register buf, Register state, Register ofs, Register limit, Register rsp,
1040 bool multi_block);
1041
1042 #ifdef _LP64
1043 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1044 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1045 Register buf, Register state, Register ofs, Register limit, Register rsp,
1046 bool multi_block, XMMRegister shuf_mask);
1047 #else
1048 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1049 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1050 Register buf, Register state, Register ofs, Register limit, Register rsp,
1051 bool multi_block);
1052 #endif
1053
1054 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1055 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1056 Register rax, Register rcx, Register rdx, Register tmp);
1057
1058 #ifdef _LP64
1059 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1060 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1061 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
1062
1063 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1064 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1065 Register rax, Register rcx, Register rdx, Register r11);
1066
1067 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1068 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1069 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1070
1071 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1072 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1073 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1074 Register tmp3, Register tmp4);
1075
1076 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1077 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1078 Register rax, Register rcx, Register rdx, Register tmp1,
1079 Register tmp2, Register tmp3, Register tmp4);
1080 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1081 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1082 Register rax, Register rcx, Register rdx, Register tmp1,
1083 Register tmp2, Register tmp3, Register tmp4);
1084 #else
1085 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1086 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1087 Register rax, Register rcx, Register rdx, Register tmp1);
1088
1089 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1090 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1091 Register rax, Register rcx, Register rdx, Register tmp);
1092
1093 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1094 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1095 Register rdx, Register tmp);
1096
1097 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1098 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1099 Register rax, Register rbx, Register rdx);
1100
1101 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1102 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1103 Register rax, Register rcx, Register rdx, Register tmp);
1104
1105 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1106 Register edx, Register ebx, Register esi, Register edi,
1107 Register ebp, Register esp);
1108
1109 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1110 Register esi, Register edi, Register ebp, Register esp);
1111
1112 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1113 Register edx, Register ebx, Register esi, Register edi,
1114 Register ebp, Register esp);
1115
1116 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1117 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1118 Register rax, Register rcx, Register rdx, Register tmp);
1119 #endif
1120
1121 void increase_precision();
1122 void restore_precision();
1123
1124 private:
1125
1126 // these are private because users should be doing movflt/movdbl
1127
1128 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1129 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1130 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1131 void movss(XMMRegister dst, AddressLiteral src);
1132
1133 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1134 void movlpd(XMMRegister dst, AddressLiteral src);
1135
1136 public:
1137
1138 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1139 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1140 void addsd(XMMRegister dst, AddressLiteral src);
1141
1142 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1143 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1144 void addss(XMMRegister dst, AddressLiteral src);
1145
1146 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1147 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1148 void addpd(XMMRegister dst, AddressLiteral src);
1149
1150 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1151 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1152 void divsd(XMMRegister dst, AddressLiteral src);
1153
1154 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1155 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1156 void divss(XMMRegister dst, AddressLiteral src);
1157
1158 // Move Unaligned Double Quadword
1159 void movdqu(Address dst, XMMRegister src);
1160 void movdqu(XMMRegister dst, Address src);
1161 void movdqu(XMMRegister dst, XMMRegister src);
1162 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1163 // AVX Unaligned forms
1164 void vmovdqu(Address dst, XMMRegister src);
1165 void vmovdqu(XMMRegister dst, Address src);
1166 void vmovdqu(XMMRegister dst, XMMRegister src);
1167 void vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1168 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1169 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1170 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1171 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1172
1173 // Move Aligned Double Quadword
1174 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1175 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1176 void movdqa(XMMRegister dst, AddressLiteral src);
1177
1178 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1179 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1180 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1181 void movsd(XMMRegister dst, AddressLiteral src);
1182
1183 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1184 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1185 void mulpd(XMMRegister dst, AddressLiteral src);
1186
1187 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1188 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1189 void mulsd(XMMRegister dst, AddressLiteral src);
1190
1191 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1192 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1193 void mulss(XMMRegister dst, AddressLiteral src);
1194
1195 // Carry-Less Multiplication Quadword
1196 void pclmulldq(XMMRegister dst, XMMRegister src) {
1197 // 0x00 - multiply lower 64 bits [0:63]
1198 Assembler::pclmulqdq(dst, src, 0x00);
1199 }
1200 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1201 // 0x11 - multiply upper 64 bits [64:127]
1202 Assembler::pclmulqdq(dst, src, 0x11);
1203 }
1204
1205 void pcmpeqb(XMMRegister dst, XMMRegister src);
1206 void pcmpeqw(XMMRegister dst, XMMRegister src);
1207
1208 void pcmpestri(XMMRegister dst, Address src, int imm8);
1209 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1210
1211 void pmovzxbw(XMMRegister dst, XMMRegister src);
1212 void pmovzxbw(XMMRegister dst, Address src);
1213
1214 void pmovmskb(Register dst, XMMRegister src);
1215
1216 void ptest(XMMRegister dst, XMMRegister src);
1217
1218 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1219 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1220 void sqrtsd(XMMRegister dst, AddressLiteral src);
1221
1222 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1223 void roundsd(XMMRegister dst, Address src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1224 void roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg);
1225
1226 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1227 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1228 void sqrtss(XMMRegister dst, AddressLiteral src);
1229
1230 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1231 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1232 void subsd(XMMRegister dst, AddressLiteral src);
1233
1234 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1235 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1236 void subss(XMMRegister dst, AddressLiteral src);
1237
1238 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1239 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1240 void ucomiss(XMMRegister dst, AddressLiteral src);
1241
1242 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1243 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1244 void ucomisd(XMMRegister dst, AddressLiteral src);
1245
1246 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1247 void xorpd(XMMRegister dst, XMMRegister src);
1248 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1249 void xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1250
1251 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1252 void xorps(XMMRegister dst, XMMRegister src);
1253 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1254 void xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1255
1256 // Shuffle Bytes
1257 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1258 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1259 void pshufb(XMMRegister dst, AddressLiteral src);
1260 // AVX 3-operands instructions
1261
1262 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1263 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1264 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1265
1266 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1267 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1268 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1269
1270 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1271 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1272
1273 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1274 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1275
1276 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1277 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1278
1279 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1280 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1281 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1282
1283 void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1284 void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); }
1285
1286 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1287
1288 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1289
1290 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1291 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1292
1293 void vpmovmskb(Register dst, XMMRegister src);
1294
1295 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1296 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1297
1298 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1299 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1300
1301 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1302 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1303
1304 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1305 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1306
1307 void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1308 void evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1309
1310 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1311 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1312
1313 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1314 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1315
1316 void vptest(XMMRegister dst, XMMRegister src);
1317
1318 void punpcklbw(XMMRegister dst, XMMRegister src);
1319 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1320
1321 void pshufd(XMMRegister dst, Address src, int mode);
1322 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1323
1324 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1325 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1326
1327 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1328 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1329 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1330
1331 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1332 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1333 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1334
1335 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1336 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1337 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1338
1339 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1340 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1341 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1342
1343 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1344 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1345 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1346
1347 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1348 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1349 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1350
1351 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1352 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1353 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1354
1355 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1356 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1357 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1358
1359 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1360 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1361
1362 // AVX Vector instructions
1363
1364 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1365 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1366 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1367
1368 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1369 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1370 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1371
1372 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1373 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1374 Assembler::vpxor(dst, nds, src, vector_len);
1375 else
1376 Assembler::vxorpd(dst, nds, src, vector_len);
1377 }
1378 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1379 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1380 Assembler::vpxor(dst, nds, src, vector_len);
1381 else
1382 Assembler::vxorpd(dst, nds, src, vector_len);
1383 }
1384 void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1385
1386 // Simple version for AVX2 256bit vectors
1387 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1388 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1389
1390 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1391 if (UseAVX > 2) {
1392 Assembler::vinserti32x4(dst, dst, src, imm8);
1393 } else if (UseAVX > 1) {
1394 // vinserti128 is available only in AVX2
1395 Assembler::vinserti128(dst, nds, src, imm8);
1396 } else {
1397 Assembler::vinsertf128(dst, nds, src, imm8);
1398 }
1399 }
1400
1401 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1402 if (UseAVX > 2) {
1403 Assembler::vinserti32x4(dst, dst, src, imm8);
1404 } else if (UseAVX > 1) {
1405 // vinserti128 is available only in AVX2
1406 Assembler::vinserti128(dst, nds, src, imm8);
1407 } else {
1408 Assembler::vinsertf128(dst, nds, src, imm8);
1409 }
1410 }
1411
1412 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1413 if (UseAVX > 2) {
1414 Assembler::vextracti32x4(dst, src, imm8);
1415 } else if (UseAVX > 1) {
1416 // vextracti128 is available only in AVX2
1417 Assembler::vextracti128(dst, src, imm8);
1418 } else {
1419 Assembler::vextractf128(dst, src, imm8);
1420 }
1421 }
1422
1423 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1424 if (UseAVX > 2) {
1425 Assembler::vextracti32x4(dst, src, imm8);
1426 } else if (UseAVX > 1) {
1427 // vextracti128 is available only in AVX2
1428 Assembler::vextracti128(dst, src, imm8);
1429 } else {
1430 Assembler::vextractf128(dst, src, imm8);
1431 }
1432 }
1433
1434 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1435 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1436 vinserti128(dst, dst, src, 1);
1437 }
1438 void vinserti128_high(XMMRegister dst, Address src) {
1439 vinserti128(dst, dst, src, 1);
1440 }
1441 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1442 vextracti128(dst, src, 1);
1443 }
1444 void vextracti128_high(Address dst, XMMRegister src) {
1445 vextracti128(dst, src, 1);
1446 }
1447
1448 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1449 if (UseAVX > 2) {
1450 Assembler::vinsertf32x4(dst, dst, src, 1);
1451 } else {
1452 Assembler::vinsertf128(dst, dst, src, 1);
1453 }
1454 }
1455
1456 void vinsertf128_high(XMMRegister dst, Address src) {
1457 if (UseAVX > 2) {
1458 Assembler::vinsertf32x4(dst, dst, src, 1);
1459 } else {
1460 Assembler::vinsertf128(dst, dst, src, 1);
1461 }
1462 }
1463
1464 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1465 if (UseAVX > 2) {
1466 Assembler::vextractf32x4(dst, src, 1);
1467 } else {
1468 Assembler::vextractf128(dst, src, 1);
1469 }
1470 }
1471
1472 void vextractf128_high(Address dst, XMMRegister src) {
1473 if (UseAVX > 2) {
1474 Assembler::vextractf32x4(dst, src, 1);
1475 } else {
1476 Assembler::vextractf128(dst, src, 1);
1477 }
1478 }
1479
1480 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1481 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1482 Assembler::vinserti64x4(dst, dst, src, 1);
1483 }
1484 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1485 Assembler::vinsertf64x4(dst, dst, src, 1);
1486 }
1487 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1488 Assembler::vextracti64x4(dst, src, 1);
1489 }
1490 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1491 Assembler::vextractf64x4(dst, src, 1);
1492 }
1493 void vextractf64x4_high(Address dst, XMMRegister src) {
1494 Assembler::vextractf64x4(dst, src, 1);
1495 }
1496 void vinsertf64x4_high(XMMRegister dst, Address src) {
1497 Assembler::vinsertf64x4(dst, dst, src, 1);
1498 }
1499
1500 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1501 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1502 vinserti128(dst, dst, src, 0);
1503 }
1504 void vinserti128_low(XMMRegister dst, Address src) {
1505 vinserti128(dst, dst, src, 0);
1506 }
1507 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1508 vextracti128(dst, src, 0);
1509 }
1510 void vextracti128_low(Address dst, XMMRegister src) {
1511 vextracti128(dst, src, 0);
1512 }
1513
1514 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1515 if (UseAVX > 2) {
1516 Assembler::vinsertf32x4(dst, dst, src, 0);
1517 } else {
1518 Assembler::vinsertf128(dst, dst, src, 0);
1519 }
1520 }
1521
1522 void vinsertf128_low(XMMRegister dst, Address src) {
1523 if (UseAVX > 2) {
1524 Assembler::vinsertf32x4(dst, dst, src, 0);
1525 } else {
1526 Assembler::vinsertf128(dst, dst, src, 0);
1527 }
1528 }
1529
1530 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1531 if (UseAVX > 2) {
1532 Assembler::vextractf32x4(dst, src, 0);
1533 } else {
1534 Assembler::vextractf128(dst, src, 0);
1535 }
1536 }
1537
1538 void vextractf128_low(Address dst, XMMRegister src) {
1539 if (UseAVX > 2) {
1540 Assembler::vextractf32x4(dst, src, 0);
1541 } else {
1542 Assembler::vextractf128(dst, src, 0);
1543 }
1544 }
1545
1546 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1547 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1548 Assembler::vinserti64x4(dst, dst, src, 0);
1549 }
1550 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1551 Assembler::vinsertf64x4(dst, dst, src, 0);
1552 }
1553 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1554 Assembler::vextracti64x4(dst, src, 0);
1555 }
1556 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1557 Assembler::vextractf64x4(dst, src, 0);
1558 }
1559 void vextractf64x4_low(Address dst, XMMRegister src) {
1560 Assembler::vextractf64x4(dst, src, 0);
1561 }
1562 void vinsertf64x4_low(XMMRegister dst, Address src) {
1563 Assembler::vinsertf64x4(dst, dst, src, 0);
1564 }
1565
1566 // Carry-Less Multiplication Quadword
1567 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1568 // 0x00 - multiply lower 64 bits [0:63]
1569 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1570 }
1571 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1572 // 0x11 - multiply upper 64 bits [64:127]
1573 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1574 }
1575 void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1576 // 0x10 - multiply nds[0:63] and src[64:127]
1577 Assembler::vpclmulqdq(dst, nds, src, 0x10);
1578 }
1579 void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1580 //0x01 - multiply nds[64:127] and src[0:63]
1581 Assembler::vpclmulqdq(dst, nds, src, 0x01);
1582 }
1583
1584 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1585 // 0x00 - multiply lower 64 bits [0:63]
1586 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1587 }
1588 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1589 // 0x11 - multiply upper 64 bits [64:127]
1590 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1591 }
1592
1593 // Data
1594
1595 void cmov32( Condition cc, Register dst, Address src);
1596 void cmov32( Condition cc, Register dst, Register src);
1597
1598 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1599
1600 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1601 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1602
1603 void movoop(Register dst, jobject obj);
1604 void movoop(Address dst, jobject obj);
1605
1606 void mov_metadata(Register dst, Metadata* obj);
1607 void mov_metadata(Address dst, Metadata* obj);
1608
1609 void movptr(ArrayAddress dst, Register src);
1610 // can this do an lea?
1611 void movptr(Register dst, ArrayAddress src);
1612
1613 void movptr(Register dst, Address src);
1614
1615 #ifdef _LP64
1616 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1617 #else
1618 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1619 #endif
1620
1621 void movptr(Register dst, intptr_t src);
1622 void movptr(Register dst, Register src);
1623 void movptr(Address dst, intptr_t src);
1624
1625 void movptr(Address dst, Register src);
1626
1627 void movptr(Register dst, RegisterOrConstant src) {
1628 if (src.is_constant()) movptr(dst, src.as_constant());
1629 else movptr(dst, src.as_register());
1630 }
1631
1632 #ifdef _LP64
1633 // Generally the next two are only used for moving NULL
1634 // Although there are situations in initializing the mark word where
1635 // they could be used. They are dangerous.
1636
1637 // They only exist on LP64 so that int32_t and intptr_t are not the same
1638 // and we have ambiguous declarations.
1639
1640 void movptr(Address dst, int32_t imm32);
1641 void movptr(Register dst, int32_t imm32);
1642 #endif // _LP64
1643
1644 // to avoid hiding movl
1645 void mov32(AddressLiteral dst, Register src);
1646 void mov32(Register dst, AddressLiteral src);
1647
1648 // to avoid hiding movb
1649 void movbyte(ArrayAddress dst, int src);
1650
1651 // Import other mov() methods from the parent class or else
1652 // they will be hidden by the following overriding declaration.
1653 using Assembler::movdl;
1654 using Assembler::movq;
1655 void movdl(XMMRegister dst, AddressLiteral src);
1656 void movq(XMMRegister dst, AddressLiteral src);
1657
1658 // Can push value or effective address
1659 void pushptr(AddressLiteral src);
1660
1661 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1662 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1663
1664 void pushoop(jobject obj);
1665 void pushklass(Metadata* obj);
1666
1667 // sign extend as need a l to ptr sized element
1668 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1669 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1670
1671 #ifdef COMPILER2
1672 // Generic instructions support for use in .ad files C2 code generation
1673 void vabsnegd(int opcode, XMMRegister dst, Register scr);
1674 void vabsnegd(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr);
1675 void vabsnegf(int opcode, XMMRegister dst, Register scr);
1676 void vabsnegf(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr);
1677 void vextendbw(bool sign, XMMRegister dst, XMMRegister src, int vector_len);
1678 void vextendbw(bool sign, XMMRegister dst, XMMRegister src);
1679 void vshiftd(int opcode, XMMRegister dst, XMMRegister src);
1680 void vshiftd(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1681 void vshiftw(int opcode, XMMRegister dst, XMMRegister src);
1682 void vshiftw(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1683 void vshiftq(int opcode, XMMRegister dst, XMMRegister src);
1684 void vshiftq(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1685 #endif
1686
1687 // C2 compiled method's prolog code.
1688 void verified_entry(Compile* C, int sp_inc = 0);
1689
1690 enum RegState {
1691 reg_readonly,
1692 reg_writable,
1693 reg_written
1694 };
1695
1696 int store_value_type_fields_to_buf(ciValueKlass* vk, bool from_interpreter = true);
1697
1698 // Unpack all value type arguments passed as oops
1699 void unpack_value_args(Compile* C, bool receiver_only);
1700 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[], int ret_off, int extra_stack_offset);
1701 bool unpack_value_helper(const GrowableArray<SigEntry>* sig, int& sig_index, VMReg from, VMRegPair* regs_to, int& to_index,
1702 RegState reg_state[], int ret_off, int extra_stack_offset);
1703 bool pack_value_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1704 VMReg to, VMRegPair* regs_from, int regs_from_count, int& from_index, RegState reg_state[],
1705 int ret_off, int extra_stack_offset);
1706 void restore_stack(Compile* C);
1707
1708 int shuffle_value_args(bool is_packing, bool receiver_only, int extra_stack_offset,
1709 BasicType* sig_bt, const GrowableArray<SigEntry>* sig_cc,
1710 int args_passed, int args_on_stack, VMRegPair* regs,
1711 int args_passed_to, int args_on_stack_to, VMRegPair* regs_to);
1712 bool shuffle_value_args_spill(bool is_packing, const GrowableArray<SigEntry>* sig_cc, int sig_cc_index,
1713 VMRegPair* regs_from, int from_index, int regs_from_count,
1714 RegState* reg_state, int sp_inc, int extra_stack_offset);
1715 VMReg spill_reg_for(VMReg reg);
1716
1717 // clear memory of size 'cnt' qwords, starting at 'base';
1718 // if 'is_large' is set, do not try to produce short loop
1719 void clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, bool is_large, bool word_copy_only);
1720
1721 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1722 void xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp);
1723
1724 #ifdef COMPILER2
1725 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1726 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1727
1728 // IndexOf strings.
1729 // Small strings are loaded through stack if they cross page boundary.
1730 void string_indexof(Register str1, Register str2,
1731 Register cnt1, Register cnt2,
1732 int int_cnt2, Register result,
1733 XMMRegister vec, Register tmp,
1734 int ae);
1735
1736 // IndexOf for constant substrings with size >= 8 elements
1737 // which don't need to be loaded through stack.
1738 void string_indexofC8(Register str1, Register str2,
1739 Register cnt1, Register cnt2,
1740 int int_cnt2, Register result,
1741 XMMRegister vec, Register tmp,
1742 int ae);
1743
1744 // Smallest code: we don't need to load through stack,
1745 // check string tail.
1746
1747 // helper function for string_compare
1748 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1749 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1750 Address::ScaleFactor scale2, Register index, int ae);
1751 // Compare strings.
1752 void string_compare(Register str1, Register str2,
1753 Register cnt1, Register cnt2, Register result,
1754 XMMRegister vec1, int ae);
1755
1756 // Search for Non-ASCII character (Negative byte value) in a byte array,
1757 // return true if it has any and false otherwise.
1758 void has_negatives(Register ary1, Register len,
1759 Register result, Register tmp1,
1760 XMMRegister vec1, XMMRegister vec2);
1761
1762 // Compare char[] or byte[] arrays.
1763 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1764 Register limit, Register result, Register chr,
1765 XMMRegister vec1, XMMRegister vec2, bool is_char);
1766
1767 #endif
1768
1769 // Fill primitive arrays
1770 void generate_fill(BasicType t, bool aligned,
1771 Register to, Register value, Register count,
1772 Register rtmp, XMMRegister xtmp);
1773
1774 void encode_iso_array(Register src, Register dst, Register len,
1775 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1776 XMMRegister tmp4, Register tmp5, Register result);
1777
1778 #ifdef _LP64
1779 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1780 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1781 Register y, Register y_idx, Register z,
1782 Register carry, Register product,
1783 Register idx, Register kdx);
1784 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1785 Register yz_idx, Register idx,
1786 Register carry, Register product, int offset);
1787 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1788 Register carry, Register carry2,
1789 Register idx, Register jdx,
1790 Register yz_idx1, Register yz_idx2,
1791 Register tmp, Register tmp3, Register tmp4);
1792 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1793 Register yz_idx, Register idx, Register jdx,
1794 Register carry, Register product,
1795 Register carry2);
1796 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1797 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1798 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1799 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1800 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1801 Register tmp2);
1802 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1803 Register rdxReg, Register raxReg);
1804 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1805 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1806 Register tmp3, Register tmp4);
1807 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1808 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1809
1810 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1811 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1812 Register raxReg);
1813 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1814 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1815 Register raxReg);
1816 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1817 Register result, Register tmp1, Register tmp2,
1818 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1819 #endif
1820
1821 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1822 void update_byte_crc32(Register crc, Register val, Register table);
1823 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1824 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1825 // Note on a naming convention:
1826 // Prefix w = register only used on a Westmere+ architecture
1827 // Prefix n = register only used on a Nehalem architecture
1828 #ifdef _LP64
1829 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1830 Register tmp1, Register tmp2, Register tmp3);
1831 #else
1832 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1833 Register tmp1, Register tmp2, Register tmp3,
1834 XMMRegister xtmp1, XMMRegister xtmp2);
1835 #endif
1836 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1837 Register in_out,
1838 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1839 XMMRegister w_xtmp2,
1840 Register tmp1,
1841 Register n_tmp2, Register n_tmp3);
1842 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1843 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1844 Register tmp1, Register tmp2,
1845 Register n_tmp3);
1846 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1847 Register in_out1, Register in_out2, Register in_out3,
1848 Register tmp1, Register tmp2, Register tmp3,
1849 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1850 Register tmp4, Register tmp5,
1851 Register n_tmp6);
1852 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1853 Register tmp1, Register tmp2, Register tmp3,
1854 Register tmp4, Register tmp5, Register tmp6,
1855 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1856 bool is_pclmulqdq_supported);
1857 // Fold 128-bit data chunk
1858 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1859 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1860 // Fold 8-bit data
1861 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1862 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1863 void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1864
1865 // Compress char[] array to byte[].
1866 void char_array_compress(Register src, Register dst, Register len,
1867 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1868 XMMRegister tmp4, Register tmp5, Register result);
1869
1870 // Inflate byte[] array to char[].
1871 void byte_array_inflate(Register src, Register dst, Register len,
1872 XMMRegister tmp1, Register tmp2);
1873
1874 #ifdef _LP64
1875 void cache_wb(Address line);
1876 void cache_wbsync(bool is_pre);
1877 #endif // _LP64
1878
1879 #include "asm/macroAssembler_common.hpp"
1880
1881 };
1882
1883 /**
1884 * class SkipIfEqual:
1885 *
1886 * Instantiating this class will result in assembly code being output that will
1887 * jump around any code emitted between the creation of the instance and it's
1888 * automatic destruction at the end of a scope block, depending on the value of
1889 * the flag passed to the constructor, which will be checked at run-time.
1890 */
1891 class SkipIfEqual {
1892 private:
1893 MacroAssembler* _masm;
1894 Label _label;
1895
1896 public:
1897 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1898 ~SkipIfEqual();
1899 };
1900
1901 #endif // CPU_X86_MACROASSEMBLER_X86_HPP