1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31 #include "runtime/signature.hpp"
32
33 class ciValueKlass;
34
35 // MacroAssembler extends Assembler by frequently used macros.
36 //
37 // Instructions for which a 'better' code sequence exists depending
38 // on arguments should also go in here.
39
40 class MacroAssembler: public Assembler {
41 friend class LIR_Assembler;
42 friend class Runtime1; // as_Address()
43
44 public:
45 // Support for VM calls
46 //
47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
48 // may customize this version by overriding it for its purposes (e.g., to save/restore
49 // additional registers when doing a VM call).
50
51 virtual void call_VM_leaf_base(
52 address entry_point, // the entry point
53 int number_of_arguments // the number of arguments to pop after the call
54 );
55
56 protected:
57 // This is the base routine called by the different versions of call_VM. The interpreter
58 // may customize this version by overriding it for its purposes (e.g., to save/restore
59 // additional registers when doing a VM call).
60 //
61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
62 // returns the register which contains the thread upon return. If a thread register has been
63 // specified, the return value will correspond to that register. If no last_java_sp is specified
64 // (noreg) than rsp will be used instead.
65 virtual void call_VM_base( // returns the register containing the thread upon return
66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
67 Register java_thread, // the thread if computed before ; use noreg otherwise
68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
69 address entry_point, // the entry point
70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
71 bool check_exceptions // whether to check for pending exceptions after return
72 );
73
74 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
75
76 // helpers for FPU flag access
77 // tmp is a temporary register, if none is available use noreg
78 void save_rax (Register tmp);
79 void restore_rax(Register tmp);
80
81 public:
82 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
83
84 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
85 // The implementation is only non-empty for the InterpreterMacroAssembler,
86 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
87 virtual void check_and_handle_popframe(Register java_thread);
88 virtual void check_and_handle_earlyret(Register java_thread);
89
90 Address as_Address(AddressLiteral adr);
91 Address as_Address(ArrayAddress adr);
92
93 // Support for NULL-checks
94 //
95 // Generates code that causes a NULL OS exception if the content of reg is NULL.
96 // If the accessed location is M[reg + offset] and the offset is known, provide the
97 // offset. No explicit code generation is needed if the offset is within a certain
98 // range (0 <= offset <= page_size).
99
100 void null_check(Register reg, int offset = -1);
101 static bool needs_explicit_null_check(intptr_t offset);
102 static bool uses_implicit_null_check(void* address);
103
104 void test_klass_is_value(Register klass, Register temp_reg, Label& is_value);
105
106 void test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable);
107 void test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable);
108 void test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened);
109
110 // Check oops array storage properties, i.e. flattened and/or null-free
111 void test_flattened_array_oop(Register oop, Register temp_reg, Label&is_flattened_array);
112 void test_non_flattened_array_oop(Register oop, Register temp_reg, Label&is_non_flattened_array);
113 void test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array);
114 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
115
116 // Required platform-specific helpers for Label::patch_instructions.
117 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
118 void pd_patch_instruction(address branch, address target, const char* file, int line) {
119 unsigned char op = branch[0];
120 assert(op == 0xE8 /* call */ ||
121 op == 0xE9 /* jmp */ ||
122 op == 0xEB /* short jmp */ ||
123 (op & 0xF0) == 0x70 /* short jcc */ ||
124 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
125 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
126 "Invalid opcode at patch point");
127
128 if (op == 0xEB || (op & 0xF0) == 0x70) {
129 // short offset operators (jmp and jcc)
130 char* disp = (char*) &branch[1];
131 int imm8 = target - (address) &disp[1];
132 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d",
133 file == NULL ? "<NULL>" : file, line);
134 *disp = imm8;
135 } else {
136 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
137 int imm32 = target - (address) &disp[1];
138 *disp = imm32;
139 }
140 }
141
142 // The following 4 methods return the offset of the appropriate move instruction
143
144 // Support for fast byte/short loading with zero extension (depending on particular CPU)
145 int load_unsigned_byte(Register dst, Address src);
146 int load_unsigned_short(Register dst, Address src);
147
148 // Support for fast byte/short loading with sign extension (depending on particular CPU)
149 int load_signed_byte(Register dst, Address src);
150 int load_signed_short(Register dst, Address src);
151
152 // Support for sign-extension (hi:lo = extend_sign(lo))
153 void extend_sign(Register hi, Register lo);
154
155 // Load and store values by size and signed-ness
156 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
157 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
158
159 // Support for inc/dec with optimal instruction selection depending on value
160
161 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
162 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
163
164 void decrementl(Address dst, int value = 1);
165 void decrementl(Register reg, int value = 1);
166
167 void decrementq(Register reg, int value = 1);
168 void decrementq(Address dst, int value = 1);
169
170 void incrementl(Address dst, int value = 1);
171 void incrementl(Register reg, int value = 1);
172
173 void incrementq(Register reg, int value = 1);
174 void incrementq(Address dst, int value = 1);
175
176 #ifdef COMPILER2
177 // special instructions for EVEX
178 void setvectmask(Register dst, Register src);
179 void restorevectmask();
180 #endif
181
182 // Support optimal SSE move instructions.
183 void movflt(XMMRegister dst, XMMRegister src) {
184 if (dst-> encoding() == src->encoding()) return;
185 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
186 else { movss (dst, src); return; }
187 }
188 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
189 void movflt(XMMRegister dst, AddressLiteral src);
190 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
191
192 void movdbl(XMMRegister dst, XMMRegister src) {
193 if (dst-> encoding() == src->encoding()) return;
194 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
195 else { movsd (dst, src); return; }
196 }
197
198 void movdbl(XMMRegister dst, AddressLiteral src);
199
200 void movdbl(XMMRegister dst, Address src) {
201 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
202 else { movlpd(dst, src); return; }
203 }
204 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
205
206 void incrementl(AddressLiteral dst);
207 void incrementl(ArrayAddress dst);
208
209 void incrementq(AddressLiteral dst);
210
211 // Alignment
212 void align(int modulus);
213 void align(int modulus, int target);
214
215 // A 5 byte nop that is safe for patching (see patch_verified_entry)
216 void fat_nop();
217
218 // Stack frame creation/removal
219 void enter();
220 void leave();
221
222 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
223 // The pointer will be loaded into the thread register.
224 void get_thread(Register thread);
225
226
227 // Support for VM calls
228 //
229 // It is imperative that all calls into the VM are handled via the call_VM macros.
230 // They make sure that the stack linkage is setup correctly. call_VM's correspond
231 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
232
233
234 void call_VM(Register oop_result,
235 address entry_point,
236 bool check_exceptions = true);
237 void call_VM(Register oop_result,
238 address entry_point,
239 Register arg_1,
240 bool check_exceptions = true);
241 void call_VM(Register oop_result,
242 address entry_point,
243 Register arg_1, Register arg_2,
244 bool check_exceptions = true);
245 void call_VM(Register oop_result,
246 address entry_point,
247 Register arg_1, Register arg_2, Register arg_3,
248 bool check_exceptions = true);
249
250 // Overloadings with last_Java_sp
251 void call_VM(Register oop_result,
252 Register last_java_sp,
253 address entry_point,
254 int number_of_arguments = 0,
255 bool check_exceptions = true);
256 void call_VM(Register oop_result,
257 Register last_java_sp,
258 address entry_point,
259 Register arg_1, bool
260 check_exceptions = true);
261 void call_VM(Register oop_result,
262 Register last_java_sp,
263 address entry_point,
264 Register arg_1, Register arg_2,
265 bool check_exceptions = true);
266 void call_VM(Register oop_result,
267 Register last_java_sp,
268 address entry_point,
269 Register arg_1, Register arg_2, Register arg_3,
270 bool check_exceptions = true);
271
272 void get_vm_result (Register oop_result, Register thread);
273 void get_vm_result_2(Register metadata_result, Register thread);
274
275 // These always tightly bind to MacroAssembler::call_VM_base
276 // bypassing the virtual implementation
277 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
278 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
279 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
280 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
281 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
282
283 void call_VM_leaf0(address entry_point);
284 void call_VM_leaf(address entry_point,
285 int number_of_arguments = 0);
286 void call_VM_leaf(address entry_point,
287 Register arg_1);
288 void call_VM_leaf(address entry_point,
289 Register arg_1, Register arg_2);
290 void call_VM_leaf(address entry_point,
291 Register arg_1, Register arg_2, Register arg_3);
292
293 // These always tightly bind to MacroAssembler::call_VM_leaf_base
294 // bypassing the virtual implementation
295 void super_call_VM_leaf(address entry_point);
296 void super_call_VM_leaf(address entry_point, Register arg_1);
297 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
298 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
299 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
300
301 // last Java Frame (fills frame anchor)
302 void set_last_Java_frame(Register thread,
303 Register last_java_sp,
304 Register last_java_fp,
305 address last_java_pc);
306
307 // thread in the default location (r15_thread on 64bit)
308 void set_last_Java_frame(Register last_java_sp,
309 Register last_java_fp,
310 address last_java_pc);
311
312 void reset_last_Java_frame(Register thread, bool clear_fp);
313
314 // thread in the default location (r15_thread on 64bit)
315 void reset_last_Java_frame(bool clear_fp);
316
317 // jobjects
318 void clear_jweak_tag(Register possibly_jweak);
319 void resolve_jobject(Register value, Register thread, Register tmp);
320
321 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
322 void c2bool(Register x);
323
324 // C++ bool manipulation
325
326 void movbool(Register dst, Address src);
327 void movbool(Address dst, bool boolconst);
328 void movbool(Address dst, Register src);
329 void testbool(Register dst);
330
331 void resolve_oop_handle(Register result, Register tmp = rscratch2);
332 void resolve_weak_handle(Register result, Register tmp);
333 void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
334 void load_method_holder_cld(Register rresult, Register rmethod);
335
336 void load_method_holder(Register holder, Register method);
337
338 // oop manipulations
339 void load_metadata(Register dst, Register src);
340 void load_storage_props(Register dst, Register src);
341 void load_klass(Register dst, Register src);
342 void store_klass(Register dst, Register src);
343
344 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
345 Register tmp1, Register thread_tmp);
346 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
347 Register tmp1, Register tmp2, Register tmp3 = noreg);
348
349 // Resolves obj access. Result is placed in the same register.
350 // All other registers are preserved.
351 void resolve(DecoratorSet decorators, Register obj);
352
353 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
354 Register thread_tmp = noreg, DecoratorSet decorators = 0);
355 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
356 Register thread_tmp = noreg, DecoratorSet decorators = 0);
357 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
358 Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
359
360 // Used for storing NULL. All other oop constants should be
361 // stored using routines that take a jobject.
362 void store_heap_oop_null(Address dst);
363
364 void load_prototype_header(Register dst, Register src);
365
366 #ifdef _LP64
367 void store_klass_gap(Register dst, Register src);
368
369 // This dummy is to prevent a call to store_heap_oop from
370 // converting a zero (like NULL) into a Register by giving
371 // the compiler two choices it can't resolve
372
373 void store_heap_oop(Address dst, void* dummy);
374
375 void encode_heap_oop(Register r);
376 void decode_heap_oop(Register r);
377 void encode_heap_oop_not_null(Register r);
378 void decode_heap_oop_not_null(Register r);
379 void encode_heap_oop_not_null(Register dst, Register src);
380 void decode_heap_oop_not_null(Register dst, Register src);
381
382 void set_narrow_oop(Register dst, jobject obj);
383 void set_narrow_oop(Address dst, jobject obj);
384 void cmp_narrow_oop(Register dst, jobject obj);
385 void cmp_narrow_oop(Address dst, jobject obj);
386
387 void encode_klass_not_null(Register r);
388 void decode_klass_not_null(Register r);
389 void encode_klass_not_null(Register dst, Register src);
390 void decode_klass_not_null(Register dst, Register src);
391 void set_narrow_klass(Register dst, Klass* k);
392 void set_narrow_klass(Address dst, Klass* k);
393 void cmp_narrow_klass(Register dst, Klass* k);
394 void cmp_narrow_klass(Address dst, Klass* k);
395
396 // Returns the byte size of the instructions generated by decode_klass_not_null()
397 // when compressed klass pointers are being used.
398 static int instr_size_for_decode_klass_not_null();
399
400 // if heap base register is used - reinit it with the correct value
401 void reinit_heapbase();
402
403 DEBUG_ONLY(void verify_heapbase(const char* msg);)
404
405 #endif // _LP64
406
407 // Int division/remainder for Java
408 // (as idivl, but checks for special case as described in JVM spec.)
409 // returns idivl instruction offset for implicit exception handling
410 int corrected_idivl(Register reg);
411
412 // Long division/remainder for Java
413 // (as idivq, but checks for special case as described in JVM spec.)
414 // returns idivq instruction offset for implicit exception handling
415 int corrected_idivq(Register reg);
416
417 void int3();
418
419 // Long operation macros for a 32bit cpu
420 // Long negation for Java
421 void lneg(Register hi, Register lo);
422
423 // Long multiplication for Java
424 // (destroys contents of eax, ebx, ecx and edx)
425 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
426
427 // Long shifts for Java
428 // (semantics as described in JVM spec.)
429 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
430 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
431
432 // Long compare for Java
433 // (semantics as described in JVM spec.)
434 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
435
436
437 // misc
438
439 // Sign extension
440 void sign_extend_short(Register reg);
441 void sign_extend_byte(Register reg);
442
443 // Division by power of 2, rounding towards 0
444 void division_with_shift(Register reg, int shift_value);
445
446 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
447 //
448 // CF (corresponds to C0) if x < y
449 // PF (corresponds to C2) if unordered
450 // ZF (corresponds to C3) if x = y
451 //
452 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
453 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
454 void fcmp(Register tmp);
455 // Variant of the above which allows y to be further down the stack
456 // and which only pops x and y if specified. If pop_right is
457 // specified then pop_left must also be specified.
458 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
459
460 // Floating-point comparison for Java
461 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
462 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
463 // (semantics as described in JVM spec.)
464 void fcmp2int(Register dst, bool unordered_is_less);
465 // Variant of the above which allows y to be further down the stack
466 // and which only pops x and y if specified. If pop_right is
467 // specified then pop_left must also be specified.
468 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
469
470 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
471 // tmp is a temporary register, if none is available use noreg
472 void fremr(Register tmp);
473
474 // dst = c = a * b + c
475 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
476 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
477
478 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
479 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
480 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
481 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
482
483
484 // same as fcmp2int, but using SSE2
485 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
486 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
487
488 // branch to L if FPU flag C2 is set/not set
489 // tmp is a temporary register, if none is available use noreg
490 void jC2 (Register tmp, Label& L);
491 void jnC2(Register tmp, Label& L);
492
493 // Pop ST (ffree & fincstp combined)
494 void fpop();
495
496 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
497 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
498 void load_float(Address src);
499
500 // Store float value to 'address'. If UseSSE >= 1, the value is stored
501 // from register xmm0. Otherwise, the value is stored from the FPU stack.
502 void store_float(Address dst);
503
504 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
505 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
506 void load_double(Address src);
507
508 // Store double value to 'address'. If UseSSE >= 2, the value is stored
509 // from register xmm0. Otherwise, the value is stored from the FPU stack.
510 void store_double(Address dst);
511
512 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
513 void push_fTOS();
514
515 // pops double TOS element from CPU stack and pushes on FPU stack
516 void pop_fTOS();
517
518 void empty_FPU_stack();
519
520 void push_IU_state();
521 void pop_IU_state();
522
523 void push_FPU_state();
524 void pop_FPU_state();
525
526 void push_CPU_state();
527 void pop_CPU_state();
528
529 // Round up to a power of two
530 void round_to(Register reg, int modulus);
531
532 // Callee saved registers handling
533 void push_callee_saved_registers();
534 void pop_callee_saved_registers();
535
536 // allocation
537 void eden_allocate(
538 Register thread, // Current thread
539 Register obj, // result: pointer to object after successful allocation
540 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
541 int con_size_in_bytes, // object size in bytes if known at compile time
542 Register t1, // temp register
543 Label& slow_case // continuation point if fast allocation fails
544 );
545 void tlab_allocate(
546 Register thread, // Current thread
547 Register obj, // result: pointer to object after successful allocation
548 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
549 int con_size_in_bytes, // object size in bytes if known at compile time
550 Register t1, // temp register
551 Register t2, // temp register
552 Label& slow_case // continuation point if fast allocation fails
553 );
554 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
555
556 // interface method calling
557 void lookup_interface_method(Register recv_klass,
558 Register intf_klass,
559 RegisterOrConstant itable_index,
560 Register method_result,
561 Register scan_temp,
562 Label& no_such_interface,
563 bool return_method = true);
564
565 // virtual method calling
566 void lookup_virtual_method(Register recv_klass,
567 RegisterOrConstant vtable_index,
568 Register method_result);
569
570 // Test sub_klass against super_klass, with fast and slow paths.
571
572 // The fast path produces a tri-state answer: yes / no / maybe-slow.
573 // One of the three labels can be NULL, meaning take the fall-through.
574 // If super_check_offset is -1, the value is loaded up from super_klass.
575 // No registers are killed, except temp_reg.
576 void check_klass_subtype_fast_path(Register sub_klass,
577 Register super_klass,
578 Register temp_reg,
579 Label* L_success,
580 Label* L_failure,
581 Label* L_slow_path,
582 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
583
584 // The rest of the type check; must be wired to a corresponding fast path.
585 // It does not repeat the fast path logic, so don't use it standalone.
586 // The temp_reg and temp2_reg can be noreg, if no temps are available.
587 // Updates the sub's secondary super cache as necessary.
588 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
589 void check_klass_subtype_slow_path(Register sub_klass,
590 Register super_klass,
591 Register temp_reg,
592 Register temp2_reg,
593 Label* L_success,
594 Label* L_failure,
595 bool set_cond_codes = false);
596
597 // Simplified, combined version, good for typical uses.
598 // Falls through on failure.
599 void check_klass_subtype(Register sub_klass,
600 Register super_klass,
601 Register temp_reg,
602 Label& L_success);
603
604 void clinit_barrier(Register klass,
605 Register thread,
606 Label* L_fast_path = NULL,
607 Label* L_slow_path = NULL);
608
609 // method handles (JSR 292)
610 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
611
612 //----
613 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
614
615 // Debugging
616
617 // only if +VerifyOops
618 // TODO: Make these macros with file and line like sparc version!
619 void verify_oop(Register reg, const char* s = "broken oop");
620 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
621
622 // TODO: verify method and klass metadata (compare against vptr?)
623 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
624 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
625
626 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
627 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
628
629 // only if +VerifyFPU
630 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
631
632 // Verify or restore cpu control state after JNI call
633 void restore_cpu_control_state_after_jni();
634
635 // prints msg, dumps registers and stops execution
636 void stop(const char* msg);
637
638 // prints msg and continues
639 void warn(const char* msg);
640
641 // dumps registers and other state
642 void print_state();
643
644 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
645 static void debug64(char* msg, int64_t pc, int64_t regs[]);
646 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
647 static void print_state64(int64_t pc, int64_t regs[]);
648
649 void os_breakpoint();
650
651 void untested() { stop("untested"); }
652
653 void unimplemented(const char* what = "");
654
655 void should_not_reach_here() { stop("should not reach here"); }
656
657 void print_CPU_state();
658
659 // Stack overflow checking
660 void bang_stack_with_offset(int offset) {
661 // stack grows down, caller passes positive offset
662 assert(offset > 0, "must bang with negative offset");
663 movl(Address(rsp, (-offset)), rax);
664 }
665
666 // Writes to stack successive pages until offset reached to check for
667 // stack overflow + shadow pages. Also, clobbers tmp
668 void bang_stack_size(Register size, Register tmp);
669
670 // Check for reserved stack access in method being exited (for JIT)
671 void reserved_stack_check();
672
673 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
674 Register tmp,
675 int offset);
676
677 // If thread_reg is != noreg the code assumes the register passed contains
678 // the thread (required on 64 bit).
679 void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
680
681 void verify_tlab();
682
683 // Biased locking support
684 // lock_reg and obj_reg must be loaded up with the appropriate values.
685 // swap_reg must be rax, and is killed.
686 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
687 // be killed; if not supplied, push/pop will be used internally to
688 // allocate a temporary (inefficient, avoid if possible).
689 // Optional slow case is for implementations (interpreter and C1) which branch to
690 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
691 // Returns offset of first potentially-faulting instruction for null
692 // check info (currently consumed only by C1). If
693 // swap_reg_contains_mark is true then returns -1 as it is assumed
694 // the calling code has already passed any potential faults.
695 int biased_locking_enter(Register lock_reg, Register obj_reg,
696 Register swap_reg, Register tmp_reg,
697 bool swap_reg_contains_mark,
698 Label& done, Label* slow_case = NULL,
699 BiasedLockingCounters* counters = NULL);
700 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
701 #ifdef COMPILER2
702 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
703 // See full desription in macroAssembler_x86.cpp.
704 void fast_lock(Register obj, Register box, Register tmp,
705 Register scr, Register cx1, Register cx2,
706 BiasedLockingCounters* counters,
707 RTMLockingCounters* rtm_counters,
708 RTMLockingCounters* stack_rtm_counters,
709 Metadata* method_data,
710 bool use_rtm, bool profile_rtm);
711 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
712 #if INCLUDE_RTM_OPT
713 void rtm_counters_update(Register abort_status, Register rtm_counters);
714 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
715 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
716 RTMLockingCounters* rtm_counters,
717 Metadata* method_data);
718 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
719 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
720 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
721 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
722 void rtm_stack_locking(Register obj, Register tmp, Register scr,
723 Register retry_on_abort_count,
724 RTMLockingCounters* stack_rtm_counters,
725 Metadata* method_data, bool profile_rtm,
726 Label& DONE_LABEL, Label& IsInflated);
727 void rtm_inflated_locking(Register obj, Register box, Register tmp,
728 Register scr, Register retry_on_busy_count,
729 Register retry_on_abort_count,
730 RTMLockingCounters* rtm_counters,
731 Metadata* method_data, bool profile_rtm,
732 Label& DONE_LABEL);
733 #endif
734 #endif
735
736 Condition negate_condition(Condition cond);
737
738 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
739 // operands. In general the names are modified to avoid hiding the instruction in Assembler
740 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
741 // here in MacroAssembler. The major exception to this rule is call
742
743 // Arithmetics
744
745
746 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
747 void addptr(Address dst, Register src);
748
749 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
750 void addptr(Register dst, int32_t src);
751 void addptr(Register dst, Register src);
752 void addptr(Register dst, RegisterOrConstant src) {
753 if (src.is_constant()) addptr(dst, (int) src.as_constant());
754 else addptr(dst, src.as_register());
755 }
756
757 void andptr(Register dst, int32_t src);
758 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
759
760 void cmp8(AddressLiteral src1, int imm);
761
762 // renamed to drag out the casting of address to int32_t/intptr_t
763 void cmp32(Register src1, int32_t imm);
764
765 void cmp32(AddressLiteral src1, int32_t imm);
766 // compare reg - mem, or reg - &mem
767 void cmp32(Register src1, AddressLiteral src2);
768
769 void cmp32(Register src1, Address src2);
770
771 #ifndef _LP64
772 void cmpklass(Address dst, Metadata* obj);
773 void cmpklass(Register dst, Metadata* obj);
774 void cmpoop(Address dst, jobject obj);
775 void cmpoop_raw(Address dst, jobject obj);
776 #endif // _LP64
777
778 void cmpoop(Register src1, Register src2);
779 void cmpoop(Register src1, Address src2);
780 void cmpoop(Register dst, jobject obj);
781 void cmpoop_raw(Register dst, jobject obj);
782
783 // NOTE src2 must be the lval. This is NOT an mem-mem compare
784 void cmpptr(Address src1, AddressLiteral src2);
785
786 void cmpptr(Register src1, AddressLiteral src2);
787
788 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
789 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
790 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
791
792 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
793 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
794
795 // cmp64 to avoild hiding cmpq
796 void cmp64(Register src1, AddressLiteral src);
797
798 void cmpxchgptr(Register reg, Address adr);
799
800 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
801
802
803 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
804 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
805
806
807 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
808
809 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
810
811 void shlptr(Register dst, int32_t shift);
812 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
813
814 void shrptr(Register dst, int32_t shift);
815 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
816
817 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
818 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
819
820 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
821
822 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
823 void subptr(Register dst, int32_t src);
824 // Force generation of a 4 byte immediate value even if it fits into 8bit
825 void subptr_imm32(Register dst, int32_t src);
826 void subptr(Register dst, Register src);
827 void subptr(Register dst, RegisterOrConstant src) {
828 if (src.is_constant()) subptr(dst, (int) src.as_constant());
829 else subptr(dst, src.as_register());
830 }
831
832 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
833 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
834
835 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
836 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
837
838 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
839
840
841
842 // Helper functions for statistics gathering.
843 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
844 void cond_inc32(Condition cond, AddressLiteral counter_addr);
845 // Unconditional atomic increment.
846 void atomic_incl(Address counter_addr);
847 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
848 #ifdef _LP64
849 void atomic_incq(Address counter_addr);
850 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
851 #endif
852 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
853 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
854
855 void lea(Register dst, AddressLiteral adr);
856 void lea(Address dst, AddressLiteral adr);
857 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
858
859 void leal32(Register dst, Address src) { leal(dst, src); }
860
861 // Import other testl() methods from the parent class or else
862 // they will be hidden by the following overriding declaration.
863 using Assembler::testl;
864 void testl(Register dst, AddressLiteral src);
865
866 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
867 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
868 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
869 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
870
871 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
872 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
873 void testptr(Register src1, Register src2);
874
875 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
876 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
877
878 // Calls
879
880 void call(Label& L, relocInfo::relocType rtype);
881 void call(Register entry);
882
883 // NOTE: this call transfers to the effective address of entry NOT
884 // the address contained by entry. This is because this is more natural
885 // for jumps/calls.
886 void call(AddressLiteral entry);
887
888 // Emit the CompiledIC call idiom
889 void ic_call(address entry, jint method_index = 0);
890
891 // Jumps
892
893 // NOTE: these jumps tranfer to the effective address of dst NOT
894 // the address contained by dst. This is because this is more natural
895 // for jumps/calls.
896 void jump(AddressLiteral dst);
897 void jump_cc(Condition cc, AddressLiteral dst);
898
899 // 32bit can do a case table jump in one instruction but we no longer allow the base
900 // to be installed in the Address class. This jump will tranfers to the address
901 // contained in the location described by entry (not the address of entry)
902 void jump(ArrayAddress entry);
903
904 // Floating
905
906 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
907 void andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
908 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
909
910 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
911 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
912 void andps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
913
914 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
915 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
916 void comiss(XMMRegister dst, AddressLiteral src);
917
918 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
919 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
920 void comisd(XMMRegister dst, AddressLiteral src);
921
922 void fadd_s(Address src) { Assembler::fadd_s(src); }
923 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
924
925 void fldcw(Address src) { Assembler::fldcw(src); }
926 void fldcw(AddressLiteral src);
927
928 void fld_s(int index) { Assembler::fld_s(index); }
929 void fld_s(Address src) { Assembler::fld_s(src); }
930 void fld_s(AddressLiteral src);
931
932 void fld_d(Address src) { Assembler::fld_d(src); }
933 void fld_d(AddressLiteral src);
934
935 void fld_x(Address src) { Assembler::fld_x(src); }
936 void fld_x(AddressLiteral src);
937
938 void fmul_s(Address src) { Assembler::fmul_s(src); }
939 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
940
941 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
942 void ldmxcsr(AddressLiteral src);
943
944 #ifdef _LP64
945 private:
946 void sha256_AVX2_one_round_compute(
947 Register reg_old_h,
948 Register reg_a,
949 Register reg_b,
950 Register reg_c,
951 Register reg_d,
952 Register reg_e,
953 Register reg_f,
954 Register reg_g,
955 Register reg_h,
956 int iter);
957 void sha256_AVX2_four_rounds_compute_first(int start);
958 void sha256_AVX2_four_rounds_compute_last(int start);
959 void sha256_AVX2_one_round_and_sched(
960 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
961 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
962 XMMRegister xmm_2, /* ymm6 */
963 XMMRegister xmm_3, /* ymm7 */
964 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
965 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
966 Register reg_c, /* edi */
967 Register reg_d, /* esi */
968 Register reg_e, /* r8d */
969 Register reg_f, /* r9d */
970 Register reg_g, /* r10d */
971 Register reg_h, /* r11d */
972 int iter);
973
974 void addm(int disp, Register r1, Register r2);
975 void gfmul(XMMRegister tmp0, XMMRegister t);
976 void schoolbookAAD(int i, Register subkeyH, XMMRegister data, XMMRegister tmp0,
977 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3);
978 void generateHtbl_one_block(Register htbl);
979 void generateHtbl_eight_blocks(Register htbl);
980 public:
981 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
982 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
983 Register buf, Register state, Register ofs, Register limit, Register rsp,
984 bool multi_block, XMMRegister shuf_mask);
985 void avx_ghash(Register state, Register htbl, Register data, Register blocks);
986 #endif
987
988 #ifdef _LP64
989 private:
990 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
991 Register e, Register f, Register g, Register h, int iteration);
992
993 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
994 Register a, Register b, Register c, Register d, Register e, Register f,
995 Register g, Register h, int iteration);
996
997 void addmq(int disp, Register r1, Register r2);
998 public:
999 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1000 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1001 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
1002 XMMRegister shuf_mask);
1003 private:
1004 void roundEnc(XMMRegister key, int rnum);
1005 void lastroundEnc(XMMRegister key, int rnum);
1006 void roundDec(XMMRegister key, int rnum);
1007 void lastroundDec(XMMRegister key, int rnum);
1008 void ev_load_key(XMMRegister xmmdst, Register key, int offset, XMMRegister xmm_shuf_mask);
1009
1010 public:
1011 void aesecb_encrypt(Register source_addr, Register dest_addr, Register key, Register len);
1012 void aesecb_decrypt(Register source_addr, Register dest_addr, Register key, Register len);
1013 void aesctr_encrypt(Register src_addr, Register dest_addr, Register key, Register counter,
1014 Register len_reg, Register used, Register used_addr, Register saved_encCounter_start);
1015
1016 #endif
1017
1018 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
1019 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
1020 Register buf, Register state, Register ofs, Register limit, Register rsp,
1021 bool multi_block);
1022
1023 #ifdef _LP64
1024 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1025 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1026 Register buf, Register state, Register ofs, Register limit, Register rsp,
1027 bool multi_block, XMMRegister shuf_mask);
1028 #else
1029 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1030 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1031 Register buf, Register state, Register ofs, Register limit, Register rsp,
1032 bool multi_block);
1033 #endif
1034
1035 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1036 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1037 Register rax, Register rcx, Register rdx, Register tmp);
1038
1039 #ifdef _LP64
1040 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1041 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1042 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
1043
1044 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1045 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1046 Register rax, Register rcx, Register rdx, Register r11);
1047
1048 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1049 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1050 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1051
1052 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1053 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1054 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1055 Register tmp3, Register tmp4);
1056
1057 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1058 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1059 Register rax, Register rcx, Register rdx, Register tmp1,
1060 Register tmp2, Register tmp3, Register tmp4);
1061 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1062 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1063 Register rax, Register rcx, Register rdx, Register tmp1,
1064 Register tmp2, Register tmp3, Register tmp4);
1065 #else
1066 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1067 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1068 Register rax, Register rcx, Register rdx, Register tmp1);
1069
1070 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1071 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1072 Register rax, Register rcx, Register rdx, Register tmp);
1073
1074 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1075 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1076 Register rdx, Register tmp);
1077
1078 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1079 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1080 Register rax, Register rbx, Register rdx);
1081
1082 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1083 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1084 Register rax, Register rcx, Register rdx, Register tmp);
1085
1086 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1087 Register edx, Register ebx, Register esi, Register edi,
1088 Register ebp, Register esp);
1089
1090 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1091 Register esi, Register edi, Register ebp, Register esp);
1092
1093 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1094 Register edx, Register ebx, Register esi, Register edi,
1095 Register ebp, Register esp);
1096
1097 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1098 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1099 Register rax, Register rcx, Register rdx, Register tmp);
1100 #endif
1101
1102 void increase_precision();
1103 void restore_precision();
1104
1105 private:
1106
1107 // these are private because users should be doing movflt/movdbl
1108
1109 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1110 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1111 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1112 void movss(XMMRegister dst, AddressLiteral src);
1113
1114 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1115 void movlpd(XMMRegister dst, AddressLiteral src);
1116
1117 public:
1118
1119 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1120 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1121 void addsd(XMMRegister dst, AddressLiteral src);
1122
1123 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1124 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1125 void addss(XMMRegister dst, AddressLiteral src);
1126
1127 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1128 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1129 void addpd(XMMRegister dst, AddressLiteral src);
1130
1131 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1132 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1133 void divsd(XMMRegister dst, AddressLiteral src);
1134
1135 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1136 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1137 void divss(XMMRegister dst, AddressLiteral src);
1138
1139 // Move Unaligned Double Quadword
1140 void movdqu(Address dst, XMMRegister src);
1141 void movdqu(XMMRegister dst, Address src);
1142 void movdqu(XMMRegister dst, XMMRegister src);
1143 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1144 // AVX Unaligned forms
1145 void vmovdqu(Address dst, XMMRegister src);
1146 void vmovdqu(XMMRegister dst, Address src);
1147 void vmovdqu(XMMRegister dst, XMMRegister src);
1148 void vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1149 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1150 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1151 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1152 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1153
1154 // Move Aligned Double Quadword
1155 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1156 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1157 void movdqa(XMMRegister dst, AddressLiteral src);
1158
1159 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1160 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1161 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1162 void movsd(XMMRegister dst, AddressLiteral src);
1163
1164 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1165 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1166 void mulpd(XMMRegister dst, AddressLiteral src);
1167
1168 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1169 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1170 void mulsd(XMMRegister dst, AddressLiteral src);
1171
1172 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1173 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1174 void mulss(XMMRegister dst, AddressLiteral src);
1175
1176 // Carry-Less Multiplication Quadword
1177 void pclmulldq(XMMRegister dst, XMMRegister src) {
1178 // 0x00 - multiply lower 64 bits [0:63]
1179 Assembler::pclmulqdq(dst, src, 0x00);
1180 }
1181 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1182 // 0x11 - multiply upper 64 bits [64:127]
1183 Assembler::pclmulqdq(dst, src, 0x11);
1184 }
1185
1186 void pcmpeqb(XMMRegister dst, XMMRegister src);
1187 void pcmpeqw(XMMRegister dst, XMMRegister src);
1188
1189 void pcmpestri(XMMRegister dst, Address src, int imm8);
1190 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1191
1192 void pmovzxbw(XMMRegister dst, XMMRegister src);
1193 void pmovzxbw(XMMRegister dst, Address src);
1194
1195 void pmovmskb(Register dst, XMMRegister src);
1196
1197 void ptest(XMMRegister dst, XMMRegister src);
1198
1199 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1200 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1201 void sqrtsd(XMMRegister dst, AddressLiteral src);
1202
1203 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1204 void roundsd(XMMRegister dst, Address src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1205 void roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg);
1206
1207 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1208 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1209 void sqrtss(XMMRegister dst, AddressLiteral src);
1210
1211 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1212 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1213 void subsd(XMMRegister dst, AddressLiteral src);
1214
1215 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1216 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1217 void subss(XMMRegister dst, AddressLiteral src);
1218
1219 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1220 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1221 void ucomiss(XMMRegister dst, AddressLiteral src);
1222
1223 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1224 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1225 void ucomisd(XMMRegister dst, AddressLiteral src);
1226
1227 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1228 void xorpd(XMMRegister dst, XMMRegister src);
1229 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1230 void xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1231
1232 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1233 void xorps(XMMRegister dst, XMMRegister src);
1234 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1235 void xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1236
1237 // Shuffle Bytes
1238 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1239 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1240 void pshufb(XMMRegister dst, AddressLiteral src);
1241 // AVX 3-operands instructions
1242
1243 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1244 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1245 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1246
1247 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1248 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1249 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1250
1251 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1252 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1253
1254 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1255 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1256
1257 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1258 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1259
1260 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1261 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1262 void vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch);
1263
1264 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1265 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1266 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1267
1268 void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1269 void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); }
1270
1271 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1272
1273 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1274
1275 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1276 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1277
1278 void vpmovmskb(Register dst, XMMRegister src);
1279
1280 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1281 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1282
1283 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1284 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1285
1286 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1287 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1288
1289 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1290 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1291
1292 void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1293 void evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1294
1295 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1296 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1297
1298 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1299 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1300
1301 void vptest(XMMRegister dst, XMMRegister src);
1302
1303 void punpcklbw(XMMRegister dst, XMMRegister src);
1304 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1305
1306 void pshufd(XMMRegister dst, Address src, int mode);
1307 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1308
1309 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1310 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1311
1312 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1313 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1314 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1315
1316 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1317 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1318 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1319
1320 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1321 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1322 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1323
1324 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1325 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1326 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1327
1328 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1329 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1330 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1331
1332 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1333 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1334 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1335
1336 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1337 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1338 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1339
1340 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1341 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1342 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1343
1344 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1345 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1346
1347 // AVX Vector instructions
1348
1349 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1350 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1351 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1352
1353 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1354 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1355 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1356
1357 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1358 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1359 Assembler::vpxor(dst, nds, src, vector_len);
1360 else
1361 Assembler::vxorpd(dst, nds, src, vector_len);
1362 }
1363 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1364 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1365 Assembler::vpxor(dst, nds, src, vector_len);
1366 else
1367 Assembler::vxorpd(dst, nds, src, vector_len);
1368 }
1369 void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1370
1371 // Simple version for AVX2 256bit vectors
1372 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1373 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1374
1375 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1376 if (UseAVX > 2) {
1377 Assembler::vinserti32x4(dst, dst, src, imm8);
1378 } else if (UseAVX > 1) {
1379 // vinserti128 is available only in AVX2
1380 Assembler::vinserti128(dst, nds, src, imm8);
1381 } else {
1382 Assembler::vinsertf128(dst, nds, src, imm8);
1383 }
1384 }
1385
1386 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1387 if (UseAVX > 2) {
1388 Assembler::vinserti32x4(dst, dst, src, imm8);
1389 } else if (UseAVX > 1) {
1390 // vinserti128 is available only in AVX2
1391 Assembler::vinserti128(dst, nds, src, imm8);
1392 } else {
1393 Assembler::vinsertf128(dst, nds, src, imm8);
1394 }
1395 }
1396
1397 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1398 if (UseAVX > 2) {
1399 Assembler::vextracti32x4(dst, src, imm8);
1400 } else if (UseAVX > 1) {
1401 // vextracti128 is available only in AVX2
1402 Assembler::vextracti128(dst, src, imm8);
1403 } else {
1404 Assembler::vextractf128(dst, src, imm8);
1405 }
1406 }
1407
1408 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1409 if (UseAVX > 2) {
1410 Assembler::vextracti32x4(dst, src, imm8);
1411 } else if (UseAVX > 1) {
1412 // vextracti128 is available only in AVX2
1413 Assembler::vextracti128(dst, src, imm8);
1414 } else {
1415 Assembler::vextractf128(dst, src, imm8);
1416 }
1417 }
1418
1419 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1420 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1421 vinserti128(dst, dst, src, 1);
1422 }
1423 void vinserti128_high(XMMRegister dst, Address src) {
1424 vinserti128(dst, dst, src, 1);
1425 }
1426 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1427 vextracti128(dst, src, 1);
1428 }
1429 void vextracti128_high(Address dst, XMMRegister src) {
1430 vextracti128(dst, src, 1);
1431 }
1432
1433 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1434 if (UseAVX > 2) {
1435 Assembler::vinsertf32x4(dst, dst, src, 1);
1436 } else {
1437 Assembler::vinsertf128(dst, dst, src, 1);
1438 }
1439 }
1440
1441 void vinsertf128_high(XMMRegister dst, Address src) {
1442 if (UseAVX > 2) {
1443 Assembler::vinsertf32x4(dst, dst, src, 1);
1444 } else {
1445 Assembler::vinsertf128(dst, dst, src, 1);
1446 }
1447 }
1448
1449 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1450 if (UseAVX > 2) {
1451 Assembler::vextractf32x4(dst, src, 1);
1452 } else {
1453 Assembler::vextractf128(dst, src, 1);
1454 }
1455 }
1456
1457 void vextractf128_high(Address dst, XMMRegister src) {
1458 if (UseAVX > 2) {
1459 Assembler::vextractf32x4(dst, src, 1);
1460 } else {
1461 Assembler::vextractf128(dst, src, 1);
1462 }
1463 }
1464
1465 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1466 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1467 Assembler::vinserti64x4(dst, dst, src, 1);
1468 }
1469 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1470 Assembler::vinsertf64x4(dst, dst, src, 1);
1471 }
1472 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1473 Assembler::vextracti64x4(dst, src, 1);
1474 }
1475 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1476 Assembler::vextractf64x4(dst, src, 1);
1477 }
1478 void vextractf64x4_high(Address dst, XMMRegister src) {
1479 Assembler::vextractf64x4(dst, src, 1);
1480 }
1481 void vinsertf64x4_high(XMMRegister dst, Address src) {
1482 Assembler::vinsertf64x4(dst, dst, src, 1);
1483 }
1484
1485 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1486 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1487 vinserti128(dst, dst, src, 0);
1488 }
1489 void vinserti128_low(XMMRegister dst, Address src) {
1490 vinserti128(dst, dst, src, 0);
1491 }
1492 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1493 vextracti128(dst, src, 0);
1494 }
1495 void vextracti128_low(Address dst, XMMRegister src) {
1496 vextracti128(dst, src, 0);
1497 }
1498
1499 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1500 if (UseAVX > 2) {
1501 Assembler::vinsertf32x4(dst, dst, src, 0);
1502 } else {
1503 Assembler::vinsertf128(dst, dst, src, 0);
1504 }
1505 }
1506
1507 void vinsertf128_low(XMMRegister dst, Address src) {
1508 if (UseAVX > 2) {
1509 Assembler::vinsertf32x4(dst, dst, src, 0);
1510 } else {
1511 Assembler::vinsertf128(dst, dst, src, 0);
1512 }
1513 }
1514
1515 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1516 if (UseAVX > 2) {
1517 Assembler::vextractf32x4(dst, src, 0);
1518 } else {
1519 Assembler::vextractf128(dst, src, 0);
1520 }
1521 }
1522
1523 void vextractf128_low(Address dst, XMMRegister src) {
1524 if (UseAVX > 2) {
1525 Assembler::vextractf32x4(dst, src, 0);
1526 } else {
1527 Assembler::vextractf128(dst, src, 0);
1528 }
1529 }
1530
1531 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1532 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1533 Assembler::vinserti64x4(dst, dst, src, 0);
1534 }
1535 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1536 Assembler::vinsertf64x4(dst, dst, src, 0);
1537 }
1538 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1539 Assembler::vextracti64x4(dst, src, 0);
1540 }
1541 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1542 Assembler::vextractf64x4(dst, src, 0);
1543 }
1544 void vextractf64x4_low(Address dst, XMMRegister src) {
1545 Assembler::vextractf64x4(dst, src, 0);
1546 }
1547 void vinsertf64x4_low(XMMRegister dst, Address src) {
1548 Assembler::vinsertf64x4(dst, dst, src, 0);
1549 }
1550
1551 // Carry-Less Multiplication Quadword
1552 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1553 // 0x00 - multiply lower 64 bits [0:63]
1554 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1555 }
1556 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1557 // 0x11 - multiply upper 64 bits [64:127]
1558 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1559 }
1560 void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1561 // 0x10 - multiply nds[0:63] and src[64:127]
1562 Assembler::vpclmulqdq(dst, nds, src, 0x10);
1563 }
1564 void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1565 //0x01 - multiply nds[64:127] and src[0:63]
1566 Assembler::vpclmulqdq(dst, nds, src, 0x01);
1567 }
1568
1569 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1570 // 0x00 - multiply lower 64 bits [0:63]
1571 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1572 }
1573 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1574 // 0x11 - multiply upper 64 bits [64:127]
1575 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1576 }
1577
1578 // Data
1579
1580 void cmov32( Condition cc, Register dst, Address src);
1581 void cmov32( Condition cc, Register dst, Register src);
1582
1583 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1584
1585 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1586 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1587
1588 void movoop(Register dst, jobject obj);
1589 void movoop(Address dst, jobject obj);
1590
1591 void mov_metadata(Register dst, Metadata* obj);
1592 void mov_metadata(Address dst, Metadata* obj);
1593
1594 void movptr(ArrayAddress dst, Register src);
1595 // can this do an lea?
1596 void movptr(Register dst, ArrayAddress src);
1597
1598 void movptr(Register dst, Address src);
1599
1600 #ifdef _LP64
1601 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1602 #else
1603 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1604 #endif
1605
1606 void movptr(Register dst, intptr_t src);
1607 void movptr(Register dst, Register src);
1608 void movptr(Address dst, intptr_t src);
1609
1610 void movptr(Address dst, Register src);
1611
1612 void movptr(Register dst, RegisterOrConstant src) {
1613 if (src.is_constant()) movptr(dst, src.as_constant());
1614 else movptr(dst, src.as_register());
1615 }
1616
1617 #ifdef _LP64
1618 // Generally the next two are only used for moving NULL
1619 // Although there are situations in initializing the mark word where
1620 // they could be used. They are dangerous.
1621
1622 // They only exist on LP64 so that int32_t and intptr_t are not the same
1623 // and we have ambiguous declarations.
1624
1625 void movptr(Address dst, int32_t imm32);
1626 void movptr(Register dst, int32_t imm32);
1627 #endif // _LP64
1628
1629 // to avoid hiding movl
1630 void mov32(AddressLiteral dst, Register src);
1631 void mov32(Register dst, AddressLiteral src);
1632
1633 // to avoid hiding movb
1634 void movbyte(ArrayAddress dst, int src);
1635
1636 // Import other mov() methods from the parent class or else
1637 // they will be hidden by the following overriding declaration.
1638 using Assembler::movdl;
1639 using Assembler::movq;
1640 void movdl(XMMRegister dst, AddressLiteral src);
1641 void movq(XMMRegister dst, AddressLiteral src);
1642
1643 // Can push value or effective address
1644 void pushptr(AddressLiteral src);
1645
1646 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1647 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1648
1649 void pushoop(jobject obj);
1650 void pushklass(Metadata* obj);
1651
1652 // sign extend as need a l to ptr sized element
1653 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1654 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1655
1656 #ifdef COMPILER2
1657 // Generic instructions support for use in .ad files C2 code generation
1658 void vabsnegd(int opcode, XMMRegister dst, Register scr);
1659 void vabsnegd(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr);
1660 void vabsnegf(int opcode, XMMRegister dst, Register scr);
1661 void vabsnegf(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr);
1662 void vextendbw(bool sign, XMMRegister dst, XMMRegister src, int vector_len);
1663 void vextendbw(bool sign, XMMRegister dst, XMMRegister src);
1664 void vshiftd(int opcode, XMMRegister dst, XMMRegister src);
1665 void vshiftd(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1666 void vshiftw(int opcode, XMMRegister dst, XMMRegister src);
1667 void vshiftw(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1668 void vshiftq(int opcode, XMMRegister dst, XMMRegister src);
1669 void vshiftq(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1670 #endif
1671
1672 // C2 compiled method's prolog code.
1673 void verified_entry(Compile* C, int sp_inc = 0);
1674
1675 enum RegState {
1676 reg_readonly,
1677 reg_writable,
1678 reg_written
1679 };
1680
1681 int store_value_type_fields_to_buf(ciValueKlass* vk, bool from_interpreter = true);
1682
1683 // Unpack all value type arguments passed as oops
1684 void unpack_value_args(Compile* C, bool receiver_only);
1685 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[], int ret_off, int extra_stack_offset);
1686 bool unpack_value_helper(const GrowableArray<SigEntry>* sig, int& sig_index, VMReg from, VMRegPair* regs_to, int& to_index,
1687 RegState reg_state[], int ret_off, int extra_stack_offset);
1688 bool pack_value_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1689 VMReg to, VMRegPair* regs_from, int regs_from_count, int& from_index, RegState reg_state[],
1690 int ret_off, int extra_stack_offset);
1691 void restore_stack(Compile* C);
1692
1693 int shuffle_value_args(bool is_packing, bool receiver_only, int extra_stack_offset,
1694 BasicType* sig_bt, const GrowableArray<SigEntry>* sig_cc,
1695 int args_passed, int args_on_stack, VMRegPair* regs,
1696 int args_passed_to, int args_on_stack_to, VMRegPair* regs_to);
1697 bool shuffle_value_args_spill(bool is_packing, const GrowableArray<SigEntry>* sig_cc, int sig_cc_index,
1698 VMRegPair* regs_from, int from_index, int regs_from_count,
1699 RegState* reg_state, int sp_inc, int extra_stack_offset);
1700 VMReg spill_reg_for(VMReg reg);
1701
1702 // clear memory of size 'cnt' qwords, starting at 'base';
1703 // if 'is_large' is set, do not try to produce short loop
1704 void clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, bool is_large, bool word_copy_only);
1705
1706 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1707 void xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp);
1708
1709 #ifdef COMPILER2
1710 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1711 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1712
1713 // IndexOf strings.
1714 // Small strings are loaded through stack if they cross page boundary.
1715 void string_indexof(Register str1, Register str2,
1716 Register cnt1, Register cnt2,
1717 int int_cnt2, Register result,
1718 XMMRegister vec, Register tmp,
1719 int ae);
1720
1721 // IndexOf for constant substrings with size >= 8 elements
1722 // which don't need to be loaded through stack.
1723 void string_indexofC8(Register str1, Register str2,
1724 Register cnt1, Register cnt2,
1725 int int_cnt2, Register result,
1726 XMMRegister vec, Register tmp,
1727 int ae);
1728
1729 // Smallest code: we don't need to load through stack,
1730 // check string tail.
1731
1732 // helper function for string_compare
1733 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1734 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1735 Address::ScaleFactor scale2, Register index, int ae);
1736 // Compare strings.
1737 void string_compare(Register str1, Register str2,
1738 Register cnt1, Register cnt2, Register result,
1739 XMMRegister vec1, int ae);
1740
1741 // Search for Non-ASCII character (Negative byte value) in a byte array,
1742 // return true if it has any and false otherwise.
1743 void has_negatives(Register ary1, Register len,
1744 Register result, Register tmp1,
1745 XMMRegister vec1, XMMRegister vec2);
1746
1747 // Compare char[] or byte[] arrays.
1748 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1749 Register limit, Register result, Register chr,
1750 XMMRegister vec1, XMMRegister vec2, bool is_char);
1751
1752 #endif
1753
1754 // Fill primitive arrays
1755 void generate_fill(BasicType t, bool aligned,
1756 Register to, Register value, Register count,
1757 Register rtmp, XMMRegister xtmp);
1758
1759 void encode_iso_array(Register src, Register dst, Register len,
1760 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1761 XMMRegister tmp4, Register tmp5, Register result);
1762
1763 #ifdef _LP64
1764 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1765 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1766 Register y, Register y_idx, Register z,
1767 Register carry, Register product,
1768 Register idx, Register kdx);
1769 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1770 Register yz_idx, Register idx,
1771 Register carry, Register product, int offset);
1772 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1773 Register carry, Register carry2,
1774 Register idx, Register jdx,
1775 Register yz_idx1, Register yz_idx2,
1776 Register tmp, Register tmp3, Register tmp4);
1777 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1778 Register yz_idx, Register idx, Register jdx,
1779 Register carry, Register product,
1780 Register carry2);
1781 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1782 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1783 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1784 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1785 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1786 Register tmp2);
1787 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1788 Register rdxReg, Register raxReg);
1789 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1790 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1791 Register tmp3, Register tmp4);
1792 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1793 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1794
1795 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1796 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1797 Register raxReg);
1798 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1799 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1800 Register raxReg);
1801 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1802 Register result, Register tmp1, Register tmp2,
1803 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1804 #endif
1805
1806 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1807 void update_byte_crc32(Register crc, Register val, Register table);
1808 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1809 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1810 // Note on a naming convention:
1811 // Prefix w = register only used on a Westmere+ architecture
1812 // Prefix n = register only used on a Nehalem architecture
1813 #ifdef _LP64
1814 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1815 Register tmp1, Register tmp2, Register tmp3);
1816 #else
1817 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1818 Register tmp1, Register tmp2, Register tmp3,
1819 XMMRegister xtmp1, XMMRegister xtmp2);
1820 #endif
1821 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1822 Register in_out,
1823 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1824 XMMRegister w_xtmp2,
1825 Register tmp1,
1826 Register n_tmp2, Register n_tmp3);
1827 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1828 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1829 Register tmp1, Register tmp2,
1830 Register n_tmp3);
1831 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1832 Register in_out1, Register in_out2, Register in_out3,
1833 Register tmp1, Register tmp2, Register tmp3,
1834 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1835 Register tmp4, Register tmp5,
1836 Register n_tmp6);
1837 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1838 Register tmp1, Register tmp2, Register tmp3,
1839 Register tmp4, Register tmp5, Register tmp6,
1840 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1841 bool is_pclmulqdq_supported);
1842 // Fold 128-bit data chunk
1843 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1844 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1845 // Fold 8-bit data
1846 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1847 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1848 void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1849
1850 // Compress char[] array to byte[].
1851 void char_array_compress(Register src, Register dst, Register len,
1852 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1853 XMMRegister tmp4, Register tmp5, Register result);
1854
1855 // Inflate byte[] array to char[].
1856 void byte_array_inflate(Register src, Register dst, Register len,
1857 XMMRegister tmp1, Register tmp2);
1858
1859 #ifdef _LP64
1860 void cache_wb(Address line);
1861 void cache_wbsync(bool is_pre);
1862 #endif // _LP64
1863
1864 #include "asm/macroAssembler_common.hpp"
1865
1866 };
1867
1868 /**
1869 * class SkipIfEqual:
1870 *
1871 * Instantiating this class will result in assembly code being output that will
1872 * jump around any code emitted between the creation of the instance and it's
1873 * automatic destruction at the end of a scope block, depending on the value of
1874 * the flag passed to the constructor, which will be checked at run-time.
1875 */
1876 class SkipIfEqual {
1877 private:
1878 MacroAssembler* _masm;
1879 Label _label;
1880
1881 public:
1882 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1883 ~SkipIfEqual();
1884 };
1885
1886 #endif // CPU_X86_MACROASSEMBLER_X86_HPP