1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
  26 #define CPU_X86_MACROASSEMBLER_X86_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "utilities/macros.hpp"
  30 #include "runtime/rtmLocking.hpp"
  31 #include "runtime/signature.hpp"
  32 
  33 // MacroAssembler extends Assembler by frequently used macros.
  34 //
  35 // Instructions for which a 'better' code sequence exists depending
  36 // on arguments should also go in here.
  37 
  38 class MacroAssembler: public Assembler {
  39   friend class LIR_Assembler;
  40   friend class Runtime1;      // as_Address()
  41 
  42  public:
  43   // Support for VM calls
  44   //
  45   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  46   // may customize this version by overriding it for its purposes (e.g., to save/restore
  47   // additional registers when doing a VM call).
  48 
  49   virtual void call_VM_leaf_base(
  50     address entry_point,               // the entry point
  51     int     number_of_arguments        // the number of arguments to pop after the call
  52   );
  53 
  54  protected:
  55   // This is the base routine called by the different versions of call_VM. The interpreter
  56   // may customize this version by overriding it for its purposes (e.g., to save/restore
  57   // additional registers when doing a VM call).
  58   //
  59   // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
  60   // returns the register which contains the thread upon return. If a thread register has been
  61   // specified, the return value will correspond to that register. If no last_java_sp is specified
  62   // (noreg) than rsp will be used instead.
  63   virtual void call_VM_base(           // returns the register containing the thread upon return
  64     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  65     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  66     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  67     address  entry_point,              // the entry point
  68     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  69     bool     check_exceptions          // whether to check for pending exceptions after return
  70   );
  71 
  72   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  73 
  74   // helpers for FPU flag access
  75   // tmp is a temporary register, if none is available use noreg
  76   void save_rax   (Register tmp);
  77   void restore_rax(Register tmp);
  78 
  79  public:
  80   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
  81 
  82  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  83  // The implementation is only non-empty for the InterpreterMacroAssembler,
  84  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  85  virtual void check_and_handle_popframe(Register java_thread);
  86  virtual void check_and_handle_earlyret(Register java_thread);
  87 
  88   Address as_Address(AddressLiteral adr);
  89   Address as_Address(ArrayAddress adr);
  90 
  91   // Support for NULL-checks
  92   //
  93   // Generates code that causes a NULL OS exception if the content of reg is NULL.
  94   // If the accessed location is M[reg + offset] and the offset is known, provide the
  95   // offset. No explicit code generation is needed if the offset is within a certain
  96   // range (0 <= offset <= page_size).
  97 
  98   void null_check(Register reg, int offset = -1);
  99   static bool needs_explicit_null_check(intptr_t offset);
 100   static bool uses_implicit_null_check(void* address);
 101 
 102   void test_klass_is_value(Register klass, Register temp_reg, Label& is_value);
 103 
 104   void test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable);
 105   void test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable);
 106   void test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened);
 107 
 108   // Check klass/oops is flat value type array (oop->_klass->_layout_helper & vt_bit)
 109   void test_flat_array_klass(Register klass, Register temp_reg, Label& is_flat_array);
 110   void test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array);
 111 
 112   // Required platform-specific helpers for Label::patch_instructions.
 113   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 114   void pd_patch_instruction(address branch, address target, const char* file, int line) {
 115     unsigned char op = branch[0];
 116     assert(op == 0xE8 /* call */ ||
 117         op == 0xE9 /* jmp */ ||
 118         op == 0xEB /* short jmp */ ||
 119         (op & 0xF0) == 0x70 /* short jcc */ ||
 120         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
 121         op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
 122         "Invalid opcode at patch point");
 123 
 124     if (op == 0xEB || (op & 0xF0) == 0x70) {
 125       // short offset operators (jmp and jcc)
 126       char* disp = (char*) &branch[1];
 127       int imm8 = target - (address) &disp[1];
 128       guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d", file, line);
 129       *disp = imm8;
 130     } else {
 131       int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
 132       int imm32 = target - (address) &disp[1];
 133       *disp = imm32;
 134     }
 135   }
 136 
 137   // The following 4 methods return the offset of the appropriate move instruction
 138 
 139   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 140   int load_unsigned_byte(Register dst, Address src);
 141   int load_unsigned_short(Register dst, Address src);
 142 
 143   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 144   int load_signed_byte(Register dst, Address src);
 145   int load_signed_short(Register dst, Address src);
 146 
 147   // Support for sign-extension (hi:lo = extend_sign(lo))
 148   void extend_sign(Register hi, Register lo);
 149 
 150   // Load and store values by size and signed-ness
 151   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 152   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 153 
 154   // Support for inc/dec with optimal instruction selection depending on value
 155 
 156   void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
 157   void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
 158 
 159   void decrementl(Address dst, int value = 1);
 160   void decrementl(Register reg, int value = 1);
 161 
 162   void decrementq(Register reg, int value = 1);
 163   void decrementq(Address dst, int value = 1);
 164 
 165   void incrementl(Address dst, int value = 1);
 166   void incrementl(Register reg, int value = 1);
 167 
 168   void incrementq(Register reg, int value = 1);
 169   void incrementq(Address dst, int value = 1);
 170 
 171 #ifdef COMPILER2
 172   // special instructions for EVEX
 173   void setvectmask(Register dst, Register src);
 174   void restorevectmask();
 175 #endif
 176 
 177   // Support optimal SSE move instructions.
 178   void movflt(XMMRegister dst, XMMRegister src) {
 179     if (dst-> encoding() == src->encoding()) return;
 180     if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
 181     else                       { movss (dst, src); return; }
 182   }
 183   void movflt(XMMRegister dst, Address src) { movss(dst, src); }
 184   void movflt(XMMRegister dst, AddressLiteral src);
 185   void movflt(Address dst, XMMRegister src) { movss(dst, src); }
 186 
 187   void movdbl(XMMRegister dst, XMMRegister src) {
 188     if (dst-> encoding() == src->encoding()) return;
 189     if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
 190     else                       { movsd (dst, src); return; }
 191   }
 192 
 193   void movdbl(XMMRegister dst, AddressLiteral src);
 194 
 195   void movdbl(XMMRegister dst, Address src) {
 196     if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
 197     else                         { movlpd(dst, src); return; }
 198   }
 199   void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
 200 
 201   void incrementl(AddressLiteral dst);
 202   void incrementl(ArrayAddress dst);
 203 
 204   void incrementq(AddressLiteral dst);
 205 
 206   // Alignment
 207   void align(int modulus);
 208   void align(int modulus, int target);
 209 
 210   // A 5 byte nop that is safe for patching (see patch_verified_entry)
 211   void fat_nop();
 212 
 213   // Stack frame creation/removal
 214   void enter();
 215   void leave();
 216 
 217   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 218   // The pointer will be loaded into the thread register.
 219   void get_thread(Register thread);
 220 
 221 
 222   // Support for VM calls
 223   //
 224   // It is imperative that all calls into the VM are handled via the call_VM macros.
 225   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 226   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 227 
 228 
 229   void call_VM(Register oop_result,
 230                address entry_point,
 231                bool check_exceptions = true);
 232   void call_VM(Register oop_result,
 233                address entry_point,
 234                Register arg_1,
 235                bool check_exceptions = true);
 236   void call_VM(Register oop_result,
 237                address entry_point,
 238                Register arg_1, Register arg_2,
 239                bool check_exceptions = true);
 240   void call_VM(Register oop_result,
 241                address entry_point,
 242                Register arg_1, Register arg_2, Register arg_3,
 243                bool check_exceptions = true);
 244 
 245   // Overloadings with last_Java_sp
 246   void call_VM(Register oop_result,
 247                Register last_java_sp,
 248                address entry_point,
 249                int number_of_arguments = 0,
 250                bool check_exceptions = true);
 251   void call_VM(Register oop_result,
 252                Register last_java_sp,
 253                address entry_point,
 254                Register arg_1, bool
 255                check_exceptions = true);
 256   void call_VM(Register oop_result,
 257                Register last_java_sp,
 258                address entry_point,
 259                Register arg_1, Register arg_2,
 260                bool check_exceptions = true);
 261   void call_VM(Register oop_result,
 262                Register last_java_sp,
 263                address entry_point,
 264                Register arg_1, Register arg_2, Register arg_3,
 265                bool check_exceptions = true);
 266 
 267   void get_vm_result  (Register oop_result, Register thread);
 268   void get_vm_result_2(Register metadata_result, Register thread);
 269 
 270   // These always tightly bind to MacroAssembler::call_VM_base
 271   // bypassing the virtual implementation
 272   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 273   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 274   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 275   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 276   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 277 
 278   void call_VM_leaf0(address entry_point);
 279   void call_VM_leaf(address entry_point,
 280                     int number_of_arguments = 0);
 281   void call_VM_leaf(address entry_point,
 282                     Register arg_1);
 283   void call_VM_leaf(address entry_point,
 284                     Register arg_1, Register arg_2);
 285   void call_VM_leaf(address entry_point,
 286                     Register arg_1, Register arg_2, Register arg_3);
 287 
 288   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 289   // bypassing the virtual implementation
 290   void super_call_VM_leaf(address entry_point);
 291   void super_call_VM_leaf(address entry_point, Register arg_1);
 292   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 293   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 294   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 295 
 296   // last Java Frame (fills frame anchor)
 297   void set_last_Java_frame(Register thread,
 298                            Register last_java_sp,
 299                            Register last_java_fp,
 300                            address last_java_pc);
 301 
 302   // thread in the default location (r15_thread on 64bit)
 303   void set_last_Java_frame(Register last_java_sp,
 304                            Register last_java_fp,
 305                            address last_java_pc);
 306 
 307   void reset_last_Java_frame(Register thread, bool clear_fp);
 308 
 309   // thread in the default location (r15_thread on 64bit)
 310   void reset_last_Java_frame(bool clear_fp);
 311 
 312   // jobjects
 313   void clear_jweak_tag(Register possibly_jweak);
 314   void resolve_jobject(Register value, Register thread, Register tmp);
 315 
 316   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 317   void c2bool(Register x);
 318 
 319   // C++ bool manipulation
 320 
 321   void movbool(Register dst, Address src);
 322   void movbool(Address dst, bool boolconst);
 323   void movbool(Address dst, Register src);
 324   void testbool(Register dst);
 325 
 326   void resolve_oop_handle(Register result, Register tmp = rscratch2);
 327   void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
 328 
 329   // oop manipulations
 330   void load_klass(Register dst, Register src);
 331   void store_klass(Register dst, Register src);
 332 
 333   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 334                       Register tmp1, Register thread_tmp);
 335   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 336                        Register tmp1, Register tmp2);
 337 
 338   // Resolves obj access. Result is placed in the same register.
 339   // All other registers are preserved.
 340   void resolve(DecoratorSet decorators, Register obj);
 341 
 342   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 343                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 344   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 345                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 346   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 347                       Register tmp2 = noreg, DecoratorSet decorators = 0);
 348 
 349   // Used for storing NULL. All other oop constants should be
 350   // stored using routines that take a jobject.
 351   void store_heap_oop_null(Address dst);
 352 
 353   void load_prototype_header(Register dst, Register src);
 354 
 355 #ifdef _LP64
 356   void store_klass_gap(Register dst, Register src);
 357 
 358   // This dummy is to prevent a call to store_heap_oop from
 359   // converting a zero (like NULL) into a Register by giving
 360   // the compiler two choices it can't resolve
 361 
 362   void store_heap_oop(Address dst, void* dummy);
 363 
 364   void encode_heap_oop(Register r);
 365   void decode_heap_oop(Register r);
 366   void encode_heap_oop_not_null(Register r);
 367   void decode_heap_oop_not_null(Register r);
 368   void encode_heap_oop_not_null(Register dst, Register src);
 369   void decode_heap_oop_not_null(Register dst, Register src);
 370 
 371   void set_narrow_oop(Register dst, jobject obj);
 372   void set_narrow_oop(Address dst, jobject obj);
 373   void cmp_narrow_oop(Register dst, jobject obj);
 374   void cmp_narrow_oop(Address dst, jobject obj);
 375 
 376   void encode_klass_not_null(Register r);
 377   void decode_klass_not_null(Register r);
 378   void encode_klass_not_null(Register dst, Register src);
 379   void decode_klass_not_null(Register dst, Register src);
 380   void set_narrow_klass(Register dst, Klass* k);
 381   void set_narrow_klass(Address dst, Klass* k);
 382   void cmp_narrow_klass(Register dst, Klass* k);
 383   void cmp_narrow_klass(Address dst, Klass* k);
 384 
 385   // Returns the byte size of the instructions generated by decode_klass_not_null()
 386   // when compressed klass pointers are being used.
 387   static int instr_size_for_decode_klass_not_null();
 388 
 389   // if heap base register is used - reinit it with the correct value
 390   void reinit_heapbase();
 391 
 392   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 393 
 394 #endif // _LP64
 395 
 396   // Int division/remainder for Java
 397   // (as idivl, but checks for special case as described in JVM spec.)
 398   // returns idivl instruction offset for implicit exception handling
 399   int corrected_idivl(Register reg);
 400 
 401   // Long division/remainder for Java
 402   // (as idivq, but checks for special case as described in JVM spec.)
 403   // returns idivq instruction offset for implicit exception handling
 404   int corrected_idivq(Register reg);
 405 
 406   void int3();
 407 
 408   // Long operation macros for a 32bit cpu
 409   // Long negation for Java
 410   void lneg(Register hi, Register lo);
 411 
 412   // Long multiplication for Java
 413   // (destroys contents of eax, ebx, ecx and edx)
 414   void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
 415 
 416   // Long shifts for Java
 417   // (semantics as described in JVM spec.)
 418   void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
 419   void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
 420 
 421   // Long compare for Java
 422   // (semantics as described in JVM spec.)
 423   void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
 424 
 425 
 426   // misc
 427 
 428   // Sign extension
 429   void sign_extend_short(Register reg);
 430   void sign_extend_byte(Register reg);
 431 
 432   // Division by power of 2, rounding towards 0
 433   void division_with_shift(Register reg, int shift_value);
 434 
 435   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
 436   //
 437   // CF (corresponds to C0) if x < y
 438   // PF (corresponds to C2) if unordered
 439   // ZF (corresponds to C3) if x = y
 440   //
 441   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 442   // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
 443   void fcmp(Register tmp);
 444   // Variant of the above which allows y to be further down the stack
 445   // and which only pops x and y if specified. If pop_right is
 446   // specified then pop_left must also be specified.
 447   void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
 448 
 449   // Floating-point comparison for Java
 450   // Compares the top-most stack entries on the FPU stack and stores the result in dst.
 451   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 452   // (semantics as described in JVM spec.)
 453   void fcmp2int(Register dst, bool unordered_is_less);
 454   // Variant of the above which allows y to be further down the stack
 455   // and which only pops x and y if specified. If pop_right is
 456   // specified then pop_left must also be specified.
 457   void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
 458 
 459   // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
 460   // tmp is a temporary register, if none is available use noreg
 461   void fremr(Register tmp);
 462 
 463   // dst = c = a * b + c
 464   void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 465   void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 466 
 467   void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 468   void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 469   void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 470   void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 471 
 472 
 473   // same as fcmp2int, but using SSE2
 474   void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 475   void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 476 
 477   // branch to L if FPU flag C2 is set/not set
 478   // tmp is a temporary register, if none is available use noreg
 479   void jC2 (Register tmp, Label& L);
 480   void jnC2(Register tmp, Label& L);
 481 
 482   // Pop ST (ffree & fincstp combined)
 483   void fpop();
 484 
 485   // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
 486   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 487   void load_float(Address src);
 488 
 489   // Store float value to 'address'. If UseSSE >= 1, the value is stored
 490   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 491   void store_float(Address dst);
 492 
 493   // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
 494   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 495   void load_double(Address src);
 496 
 497   // Store double value to 'address'. If UseSSE >= 2, the value is stored
 498   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 499   void store_double(Address dst);
 500 
 501   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
 502   void push_fTOS();
 503 
 504   // pops double TOS element from CPU stack and pushes on FPU stack
 505   void pop_fTOS();
 506 
 507   void empty_FPU_stack();
 508 
 509   void push_IU_state();
 510   void pop_IU_state();
 511 
 512   void push_FPU_state();
 513   void pop_FPU_state();
 514 
 515   void push_CPU_state();
 516   void pop_CPU_state();
 517 
 518   // Round up to a power of two
 519   void round_to(Register reg, int modulus);
 520 
 521   // Callee saved registers handling
 522   void push_callee_saved_registers();
 523   void pop_callee_saved_registers();
 524 
 525   // allocation
 526   void eden_allocate(
 527     Register thread,                   // Current thread
 528     Register obj,                      // result: pointer to object after successful allocation
 529     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 530     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 531     Register t1,                       // temp register
 532     Label&   slow_case                 // continuation point if fast allocation fails
 533   );
 534   void tlab_allocate(
 535     Register thread,                   // Current thread
 536     Register obj,                      // result: pointer to object after successful allocation
 537     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 538     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 539     Register t1,                       // temp register
 540     Register t2,                       // temp register
 541     Label&   slow_case                 // continuation point if fast allocation fails
 542   );
 543   void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
 544 
 545   // interface method calling
 546   void lookup_interface_method(Register recv_klass,
 547                                Register intf_klass,
 548                                RegisterOrConstant itable_index,
 549                                Register method_result,
 550                                Register scan_temp,
 551                                Label& no_such_interface,
 552                                bool return_method = true);
 553 
 554   // virtual method calling
 555   void lookup_virtual_method(Register recv_klass,
 556                              RegisterOrConstant vtable_index,
 557                              Register method_result);
 558 
 559   // Test sub_klass against super_klass, with fast and slow paths.
 560 
 561   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 562   // One of the three labels can be NULL, meaning take the fall-through.
 563   // If super_check_offset is -1, the value is loaded up from super_klass.
 564   // No registers are killed, except temp_reg.
 565   void check_klass_subtype_fast_path(Register sub_klass,
 566                                      Register super_klass,
 567                                      Register temp_reg,
 568                                      Label* L_success,
 569                                      Label* L_failure,
 570                                      Label* L_slow_path,
 571                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 572 
 573   // The rest of the type check; must be wired to a corresponding fast path.
 574   // It does not repeat the fast path logic, so don't use it standalone.
 575   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 576   // Updates the sub's secondary super cache as necessary.
 577   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 578   void check_klass_subtype_slow_path(Register sub_klass,
 579                                      Register super_klass,
 580                                      Register temp_reg,
 581                                      Register temp2_reg,
 582                                      Label* L_success,
 583                                      Label* L_failure,
 584                                      bool set_cond_codes = false);
 585 
 586   // Simplified, combined version, good for typical uses.
 587   // Falls through on failure.
 588   void check_klass_subtype(Register sub_klass,
 589                            Register super_klass,
 590                            Register temp_reg,
 591                            Label& L_success);
 592 
 593   // method handles (JSR 292)
 594   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 595 
 596   //----
 597   void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
 598 
 599   // Debugging
 600 
 601   // only if +VerifyOops
 602   // TODO: Make these macros with file and line like sparc version!
 603   void verify_oop(Register reg, const char* s = "broken oop");
 604   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 605 
 606   // TODO: verify method and klass metadata (compare against vptr?)
 607   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 608   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 609 
 610 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 611 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 612 
 613   // only if +VerifyFPU
 614   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 615 
 616   // Verify or restore cpu control state after JNI call
 617   void restore_cpu_control_state_after_jni();
 618 
 619   // prints msg, dumps registers and stops execution
 620   void stop(const char* msg);
 621 
 622   // prints msg and continues
 623   void warn(const char* msg);
 624 
 625   // dumps registers and other state
 626   void print_state();
 627 
 628   static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
 629   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 630   static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
 631   static void print_state64(int64_t pc, int64_t regs[]);
 632 
 633   void os_breakpoint();
 634 
 635   void untested()                                { stop("untested"); }
 636 
 637   void unimplemented(const char* what = "");
 638 
 639   void should_not_reach_here()                   { stop("should not reach here"); }
 640 
 641   void print_CPU_state();
 642 
 643   // Stack overflow checking
 644   void bang_stack_with_offset(int offset) {
 645     // stack grows down, caller passes positive offset
 646     assert(offset > 0, "must bang with negative offset");
 647     movl(Address(rsp, (-offset)), rax);
 648   }
 649 
 650   // Writes to stack successive pages until offset reached to check for
 651   // stack overflow + shadow pages.  Also, clobbers tmp
 652   void bang_stack_size(Register size, Register tmp);
 653 
 654   // Check for reserved stack access in method being exited (for JIT)
 655   void reserved_stack_check();
 656 
 657   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 658                                                 Register tmp,
 659                                                 int offset);
 660 
 661   // If thread_reg is != noreg the code assumes the register passed contains
 662   // the thread (required on 64 bit).
 663   void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
 664 
 665   void verify_tlab();
 666 
 667   // Biased locking support
 668   // lock_reg and obj_reg must be loaded up with the appropriate values.
 669   // swap_reg must be rax, and is killed.
 670   // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
 671   // be killed; if not supplied, push/pop will be used internally to
 672   // allocate a temporary (inefficient, avoid if possible).
 673   // Optional slow case is for implementations (interpreter and C1) which branch to
 674   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 675   // Returns offset of first potentially-faulting instruction for null
 676   // check info (currently consumed only by C1). If
 677   // swap_reg_contains_mark is true then returns -1 as it is assumed
 678   // the calling code has already passed any potential faults.
 679   int biased_locking_enter(Register lock_reg, Register obj_reg,
 680                            Register swap_reg, Register tmp_reg,
 681                            bool swap_reg_contains_mark,
 682                            Label& done, Label* slow_case = NULL,
 683                            BiasedLockingCounters* counters = NULL);
 684   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 685 #ifdef COMPILER2
 686   // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
 687   // See full desription in macroAssembler_x86.cpp.
 688   void fast_lock(Register obj, Register box, Register tmp,
 689                  Register scr, Register cx1, Register cx2,
 690                  BiasedLockingCounters* counters,
 691                  RTMLockingCounters* rtm_counters,
 692                  RTMLockingCounters* stack_rtm_counters,
 693                  Metadata* method_data,
 694                  bool use_rtm, bool profile_rtm);
 695   void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
 696 #if INCLUDE_RTM_OPT
 697   void rtm_counters_update(Register abort_status, Register rtm_counters);
 698   void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
 699   void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
 700                                    RTMLockingCounters* rtm_counters,
 701                                    Metadata* method_data);
 702   void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
 703                      RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
 704   void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
 705   void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
 706   void rtm_stack_locking(Register obj, Register tmp, Register scr,
 707                          Register retry_on_abort_count,
 708                          RTMLockingCounters* stack_rtm_counters,
 709                          Metadata* method_data, bool profile_rtm,
 710                          Label& DONE_LABEL, Label& IsInflated);
 711   void rtm_inflated_locking(Register obj, Register box, Register tmp,
 712                             Register scr, Register retry_on_busy_count,
 713                             Register retry_on_abort_count,
 714                             RTMLockingCounters* rtm_counters,
 715                             Metadata* method_data, bool profile_rtm,
 716                             Label& DONE_LABEL);
 717 #endif
 718 #endif
 719 
 720   Condition negate_condition(Condition cond);
 721 
 722   // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
 723   // operands. In general the names are modified to avoid hiding the instruction in Assembler
 724   // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
 725   // here in MacroAssembler. The major exception to this rule is call
 726 
 727   // Arithmetics
 728 
 729 
 730   void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
 731   void addptr(Address dst, Register src);
 732 
 733   void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
 734   void addptr(Register dst, int32_t src);
 735   void addptr(Register dst, Register src);
 736   void addptr(Register dst, RegisterOrConstant src) {
 737     if (src.is_constant()) addptr(dst, (int) src.as_constant());
 738     else                   addptr(dst,       src.as_register());
 739   }
 740 
 741   void andptr(Register dst, int32_t src);
 742   void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
 743 
 744   void cmp8(AddressLiteral src1, int imm);
 745 
 746   // renamed to drag out the casting of address to int32_t/intptr_t
 747   void cmp32(Register src1, int32_t imm);
 748 
 749   void cmp32(AddressLiteral src1, int32_t imm);
 750   // compare reg - mem, or reg - &mem
 751   void cmp32(Register src1, AddressLiteral src2);
 752 
 753   void cmp32(Register src1, Address src2);
 754 
 755 #ifndef _LP64
 756   void cmpklass(Address dst, Metadata* obj);
 757   void cmpklass(Register dst, Metadata* obj);
 758   void cmpoop(Address dst, jobject obj);
 759   void cmpoop_raw(Address dst, jobject obj);
 760 #endif // _LP64
 761 
 762   void cmpoop(Register src1, Register src2);
 763   void cmpoop(Register src1, Address src2);
 764   void cmpoop(Register dst, jobject obj);
 765   void cmpoop_raw(Register dst, jobject obj);
 766 
 767   // NOTE src2 must be the lval. This is NOT an mem-mem compare
 768   void cmpptr(Address src1, AddressLiteral src2);
 769 
 770   void cmpptr(Register src1, AddressLiteral src2);
 771 
 772   void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 773   void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 774   // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 775 
 776   void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 777   void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 778 
 779   // cmp64 to avoild hiding cmpq
 780   void cmp64(Register src1, AddressLiteral src);
 781 
 782   void cmpxchgptr(Register reg, Address adr);
 783 
 784   void locked_cmpxchgptr(Register reg, AddressLiteral adr);
 785 
 786 
 787   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
 788   void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
 789 
 790 
 791   void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
 792 
 793   void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
 794 
 795   void shlptr(Register dst, int32_t shift);
 796   void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
 797 
 798   void shrptr(Register dst, int32_t shift);
 799   void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
 800 
 801   void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
 802   void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
 803 
 804   void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 805 
 806   void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 807   void subptr(Register dst, int32_t src);
 808   // Force generation of a 4 byte immediate value even if it fits into 8bit
 809   void subptr_imm32(Register dst, int32_t src);
 810   void subptr(Register dst, Register src);
 811   void subptr(Register dst, RegisterOrConstant src) {
 812     if (src.is_constant()) subptr(dst, (int) src.as_constant());
 813     else                   subptr(dst,       src.as_register());
 814   }
 815 
 816   void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 817   void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 818 
 819   void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 820   void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 821 
 822   void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
 823 
 824 
 825 
 826   // Helper functions for statistics gathering.
 827   // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
 828   void cond_inc32(Condition cond, AddressLiteral counter_addr);
 829   // Unconditional atomic increment.
 830   void atomic_incl(Address counter_addr);
 831   void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
 832 #ifdef _LP64
 833   void atomic_incq(Address counter_addr);
 834   void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
 835 #endif
 836   void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
 837   void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
 838 
 839   void lea(Register dst, AddressLiteral adr);
 840   void lea(Address dst, AddressLiteral adr);
 841   void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
 842 
 843   void leal32(Register dst, Address src) { leal(dst, src); }
 844 
 845   // Import other testl() methods from the parent class or else
 846   // they will be hidden by the following overriding declaration.
 847   using Assembler::testl;
 848   void testl(Register dst, AddressLiteral src);
 849 
 850   void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 851   void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 852   void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 853   void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
 854 
 855   void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
 856   void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
 857   void testptr(Register src1, Register src2);
 858 
 859   void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 860   void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 861 
 862   // Calls
 863 
 864   void call(Label& L, relocInfo::relocType rtype);
 865   void call(Register entry);
 866 
 867   // NOTE: this call transfers to the effective address of entry NOT
 868   // the address contained by entry. This is because this is more natural
 869   // for jumps/calls.
 870   void call(AddressLiteral entry);
 871 
 872   // Emit the CompiledIC call idiom
 873   void ic_call(address entry, jint method_index = 0);
 874 
 875   // Jumps
 876 
 877   // NOTE: these jumps tranfer to the effective address of dst NOT
 878   // the address contained by dst. This is because this is more natural
 879   // for jumps/calls.
 880   void jump(AddressLiteral dst);
 881   void jump_cc(Condition cc, AddressLiteral dst);
 882 
 883   // 32bit can do a case table jump in one instruction but we no longer allow the base
 884   // to be installed in the Address class. This jump will tranfers to the address
 885   // contained in the location described by entry (not the address of entry)
 886   void jump(ArrayAddress entry);
 887 
 888   // Floating
 889 
 890   void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
 891   void andpd(XMMRegister dst, AddressLiteral src);
 892   void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
 893 
 894   void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
 895   void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
 896   void andps(XMMRegister dst, AddressLiteral src);
 897 
 898   void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
 899   void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
 900   void comiss(XMMRegister dst, AddressLiteral src);
 901 
 902   void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
 903   void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
 904   void comisd(XMMRegister dst, AddressLiteral src);
 905 
 906   void fadd_s(Address src)        { Assembler::fadd_s(src); }
 907   void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
 908 
 909   void fldcw(Address src) { Assembler::fldcw(src); }
 910   void fldcw(AddressLiteral src);
 911 
 912   void fld_s(int index)   { Assembler::fld_s(index); }
 913   void fld_s(Address src) { Assembler::fld_s(src); }
 914   void fld_s(AddressLiteral src);
 915 
 916   void fld_d(Address src) { Assembler::fld_d(src); }
 917   void fld_d(AddressLiteral src);
 918 
 919   void fld_x(Address src) { Assembler::fld_x(src); }
 920   void fld_x(AddressLiteral src);
 921 
 922   void fmul_s(Address src)        { Assembler::fmul_s(src); }
 923   void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
 924 
 925   void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
 926   void ldmxcsr(AddressLiteral src);
 927 
 928 #ifdef _LP64
 929  private:
 930   void sha256_AVX2_one_round_compute(
 931     Register  reg_old_h,
 932     Register  reg_a,
 933     Register  reg_b,
 934     Register  reg_c,
 935     Register  reg_d,
 936     Register  reg_e,
 937     Register  reg_f,
 938     Register  reg_g,
 939     Register  reg_h,
 940     int iter);
 941   void sha256_AVX2_four_rounds_compute_first(int start);
 942   void sha256_AVX2_four_rounds_compute_last(int start);
 943   void sha256_AVX2_one_round_and_sched(
 944         XMMRegister xmm_0,     /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
 945         XMMRegister xmm_1,     /* ymm5 */  /* full cycle is 16 iterations */
 946         XMMRegister xmm_2,     /* ymm6 */
 947         XMMRegister xmm_3,     /* ymm7 */
 948         Register    reg_a,      /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
 949         Register    reg_b,      /* ebx */    /* full cycle is 8 iterations */
 950         Register    reg_c,      /* edi */
 951         Register    reg_d,      /* esi */
 952         Register    reg_e,      /* r8d */
 953         Register    reg_f,      /* r9d */
 954         Register    reg_g,      /* r10d */
 955         Register    reg_h,      /* r11d */
 956         int iter);
 957 
 958   void addm(int disp, Register r1, Register r2);
 959   void gfmul(XMMRegister tmp0, XMMRegister t);
 960   void schoolbookAAD(int i, Register subkeyH, XMMRegister data, XMMRegister tmp0,
 961                      XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3);
 962   void generateHtbl_one_block(Register htbl);
 963   void generateHtbl_eight_blocks(Register htbl);
 964  public:
 965   void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 966                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 967                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 968                    bool multi_block, XMMRegister shuf_mask);
 969   void avx_ghash(Register state, Register htbl, Register data, Register blocks);
 970 #endif
 971 
 972 #ifdef _LP64
 973  private:
 974   void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
 975                                      Register e, Register f, Register g, Register h, int iteration);
 976 
 977   void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 978                                           Register a, Register b, Register c, Register d, Register e, Register f,
 979                                           Register g, Register h, int iteration);
 980 
 981   void addmq(int disp, Register r1, Register r2);
 982  public:
 983   void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 984                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 985                    Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
 986                    XMMRegister shuf_mask);
 987 #endif
 988 
 989   void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
 990                  XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
 991                  Register buf, Register state, Register ofs, Register limit, Register rsp,
 992                  bool multi_block);
 993 
 994 #ifdef _LP64
 995   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 996                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 997                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 998                    bool multi_block, XMMRegister shuf_mask);
 999 #else
1000   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1001                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1002                    Register buf, Register state, Register ofs, Register limit, Register rsp,
1003                    bool multi_block);
1004 #endif
1005 
1006   void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1007                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1008                 Register rax, Register rcx, Register rdx, Register tmp);
1009 
1010 #ifdef _LP64
1011   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1012                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1013                 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
1014 
1015   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1016                   XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1017                   Register rax, Register rcx, Register rdx, Register r11);
1018 
1019   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1020                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1021                 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1022 
1023   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1024                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1025                 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1026                 Register tmp3, Register tmp4);
1027 
1028   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1029                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1030                 Register rax, Register rcx, Register rdx, Register tmp1,
1031                 Register tmp2, Register tmp3, Register tmp4);
1032   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1033                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1034                 Register rax, Register rcx, Register rdx, Register tmp1,
1035                 Register tmp2, Register tmp3, Register tmp4);
1036 #else
1037   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1038                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1039                 Register rax, Register rcx, Register rdx, Register tmp1);
1040 
1041   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1042                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1043                 Register rax, Register rcx, Register rdx, Register tmp);
1044 
1045   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1046                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1047                 Register rdx, Register tmp);
1048 
1049   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1050                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1051                 Register rax, Register rbx, Register rdx);
1052 
1053   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1054                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1055                 Register rax, Register rcx, Register rdx, Register tmp);
1056 
1057   void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1058                         Register edx, Register ebx, Register esi, Register edi,
1059                         Register ebp, Register esp);
1060 
1061   void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1062                          Register esi, Register edi, Register ebp, Register esp);
1063 
1064   void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1065                         Register edx, Register ebx, Register esi, Register edi,
1066                         Register ebp, Register esp);
1067 
1068   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1069                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1070                 Register rax, Register rcx, Register rdx, Register tmp);
1071 #endif
1072 
1073   void increase_precision();
1074   void restore_precision();
1075 
1076 private:
1077 
1078   // these are private because users should be doing movflt/movdbl
1079 
1080   void movss(Address dst, XMMRegister src)     { Assembler::movss(dst, src); }
1081   void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1082   void movss(XMMRegister dst, Address src)     { Assembler::movss(dst, src); }
1083   void movss(XMMRegister dst, AddressLiteral src);
1084 
1085   void movlpd(XMMRegister dst, Address src)    {Assembler::movlpd(dst, src); }
1086   void movlpd(XMMRegister dst, AddressLiteral src);
1087 
1088 public:
1089 
1090   void addsd(XMMRegister dst, XMMRegister src)    { Assembler::addsd(dst, src); }
1091   void addsd(XMMRegister dst, Address src)        { Assembler::addsd(dst, src); }
1092   void addsd(XMMRegister dst, AddressLiteral src);
1093 
1094   void addss(XMMRegister dst, XMMRegister src)    { Assembler::addss(dst, src); }
1095   void addss(XMMRegister dst, Address src)        { Assembler::addss(dst, src); }
1096   void addss(XMMRegister dst, AddressLiteral src);
1097 
1098   void addpd(XMMRegister dst, XMMRegister src)    { Assembler::addpd(dst, src); }
1099   void addpd(XMMRegister dst, Address src)        { Assembler::addpd(dst, src); }
1100   void addpd(XMMRegister dst, AddressLiteral src);
1101 
1102   void divsd(XMMRegister dst, XMMRegister src)    { Assembler::divsd(dst, src); }
1103   void divsd(XMMRegister dst, Address src)        { Assembler::divsd(dst, src); }
1104   void divsd(XMMRegister dst, AddressLiteral src);
1105 
1106   void divss(XMMRegister dst, XMMRegister src)    { Assembler::divss(dst, src); }
1107   void divss(XMMRegister dst, Address src)        { Assembler::divss(dst, src); }
1108   void divss(XMMRegister dst, AddressLiteral src);
1109 
1110   // Move Unaligned Double Quadword
1111   void movdqu(Address     dst, XMMRegister src);
1112   void movdqu(XMMRegister dst, Address src);
1113   void movdqu(XMMRegister dst, XMMRegister src);
1114   void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1115   // AVX Unaligned forms
1116   void vmovdqu(Address     dst, XMMRegister src);
1117   void vmovdqu(XMMRegister dst, Address src);
1118   void vmovdqu(XMMRegister dst, XMMRegister src);
1119   void vmovdqu(XMMRegister dst, AddressLiteral src);
1120   void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1121   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1122   void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1123   void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1124 
1125   // Move Aligned Double Quadword
1126   void movdqa(XMMRegister dst, Address src)       { Assembler::movdqa(dst, src); }
1127   void movdqa(XMMRegister dst, XMMRegister src)   { Assembler::movdqa(dst, src); }
1128   void movdqa(XMMRegister dst, AddressLiteral src);
1129 
1130   void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1131   void movsd(Address dst, XMMRegister src)     { Assembler::movsd(dst, src); }
1132   void movsd(XMMRegister dst, Address src)     { Assembler::movsd(dst, src); }
1133   void movsd(XMMRegister dst, AddressLiteral src);
1134 
1135   void mulpd(XMMRegister dst, XMMRegister src)    { Assembler::mulpd(dst, src); }
1136   void mulpd(XMMRegister dst, Address src)        { Assembler::mulpd(dst, src); }
1137   void mulpd(XMMRegister dst, AddressLiteral src);
1138 
1139   void mulsd(XMMRegister dst, XMMRegister src)    { Assembler::mulsd(dst, src); }
1140   void mulsd(XMMRegister dst, Address src)        { Assembler::mulsd(dst, src); }
1141   void mulsd(XMMRegister dst, AddressLiteral src);
1142 
1143   void mulss(XMMRegister dst, XMMRegister src)    { Assembler::mulss(dst, src); }
1144   void mulss(XMMRegister dst, Address src)        { Assembler::mulss(dst, src); }
1145   void mulss(XMMRegister dst, AddressLiteral src);
1146 
1147   // Carry-Less Multiplication Quadword
1148   void pclmulldq(XMMRegister dst, XMMRegister src) {
1149     // 0x00 - multiply lower 64 bits [0:63]
1150     Assembler::pclmulqdq(dst, src, 0x00);
1151   }
1152   void pclmulhdq(XMMRegister dst, XMMRegister src) {
1153     // 0x11 - multiply upper 64 bits [64:127]
1154     Assembler::pclmulqdq(dst, src, 0x11);
1155   }
1156 
1157   void pcmpeqb(XMMRegister dst, XMMRegister src);
1158   void pcmpeqw(XMMRegister dst, XMMRegister src);
1159 
1160   void pcmpestri(XMMRegister dst, Address src, int imm8);
1161   void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1162 
1163   void pmovzxbw(XMMRegister dst, XMMRegister src);
1164   void pmovzxbw(XMMRegister dst, Address src);
1165 
1166   void pmovmskb(Register dst, XMMRegister src);
1167 
1168   void ptest(XMMRegister dst, XMMRegister src);
1169 
1170   void sqrtsd(XMMRegister dst, XMMRegister src)    { Assembler::sqrtsd(dst, src); }
1171   void sqrtsd(XMMRegister dst, Address src)        { Assembler::sqrtsd(dst, src); }
1172   void sqrtsd(XMMRegister dst, AddressLiteral src);
1173 
1174   void sqrtss(XMMRegister dst, XMMRegister src)    { Assembler::sqrtss(dst, src); }
1175   void sqrtss(XMMRegister dst, Address src)        { Assembler::sqrtss(dst, src); }
1176   void sqrtss(XMMRegister dst, AddressLiteral src);
1177 
1178   void subsd(XMMRegister dst, XMMRegister src)    { Assembler::subsd(dst, src); }
1179   void subsd(XMMRegister dst, Address src)        { Assembler::subsd(dst, src); }
1180   void subsd(XMMRegister dst, AddressLiteral src);
1181 
1182   void subss(XMMRegister dst, XMMRegister src)    { Assembler::subss(dst, src); }
1183   void subss(XMMRegister dst, Address src)        { Assembler::subss(dst, src); }
1184   void subss(XMMRegister dst, AddressLiteral src);
1185 
1186   void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1187   void ucomiss(XMMRegister dst, Address src)     { Assembler::ucomiss(dst, src); }
1188   void ucomiss(XMMRegister dst, AddressLiteral src);
1189 
1190   void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1191   void ucomisd(XMMRegister dst, Address src)     { Assembler::ucomisd(dst, src); }
1192   void ucomisd(XMMRegister dst, AddressLiteral src);
1193 
1194   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1195   void xorpd(XMMRegister dst, XMMRegister src);
1196   void xorpd(XMMRegister dst, Address src)     { Assembler::xorpd(dst, src); }
1197   void xorpd(XMMRegister dst, AddressLiteral src);
1198 
1199   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1200   void xorps(XMMRegister dst, XMMRegister src);
1201   void xorps(XMMRegister dst, Address src)     { Assembler::xorps(dst, src); }
1202   void xorps(XMMRegister dst, AddressLiteral src);
1203 
1204   // Shuffle Bytes
1205   void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1206   void pshufb(XMMRegister dst, Address src)     { Assembler::pshufb(dst, src); }
1207   void pshufb(XMMRegister dst, AddressLiteral src);
1208   // AVX 3-operands instructions
1209 
1210   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1211   void vaddsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddsd(dst, nds, src); }
1212   void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1213 
1214   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1215   void vaddss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddss(dst, nds, src); }
1216   void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1217 
1218   void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1219   void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1220 
1221   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1222   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1223 
1224   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1225   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1226 
1227   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1228   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1229   void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1230 
1231   void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1232   void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); }
1233 
1234   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1235 
1236   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1237 
1238   void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1239   void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1240 
1241   void vpmovmskb(Register dst, XMMRegister src);
1242 
1243   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1244   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1245 
1246   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1247   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1248 
1249   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1250   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1251 
1252   void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1253   void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1254 
1255   void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1256   void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1257 
1258   void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1259   void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1260 
1261   void vptest(XMMRegister dst, XMMRegister src);
1262 
1263   void punpcklbw(XMMRegister dst, XMMRegister src);
1264   void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1265 
1266   void pshufd(XMMRegister dst, Address src, int mode);
1267   void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1268 
1269   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1270   void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1271 
1272   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1273   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandpd(dst, nds, src, vector_len); }
1274   void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1275 
1276   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1277   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandps(dst, nds, src, vector_len); }
1278   void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1279 
1280   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1281   void vdivsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivsd(dst, nds, src); }
1282   void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1283 
1284   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1285   void vdivss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivss(dst, nds, src); }
1286   void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1287 
1288   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1289   void vmulsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulsd(dst, nds, src); }
1290   void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1291 
1292   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1293   void vmulss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulss(dst, nds, src); }
1294   void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1295 
1296   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1297   void vsubsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubsd(dst, nds, src); }
1298   void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1299 
1300   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1301   void vsubss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubss(dst, nds, src); }
1302   void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1303 
1304   void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1305   void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1306 
1307   // AVX Vector instructions
1308 
1309   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1310   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1311   void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1312 
1313   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1314   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1315   void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1316 
1317   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1318     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1319       Assembler::vpxor(dst, nds, src, vector_len);
1320     else
1321       Assembler::vxorpd(dst, nds, src, vector_len);
1322   }
1323   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1324     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1325       Assembler::vpxor(dst, nds, src, vector_len);
1326     else
1327       Assembler::vxorpd(dst, nds, src, vector_len);
1328   }
1329 
1330   // Simple version for AVX2 256bit vectors
1331   void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1332   void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1333 
1334   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1335     if (UseAVX > 2) {
1336       Assembler::vinserti32x4(dst, dst, src, imm8);
1337     } else if (UseAVX > 1) {
1338       // vinserti128 is available only in AVX2
1339       Assembler::vinserti128(dst, nds, src, imm8);
1340     } else {
1341       Assembler::vinsertf128(dst, nds, src, imm8);
1342     }
1343   }
1344 
1345   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1346     if (UseAVX > 2) {
1347       Assembler::vinserti32x4(dst, dst, src, imm8);
1348     } else if (UseAVX > 1) {
1349       // vinserti128 is available only in AVX2
1350       Assembler::vinserti128(dst, nds, src, imm8);
1351     } else {
1352       Assembler::vinsertf128(dst, nds, src, imm8);
1353     }
1354   }
1355 
1356   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1357     if (UseAVX > 2) {
1358       Assembler::vextracti32x4(dst, src, imm8);
1359     } else if (UseAVX > 1) {
1360       // vextracti128 is available only in AVX2
1361       Assembler::vextracti128(dst, src, imm8);
1362     } else {
1363       Assembler::vextractf128(dst, src, imm8);
1364     }
1365   }
1366 
1367   void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1368     if (UseAVX > 2) {
1369       Assembler::vextracti32x4(dst, src, imm8);
1370     } else if (UseAVX > 1) {
1371       // vextracti128 is available only in AVX2
1372       Assembler::vextracti128(dst, src, imm8);
1373     } else {
1374       Assembler::vextractf128(dst, src, imm8);
1375     }
1376   }
1377 
1378   // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1379   void vinserti128_high(XMMRegister dst, XMMRegister src) {
1380     vinserti128(dst, dst, src, 1);
1381   }
1382   void vinserti128_high(XMMRegister dst, Address src) {
1383     vinserti128(dst, dst, src, 1);
1384   }
1385   void vextracti128_high(XMMRegister dst, XMMRegister src) {
1386     vextracti128(dst, src, 1);
1387   }
1388   void vextracti128_high(Address dst, XMMRegister src) {
1389     vextracti128(dst, src, 1);
1390   }
1391 
1392   void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1393     if (UseAVX > 2) {
1394       Assembler::vinsertf32x4(dst, dst, src, 1);
1395     } else {
1396       Assembler::vinsertf128(dst, dst, src, 1);
1397     }
1398   }
1399 
1400   void vinsertf128_high(XMMRegister dst, Address src) {
1401     if (UseAVX > 2) {
1402       Assembler::vinsertf32x4(dst, dst, src, 1);
1403     } else {
1404       Assembler::vinsertf128(dst, dst, src, 1);
1405     }
1406   }
1407 
1408   void vextractf128_high(XMMRegister dst, XMMRegister src) {
1409     if (UseAVX > 2) {
1410       Assembler::vextractf32x4(dst, src, 1);
1411     } else {
1412       Assembler::vextractf128(dst, src, 1);
1413     }
1414   }
1415 
1416   void vextractf128_high(Address dst, XMMRegister src) {
1417     if (UseAVX > 2) {
1418       Assembler::vextractf32x4(dst, src, 1);
1419     } else {
1420       Assembler::vextractf128(dst, src, 1);
1421     }
1422   }
1423 
1424   // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1425   void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1426     Assembler::vinserti64x4(dst, dst, src, 1);
1427   }
1428   void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1429     Assembler::vinsertf64x4(dst, dst, src, 1);
1430   }
1431   void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1432     Assembler::vextracti64x4(dst, src, 1);
1433   }
1434   void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1435     Assembler::vextractf64x4(dst, src, 1);
1436   }
1437   void vextractf64x4_high(Address dst, XMMRegister src) {
1438     Assembler::vextractf64x4(dst, src, 1);
1439   }
1440   void vinsertf64x4_high(XMMRegister dst, Address src) {
1441     Assembler::vinsertf64x4(dst, dst, src, 1);
1442   }
1443 
1444   // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1445   void vinserti128_low(XMMRegister dst, XMMRegister src) {
1446     vinserti128(dst, dst, src, 0);
1447   }
1448   void vinserti128_low(XMMRegister dst, Address src) {
1449     vinserti128(dst, dst, src, 0);
1450   }
1451   void vextracti128_low(XMMRegister dst, XMMRegister src) {
1452     vextracti128(dst, src, 0);
1453   }
1454   void vextracti128_low(Address dst, XMMRegister src) {
1455     vextracti128(dst, src, 0);
1456   }
1457 
1458   void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1459     if (UseAVX > 2) {
1460       Assembler::vinsertf32x4(dst, dst, src, 0);
1461     } else {
1462       Assembler::vinsertf128(dst, dst, src, 0);
1463     }
1464   }
1465 
1466   void vinsertf128_low(XMMRegister dst, Address src) {
1467     if (UseAVX > 2) {
1468       Assembler::vinsertf32x4(dst, dst, src, 0);
1469     } else {
1470       Assembler::vinsertf128(dst, dst, src, 0);
1471     }
1472   }
1473 
1474   void vextractf128_low(XMMRegister dst, XMMRegister src) {
1475     if (UseAVX > 2) {
1476       Assembler::vextractf32x4(dst, src, 0);
1477     } else {
1478       Assembler::vextractf128(dst, src, 0);
1479     }
1480   }
1481 
1482   void vextractf128_low(Address dst, XMMRegister src) {
1483     if (UseAVX > 2) {
1484       Assembler::vextractf32x4(dst, src, 0);
1485     } else {
1486       Assembler::vextractf128(dst, src, 0);
1487     }
1488   }
1489 
1490   // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1491   void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1492     Assembler::vinserti64x4(dst, dst, src, 0);
1493   }
1494   void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1495     Assembler::vinsertf64x4(dst, dst, src, 0);
1496   }
1497   void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1498     Assembler::vextracti64x4(dst, src, 0);
1499   }
1500   void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1501     Assembler::vextractf64x4(dst, src, 0);
1502   }
1503   void vextractf64x4_low(Address dst, XMMRegister src) {
1504     Assembler::vextractf64x4(dst, src, 0);
1505   }
1506   void vinsertf64x4_low(XMMRegister dst, Address src) {
1507     Assembler::vinsertf64x4(dst, dst, src, 0);
1508   }
1509 
1510   // Carry-Less Multiplication Quadword
1511   void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1512     // 0x00 - multiply lower 64 bits [0:63]
1513     Assembler::vpclmulqdq(dst, nds, src, 0x00);
1514   }
1515   void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1516     // 0x11 - multiply upper 64 bits [64:127]
1517     Assembler::vpclmulqdq(dst, nds, src, 0x11);
1518   }
1519   void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1520     // 0x10 - multiply nds[0:63] and src[64:127]
1521     Assembler::vpclmulqdq(dst, nds, src, 0x10);
1522   }
1523   void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1524     //0x01 - multiply nds[64:127] and src[0:63]
1525     Assembler::vpclmulqdq(dst, nds, src, 0x01);
1526   }
1527 
1528   void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1529     // 0x00 - multiply lower 64 bits [0:63]
1530     Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1531   }
1532   void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1533     // 0x11 - multiply upper 64 bits [64:127]
1534     Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1535   }
1536 
1537   // Data
1538 
1539   void cmov32( Condition cc, Register dst, Address  src);
1540   void cmov32( Condition cc, Register dst, Register src);
1541 
1542   void cmov(   Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1543 
1544   void cmovptr(Condition cc, Register dst, Address  src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1545   void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1546 
1547   void movoop(Register dst, jobject obj);
1548   void movoop(Address dst, jobject obj);
1549 
1550   void mov_metadata(Register dst, Metadata* obj);
1551   void mov_metadata(Address dst, Metadata* obj);
1552 
1553   void movptr(ArrayAddress dst, Register src);
1554   // can this do an lea?
1555   void movptr(Register dst, ArrayAddress src);
1556 
1557   void movptr(Register dst, Address src);
1558 
1559 #ifdef _LP64
1560   void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1561 #else
1562   void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1563 #endif
1564 
1565   void movptr(Register dst, intptr_t src);
1566   void movptr(Register dst, Register src);
1567   void movptr(Address dst, intptr_t src);
1568 
1569   void movptr(Address dst, Register src);
1570 
1571   void movptr(Register dst, RegisterOrConstant src) {
1572     if (src.is_constant()) movptr(dst, src.as_constant());
1573     else                   movptr(dst, src.as_register());
1574   }
1575 
1576 #ifdef _LP64
1577   // Generally the next two are only used for moving NULL
1578   // Although there are situations in initializing the mark word where
1579   // they could be used. They are dangerous.
1580 
1581   // They only exist on LP64 so that int32_t and intptr_t are not the same
1582   // and we have ambiguous declarations.
1583 
1584   void movptr(Address dst, int32_t imm32);
1585   void movptr(Register dst, int32_t imm32);
1586 #endif // _LP64
1587 
1588   // to avoid hiding movl
1589   void mov32(AddressLiteral dst, Register src);
1590   void mov32(Register dst, AddressLiteral src);
1591 
1592   // to avoid hiding movb
1593   void movbyte(ArrayAddress dst, int src);
1594 
1595   // Import other mov() methods from the parent class or else
1596   // they will be hidden by the following overriding declaration.
1597   using Assembler::movdl;
1598   using Assembler::movq;
1599   void movdl(XMMRegister dst, AddressLiteral src);
1600   void movq(XMMRegister dst, AddressLiteral src);
1601 
1602   // Can push value or effective address
1603   void pushptr(AddressLiteral src);
1604 
1605   void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1606   void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1607 
1608   void pushoop(jobject obj);
1609   void pushklass(Metadata* obj);
1610 
1611   // sign extend as need a l to ptr sized element
1612   void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1613   void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1614 
1615   // C2 compiled method's prolog code.
1616   void verified_entry(Compile* C, int sp_inc = 0);
1617 
1618   enum RegState {
1619     reg_readonly,
1620     reg_writable,
1621     reg_written
1622   };
1623 
1624   // Unpack all value type arguments passed as oops
1625   void unpack_value_args(Compile* C, bool receiver_only);
1626   bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[], int ret_off);
1627   bool unpack_value_helper(const GrowableArray<SigEntry>* sig, int& sig_index, VMReg from, VMRegPair* regs_to, int& to_index, RegState reg_state[], int ret_off);
1628   void restore_stack(Compile* C);
1629 
1630   // clear memory of size 'cnt' qwords, starting at 'base';
1631   // if 'is_large' is set, do not try to produce short loop
1632   void clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, bool is_large, bool word_copy_only);
1633 
1634   // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1635   void xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp);
1636 
1637 #ifdef COMPILER2
1638   void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1639                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1640 
1641   // IndexOf strings.
1642   // Small strings are loaded through stack if they cross page boundary.
1643   void string_indexof(Register str1, Register str2,
1644                       Register cnt1, Register cnt2,
1645                       int int_cnt2,  Register result,
1646                       XMMRegister vec, Register tmp,
1647                       int ae);
1648 
1649   // IndexOf for constant substrings with size >= 8 elements
1650   // which don't need to be loaded through stack.
1651   void string_indexofC8(Register str1, Register str2,
1652                       Register cnt1, Register cnt2,
1653                       int int_cnt2,  Register result,
1654                       XMMRegister vec, Register tmp,
1655                       int ae);
1656 
1657     // Smallest code: we don't need to load through stack,
1658     // check string tail.
1659 
1660   // helper function for string_compare
1661   void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1662                           Address::ScaleFactor scale, Address::ScaleFactor scale1,
1663                           Address::ScaleFactor scale2, Register index, int ae);
1664   // Compare strings.
1665   void string_compare(Register str1, Register str2,
1666                       Register cnt1, Register cnt2, Register result,
1667                       XMMRegister vec1, int ae);
1668 
1669   // Search for Non-ASCII character (Negative byte value) in a byte array,
1670   // return true if it has any and false otherwise.
1671   void has_negatives(Register ary1, Register len,
1672                      Register result, Register tmp1,
1673                      XMMRegister vec1, XMMRegister vec2);
1674 
1675   // Compare char[] or byte[] arrays.
1676   void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1677                      Register limit, Register result, Register chr,
1678                      XMMRegister vec1, XMMRegister vec2, bool is_char);
1679 
1680 #endif
1681 
1682   // Fill primitive arrays
1683   void generate_fill(BasicType t, bool aligned,
1684                      Register to, Register value, Register count,
1685                      Register rtmp, XMMRegister xtmp);
1686 
1687   void encode_iso_array(Register src, Register dst, Register len,
1688                         XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1689                         XMMRegister tmp4, Register tmp5, Register result);
1690 
1691 #ifdef _LP64
1692   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1693   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1694                              Register y, Register y_idx, Register z,
1695                              Register carry, Register product,
1696                              Register idx, Register kdx);
1697   void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1698                               Register yz_idx, Register idx,
1699                               Register carry, Register product, int offset);
1700   void multiply_128_x_128_bmi2_loop(Register y, Register z,
1701                                     Register carry, Register carry2,
1702                                     Register idx, Register jdx,
1703                                     Register yz_idx1, Register yz_idx2,
1704                                     Register tmp, Register tmp3, Register tmp4);
1705   void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1706                                Register yz_idx, Register idx, Register jdx,
1707                                Register carry, Register product,
1708                                Register carry2);
1709   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1710                        Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1711   void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1712                      Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1713   void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1714                             Register tmp2);
1715   void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1716                        Register rdxReg, Register raxReg);
1717   void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1718   void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1719                        Register tmp3, Register tmp4);
1720   void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1721                      Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1722 
1723   void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1724                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1725                Register raxReg);
1726   void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1727                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1728                Register raxReg);
1729   void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1730                            Register result, Register tmp1, Register tmp2,
1731                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1732 #endif
1733 
1734   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1735   void update_byte_crc32(Register crc, Register val, Register table);
1736   void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1737   // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1738   // Note on a naming convention:
1739   // Prefix w = register only used on a Westmere+ architecture
1740   // Prefix n = register only used on a Nehalem architecture
1741 #ifdef _LP64
1742   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1743                        Register tmp1, Register tmp2, Register tmp3);
1744 #else
1745   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1746                        Register tmp1, Register tmp2, Register tmp3,
1747                        XMMRegister xtmp1, XMMRegister xtmp2);
1748 #endif
1749   void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1750                         Register in_out,
1751                         uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1752                         XMMRegister w_xtmp2,
1753                         Register tmp1,
1754                         Register n_tmp2, Register n_tmp3);
1755   void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1756                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1757                        Register tmp1, Register tmp2,
1758                        Register n_tmp3);
1759   void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1760                          Register in_out1, Register in_out2, Register in_out3,
1761                          Register tmp1, Register tmp2, Register tmp3,
1762                          XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1763                          Register tmp4, Register tmp5,
1764                          Register n_tmp6);
1765   void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1766                             Register tmp1, Register tmp2, Register tmp3,
1767                             Register tmp4, Register tmp5, Register tmp6,
1768                             XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1769                             bool is_pclmulqdq_supported);
1770   // Fold 128-bit data chunk
1771   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1772   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1773   // Fold 8-bit data
1774   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1775   void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1776   void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1777 
1778   // Compress char[] array to byte[].
1779   void char_array_compress(Register src, Register dst, Register len,
1780                            XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1781                            XMMRegister tmp4, Register tmp5, Register result);
1782 
1783   // Inflate byte[] array to char[].
1784   void byte_array_inflate(Register src, Register dst, Register len,
1785                           XMMRegister tmp1, Register tmp2);
1786 
1787 };
1788 
1789 /**
1790  * class SkipIfEqual:
1791  *
1792  * Instantiating this class will result in assembly code being output that will
1793  * jump around any code emitted between the creation of the instance and it's
1794  * automatic destruction at the end of a scope block, depending on the value of
1795  * the flag passed to the constructor, which will be checked at run-time.
1796  */
1797 class SkipIfEqual {
1798  private:
1799   MacroAssembler* _masm;
1800   Label _label;
1801 
1802  public:
1803    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1804    ~SkipIfEqual();
1805 };
1806 
1807 #endif // CPU_X86_MACROASSEMBLER_X86_HPP