1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 protected:
42
43 Address as_Address(AddressLiteral adr);
44 Address as_Address(ArrayAddress adr);
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51
52 virtual void call_VM_leaf_base(
53 address entry_point, // the entry point
54 int number_of_arguments // the number of arguments to pop after the call
55 );
56
57 // This is the base routine called by the different versions of call_VM. The interpreter
58 // may customize this version by overriding it for its purposes (e.g., to save/restore
59 // additional registers when doing a VM call).
60 //
61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
62 // returns the register which contains the thread upon return. If a thread register has been
63 // specified, the return value will correspond to that register. If no last_java_sp is specified
64 // (noreg) than rsp will be used instead.
65 virtual void call_VM_base( // returns the register containing the thread upon return
66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
67 Register java_thread, // the thread if computed before ; use noreg otherwise
68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
69 address entry_point, // the entry point
70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
71 bool check_exceptions // whether to check for pending exceptions after return
72 );
73
74 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
75
76 // helpers for FPU flag access
77 // tmp is a temporary register, if none is available use noreg
78 void save_rax (Register tmp);
79 void restore_rax(Register tmp);
80
81 public:
82 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
83
84 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
85 // The implementation is only non-empty for the InterpreterMacroAssembler,
86 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
87 virtual void check_and_handle_popframe(Register java_thread);
88 virtual void check_and_handle_earlyret(Register java_thread);
89
90 // Support for NULL-checks
91 //
92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
93 // If the accessed location is M[reg + offset] and the offset is known, provide the
94 // offset. No explicit code generation is needed if the offset is within a certain
95 // range (0 <= offset <= page_size).
96
97 void null_check(Register reg, int offset = -1);
98 static bool needs_explicit_null_check(intptr_t offset);
99
100 void test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable);
101 void test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable);
102 void test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened);
103 void test_value_is_not_buffered(Register value, Register temp_reg, Label& not_buffered);
104
105 // Required platform-specific helpers for Label::patch_instructions.
106 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
107 void pd_patch_instruction(address branch, address target) {
108 unsigned char op = branch[0];
109 assert(op == 0xE8 /* call */ ||
110 op == 0xE9 /* jmp */ ||
111 op == 0xEB /* short jmp */ ||
112 (op & 0xF0) == 0x70 /* short jcc */ ||
113 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
114 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
115 "Invalid opcode at patch point");
116
117 if (op == 0xEB || (op & 0xF0) == 0x70) {
118 // short offset operators (jmp and jcc)
119 char* disp = (char*) &branch[1];
120 int imm8 = target - (address) &disp[1];
121 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
122 *disp = imm8;
123 } else {
124 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
125 int imm32 = target - (address) &disp[1];
126 *disp = imm32;
127 }
128 }
129
130 // The following 4 methods return the offset of the appropriate move instruction
131
132 // Support for fast byte/short loading with zero extension (depending on particular CPU)
133 int load_unsigned_byte(Register dst, Address src);
134 int load_unsigned_short(Register dst, Address src);
135
136 // Support for fast byte/short loading with sign extension (depending on particular CPU)
137 int load_signed_byte(Register dst, Address src);
138 int load_signed_short(Register dst, Address src);
139
140 // Support for sign-extension (hi:lo = extend_sign(lo))
141 void extend_sign(Register hi, Register lo);
142
143 // Load and store values by size and signed-ness
144 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
145 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
146
147 // Support for inc/dec with optimal instruction selection depending on value
148
149 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
150 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
151
152 void decrementl(Address dst, int value = 1);
153 void decrementl(Register reg, int value = 1);
154
155 void decrementq(Register reg, int value = 1);
156 void decrementq(Address dst, int value = 1);
157
158 void incrementl(Address dst, int value = 1);
159 void incrementl(Register reg, int value = 1);
160
161 void incrementq(Register reg, int value = 1);
162 void incrementq(Address dst, int value = 1);
163
164 // special instructions for EVEX
165 void setvectmask(Register dst, Register src);
166 void restorevectmask();
167
168 // Support optimal SSE move instructions.
169 void movflt(XMMRegister dst, XMMRegister src) {
170 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
171 else { movss (dst, src); return; }
172 }
173 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
174 void movflt(XMMRegister dst, AddressLiteral src);
175 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
176
177 void movdbl(XMMRegister dst, XMMRegister src) {
178 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
179 else { movsd (dst, src); return; }
180 }
181
182 void movdbl(XMMRegister dst, AddressLiteral src);
183
184 void movdbl(XMMRegister dst, Address src) {
185 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
186 else { movlpd(dst, src); return; }
187 }
188 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
189
190 void incrementl(AddressLiteral dst);
191 void incrementl(ArrayAddress dst);
192
193 void incrementq(AddressLiteral dst);
194
195 // Alignment
196 void align(int modulus);
197 void align(int modulus, int target);
198
199 // A 5 byte nop that is safe for patching (see patch_verified_entry)
200 void fat_nop();
201
202 // Stack frame creation/removal
203 void enter();
204 void leave();
205
206 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
207 // The pointer will be loaded into the thread register.
208 void get_thread(Register thread);
209
210
211 // Support for VM calls
212 //
213 // It is imperative that all calls into the VM are handled via the call_VM macros.
214 // They make sure that the stack linkage is setup correctly. call_VM's correspond
215 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
216
217
218 void call_VM(Register oop_result,
219 address entry_point,
220 bool check_exceptions = true);
221 void call_VM(Register oop_result,
222 address entry_point,
223 Register arg_1,
224 bool check_exceptions = true);
225 void call_VM(Register oop_result,
226 address entry_point,
227 Register arg_1, Register arg_2,
228 bool check_exceptions = true);
229 void call_VM(Register oop_result,
230 address entry_point,
231 Register arg_1, Register arg_2, Register arg_3,
232 bool check_exceptions = true);
233
234 // Overloadings with last_Java_sp
235 void call_VM(Register oop_result,
236 Register last_java_sp,
237 address entry_point,
238 int number_of_arguments = 0,
239 bool check_exceptions = true);
240 void call_VM(Register oop_result,
241 Register last_java_sp,
242 address entry_point,
243 Register arg_1, bool
244 check_exceptions = true);
245 void call_VM(Register oop_result,
246 Register last_java_sp,
247 address entry_point,
248 Register arg_1, Register arg_2,
249 bool check_exceptions = true);
250 void call_VM(Register oop_result,
251 Register last_java_sp,
252 address entry_point,
253 Register arg_1, Register arg_2, Register arg_3,
254 bool check_exceptions = true);
255
256 void get_vm_result (Register oop_result, Register thread);
257 void get_vm_result_2(Register metadata_result, Register thread);
258
259 // These always tightly bind to MacroAssembler::call_VM_base
260 // bypassing the virtual implementation
261 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
262 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
263 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
264 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
265 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
266
267 void call_VM_leaf0(address entry_point);
268 void call_VM_leaf(address entry_point,
269 int number_of_arguments = 0);
270 void call_VM_leaf(address entry_point,
271 Register arg_1);
272 void call_VM_leaf(address entry_point,
273 Register arg_1, Register arg_2);
274 void call_VM_leaf(address entry_point,
275 Register arg_1, Register arg_2, Register arg_3);
276
277 // These always tightly bind to MacroAssembler::call_VM_leaf_base
278 // bypassing the virtual implementation
279 void super_call_VM_leaf(address entry_point);
280 void super_call_VM_leaf(address entry_point, Register arg_1);
281 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
282 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
283 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
284
285 // last Java Frame (fills frame anchor)
286 void set_last_Java_frame(Register thread,
287 Register last_java_sp,
288 Register last_java_fp,
289 address last_java_pc);
290
291 // thread in the default location (r15_thread on 64bit)
292 void set_last_Java_frame(Register last_java_sp,
293 Register last_java_fp,
294 address last_java_pc);
295
296 void reset_last_Java_frame(Register thread, bool clear_fp);
297
298 // thread in the default location (r15_thread on 64bit)
299 void reset_last_Java_frame(bool clear_fp);
300
301 // Stores
302 void store_check(Register obj); // store check for obj - register is destroyed afterwards
303 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
304
305 void resolve_jobject(Register value, Register thread, Register tmp);
306 void clear_jweak_tag(Register possibly_jweak);
307
308 #if INCLUDE_ALL_GCS
309
310 void g1_write_barrier_pre(Register obj,
311 Register pre_val,
312 Register thread,
313 Register tmp,
314 bool tosca_live,
315 bool expand_call);
316
317 void g1_write_barrier_post(Register store_addr,
318 Register new_val,
319 Register thread,
320 Register tmp,
321 Register tmp2);
322
323 #endif // INCLUDE_ALL_GCS
324
325 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
326 void c2bool(Register x);
327
328 // C++ bool manipulation
329
330 void movbool(Register dst, Address src);
331 void movbool(Address dst, bool boolconst);
332 void movbool(Address dst, Register src);
333 void testbool(Register dst);
334
335 void resolve_oop_handle(Register result);
336 void load_mirror(Register mirror, Register method);
337
338 // oop manipulations
339 void load_klass(Register dst, Register src);
340 void store_klass(Register dst, Register src);
341
342 void load_heap_oop(Register dst, Address src);
343 void load_heap_oop_not_null(Register dst, Address src);
344 void store_heap_oop(Address dst, Register src);
345 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
346
347 // Used for storing NULL. All other oop constants should be
348 // stored using routines that take a jobject.
349 void store_heap_oop_null(Address dst);
350
351 void load_prototype_header(Register dst, Register src);
352
353 #ifdef _LP64
354 void store_klass_gap(Register dst, Register src);
355
356 // This dummy is to prevent a call to store_heap_oop from
357 // converting a zero (like NULL) into a Register by giving
358 // the compiler two choices it can't resolve
359
360 void store_heap_oop(Address dst, void* dummy);
361
362 void encode_heap_oop(Register r);
363 void decode_heap_oop(Register r);
364 void encode_heap_oop_not_null(Register r);
365 void decode_heap_oop_not_null(Register r);
366 void encode_heap_oop_not_null(Register dst, Register src);
367 void decode_heap_oop_not_null(Register dst, Register src);
368
369 void set_narrow_oop(Register dst, jobject obj);
370 void set_narrow_oop(Address dst, jobject obj);
371 void cmp_narrow_oop(Register dst, jobject obj);
372 void cmp_narrow_oop(Address dst, jobject obj);
373
374 void encode_klass_not_null(Register r);
375 void decode_klass_not_null(Register r);
376 void encode_klass_not_null(Register dst, Register src);
377 void decode_klass_not_null(Register dst, Register src);
378 void set_narrow_klass(Register dst, Klass* k);
379 void set_narrow_klass(Address dst, Klass* k);
380 void cmp_narrow_klass(Register dst, Klass* k);
381 void cmp_narrow_klass(Address dst, Klass* k);
382
383 // Returns the byte size of the instructions generated by decode_klass_not_null()
384 // when compressed klass pointers are being used.
385 static int instr_size_for_decode_klass_not_null();
386
387 // if heap base register is used - reinit it with the correct value
388 void reinit_heapbase();
389
390 DEBUG_ONLY(void verify_heapbase(const char* msg);)
391
392 #endif // _LP64
393
394 // Int division/remainder for Java
395 // (as idivl, but checks for special case as described in JVM spec.)
396 // returns idivl instruction offset for implicit exception handling
397 int corrected_idivl(Register reg);
398
399 // Long division/remainder for Java
400 // (as idivq, but checks for special case as described in JVM spec.)
401 // returns idivq instruction offset for implicit exception handling
402 int corrected_idivq(Register reg);
403
404 void int3();
405
406 // Long operation macros for a 32bit cpu
407 // Long negation for Java
408 void lneg(Register hi, Register lo);
409
410 // Long multiplication for Java
411 // (destroys contents of eax, ebx, ecx and edx)
412 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
413
414 // Long shifts for Java
415 // (semantics as described in JVM spec.)
416 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
417 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
418
419 // Long compare for Java
420 // (semantics as described in JVM spec.)
421 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
422
423
424 // misc
425
426 // Sign extension
427 void sign_extend_short(Register reg);
428 void sign_extend_byte(Register reg);
429
430 // Division by power of 2, rounding towards 0
431 void division_with_shift(Register reg, int shift_value);
432
433 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
434 //
435 // CF (corresponds to C0) if x < y
436 // PF (corresponds to C2) if unordered
437 // ZF (corresponds to C3) if x = y
438 //
439 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
440 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
441 void fcmp(Register tmp);
442 // Variant of the above which allows y to be further down the stack
443 // and which only pops x and y if specified. If pop_right is
444 // specified then pop_left must also be specified.
445 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
446
447 // Floating-point comparison for Java
448 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
449 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
450 // (semantics as described in JVM spec.)
451 void fcmp2int(Register dst, bool unordered_is_less);
452 // Variant of the above which allows y to be further down the stack
453 // and which only pops x and y if specified. If pop_right is
454 // specified then pop_left must also be specified.
455 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
456
457 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
458 // tmp is a temporary register, if none is available use noreg
459 void fremr(Register tmp);
460
461 // dst = c = a * b + c
462 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
463 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
464
465 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
466 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
467 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
468 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
469
470
471 // same as fcmp2int, but using SSE2
472 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
473 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
474
475 // branch to L if FPU flag C2 is set/not set
476 // tmp is a temporary register, if none is available use noreg
477 void jC2 (Register tmp, Label& L);
478 void jnC2(Register tmp, Label& L);
479
480 // Pop ST (ffree & fincstp combined)
481 void fpop();
482
483 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
484 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
485 void load_float(Address src);
486
487 // Store float value to 'address'. If UseSSE >= 1, the value is stored
488 // from register xmm0. Otherwise, the value is stored from the FPU stack.
489 void store_float(Address dst);
490
491 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
492 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
493 void load_double(Address src);
494
495 // Store double value to 'address'. If UseSSE >= 2, the value is stored
496 // from register xmm0. Otherwise, the value is stored from the FPU stack.
497 void store_double(Address dst);
498
499 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
500 void push_fTOS();
501
502 // pops double TOS element from CPU stack and pushes on FPU stack
503 void pop_fTOS();
504
505 void empty_FPU_stack();
506
507 void push_IU_state();
508 void pop_IU_state();
509
510 void push_FPU_state();
511 void pop_FPU_state();
512
513 void push_CPU_state();
514 void pop_CPU_state();
515
516 // Round up to a power of two
517 void round_to(Register reg, int modulus);
518
519 // Callee saved registers handling
520 void push_callee_saved_registers();
521 void pop_callee_saved_registers();
522
523 // allocation
524 void eden_allocate(
525 Register obj, // result: pointer to object after successful allocation
526 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
527 int con_size_in_bytes, // object size in bytes if known at compile time
528 Register t1, // temp register
529 Label& slow_case // continuation point if fast allocation fails
530 );
531 void tlab_allocate(
532 Register obj, // result: pointer to object after successful allocation
533 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
534 int con_size_in_bytes, // object size in bytes if known at compile time
535 Register t1, // temp register
536 Register t2, // temp register
537 Label& slow_case // continuation point if fast allocation fails
538 );
539 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
540 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
541
542 void incr_allocated_bytes(Register thread,
543 Register var_size_in_bytes, int con_size_in_bytes,
544 Register t1 = noreg);
545
546 // interface method calling
547 void lookup_interface_method(Register recv_klass,
548 Register intf_klass,
549 RegisterOrConstant itable_index,
550 Register method_result,
551 Register scan_temp,
552 Label& no_such_interface,
553 bool return_method = true);
554
555 // virtual method calling
556 void lookup_virtual_method(Register recv_klass,
557 RegisterOrConstant vtable_index,
558 Register method_result);
559
560 // Test sub_klass against super_klass, with fast and slow paths.
561
562 // The fast path produces a tri-state answer: yes / no / maybe-slow.
563 // One of the three labels can be NULL, meaning take the fall-through.
564 // If super_check_offset is -1, the value is loaded up from super_klass.
565 // No registers are killed, except temp_reg.
566 void check_klass_subtype_fast_path(Register sub_klass,
567 Register super_klass,
568 Register temp_reg,
569 Label* L_success,
570 Label* L_failure,
571 Label* L_slow_path,
572 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
573
574 // The rest of the type check; must be wired to a corresponding fast path.
575 // It does not repeat the fast path logic, so don't use it standalone.
576 // The temp_reg and temp2_reg can be noreg, if no temps are available.
577 // Updates the sub's secondary super cache as necessary.
578 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
579 void check_klass_subtype_slow_path(Register sub_klass,
580 Register super_klass,
581 Register temp_reg,
582 Register temp2_reg,
583 Label* L_success,
584 Label* L_failure,
585 bool set_cond_codes = false);
586
587 // Simplified, combined version, good for typical uses.
588 // Falls through on failure.
589 void check_klass_subtype(Register sub_klass,
590 Register super_klass,
591 Register temp_reg,
592 Label& L_success);
593
594 // method handles (JSR 292)
595 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
596
597 //----
598 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
599
600 // Debugging
601
602 // only if +VerifyOops
603 // TODO: Make these macros with file and line like sparc version!
604 void verify_oop(Register reg, const char* s = "broken oop");
605 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
606
607 // TODO: verify method and klass metadata (compare against vptr?)
608 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
609 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
610
611 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
612 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
613
614 // only if +VerifyFPU
615 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
616
617 // Verify or restore cpu control state after JNI call
618 void restore_cpu_control_state_after_jni();
619
620 // prints msg, dumps registers and stops execution
621 void stop(const char* msg);
622
623 // prints msg and continues
624 void warn(const char* msg);
625
626 // dumps registers and other state
627 void print_state();
628
629 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
630 static void debug64(char* msg, int64_t pc, int64_t regs[]);
631 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
632 static void print_state64(int64_t pc, int64_t regs[]);
633
634 void os_breakpoint();
635
636 void untested() { stop("untested"); }
637
638 void unimplemented(const char* what = "");
639
640 void should_not_reach_here() { stop("should not reach here"); }
641
642 void print_CPU_state();
643
644 // Stack overflow checking
645 void bang_stack_with_offset(int offset) {
646 // stack grows down, caller passes positive offset
647 assert(offset > 0, "must bang with negative offset");
648 movl(Address(rsp, (-offset)), rax);
649 }
650
651 // Writes to stack successive pages until offset reached to check for
652 // stack overflow + shadow pages. Also, clobbers tmp
653 void bang_stack_size(Register size, Register tmp);
654
655 // Check for reserved stack access in method being exited (for JIT)
656 void reserved_stack_check();
657
658 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
659 Register tmp,
660 int offset);
661
662 // Support for serializing memory accesses between threads
663 void serialize_memory(Register thread, Register tmp);
664
665 #ifdef _LP64
666 void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
667 #else
668 void safepoint_poll(Label& slow_path);
669 #endif
670
671 void verify_tlab();
672
673 // Biased locking support
674 // lock_reg and obj_reg must be loaded up with the appropriate values.
675 // swap_reg must be rax, and is killed.
676 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
677 // be killed; if not supplied, push/pop will be used internally to
678 // allocate a temporary (inefficient, avoid if possible).
679 // Optional slow case is for implementations (interpreter and C1) which branch to
680 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
681 // Returns offset of first potentially-faulting instruction for null
682 // check info (currently consumed only by C1). If
683 // swap_reg_contains_mark is true then returns -1 as it is assumed
684 // the calling code has already passed any potential faults.
685 int biased_locking_enter(Register lock_reg, Register obj_reg,
686 Register swap_reg, Register tmp_reg,
687 bool swap_reg_contains_mark,
688 Label& done, Label* slow_case = NULL,
689 BiasedLockingCounters* counters = NULL);
690 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
691 #ifdef COMPILER2
692 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
693 // See full desription in macroAssembler_x86.cpp.
694 void fast_lock(Register obj, Register box, Register tmp,
695 Register scr, Register cx1, Register cx2,
696 BiasedLockingCounters* counters,
697 RTMLockingCounters* rtm_counters,
698 RTMLockingCounters* stack_rtm_counters,
699 Metadata* method_data,
700 bool use_rtm, bool profile_rtm);
701 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
702 #if INCLUDE_RTM_OPT
703 void rtm_counters_update(Register abort_status, Register rtm_counters);
704 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
705 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
706 RTMLockingCounters* rtm_counters,
707 Metadata* method_data);
708 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
709 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
710 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
711 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
712 void rtm_stack_locking(Register obj, Register tmp, Register scr,
713 Register retry_on_abort_count,
714 RTMLockingCounters* stack_rtm_counters,
715 Metadata* method_data, bool profile_rtm,
716 Label& DONE_LABEL, Label& IsInflated);
717 void rtm_inflated_locking(Register obj, Register box, Register tmp,
718 Register scr, Register retry_on_busy_count,
719 Register retry_on_abort_count,
720 RTMLockingCounters* rtm_counters,
721 Metadata* method_data, bool profile_rtm,
722 Label& DONE_LABEL);
723 #endif
724 #endif
725
726 Condition negate_condition(Condition cond);
727
728 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
729 // operands. In general the names are modified to avoid hiding the instruction in Assembler
730 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
731 // here in MacroAssembler. The major exception to this rule is call
732
733 // Arithmetics
734
735
736 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
737 void addptr(Address dst, Register src);
738
739 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
740 void addptr(Register dst, int32_t src);
741 void addptr(Register dst, Register src);
742 void addptr(Register dst, RegisterOrConstant src) {
743 if (src.is_constant()) addptr(dst, (int) src.as_constant());
744 else addptr(dst, src.as_register());
745 }
746
747 void andptr(Register dst, int32_t src);
748 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
749
750 void cmp8(AddressLiteral src1, int imm);
751
752 // renamed to drag out the casting of address to int32_t/intptr_t
753 void cmp32(Register src1, int32_t imm);
754
755 void cmp32(AddressLiteral src1, int32_t imm);
756 // compare reg - mem, or reg - &mem
757 void cmp32(Register src1, AddressLiteral src2);
758
759 void cmp32(Register src1, Address src2);
760
761 #ifndef _LP64
762 void cmpklass(Address dst, Metadata* obj);
763 void cmpklass(Register dst, Metadata* obj);
764 void cmpoop(Address dst, jobject obj);
765 #endif // _LP64
766
767 void cmpoop(Register src1, Register src2);
768 void cmpoop(Register src1, Address src2);
769 void cmpoop(Register dst, jobject obj);
770
771 // NOTE src2 must be the lval. This is NOT an mem-mem compare
772 void cmpptr(Address src1, AddressLiteral src2);
773
774 void cmpptr(Register src1, AddressLiteral src2);
775
776 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
777 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
778 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
779
780 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
781 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
782
783 // cmp64 to avoild hiding cmpq
784 void cmp64(Register src1, AddressLiteral src);
785
786 void cmpxchgptr(Register reg, Address adr);
787
788 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
789
790
791 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
792 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
793
794
795 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
796
797 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
798
799 void shlptr(Register dst, int32_t shift);
800 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
801
802 void shrptr(Register dst, int32_t shift);
803 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
804
805 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
806 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
807
808 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
809
810 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
811 void subptr(Register dst, int32_t src);
812 // Force generation of a 4 byte immediate value even if it fits into 8bit
813 void subptr_imm32(Register dst, int32_t src);
814 void subptr(Register dst, Register src);
815 void subptr(Register dst, RegisterOrConstant src) {
816 if (src.is_constant()) subptr(dst, (int) src.as_constant());
817 else subptr(dst, src.as_register());
818 }
819
820 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
821 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
822
823 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
824 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
825
826 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
827
828
829
830 // Helper functions for statistics gathering.
831 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
832 void cond_inc32(Condition cond, AddressLiteral counter_addr);
833 // Unconditional atomic increment.
834 void atomic_incl(Address counter_addr);
835 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
836 #ifdef _LP64
837 void atomic_incq(Address counter_addr);
838 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
839 #endif
840 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
841 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
842
843 void lea(Register dst, AddressLiteral adr);
844 void lea(Address dst, AddressLiteral adr);
845 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
846
847 void leal32(Register dst, Address src) { leal(dst, src); }
848
849 // Import other testl() methods from the parent class or else
850 // they will be hidden by the following overriding declaration.
851 using Assembler::testl;
852 void testl(Register dst, AddressLiteral src);
853
854 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
855 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
856 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
857 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
858
859 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
860 void testptr(Register src1, Register src2);
861
862 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
863 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
864
865 // Calls
866
867 void call(Label& L, relocInfo::relocType rtype);
868 void call(Register entry);
869
870 // NOTE: this call transfers to the effective address of entry NOT
871 // the address contained by entry. This is because this is more natural
872 // for jumps/calls.
873 void call(AddressLiteral entry);
874
875 // Emit the CompiledIC call idiom
876 void ic_call(address entry, jint method_index = 0);
877
878 // Jumps
879
880 // NOTE: these jumps tranfer to the effective address of dst NOT
881 // the address contained by dst. This is because this is more natural
882 // for jumps/calls.
883 void jump(AddressLiteral dst);
884 void jump_cc(Condition cc, AddressLiteral dst);
885
886 // 32bit can do a case table jump in one instruction but we no longer allow the base
887 // to be installed in the Address class. This jump will tranfers to the address
888 // contained in the location described by entry (not the address of entry)
889 void jump(ArrayAddress entry);
890
891 // Floating
892
893 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
894 void andpd(XMMRegister dst, AddressLiteral src);
895 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
896
897 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
898 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
899 void andps(XMMRegister dst, AddressLiteral src);
900
901 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
902 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
903 void comiss(XMMRegister dst, AddressLiteral src);
904
905 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
906 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
907 void comisd(XMMRegister dst, AddressLiteral src);
908
909 void fadd_s(Address src) { Assembler::fadd_s(src); }
910 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
911
912 void fldcw(Address src) { Assembler::fldcw(src); }
913 void fldcw(AddressLiteral src);
914
915 void fld_s(int index) { Assembler::fld_s(index); }
916 void fld_s(Address src) { Assembler::fld_s(src); }
917 void fld_s(AddressLiteral src);
918
919 void fld_d(Address src) { Assembler::fld_d(src); }
920 void fld_d(AddressLiteral src);
921
922 void fld_x(Address src) { Assembler::fld_x(src); }
923 void fld_x(AddressLiteral src);
924
925 void fmul_s(Address src) { Assembler::fmul_s(src); }
926 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
927
928 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
929 void ldmxcsr(AddressLiteral src);
930
931 #ifdef _LP64
932 private:
933 void sha256_AVX2_one_round_compute(
934 Register reg_old_h,
935 Register reg_a,
936 Register reg_b,
937 Register reg_c,
938 Register reg_d,
939 Register reg_e,
940 Register reg_f,
941 Register reg_g,
942 Register reg_h,
943 int iter);
944 void sha256_AVX2_four_rounds_compute_first(int start);
945 void sha256_AVX2_four_rounds_compute_last(int start);
946 void sha256_AVX2_one_round_and_sched(
947 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
948 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
949 XMMRegister xmm_2, /* ymm6 */
950 XMMRegister xmm_3, /* ymm7 */
951 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
952 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
953 Register reg_c, /* edi */
954 Register reg_d, /* esi */
955 Register reg_e, /* r8d */
956 Register reg_f, /* r9d */
957 Register reg_g, /* r10d */
958 Register reg_h, /* r11d */
959 int iter);
960
961 void addm(int disp, Register r1, Register r2);
962
963 public:
964 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
965 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
966 Register buf, Register state, Register ofs, Register limit, Register rsp,
967 bool multi_block, XMMRegister shuf_mask);
968 #endif
969
970 #ifdef _LP64
971 private:
972 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
973 Register e, Register f, Register g, Register h, int iteration);
974
975 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
976 Register a, Register b, Register c, Register d, Register e, Register f,
977 Register g, Register h, int iteration);
978
979 void addmq(int disp, Register r1, Register r2);
980 public:
981 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
982 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
983 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
984 XMMRegister shuf_mask);
985 #endif
986
987 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
988 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
989 Register buf, Register state, Register ofs, Register limit, Register rsp,
990 bool multi_block);
991
992 #ifdef _LP64
993 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
994 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
995 Register buf, Register state, Register ofs, Register limit, Register rsp,
996 bool multi_block, XMMRegister shuf_mask);
997 #else
998 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
999 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1000 Register buf, Register state, Register ofs, Register limit, Register rsp,
1001 bool multi_block);
1002 #endif
1003
1004 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1005 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1006 Register rax, Register rcx, Register rdx, Register tmp);
1007
1008 #ifdef _LP64
1009 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1010 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1011 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
1012
1013 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1014 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1015 Register rax, Register rcx, Register rdx, Register r11);
1016
1017 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1018 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1019 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1020
1021 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1022 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1023 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1024 Register tmp3, Register tmp4);
1025
1026 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1027 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1028 Register rax, Register rcx, Register rdx, Register tmp1,
1029 Register tmp2, Register tmp3, Register tmp4);
1030 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1031 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1032 Register rax, Register rcx, Register rdx, Register tmp1,
1033 Register tmp2, Register tmp3, Register tmp4);
1034 #else
1035 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1036 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1037 Register rax, Register rcx, Register rdx, Register tmp1);
1038
1039 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1040 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1041 Register rax, Register rcx, Register rdx, Register tmp);
1042
1043 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1044 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1045 Register rdx, Register tmp);
1046
1047 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1048 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1049 Register rax, Register rbx, Register rdx);
1050
1051 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1052 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1053 Register rax, Register rcx, Register rdx, Register tmp);
1054
1055 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1056 Register edx, Register ebx, Register esi, Register edi,
1057 Register ebp, Register esp);
1058
1059 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1060 Register esi, Register edi, Register ebp, Register esp);
1061
1062 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1063 Register edx, Register ebx, Register esi, Register edi,
1064 Register ebp, Register esp);
1065
1066 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1067 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1068 Register rax, Register rcx, Register rdx, Register tmp);
1069 #endif
1070
1071 void increase_precision();
1072 void restore_precision();
1073
1074 private:
1075
1076 // these are private because users should be doing movflt/movdbl
1077
1078 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1079 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1080 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1081 void movss(XMMRegister dst, AddressLiteral src);
1082
1083 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1084 void movlpd(XMMRegister dst, AddressLiteral src);
1085
1086 public:
1087
1088 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1089 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1090 void addsd(XMMRegister dst, AddressLiteral src);
1091
1092 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1093 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1094 void addss(XMMRegister dst, AddressLiteral src);
1095
1096 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1097 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1098 void addpd(XMMRegister dst, AddressLiteral src);
1099
1100 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1101 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1102 void divsd(XMMRegister dst, AddressLiteral src);
1103
1104 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1105 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1106 void divss(XMMRegister dst, AddressLiteral src);
1107
1108 // Move Unaligned Double Quadword
1109 void movdqu(Address dst, XMMRegister src);
1110 void movdqu(XMMRegister dst, Address src);
1111 void movdqu(XMMRegister dst, XMMRegister src);
1112 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1113 // AVX Unaligned forms
1114 void vmovdqu(Address dst, XMMRegister src);
1115 void vmovdqu(XMMRegister dst, Address src);
1116 void vmovdqu(XMMRegister dst, XMMRegister src);
1117 void vmovdqu(XMMRegister dst, AddressLiteral src);
1118
1119 // Move Aligned Double Quadword
1120 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1121 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1122 void movdqa(XMMRegister dst, AddressLiteral src);
1123
1124 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1125 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1126 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1127 void movsd(XMMRegister dst, AddressLiteral src);
1128
1129 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1130 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1131 void mulpd(XMMRegister dst, AddressLiteral src);
1132
1133 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1134 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1135 void mulsd(XMMRegister dst, AddressLiteral src);
1136
1137 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1138 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1139 void mulss(XMMRegister dst, AddressLiteral src);
1140
1141 // Carry-Less Multiplication Quadword
1142 void pclmulldq(XMMRegister dst, XMMRegister src) {
1143 // 0x00 - multiply lower 64 bits [0:63]
1144 Assembler::pclmulqdq(dst, src, 0x00);
1145 }
1146 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1147 // 0x11 - multiply upper 64 bits [64:127]
1148 Assembler::pclmulqdq(dst, src, 0x11);
1149 }
1150
1151 void pcmpeqb(XMMRegister dst, XMMRegister src);
1152 void pcmpeqw(XMMRegister dst, XMMRegister src);
1153
1154 void pcmpestri(XMMRegister dst, Address src, int imm8);
1155 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1156
1157 void pmovzxbw(XMMRegister dst, XMMRegister src);
1158 void pmovzxbw(XMMRegister dst, Address src);
1159
1160 void pmovmskb(Register dst, XMMRegister src);
1161
1162 void ptest(XMMRegister dst, XMMRegister src);
1163
1164 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1165 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1166 void sqrtsd(XMMRegister dst, AddressLiteral src);
1167
1168 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1169 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1170 void sqrtss(XMMRegister dst, AddressLiteral src);
1171
1172 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1173 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1174 void subsd(XMMRegister dst, AddressLiteral src);
1175
1176 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1177 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1178 void subss(XMMRegister dst, AddressLiteral src);
1179
1180 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1181 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1182 void ucomiss(XMMRegister dst, AddressLiteral src);
1183
1184 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1185 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1186 void ucomisd(XMMRegister dst, AddressLiteral src);
1187
1188 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1189 void xorpd(XMMRegister dst, XMMRegister src);
1190 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1191 void xorpd(XMMRegister dst, AddressLiteral src);
1192
1193 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1194 void xorps(XMMRegister dst, XMMRegister src);
1195 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1196 void xorps(XMMRegister dst, AddressLiteral src);
1197
1198 // Shuffle Bytes
1199 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1200 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1201 void pshufb(XMMRegister dst, AddressLiteral src);
1202 // AVX 3-operands instructions
1203
1204 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1205 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1206 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1207
1208 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1209 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1210 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1211
1212 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1213 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1214
1215 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1216 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1217
1218 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1219 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1220
1221 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1222 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1223 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1224
1225 void vpbroadcastw(XMMRegister dst, XMMRegister src);
1226
1227 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1228 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1229
1230 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1231 void vpmovmskb(Register dst, XMMRegister src);
1232
1233 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1234 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1235
1236 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1237 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1238
1239 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1240 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1241
1242 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1243 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1244
1245 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1246 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1247
1248 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1249 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1250
1251 void vptest(XMMRegister dst, XMMRegister src);
1252
1253 void punpcklbw(XMMRegister dst, XMMRegister src);
1254 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1255
1256 void pshufd(XMMRegister dst, Address src, int mode);
1257 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1258
1259 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1260 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1261
1262 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1263 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1264 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1265
1266 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1267 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1268 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1269
1270 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1271 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1272 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1273
1274 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1275 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1276 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1277
1278 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1279 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1280 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1281
1282 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1283 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1284 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1285
1286 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1287 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1288 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1289
1290 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1291 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1292 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1293
1294 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1295 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1296
1297 // AVX Vector instructions
1298
1299 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1300 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1301 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1302
1303 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1304 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1305 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1306
1307 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1308 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1309 Assembler::vpxor(dst, nds, src, vector_len);
1310 else
1311 Assembler::vxorpd(dst, nds, src, vector_len);
1312 }
1313 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1314 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1315 Assembler::vpxor(dst, nds, src, vector_len);
1316 else
1317 Assembler::vxorpd(dst, nds, src, vector_len);
1318 }
1319
1320 // Simple version for AVX2 256bit vectors
1321 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1322 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1323
1324 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1325 if (UseAVX > 2) {
1326 Assembler::vinserti32x4(dst, dst, src, imm8);
1327 } else if (UseAVX > 1) {
1328 // vinserti128 is available only in AVX2
1329 Assembler::vinserti128(dst, nds, src, imm8);
1330 } else {
1331 Assembler::vinsertf128(dst, nds, src, imm8);
1332 }
1333 }
1334
1335 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1336 if (UseAVX > 2) {
1337 Assembler::vinserti32x4(dst, dst, src, imm8);
1338 } else if (UseAVX > 1) {
1339 // vinserti128 is available only in AVX2
1340 Assembler::vinserti128(dst, nds, src, imm8);
1341 } else {
1342 Assembler::vinsertf128(dst, nds, src, imm8);
1343 }
1344 }
1345
1346 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1347 if (UseAVX > 2) {
1348 Assembler::vextracti32x4(dst, src, imm8);
1349 } else if (UseAVX > 1) {
1350 // vextracti128 is available only in AVX2
1351 Assembler::vextracti128(dst, src, imm8);
1352 } else {
1353 Assembler::vextractf128(dst, src, imm8);
1354 }
1355 }
1356
1357 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1358 if (UseAVX > 2) {
1359 Assembler::vextracti32x4(dst, src, imm8);
1360 } else if (UseAVX > 1) {
1361 // vextracti128 is available only in AVX2
1362 Assembler::vextracti128(dst, src, imm8);
1363 } else {
1364 Assembler::vextractf128(dst, src, imm8);
1365 }
1366 }
1367
1368 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1369 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1370 vinserti128(dst, dst, src, 1);
1371 }
1372 void vinserti128_high(XMMRegister dst, Address src) {
1373 vinserti128(dst, dst, src, 1);
1374 }
1375 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1376 vextracti128(dst, src, 1);
1377 }
1378 void vextracti128_high(Address dst, XMMRegister src) {
1379 vextracti128(dst, src, 1);
1380 }
1381
1382 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1383 if (UseAVX > 2) {
1384 Assembler::vinsertf32x4(dst, dst, src, 1);
1385 } else {
1386 Assembler::vinsertf128(dst, dst, src, 1);
1387 }
1388 }
1389
1390 void vinsertf128_high(XMMRegister dst, Address src) {
1391 if (UseAVX > 2) {
1392 Assembler::vinsertf32x4(dst, dst, src, 1);
1393 } else {
1394 Assembler::vinsertf128(dst, dst, src, 1);
1395 }
1396 }
1397
1398 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1399 if (UseAVX > 2) {
1400 Assembler::vextractf32x4(dst, src, 1);
1401 } else {
1402 Assembler::vextractf128(dst, src, 1);
1403 }
1404 }
1405
1406 void vextractf128_high(Address dst, XMMRegister src) {
1407 if (UseAVX > 2) {
1408 Assembler::vextractf32x4(dst, src, 1);
1409 } else {
1410 Assembler::vextractf128(dst, src, 1);
1411 }
1412 }
1413
1414 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1415 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1416 Assembler::vinserti64x4(dst, dst, src, 1);
1417 }
1418 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1419 Assembler::vinsertf64x4(dst, dst, src, 1);
1420 }
1421 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1422 Assembler::vextracti64x4(dst, src, 1);
1423 }
1424 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1425 Assembler::vextractf64x4(dst, src, 1);
1426 }
1427 void vextractf64x4_high(Address dst, XMMRegister src) {
1428 Assembler::vextractf64x4(dst, src, 1);
1429 }
1430 void vinsertf64x4_high(XMMRegister dst, Address src) {
1431 Assembler::vinsertf64x4(dst, dst, src, 1);
1432 }
1433
1434 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1435 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1436 vinserti128(dst, dst, src, 0);
1437 }
1438 void vinserti128_low(XMMRegister dst, Address src) {
1439 vinserti128(dst, dst, src, 0);
1440 }
1441 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1442 vextracti128(dst, src, 0);
1443 }
1444 void vextracti128_low(Address dst, XMMRegister src) {
1445 vextracti128(dst, src, 0);
1446 }
1447
1448 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1449 if (UseAVX > 2) {
1450 Assembler::vinsertf32x4(dst, dst, src, 0);
1451 } else {
1452 Assembler::vinsertf128(dst, dst, src, 0);
1453 }
1454 }
1455
1456 void vinsertf128_low(XMMRegister dst, Address src) {
1457 if (UseAVX > 2) {
1458 Assembler::vinsertf32x4(dst, dst, src, 0);
1459 } else {
1460 Assembler::vinsertf128(dst, dst, src, 0);
1461 }
1462 }
1463
1464 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1465 if (UseAVX > 2) {
1466 Assembler::vextractf32x4(dst, src, 0);
1467 } else {
1468 Assembler::vextractf128(dst, src, 0);
1469 }
1470 }
1471
1472 void vextractf128_low(Address dst, XMMRegister src) {
1473 if (UseAVX > 2) {
1474 Assembler::vextractf32x4(dst, src, 0);
1475 } else {
1476 Assembler::vextractf128(dst, src, 0);
1477 }
1478 }
1479
1480 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1481 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1482 Assembler::vinserti64x4(dst, dst, src, 0);
1483 }
1484 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1485 Assembler::vinsertf64x4(dst, dst, src, 0);
1486 }
1487 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1488 Assembler::vextracti64x4(dst, src, 0);
1489 }
1490 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1491 Assembler::vextractf64x4(dst, src, 0);
1492 }
1493 void vextractf64x4_low(Address dst, XMMRegister src) {
1494 Assembler::vextractf64x4(dst, src, 0);
1495 }
1496 void vinsertf64x4_low(XMMRegister dst, Address src) {
1497 Assembler::vinsertf64x4(dst, dst, src, 0);
1498 }
1499
1500 // Carry-Less Multiplication Quadword
1501 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1502 // 0x00 - multiply lower 64 bits [0:63]
1503 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1504 }
1505 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1506 // 0x11 - multiply upper 64 bits [64:127]
1507 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1508 }
1509
1510 // Data
1511
1512 void cmov32( Condition cc, Register dst, Address src);
1513 void cmov32( Condition cc, Register dst, Register src);
1514
1515 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1516
1517 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1518 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1519
1520 void movoop(Register dst, jobject obj);
1521 void movoop(Address dst, jobject obj);
1522
1523 void mov_metadata(Register dst, Metadata* obj);
1524 void mov_metadata(Address dst, Metadata* obj);
1525
1526 void movptr(ArrayAddress dst, Register src);
1527 // can this do an lea?
1528 void movptr(Register dst, ArrayAddress src);
1529
1530 void movptr(Register dst, Address src);
1531
1532 #ifdef _LP64
1533 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1534 #else
1535 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1536 #endif
1537
1538 void movptr(Register dst, intptr_t src);
1539 void movptr(Register dst, Register src);
1540 void movptr(Address dst, intptr_t src);
1541
1542 void movptr(Address dst, Register src);
1543
1544 void movptr(Register dst, RegisterOrConstant src) {
1545 if (src.is_constant()) movptr(dst, src.as_constant());
1546 else movptr(dst, src.as_register());
1547 }
1548
1549 #ifdef _LP64
1550 // Generally the next two are only used for moving NULL
1551 // Although there are situations in initializing the mark word where
1552 // they could be used. They are dangerous.
1553
1554 // They only exist on LP64 so that int32_t and intptr_t are not the same
1555 // and we have ambiguous declarations.
1556
1557 void movptr(Address dst, int32_t imm32);
1558 void movptr(Register dst, int32_t imm32);
1559 #endif // _LP64
1560
1561 // to avoid hiding movl
1562 void mov32(AddressLiteral dst, Register src);
1563 void mov32(Register dst, AddressLiteral src);
1564
1565 // to avoid hiding movb
1566 void movbyte(ArrayAddress dst, int src);
1567
1568 // Import other mov() methods from the parent class or else
1569 // they will be hidden by the following overriding declaration.
1570 using Assembler::movdl;
1571 using Assembler::movq;
1572 void movdl(XMMRegister dst, AddressLiteral src);
1573 void movq(XMMRegister dst, AddressLiteral src);
1574
1575 // Can push value or effective address
1576 void pushptr(AddressLiteral src);
1577
1578 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1579 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1580
1581 void pushoop(jobject obj);
1582 void pushklass(Metadata* obj);
1583
1584 // sign extend as need a l to ptr sized element
1585 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1586 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1587
1588 // C2 compiled method's prolog code.
1589 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1590
1591 // clear memory of size 'cnt' qwords, starting at 'base';
1592 // if 'is_large' is set, do not try to produce short loop
1593 void clear_mem(Register base, Register cnt, Register rtmp, bool is_large);
1594
1595 #ifdef COMPILER2
1596 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1597 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1598
1599 // IndexOf strings.
1600 // Small strings are loaded through stack if they cross page boundary.
1601 void string_indexof(Register str1, Register str2,
1602 Register cnt1, Register cnt2,
1603 int int_cnt2, Register result,
1604 XMMRegister vec, Register tmp,
1605 int ae);
1606
1607 // IndexOf for constant substrings with size >= 8 elements
1608 // which don't need to be loaded through stack.
1609 void string_indexofC8(Register str1, Register str2,
1610 Register cnt1, Register cnt2,
1611 int int_cnt2, Register result,
1612 XMMRegister vec, Register tmp,
1613 int ae);
1614
1615 // Smallest code: we don't need to load through stack,
1616 // check string tail.
1617
1618 // helper function for string_compare
1619 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1620 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1621 Address::ScaleFactor scale2, Register index, int ae);
1622 // Compare strings.
1623 void string_compare(Register str1, Register str2,
1624 Register cnt1, Register cnt2, Register result,
1625 XMMRegister vec1, int ae);
1626
1627 // Search for Non-ASCII character (Negative byte value) in a byte array,
1628 // return true if it has any and false otherwise.
1629 void has_negatives(Register ary1, Register len,
1630 Register result, Register tmp1,
1631 XMMRegister vec1, XMMRegister vec2);
1632
1633 // Compare char[] or byte[] arrays.
1634 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1635 Register limit, Register result, Register chr,
1636 XMMRegister vec1, XMMRegister vec2, bool is_char);
1637
1638 #endif
1639
1640 // Fill primitive arrays
1641 void generate_fill(BasicType t, bool aligned,
1642 Register to, Register value, Register count,
1643 Register rtmp, XMMRegister xtmp);
1644
1645 void encode_iso_array(Register src, Register dst, Register len,
1646 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1647 XMMRegister tmp4, Register tmp5, Register result);
1648
1649 #ifdef _LP64
1650 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1651 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1652 Register y, Register y_idx, Register z,
1653 Register carry, Register product,
1654 Register idx, Register kdx);
1655 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1656 Register yz_idx, Register idx,
1657 Register carry, Register product, int offset);
1658 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1659 Register carry, Register carry2,
1660 Register idx, Register jdx,
1661 Register yz_idx1, Register yz_idx2,
1662 Register tmp, Register tmp3, Register tmp4);
1663 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1664 Register yz_idx, Register idx, Register jdx,
1665 Register carry, Register product,
1666 Register carry2);
1667 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1668 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1669 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1670 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1671 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1672 Register tmp2);
1673 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1674 Register rdxReg, Register raxReg);
1675 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1676 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1677 Register tmp3, Register tmp4);
1678 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1679 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1680
1681 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1682 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1683 Register raxReg);
1684 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1685 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1686 Register raxReg);
1687 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1688 Register result, Register tmp1, Register tmp2,
1689 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1690 #endif
1691
1692 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1693 void update_byte_crc32(Register crc, Register val, Register table);
1694 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1695 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1696 // Note on a naming convention:
1697 // Prefix w = register only used on a Westmere+ architecture
1698 // Prefix n = register only used on a Nehalem architecture
1699 #ifdef _LP64
1700 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1701 Register tmp1, Register tmp2, Register tmp3);
1702 #else
1703 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1704 Register tmp1, Register tmp2, Register tmp3,
1705 XMMRegister xtmp1, XMMRegister xtmp2);
1706 #endif
1707 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1708 Register in_out,
1709 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1710 XMMRegister w_xtmp2,
1711 Register tmp1,
1712 Register n_tmp2, Register n_tmp3);
1713 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1714 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1715 Register tmp1, Register tmp2,
1716 Register n_tmp3);
1717 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1718 Register in_out1, Register in_out2, Register in_out3,
1719 Register tmp1, Register tmp2, Register tmp3,
1720 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1721 Register tmp4, Register tmp5,
1722 Register n_tmp6);
1723 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1724 Register tmp1, Register tmp2, Register tmp3,
1725 Register tmp4, Register tmp5, Register tmp6,
1726 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1727 bool is_pclmulqdq_supported);
1728 // Fold 128-bit data chunk
1729 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1730 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1731 // Fold 8-bit data
1732 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1733 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1734
1735 // Compress char[] array to byte[].
1736 void char_array_compress(Register src, Register dst, Register len,
1737 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1738 XMMRegister tmp4, Register tmp5, Register result);
1739
1740 // Inflate byte[] array to char[].
1741 void byte_array_inflate(Register src, Register dst, Register len,
1742 XMMRegister tmp1, Register tmp2);
1743
1744 };
1745
1746 /**
1747 * class SkipIfEqual:
1748 *
1749 * Instantiating this class will result in assembly code being output that will
1750 * jump around any code emitted between the creation of the instance and it's
1751 * automatic destruction at the end of a scope block, depending on the value of
1752 * the flag passed to the constructor, which will be checked at run-time.
1753 */
1754 class SkipIfEqual {
1755 private:
1756 MacroAssembler* _masm;
1757 Label _label;
1758
1759 public:
1760 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1761 ~SkipIfEqual();
1762 };
1763
1764 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP