1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
  26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "utilities/macros.hpp"
  30 #include "runtime/rtmLocking.hpp"
  31 
  32 // MacroAssembler extends Assembler by frequently used macros.
  33 //
  34 // Instructions for which a 'better' code sequence exists depending
  35 // on arguments should also go in here.
  36 
  37 class MacroAssembler: public Assembler {
  38   friend class LIR_Assembler;
  39   friend class Runtime1;      // as_Address()
  40 
  41  protected:
  42 
  43   Address as_Address(AddressLiteral adr);
  44   Address as_Address(ArrayAddress adr);
  45 
  46   // Support for VM calls
  47   //
  48   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  49   // may customize this version by overriding it for its purposes (e.g., to save/restore
  50   // additional registers when doing a VM call).
  51 
  52   virtual void call_VM_leaf_base(
  53     address entry_point,               // the entry point
  54     int     number_of_arguments        // the number of arguments to pop after the call
  55   );
  56 
  57   // This is the base routine called by the different versions of call_VM. The interpreter
  58   // may customize this version by overriding it for its purposes (e.g., to save/restore
  59   // additional registers when doing a VM call).
  60   //
  61   // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
  62   // returns the register which contains the thread upon return. If a thread register has been
  63   // specified, the return value will correspond to that register. If no last_java_sp is specified
  64   // (noreg) than rsp will be used instead.
  65   virtual void call_VM_base(           // returns the register containing the thread upon return
  66     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  67     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  68     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  69     address  entry_point,              // the entry point
  70     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  71     bool     check_exceptions          // whether to check for pending exceptions after return
  72   );
  73 
  74   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  75 
  76   // helpers for FPU flag access
  77   // tmp is a temporary register, if none is available use noreg
  78   void save_rax   (Register tmp);
  79   void restore_rax(Register tmp);
  80 
  81  public:
  82   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
  83 
  84  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  85  // The implementation is only non-empty for the InterpreterMacroAssembler,
  86  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  87  virtual void check_and_handle_popframe(Register java_thread);
  88  virtual void check_and_handle_earlyret(Register java_thread);
  89 
  90   // Support for NULL-checks
  91   //
  92   // Generates code that causes a NULL OS exception if the content of reg is NULL.
  93   // If the accessed location is M[reg + offset] and the offset is known, provide the
  94   // offset. No explicit code generation is needed if the offset is within a certain
  95   // range (0 <= offset <= page_size).
  96 
  97   void null_check(Register reg, int offset = -1);
  98   static bool needs_explicit_null_check(intptr_t offset);
  99 
 100   void test_klass_is_value(Register klass, Register temp_reg, Label& is_value);
 101 
 102   void test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable);
 103   void test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable);
 104   void test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened);
 105   void test_value_is_not_buffered(Register value, Register temp_reg, Label& not_buffered);
 106 
 107   // Check klass/oops is flat value type array (oop->_klass->_layout_helper & vt_bit)
 108   void test_flat_array_klass(Register klass, Register temp_reg, Label& is_flat_array);
 109   void test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array);
 110 
 111   void test_oop_is_not_value(Register oop, Register temp, Label& is_not_value);
 112 
 113   // Required platform-specific helpers for Label::patch_instructions.
 114   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 115   void pd_patch_instruction(address branch, address target) {
 116     unsigned char op = branch[0];
 117     assert(op == 0xE8 /* call */ ||
 118         op == 0xE9 /* jmp */ ||
 119         op == 0xEB /* short jmp */ ||
 120         (op & 0xF0) == 0x70 /* short jcc */ ||
 121         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
 122         op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
 123         "Invalid opcode at patch point");
 124 
 125     if (op == 0xEB || (op & 0xF0) == 0x70) {
 126       // short offset operators (jmp and jcc)
 127       char* disp = (char*) &branch[1];
 128       int imm8 = target - (address) &disp[1];
 129       guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
 130       *disp = imm8;
 131     } else {
 132       int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
 133       int imm32 = target - (address) &disp[1];
 134       *disp = imm32;
 135     }
 136   }
 137 
 138   // The following 4 methods return the offset of the appropriate move instruction
 139 
 140   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 141   int load_unsigned_byte(Register dst, Address src);
 142   int load_unsigned_short(Register dst, Address src);
 143 
 144   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 145   int load_signed_byte(Register dst, Address src);
 146   int load_signed_short(Register dst, Address src);
 147 
 148   // Support for sign-extension (hi:lo = extend_sign(lo))
 149   void extend_sign(Register hi, Register lo);
 150 
 151   // Load and store values by size and signed-ness
 152   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 153   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 154 
 155   // Support for inc/dec with optimal instruction selection depending on value
 156 
 157   void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
 158   void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
 159 
 160   void decrementl(Address dst, int value = 1);
 161   void decrementl(Register reg, int value = 1);
 162 
 163   void decrementq(Register reg, int value = 1);
 164   void decrementq(Address dst, int value = 1);
 165 
 166   void incrementl(Address dst, int value = 1);
 167   void incrementl(Register reg, int value = 1);
 168 
 169   void incrementq(Register reg, int value = 1);
 170   void incrementq(Address dst, int value = 1);
 171 
 172   // special instructions for EVEX
 173   void setvectmask(Register dst, Register src);
 174   void restorevectmask();
 175 
 176   // Support optimal SSE move instructions.
 177   void movflt(XMMRegister dst, XMMRegister src) {
 178     if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
 179     else                       { movss (dst, src); return; }
 180   }
 181   void movflt(XMMRegister dst, Address src) { movss(dst, src); }
 182   void movflt(XMMRegister dst, AddressLiteral src);
 183   void movflt(Address dst, XMMRegister src) { movss(dst, src); }
 184 
 185   void movdbl(XMMRegister dst, XMMRegister src) {
 186     if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
 187     else                       { movsd (dst, src); return; }
 188   }
 189 
 190   void movdbl(XMMRegister dst, AddressLiteral src);
 191 
 192   void movdbl(XMMRegister dst, Address src) {
 193     if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
 194     else                         { movlpd(dst, src); return; }
 195   }
 196   void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
 197 
 198   void incrementl(AddressLiteral dst);
 199   void incrementl(ArrayAddress dst);
 200 
 201   void incrementq(AddressLiteral dst);
 202 
 203   // Alignment
 204   void align(int modulus);
 205   void align(int modulus, int target);
 206 
 207   // A 5 byte nop that is safe for patching (see patch_verified_entry)
 208   void fat_nop();
 209 
 210   // Stack frame creation/removal
 211   void enter();
 212   void leave();
 213 
 214   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 215   // The pointer will be loaded into the thread register.
 216   void get_thread(Register thread);
 217 
 218 
 219   // Support for VM calls
 220   //
 221   // It is imperative that all calls into the VM are handled via the call_VM macros.
 222   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 223   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 224 
 225 
 226   void call_VM(Register oop_result,
 227                address entry_point,
 228                bool check_exceptions = true);
 229   void call_VM(Register oop_result,
 230                address entry_point,
 231                Register arg_1,
 232                bool check_exceptions = true);
 233   void call_VM(Register oop_result,
 234                address entry_point,
 235                Register arg_1, Register arg_2,
 236                bool check_exceptions = true);
 237   void call_VM(Register oop_result,
 238                address entry_point,
 239                Register arg_1, Register arg_2, Register arg_3,
 240                bool check_exceptions = true);
 241 
 242   // Overloadings with last_Java_sp
 243   void call_VM(Register oop_result,
 244                Register last_java_sp,
 245                address entry_point,
 246                int number_of_arguments = 0,
 247                bool check_exceptions = true);
 248   void call_VM(Register oop_result,
 249                Register last_java_sp,
 250                address entry_point,
 251                Register arg_1, bool
 252                check_exceptions = true);
 253   void call_VM(Register oop_result,
 254                Register last_java_sp,
 255                address entry_point,
 256                Register arg_1, Register arg_2,
 257                bool check_exceptions = true);
 258   void call_VM(Register oop_result,
 259                Register last_java_sp,
 260                address entry_point,
 261                Register arg_1, Register arg_2, Register arg_3,
 262                bool check_exceptions = true);
 263 
 264   void get_vm_result  (Register oop_result, Register thread);
 265   void get_vm_result_2(Register metadata_result, Register thread);
 266 
 267   // These always tightly bind to MacroAssembler::call_VM_base
 268   // bypassing the virtual implementation
 269   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 270   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 271   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 272   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 273   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 274 
 275   void call_VM_leaf0(address entry_point);
 276   void call_VM_leaf(address entry_point,
 277                     int number_of_arguments = 0);
 278   void call_VM_leaf(address entry_point,
 279                     Register arg_1);
 280   void call_VM_leaf(address entry_point,
 281                     Register arg_1, Register arg_2);
 282   void call_VM_leaf(address entry_point,
 283                     Register arg_1, Register arg_2, Register arg_3);
 284 
 285   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 286   // bypassing the virtual implementation
 287   void super_call_VM_leaf(address entry_point);
 288   void super_call_VM_leaf(address entry_point, Register arg_1);
 289   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 290   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 291   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 292 
 293   // last Java Frame (fills frame anchor)
 294   void set_last_Java_frame(Register thread,
 295                            Register last_java_sp,
 296                            Register last_java_fp,
 297                            address last_java_pc);
 298 
 299   // thread in the default location (r15_thread on 64bit)
 300   void set_last_Java_frame(Register last_java_sp,
 301                            Register last_java_fp,
 302                            address last_java_pc);
 303 
 304   void reset_last_Java_frame(Register thread, bool clear_fp);
 305 
 306   // thread in the default location (r15_thread on 64bit)
 307   void reset_last_Java_frame(bool clear_fp);
 308 
 309   // Stores
 310   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 311   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 312 
 313   void resolve_jobject(Register value, Register thread, Register tmp);
 314   void clear_jweak_tag(Register possibly_jweak);
 315 
 316 #if INCLUDE_ALL_GCS
 317 
 318   void g1_write_barrier_pre(Register obj,
 319                             Register pre_val,
 320                             Register thread,
 321                             Register tmp,
 322                             bool tosca_live,
 323                             bool expand_call);
 324 
 325   void g1_write_barrier_post(Register store_addr,
 326                              Register new_val,
 327                              Register thread,
 328                              Register tmp,
 329                              Register tmp2);
 330 
 331 #endif // INCLUDE_ALL_GCS
 332 
 333   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 334   void c2bool(Register x);
 335 
 336   // C++ bool manipulation
 337 
 338   void movbool(Register dst, Address src);
 339   void movbool(Address dst, bool boolconst);
 340   void movbool(Address dst, Register src);
 341   void testbool(Register dst);
 342 
 343   void resolve_oop_handle(Register result);
 344   void load_mirror(Register mirror, Register method);
 345 
 346   // oop manipulations
 347   void load_klass(Register dst, Register src);
 348   void store_klass(Register dst, Register src);
 349 
 350   void load_heap_oop(Register dst, Address src);
 351   void load_heap_oop_not_null(Register dst, Address src);
 352   void store_heap_oop(Address dst, Register src);
 353   void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
 354 
 355   // Used for storing NULL. All other oop constants should be
 356   // stored using routines that take a jobject.
 357   void store_heap_oop_null(Address dst);
 358 
 359   void load_prototype_header(Register dst, Register src);
 360 
 361 #ifdef _LP64
 362   void store_klass_gap(Register dst, Register src);
 363 
 364   // This dummy is to prevent a call to store_heap_oop from
 365   // converting a zero (like NULL) into a Register by giving
 366   // the compiler two choices it can't resolve
 367 
 368   void store_heap_oop(Address dst, void* dummy);
 369 
 370   void encode_heap_oop(Register r);
 371   void decode_heap_oop(Register r);
 372   void encode_heap_oop_not_null(Register r);
 373   void decode_heap_oop_not_null(Register r);
 374   void encode_heap_oop_not_null(Register dst, Register src);
 375   void decode_heap_oop_not_null(Register dst, Register src);
 376 
 377   void set_narrow_oop(Register dst, jobject obj);
 378   void set_narrow_oop(Address dst, jobject obj);
 379   void cmp_narrow_oop(Register dst, jobject obj);
 380   void cmp_narrow_oop(Address dst, jobject obj);
 381 
 382   void encode_klass_not_null(Register r);
 383   void decode_klass_not_null(Register r);
 384   void encode_klass_not_null(Register dst, Register src);
 385   void decode_klass_not_null(Register dst, Register src);
 386   void set_narrow_klass(Register dst, Klass* k);
 387   void set_narrow_klass(Address dst, Klass* k);
 388   void cmp_narrow_klass(Register dst, Klass* k);
 389   void cmp_narrow_klass(Address dst, Klass* k);
 390 
 391   // Returns the byte size of the instructions generated by decode_klass_not_null()
 392   // when compressed klass pointers are being used.
 393   static int instr_size_for_decode_klass_not_null();
 394 
 395   // if heap base register is used - reinit it with the correct value
 396   void reinit_heapbase();
 397 
 398   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 399 
 400 #endif // _LP64
 401 
 402   // Int division/remainder for Java
 403   // (as idivl, but checks for special case as described in JVM spec.)
 404   // returns idivl instruction offset for implicit exception handling
 405   int corrected_idivl(Register reg);
 406 
 407   // Long division/remainder for Java
 408   // (as idivq, but checks for special case as described in JVM spec.)
 409   // returns idivq instruction offset for implicit exception handling
 410   int corrected_idivq(Register reg);
 411 
 412   void int3();
 413 
 414   // Long operation macros for a 32bit cpu
 415   // Long negation for Java
 416   void lneg(Register hi, Register lo);
 417 
 418   // Long multiplication for Java
 419   // (destroys contents of eax, ebx, ecx and edx)
 420   void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
 421 
 422   // Long shifts for Java
 423   // (semantics as described in JVM spec.)
 424   void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
 425   void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
 426 
 427   // Long compare for Java
 428   // (semantics as described in JVM spec.)
 429   void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
 430 
 431 
 432   // misc
 433 
 434   // Sign extension
 435   void sign_extend_short(Register reg);
 436   void sign_extend_byte(Register reg);
 437 
 438   // Division by power of 2, rounding towards 0
 439   void division_with_shift(Register reg, int shift_value);
 440 
 441   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
 442   //
 443   // CF (corresponds to C0) if x < y
 444   // PF (corresponds to C2) if unordered
 445   // ZF (corresponds to C3) if x = y
 446   //
 447   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 448   // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
 449   void fcmp(Register tmp);
 450   // Variant of the above which allows y to be further down the stack
 451   // and which only pops x and y if specified. If pop_right is
 452   // specified then pop_left must also be specified.
 453   void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
 454 
 455   // Floating-point comparison for Java
 456   // Compares the top-most stack entries on the FPU stack and stores the result in dst.
 457   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 458   // (semantics as described in JVM spec.)
 459   void fcmp2int(Register dst, bool unordered_is_less);
 460   // Variant of the above which allows y to be further down the stack
 461   // and which only pops x and y if specified. If pop_right is
 462   // specified then pop_left must also be specified.
 463   void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
 464 
 465   // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
 466   // tmp is a temporary register, if none is available use noreg
 467   void fremr(Register tmp);
 468 
 469   // dst = c = a * b + c
 470   void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 471   void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 472 
 473   void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 474   void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 475   void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 476   void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 477 
 478 
 479   // same as fcmp2int, but using SSE2
 480   void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 481   void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 482 
 483   // branch to L if FPU flag C2 is set/not set
 484   // tmp is a temporary register, if none is available use noreg
 485   void jC2 (Register tmp, Label& L);
 486   void jnC2(Register tmp, Label& L);
 487 
 488   // Pop ST (ffree & fincstp combined)
 489   void fpop();
 490 
 491   // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
 492   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 493   void load_float(Address src);
 494 
 495   // Store float value to 'address'. If UseSSE >= 1, the value is stored
 496   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 497   void store_float(Address dst);
 498 
 499   // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
 500   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 501   void load_double(Address src);
 502 
 503   // Store double value to 'address'. If UseSSE >= 2, the value is stored
 504   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 505   void store_double(Address dst);
 506 
 507   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
 508   void push_fTOS();
 509 
 510   // pops double TOS element from CPU stack and pushes on FPU stack
 511   void pop_fTOS();
 512 
 513   void empty_FPU_stack();
 514 
 515   void push_IU_state();
 516   void pop_IU_state();
 517 
 518   void push_FPU_state();
 519   void pop_FPU_state();
 520 
 521   void push_CPU_state();
 522   void pop_CPU_state();
 523 
 524   // Round up to a power of two
 525   void round_to(Register reg, int modulus);
 526 
 527   // Callee saved registers handling
 528   void push_callee_saved_registers();
 529   void pop_callee_saved_registers();
 530 
 531   // allocation
 532   void eden_allocate(
 533     Register obj,                      // result: pointer to object after successful allocation
 534     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 535     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 536     Register t1,                       // temp register
 537     Label&   slow_case                 // continuation point if fast allocation fails
 538   );
 539   void tlab_allocate(
 540     Register obj,                      // result: pointer to object after successful allocation
 541     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 542     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 543     Register t1,                       // temp register
 544     Register t2,                       // temp register
 545     Label&   slow_case                 // continuation point if fast allocation fails
 546   );
 547   void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
 548 
 549   void incr_allocated_bytes(Register thread,
 550                             Register var_size_in_bytes, int con_size_in_bytes,
 551                             Register t1 = noreg);
 552 
 553   // interface method calling
 554   void lookup_interface_method(Register recv_klass,
 555                                Register intf_klass,
 556                                RegisterOrConstant itable_index,
 557                                Register method_result,
 558                                Register scan_temp,
 559                                Label& no_such_interface,
 560                                bool return_method = true);
 561 
 562   // virtual method calling
 563   void lookup_virtual_method(Register recv_klass,
 564                              RegisterOrConstant vtable_index,
 565                              Register method_result);
 566 
 567   // Test sub_klass against super_klass, with fast and slow paths.
 568 
 569   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 570   // One of the three labels can be NULL, meaning take the fall-through.
 571   // If super_check_offset is -1, the value is loaded up from super_klass.
 572   // No registers are killed, except temp_reg.
 573   void check_klass_subtype_fast_path(Register sub_klass,
 574                                      Register super_klass,
 575                                      Register temp_reg,
 576                                      Label* L_success,
 577                                      Label* L_failure,
 578                                      Label* L_slow_path,
 579                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 580 
 581   // The rest of the type check; must be wired to a corresponding fast path.
 582   // It does not repeat the fast path logic, so don't use it standalone.
 583   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 584   // Updates the sub's secondary super cache as necessary.
 585   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 586   void check_klass_subtype_slow_path(Register sub_klass,
 587                                      Register super_klass,
 588                                      Register temp_reg,
 589                                      Register temp2_reg,
 590                                      Label* L_success,
 591                                      Label* L_failure,
 592                                      bool set_cond_codes = false);
 593 
 594   // Simplified, combined version, good for typical uses.
 595   // Falls through on failure.
 596   void check_klass_subtype(Register sub_klass,
 597                            Register super_klass,
 598                            Register temp_reg,
 599                            Label& L_success);
 600 
 601   // method handles (JSR 292)
 602   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 603 
 604   //----
 605   void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
 606 
 607   // Debugging
 608 
 609   // only if +VerifyOops
 610   // TODO: Make these macros with file and line like sparc version!
 611   void verify_oop(Register reg, const char* s = "broken oop");
 612   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 613 
 614   // TODO: verify method and klass metadata (compare against vptr?)
 615   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 616   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 617 
 618 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 619 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 620 
 621   // only if +VerifyFPU
 622   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 623 
 624   // Verify or restore cpu control state after JNI call
 625   void restore_cpu_control_state_after_jni();
 626 
 627   // prints msg, dumps registers and stops execution
 628   void stop(const char* msg);
 629 
 630   // prints msg and continues
 631   void warn(const char* msg);
 632 
 633   // dumps registers and other state
 634   void print_state();
 635 
 636   static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
 637   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 638   static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
 639   static void print_state64(int64_t pc, int64_t regs[]);
 640 
 641   void os_breakpoint();
 642 
 643   void untested()                                { stop("untested"); }
 644 
 645   void unimplemented(const char* what = "");
 646 
 647   void should_not_reach_here()                   { stop("should not reach here"); }
 648 
 649   void print_CPU_state();
 650 
 651   // Stack overflow checking
 652   void bang_stack_with_offset(int offset) {
 653     // stack grows down, caller passes positive offset
 654     assert(offset > 0, "must bang with negative offset");
 655     movl(Address(rsp, (-offset)), rax);
 656   }
 657 
 658   // Writes to stack successive pages until offset reached to check for
 659   // stack overflow + shadow pages.  Also, clobbers tmp
 660   void bang_stack_size(Register size, Register tmp);
 661 
 662   // Check for reserved stack access in method being exited (for JIT)
 663   void reserved_stack_check();
 664 
 665   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 666                                                 Register tmp,
 667                                                 int offset);
 668 
 669   // Support for serializing memory accesses between threads
 670   void serialize_memory(Register thread, Register tmp);
 671 
 672   // If thread_reg is != noreg the code assumes the register passed contains
 673   // the thread (required on 64 bit).
 674   void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
 675 
 676   void verify_tlab();
 677 
 678   // Biased locking support
 679   // lock_reg and obj_reg must be loaded up with the appropriate values.
 680   // swap_reg must be rax, and is killed.
 681   // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
 682   // be killed; if not supplied, push/pop will be used internally to
 683   // allocate a temporary (inefficient, avoid if possible).
 684   // Optional slow case is for implementations (interpreter and C1) which branch to
 685   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 686   // Returns offset of first potentially-faulting instruction for null
 687   // check info (currently consumed only by C1). If
 688   // swap_reg_contains_mark is true then returns -1 as it is assumed
 689   // the calling code has already passed any potential faults.
 690   int biased_locking_enter(Register lock_reg, Register obj_reg,
 691                            Register swap_reg, Register tmp_reg,
 692                            bool swap_reg_contains_mark,
 693                            Label& done, Label* slow_case = NULL,
 694                            BiasedLockingCounters* counters = NULL);
 695   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 696 #ifdef COMPILER2
 697   // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
 698   // See full desription in macroAssembler_x86.cpp.
 699   void fast_lock(Register obj, Register box, Register tmp,
 700                  Register scr, Register cx1, Register cx2,
 701                  BiasedLockingCounters* counters,
 702                  RTMLockingCounters* rtm_counters,
 703                  RTMLockingCounters* stack_rtm_counters,
 704                  Metadata* method_data,
 705                  bool use_rtm, bool profile_rtm);
 706   void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
 707 #if INCLUDE_RTM_OPT
 708   void rtm_counters_update(Register abort_status, Register rtm_counters);
 709   void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
 710   void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
 711                                    RTMLockingCounters* rtm_counters,
 712                                    Metadata* method_data);
 713   void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
 714                      RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
 715   void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
 716   void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
 717   void rtm_stack_locking(Register obj, Register tmp, Register scr,
 718                          Register retry_on_abort_count,
 719                          RTMLockingCounters* stack_rtm_counters,
 720                          Metadata* method_data, bool profile_rtm,
 721                          Label& DONE_LABEL, Label& IsInflated);
 722   void rtm_inflated_locking(Register obj, Register box, Register tmp,
 723                             Register scr, Register retry_on_busy_count,
 724                             Register retry_on_abort_count,
 725                             RTMLockingCounters* rtm_counters,
 726                             Metadata* method_data, bool profile_rtm,
 727                             Label& DONE_LABEL);
 728 #endif
 729 #endif
 730 
 731   Condition negate_condition(Condition cond);
 732 
 733   // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
 734   // operands. In general the names are modified to avoid hiding the instruction in Assembler
 735   // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
 736   // here in MacroAssembler. The major exception to this rule is call
 737 
 738   // Arithmetics
 739 
 740 
 741   void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
 742   void addptr(Address dst, Register src);
 743 
 744   void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
 745   void addptr(Register dst, int32_t src);
 746   void addptr(Register dst, Register src);
 747   void addptr(Register dst, RegisterOrConstant src) {
 748     if (src.is_constant()) addptr(dst, (int) src.as_constant());
 749     else                   addptr(dst,       src.as_register());
 750   }
 751 
 752   void andptr(Register dst, int32_t src);
 753   void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
 754 
 755   void cmp8(AddressLiteral src1, int imm);
 756 
 757   // renamed to drag out the casting of address to int32_t/intptr_t
 758   void cmp32(Register src1, int32_t imm);
 759 
 760   void cmp32(AddressLiteral src1, int32_t imm);
 761   // compare reg - mem, or reg - &mem
 762   void cmp32(Register src1, AddressLiteral src2);
 763 
 764   void cmp32(Register src1, Address src2);
 765 
 766 #ifndef _LP64
 767   void cmpklass(Address dst, Metadata* obj);
 768   void cmpklass(Register dst, Metadata* obj);
 769   void cmpoop(Address dst, jobject obj);
 770 #endif // _LP64
 771 
 772   void cmpoop(Register src1, Register src2);
 773   void cmpoop(Register src1, Address src2);
 774   void cmpoop(Register dst, jobject obj);
 775 
 776   // NOTE src2 must be the lval. This is NOT an mem-mem compare
 777   void cmpptr(Address src1, AddressLiteral src2);
 778 
 779   void cmpptr(Register src1, AddressLiteral src2);
 780 
 781   void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 782   void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 783   // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 784 
 785   void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 786   void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 787 
 788   // cmp64 to avoild hiding cmpq
 789   void cmp64(Register src1, AddressLiteral src);
 790 
 791   void cmpxchgptr(Register reg, Address adr);
 792 
 793   void locked_cmpxchgptr(Register reg, AddressLiteral adr);
 794 
 795 
 796   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
 797   void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
 798 
 799 
 800   void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
 801 
 802   void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
 803 
 804   void shlptr(Register dst, int32_t shift);
 805   void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
 806 
 807   void shrptr(Register dst, int32_t shift);
 808   void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
 809 
 810   void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
 811   void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
 812 
 813   void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 814 
 815   void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 816   void subptr(Register dst, int32_t src);
 817   // Force generation of a 4 byte immediate value even if it fits into 8bit
 818   void subptr_imm32(Register dst, int32_t src);
 819   void subptr(Register dst, Register src);
 820   void subptr(Register dst, RegisterOrConstant src) {
 821     if (src.is_constant()) subptr(dst, (int) src.as_constant());
 822     else                   subptr(dst,       src.as_register());
 823   }
 824 
 825   void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 826   void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 827 
 828   void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 829   void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 830 
 831   void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
 832 
 833 
 834 
 835   // Helper functions for statistics gathering.
 836   // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
 837   void cond_inc32(Condition cond, AddressLiteral counter_addr);
 838   // Unconditional atomic increment.
 839   void atomic_incl(Address counter_addr);
 840   void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
 841 #ifdef _LP64
 842   void atomic_incq(Address counter_addr);
 843   void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
 844 #endif
 845   void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
 846   void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
 847 
 848   void lea(Register dst, AddressLiteral adr);
 849   void lea(Address dst, AddressLiteral adr);
 850   void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
 851 
 852   void leal32(Register dst, Address src) { leal(dst, src); }
 853 
 854   // Import other testl() methods from the parent class or else
 855   // they will be hidden by the following overriding declaration.
 856   using Assembler::testl;
 857   void testl(Register dst, AddressLiteral src);
 858 
 859   void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 860   void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 861   void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 862   void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
 863 
 864   void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
 865   void testptr(Register src1, Register src2);
 866 
 867   void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 868   void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 869 
 870   // Calls
 871 
 872   void call(Label& L, relocInfo::relocType rtype);
 873   void call(Register entry);
 874 
 875   // NOTE: this call transfers to the effective address of entry NOT
 876   // the address contained by entry. This is because this is more natural
 877   // for jumps/calls.
 878   void call(AddressLiteral entry);
 879 
 880   // Emit the CompiledIC call idiom
 881   void ic_call(address entry, jint method_index = 0);
 882 
 883   // Jumps
 884 
 885   // NOTE: these jumps tranfer to the effective address of dst NOT
 886   // the address contained by dst. This is because this is more natural
 887   // for jumps/calls.
 888   void jump(AddressLiteral dst);
 889   void jump_cc(Condition cc, AddressLiteral dst);
 890 
 891   // 32bit can do a case table jump in one instruction but we no longer allow the base
 892   // to be installed in the Address class. This jump will tranfers to the address
 893   // contained in the location described by entry (not the address of entry)
 894   void jump(ArrayAddress entry);
 895 
 896   // Floating
 897 
 898   void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
 899   void andpd(XMMRegister dst, AddressLiteral src);
 900   void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
 901 
 902   void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
 903   void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
 904   void andps(XMMRegister dst, AddressLiteral src);
 905 
 906   void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
 907   void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
 908   void comiss(XMMRegister dst, AddressLiteral src);
 909 
 910   void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
 911   void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
 912   void comisd(XMMRegister dst, AddressLiteral src);
 913 
 914   void fadd_s(Address src)        { Assembler::fadd_s(src); }
 915   void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
 916 
 917   void fldcw(Address src) { Assembler::fldcw(src); }
 918   void fldcw(AddressLiteral src);
 919 
 920   void fld_s(int index)   { Assembler::fld_s(index); }
 921   void fld_s(Address src) { Assembler::fld_s(src); }
 922   void fld_s(AddressLiteral src);
 923 
 924   void fld_d(Address src) { Assembler::fld_d(src); }
 925   void fld_d(AddressLiteral src);
 926 
 927   void fld_x(Address src) { Assembler::fld_x(src); }
 928   void fld_x(AddressLiteral src);
 929 
 930   void fmul_s(Address src)        { Assembler::fmul_s(src); }
 931   void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
 932 
 933   void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
 934   void ldmxcsr(AddressLiteral src);
 935 
 936 #ifdef _LP64
 937  private:
 938   void sha256_AVX2_one_round_compute(
 939     Register  reg_old_h,
 940     Register  reg_a,
 941     Register  reg_b,
 942     Register  reg_c,
 943     Register  reg_d,
 944     Register  reg_e,
 945     Register  reg_f,
 946     Register  reg_g,
 947     Register  reg_h,
 948     int iter);
 949   void sha256_AVX2_four_rounds_compute_first(int start);
 950   void sha256_AVX2_four_rounds_compute_last(int start);
 951   void sha256_AVX2_one_round_and_sched(
 952         XMMRegister xmm_0,     /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
 953         XMMRegister xmm_1,     /* ymm5 */  /* full cycle is 16 iterations */
 954         XMMRegister xmm_2,     /* ymm6 */
 955         XMMRegister xmm_3,     /* ymm7 */
 956         Register    reg_a,      /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
 957         Register    reg_b,      /* ebx */    /* full cycle is 8 iterations */
 958         Register    reg_c,      /* edi */
 959         Register    reg_d,      /* esi */
 960         Register    reg_e,      /* r8d */
 961         Register    reg_f,      /* r9d */
 962         Register    reg_g,      /* r10d */
 963         Register    reg_h,      /* r11d */
 964         int iter);
 965 
 966   void addm(int disp, Register r1, Register r2);
 967 
 968  public:
 969   void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 970                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 971                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 972                    bool multi_block, XMMRegister shuf_mask);
 973 #endif
 974 
 975 #ifdef _LP64
 976  private:
 977   void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
 978                                      Register e, Register f, Register g, Register h, int iteration);
 979 
 980   void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 981                                           Register a, Register b, Register c, Register d, Register e, Register f,
 982                                           Register g, Register h, int iteration);
 983 
 984   void addmq(int disp, Register r1, Register r2);
 985  public:
 986   void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 987                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 988                    Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
 989                    XMMRegister shuf_mask);
 990 #endif
 991 
 992   void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
 993                  XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
 994                  Register buf, Register state, Register ofs, Register limit, Register rsp,
 995                  bool multi_block);
 996 
 997 #ifdef _LP64
 998   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 999                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1000                    Register buf, Register state, Register ofs, Register limit, Register rsp,
1001                    bool multi_block, XMMRegister shuf_mask);
1002 #else
1003   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1004                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1005                    Register buf, Register state, Register ofs, Register limit, Register rsp,
1006                    bool multi_block);
1007 #endif
1008 
1009   void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1010                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1011                 Register rax, Register rcx, Register rdx, Register tmp);
1012 
1013 #ifdef _LP64
1014   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1015                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1016                 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
1017 
1018   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1019                   XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1020                   Register rax, Register rcx, Register rdx, Register r11);
1021 
1022   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1023                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1024                 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1025 
1026   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1027                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1028                 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1029                 Register tmp3, Register tmp4);
1030 
1031   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1032                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1033                 Register rax, Register rcx, Register rdx, Register tmp1,
1034                 Register tmp2, Register tmp3, Register tmp4);
1035   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1036                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1037                 Register rax, Register rcx, Register rdx, Register tmp1,
1038                 Register tmp2, Register tmp3, Register tmp4);
1039 #else
1040   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1041                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1042                 Register rax, Register rcx, Register rdx, Register tmp1);
1043 
1044   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1045                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1046                 Register rax, Register rcx, Register rdx, Register tmp);
1047 
1048   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1049                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1050                 Register rdx, Register tmp);
1051 
1052   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1053                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1054                 Register rax, Register rbx, Register rdx);
1055 
1056   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1057                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1058                 Register rax, Register rcx, Register rdx, Register tmp);
1059 
1060   void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1061                         Register edx, Register ebx, Register esi, Register edi,
1062                         Register ebp, Register esp);
1063 
1064   void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1065                          Register esi, Register edi, Register ebp, Register esp);
1066 
1067   void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1068                         Register edx, Register ebx, Register esi, Register edi,
1069                         Register ebp, Register esp);
1070 
1071   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1072                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1073                 Register rax, Register rcx, Register rdx, Register tmp);
1074 #endif
1075 
1076   void increase_precision();
1077   void restore_precision();
1078 
1079 private:
1080 
1081   // these are private because users should be doing movflt/movdbl
1082 
1083   void movss(Address dst, XMMRegister src)     { Assembler::movss(dst, src); }
1084   void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1085   void movss(XMMRegister dst, Address src)     { Assembler::movss(dst, src); }
1086   void movss(XMMRegister dst, AddressLiteral src);
1087 
1088   void movlpd(XMMRegister dst, Address src)    {Assembler::movlpd(dst, src); }
1089   void movlpd(XMMRegister dst, AddressLiteral src);
1090 
1091 public:
1092 
1093   void addsd(XMMRegister dst, XMMRegister src)    { Assembler::addsd(dst, src); }
1094   void addsd(XMMRegister dst, Address src)        { Assembler::addsd(dst, src); }
1095   void addsd(XMMRegister dst, AddressLiteral src);
1096 
1097   void addss(XMMRegister dst, XMMRegister src)    { Assembler::addss(dst, src); }
1098   void addss(XMMRegister dst, Address src)        { Assembler::addss(dst, src); }
1099   void addss(XMMRegister dst, AddressLiteral src);
1100 
1101   void addpd(XMMRegister dst, XMMRegister src)    { Assembler::addpd(dst, src); }
1102   void addpd(XMMRegister dst, Address src)        { Assembler::addpd(dst, src); }
1103   void addpd(XMMRegister dst, AddressLiteral src);
1104 
1105   void divsd(XMMRegister dst, XMMRegister src)    { Assembler::divsd(dst, src); }
1106   void divsd(XMMRegister dst, Address src)        { Assembler::divsd(dst, src); }
1107   void divsd(XMMRegister dst, AddressLiteral src);
1108 
1109   void divss(XMMRegister dst, XMMRegister src)    { Assembler::divss(dst, src); }
1110   void divss(XMMRegister dst, Address src)        { Assembler::divss(dst, src); }
1111   void divss(XMMRegister dst, AddressLiteral src);
1112 
1113   // Move Unaligned Double Quadword
1114   void movdqu(Address     dst, XMMRegister src);
1115   void movdqu(XMMRegister dst, Address src);
1116   void movdqu(XMMRegister dst, XMMRegister src);
1117   void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1118   // AVX Unaligned forms
1119   void vmovdqu(Address     dst, XMMRegister src);
1120   void vmovdqu(XMMRegister dst, Address src);
1121   void vmovdqu(XMMRegister dst, XMMRegister src);
1122   void vmovdqu(XMMRegister dst, AddressLiteral src);
1123 
1124   // Move Aligned Double Quadword
1125   void movdqa(XMMRegister dst, Address src)       { Assembler::movdqa(dst, src); }
1126   void movdqa(XMMRegister dst, XMMRegister src)   { Assembler::movdqa(dst, src); }
1127   void movdqa(XMMRegister dst, AddressLiteral src);
1128 
1129   void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1130   void movsd(Address dst, XMMRegister src)     { Assembler::movsd(dst, src); }
1131   void movsd(XMMRegister dst, Address src)     { Assembler::movsd(dst, src); }
1132   void movsd(XMMRegister dst, AddressLiteral src);
1133 
1134   void mulpd(XMMRegister dst, XMMRegister src)    { Assembler::mulpd(dst, src); }
1135   void mulpd(XMMRegister dst, Address src)        { Assembler::mulpd(dst, src); }
1136   void mulpd(XMMRegister dst, AddressLiteral src);
1137 
1138   void mulsd(XMMRegister dst, XMMRegister src)    { Assembler::mulsd(dst, src); }
1139   void mulsd(XMMRegister dst, Address src)        { Assembler::mulsd(dst, src); }
1140   void mulsd(XMMRegister dst, AddressLiteral src);
1141 
1142   void mulss(XMMRegister dst, XMMRegister src)    { Assembler::mulss(dst, src); }
1143   void mulss(XMMRegister dst, Address src)        { Assembler::mulss(dst, src); }
1144   void mulss(XMMRegister dst, AddressLiteral src);
1145 
1146   // Carry-Less Multiplication Quadword
1147   void pclmulldq(XMMRegister dst, XMMRegister src) {
1148     // 0x00 - multiply lower 64 bits [0:63]
1149     Assembler::pclmulqdq(dst, src, 0x00);
1150   }
1151   void pclmulhdq(XMMRegister dst, XMMRegister src) {
1152     // 0x11 - multiply upper 64 bits [64:127]
1153     Assembler::pclmulqdq(dst, src, 0x11);
1154   }
1155 
1156   void pcmpeqb(XMMRegister dst, XMMRegister src);
1157   void pcmpeqw(XMMRegister dst, XMMRegister src);
1158 
1159   void pcmpestri(XMMRegister dst, Address src, int imm8);
1160   void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1161 
1162   void pmovzxbw(XMMRegister dst, XMMRegister src);
1163   void pmovzxbw(XMMRegister dst, Address src);
1164 
1165   void pmovmskb(Register dst, XMMRegister src);
1166 
1167   void ptest(XMMRegister dst, XMMRegister src);
1168 
1169   void sqrtsd(XMMRegister dst, XMMRegister src)    { Assembler::sqrtsd(dst, src); }
1170   void sqrtsd(XMMRegister dst, Address src)        { Assembler::sqrtsd(dst, src); }
1171   void sqrtsd(XMMRegister dst, AddressLiteral src);
1172 
1173   void sqrtss(XMMRegister dst, XMMRegister src)    { Assembler::sqrtss(dst, src); }
1174   void sqrtss(XMMRegister dst, Address src)        { Assembler::sqrtss(dst, src); }
1175   void sqrtss(XMMRegister dst, AddressLiteral src);
1176 
1177   void subsd(XMMRegister dst, XMMRegister src)    { Assembler::subsd(dst, src); }
1178   void subsd(XMMRegister dst, Address src)        { Assembler::subsd(dst, src); }
1179   void subsd(XMMRegister dst, AddressLiteral src);
1180 
1181   void subss(XMMRegister dst, XMMRegister src)    { Assembler::subss(dst, src); }
1182   void subss(XMMRegister dst, Address src)        { Assembler::subss(dst, src); }
1183   void subss(XMMRegister dst, AddressLiteral src);
1184 
1185   void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1186   void ucomiss(XMMRegister dst, Address src)     { Assembler::ucomiss(dst, src); }
1187   void ucomiss(XMMRegister dst, AddressLiteral src);
1188 
1189   void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1190   void ucomisd(XMMRegister dst, Address src)     { Assembler::ucomisd(dst, src); }
1191   void ucomisd(XMMRegister dst, AddressLiteral src);
1192 
1193   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1194   void xorpd(XMMRegister dst, XMMRegister src);
1195   void xorpd(XMMRegister dst, Address src)     { Assembler::xorpd(dst, src); }
1196   void xorpd(XMMRegister dst, AddressLiteral src);
1197 
1198   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1199   void xorps(XMMRegister dst, XMMRegister src);
1200   void xorps(XMMRegister dst, Address src)     { Assembler::xorps(dst, src); }
1201   void xorps(XMMRegister dst, AddressLiteral src);
1202 
1203   // Shuffle Bytes
1204   void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1205   void pshufb(XMMRegister dst, Address src)     { Assembler::pshufb(dst, src); }
1206   void pshufb(XMMRegister dst, AddressLiteral src);
1207   // AVX 3-operands instructions
1208 
1209   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1210   void vaddsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddsd(dst, nds, src); }
1211   void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1212 
1213   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1214   void vaddss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddss(dst, nds, src); }
1215   void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1216 
1217   void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1218   void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1219 
1220   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1221   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1222 
1223   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1224   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1225 
1226   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1227   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1228   void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1229 
1230   void vpbroadcastw(XMMRegister dst, XMMRegister src);
1231 
1232   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1233   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1234 
1235   void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1236   void vpmovmskb(Register dst, XMMRegister src);
1237 
1238   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1239   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1240 
1241   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1242   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1243 
1244   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1245   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1246 
1247   void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1248   void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1249 
1250   void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1251   void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1252 
1253   void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1254   void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1255 
1256   void vptest(XMMRegister dst, XMMRegister src);
1257 
1258   void punpcklbw(XMMRegister dst, XMMRegister src);
1259   void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1260 
1261   void pshufd(XMMRegister dst, Address src, int mode);
1262   void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1263 
1264   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1265   void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1266 
1267   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1268   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandpd(dst, nds, src, vector_len); }
1269   void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1270 
1271   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1272   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandps(dst, nds, src, vector_len); }
1273   void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1274 
1275   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1276   void vdivsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivsd(dst, nds, src); }
1277   void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1278 
1279   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1280   void vdivss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivss(dst, nds, src); }
1281   void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1282 
1283   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1284   void vmulsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulsd(dst, nds, src); }
1285   void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1286 
1287   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1288   void vmulss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulss(dst, nds, src); }
1289   void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1290 
1291   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1292   void vsubsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubsd(dst, nds, src); }
1293   void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1294 
1295   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1296   void vsubss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubss(dst, nds, src); }
1297   void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1298 
1299   void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1300   void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1301 
1302   // AVX Vector instructions
1303 
1304   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1305   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1306   void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1307 
1308   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1309   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1310   void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1311 
1312   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1313     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1314       Assembler::vpxor(dst, nds, src, vector_len);
1315     else
1316       Assembler::vxorpd(dst, nds, src, vector_len);
1317   }
1318   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1319     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1320       Assembler::vpxor(dst, nds, src, vector_len);
1321     else
1322       Assembler::vxorpd(dst, nds, src, vector_len);
1323   }
1324 
1325   // Simple version for AVX2 256bit vectors
1326   void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1327   void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1328 
1329   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1330     if (UseAVX > 2) {
1331       Assembler::vinserti32x4(dst, dst, src, imm8);
1332     } else if (UseAVX > 1) {
1333       // vinserti128 is available only in AVX2
1334       Assembler::vinserti128(dst, nds, src, imm8);
1335     } else {
1336       Assembler::vinsertf128(dst, nds, src, imm8);
1337     }
1338   }
1339 
1340   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1341     if (UseAVX > 2) {
1342       Assembler::vinserti32x4(dst, dst, src, imm8);
1343     } else if (UseAVX > 1) {
1344       // vinserti128 is available only in AVX2
1345       Assembler::vinserti128(dst, nds, src, imm8);
1346     } else {
1347       Assembler::vinsertf128(dst, nds, src, imm8);
1348     }
1349   }
1350 
1351   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1352     if (UseAVX > 2) {
1353       Assembler::vextracti32x4(dst, src, imm8);
1354     } else if (UseAVX > 1) {
1355       // vextracti128 is available only in AVX2
1356       Assembler::vextracti128(dst, src, imm8);
1357     } else {
1358       Assembler::vextractf128(dst, src, imm8);
1359     }
1360   }
1361 
1362   void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1363     if (UseAVX > 2) {
1364       Assembler::vextracti32x4(dst, src, imm8);
1365     } else if (UseAVX > 1) {
1366       // vextracti128 is available only in AVX2
1367       Assembler::vextracti128(dst, src, imm8);
1368     } else {
1369       Assembler::vextractf128(dst, src, imm8);
1370     }
1371   }
1372 
1373   // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1374   void vinserti128_high(XMMRegister dst, XMMRegister src) {
1375     vinserti128(dst, dst, src, 1);
1376   }
1377   void vinserti128_high(XMMRegister dst, Address src) {
1378     vinserti128(dst, dst, src, 1);
1379   }
1380   void vextracti128_high(XMMRegister dst, XMMRegister src) {
1381     vextracti128(dst, src, 1);
1382   }
1383   void vextracti128_high(Address dst, XMMRegister src) {
1384     vextracti128(dst, src, 1);
1385   }
1386 
1387   void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1388     if (UseAVX > 2) {
1389       Assembler::vinsertf32x4(dst, dst, src, 1);
1390     } else {
1391       Assembler::vinsertf128(dst, dst, src, 1);
1392     }
1393   }
1394 
1395   void vinsertf128_high(XMMRegister dst, Address src) {
1396     if (UseAVX > 2) {
1397       Assembler::vinsertf32x4(dst, dst, src, 1);
1398     } else {
1399       Assembler::vinsertf128(dst, dst, src, 1);
1400     }
1401   }
1402 
1403   void vextractf128_high(XMMRegister dst, XMMRegister src) {
1404     if (UseAVX > 2) {
1405       Assembler::vextractf32x4(dst, src, 1);
1406     } else {
1407       Assembler::vextractf128(dst, src, 1);
1408     }
1409   }
1410 
1411   void vextractf128_high(Address dst, XMMRegister src) {
1412     if (UseAVX > 2) {
1413       Assembler::vextractf32x4(dst, src, 1);
1414     } else {
1415       Assembler::vextractf128(dst, src, 1);
1416     }
1417   }
1418 
1419   // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1420   void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1421     Assembler::vinserti64x4(dst, dst, src, 1);
1422   }
1423   void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1424     Assembler::vinsertf64x4(dst, dst, src, 1);
1425   }
1426   void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1427     Assembler::vextracti64x4(dst, src, 1);
1428   }
1429   void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1430     Assembler::vextractf64x4(dst, src, 1);
1431   }
1432   void vextractf64x4_high(Address dst, XMMRegister src) {
1433     Assembler::vextractf64x4(dst, src, 1);
1434   }
1435   void vinsertf64x4_high(XMMRegister dst, Address src) {
1436     Assembler::vinsertf64x4(dst, dst, src, 1);
1437   }
1438 
1439   // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1440   void vinserti128_low(XMMRegister dst, XMMRegister src) {
1441     vinserti128(dst, dst, src, 0);
1442   }
1443   void vinserti128_low(XMMRegister dst, Address src) {
1444     vinserti128(dst, dst, src, 0);
1445   }
1446   void vextracti128_low(XMMRegister dst, XMMRegister src) {
1447     vextracti128(dst, src, 0);
1448   }
1449   void vextracti128_low(Address dst, XMMRegister src) {
1450     vextracti128(dst, src, 0);
1451   }
1452 
1453   void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1454     if (UseAVX > 2) {
1455       Assembler::vinsertf32x4(dst, dst, src, 0);
1456     } else {
1457       Assembler::vinsertf128(dst, dst, src, 0);
1458     }
1459   }
1460 
1461   void vinsertf128_low(XMMRegister dst, Address src) {
1462     if (UseAVX > 2) {
1463       Assembler::vinsertf32x4(dst, dst, src, 0);
1464     } else {
1465       Assembler::vinsertf128(dst, dst, src, 0);
1466     }
1467   }
1468 
1469   void vextractf128_low(XMMRegister dst, XMMRegister src) {
1470     if (UseAVX > 2) {
1471       Assembler::vextractf32x4(dst, src, 0);
1472     } else {
1473       Assembler::vextractf128(dst, src, 0);
1474     }
1475   }
1476 
1477   void vextractf128_low(Address dst, XMMRegister src) {
1478     if (UseAVX > 2) {
1479       Assembler::vextractf32x4(dst, src, 0);
1480     } else {
1481       Assembler::vextractf128(dst, src, 0);
1482     }
1483   }
1484 
1485   // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1486   void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1487     Assembler::vinserti64x4(dst, dst, src, 0);
1488   }
1489   void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1490     Assembler::vinsertf64x4(dst, dst, src, 0);
1491   }
1492   void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1493     Assembler::vextracti64x4(dst, src, 0);
1494   }
1495   void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1496     Assembler::vextractf64x4(dst, src, 0);
1497   }
1498   void vextractf64x4_low(Address dst, XMMRegister src) {
1499     Assembler::vextractf64x4(dst, src, 0);
1500   }
1501   void vinsertf64x4_low(XMMRegister dst, Address src) {
1502     Assembler::vinsertf64x4(dst, dst, src, 0);
1503   }
1504 
1505   // Carry-Less Multiplication Quadword
1506   void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1507     // 0x00 - multiply lower 64 bits [0:63]
1508     Assembler::vpclmulqdq(dst, nds, src, 0x00);
1509   }
1510   void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1511     // 0x11 - multiply upper 64 bits [64:127]
1512     Assembler::vpclmulqdq(dst, nds, src, 0x11);
1513   }
1514 
1515   // Data
1516 
1517   void cmov32( Condition cc, Register dst, Address  src);
1518   void cmov32( Condition cc, Register dst, Register src);
1519 
1520   void cmov(   Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1521 
1522   void cmovptr(Condition cc, Register dst, Address  src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1523   void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1524 
1525   void movoop(Register dst, jobject obj);
1526   void movoop(Address dst, jobject obj);
1527 
1528   void mov_metadata(Register dst, Metadata* obj);
1529   void mov_metadata(Address dst, Metadata* obj);
1530 
1531   void movptr(ArrayAddress dst, Register src);
1532   // can this do an lea?
1533   void movptr(Register dst, ArrayAddress src);
1534 
1535   void movptr(Register dst, Address src);
1536 
1537 #ifdef _LP64
1538   void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1539 #else
1540   void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1541 #endif
1542 
1543   void movptr(Register dst, intptr_t src);
1544   void movptr(Register dst, Register src);
1545   void movptr(Address dst, intptr_t src);
1546 
1547   void movptr(Address dst, Register src);
1548 
1549   void movptr(Register dst, RegisterOrConstant src) {
1550     if (src.is_constant()) movptr(dst, src.as_constant());
1551     else                   movptr(dst, src.as_register());
1552   }
1553 
1554 #ifdef _LP64
1555   // Generally the next two are only used for moving NULL
1556   // Although there are situations in initializing the mark word where
1557   // they could be used. They are dangerous.
1558 
1559   // They only exist on LP64 so that int32_t and intptr_t are not the same
1560   // and we have ambiguous declarations.
1561 
1562   void movptr(Address dst, int32_t imm32);
1563   void movptr(Register dst, int32_t imm32);
1564 #endif // _LP64
1565 
1566   // to avoid hiding movl
1567   void mov32(AddressLiteral dst, Register src);
1568   void mov32(Register dst, AddressLiteral src);
1569 
1570   // to avoid hiding movb
1571   void movbyte(ArrayAddress dst, int src);
1572 
1573   // Import other mov() methods from the parent class or else
1574   // they will be hidden by the following overriding declaration.
1575   using Assembler::movdl;
1576   using Assembler::movq;
1577   void movdl(XMMRegister dst, AddressLiteral src);
1578   void movq(XMMRegister dst, AddressLiteral src);
1579 
1580   // Can push value or effective address
1581   void pushptr(AddressLiteral src);
1582 
1583   void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1584   void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1585 
1586   void pushoop(jobject obj);
1587   void pushklass(Metadata* obj);
1588 
1589   // sign extend as need a l to ptr sized element
1590   void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1591   void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1592 
1593   // C2 compiled method's prolog code.
1594   void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1595 
1596   // clear memory of size 'cnt' qwords, starting at 'base';
1597   // if 'is_large' is set, do not try to produce short loop
1598   void clear_mem(Register base, Register cnt, Register rtmp, bool is_large);
1599 
1600 #ifdef COMPILER2
1601   void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1602                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1603 
1604   // IndexOf strings.
1605   // Small strings are loaded through stack if they cross page boundary.
1606   void string_indexof(Register str1, Register str2,
1607                       Register cnt1, Register cnt2,
1608                       int int_cnt2,  Register result,
1609                       XMMRegister vec, Register tmp,
1610                       int ae);
1611 
1612   // IndexOf for constant substrings with size >= 8 elements
1613   // which don't need to be loaded through stack.
1614   void string_indexofC8(Register str1, Register str2,
1615                       Register cnt1, Register cnt2,
1616                       int int_cnt2,  Register result,
1617                       XMMRegister vec, Register tmp,
1618                       int ae);
1619 
1620     // Smallest code: we don't need to load through stack,
1621     // check string tail.
1622 
1623   // helper function for string_compare
1624   void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1625                           Address::ScaleFactor scale, Address::ScaleFactor scale1,
1626                           Address::ScaleFactor scale2, Register index, int ae);
1627   // Compare strings.
1628   void string_compare(Register str1, Register str2,
1629                       Register cnt1, Register cnt2, Register result,
1630                       XMMRegister vec1, int ae);
1631 
1632   // Search for Non-ASCII character (Negative byte value) in a byte array,
1633   // return true if it has any and false otherwise.
1634   void has_negatives(Register ary1, Register len,
1635                      Register result, Register tmp1,
1636                      XMMRegister vec1, XMMRegister vec2);
1637 
1638   // Compare char[] or byte[] arrays.
1639   void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1640                      Register limit, Register result, Register chr,
1641                      XMMRegister vec1, XMMRegister vec2, bool is_char);
1642 
1643 #endif
1644 
1645   // Fill primitive arrays
1646   void generate_fill(BasicType t, bool aligned,
1647                      Register to, Register value, Register count,
1648                      Register rtmp, XMMRegister xtmp);
1649 
1650   void encode_iso_array(Register src, Register dst, Register len,
1651                         XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1652                         XMMRegister tmp4, Register tmp5, Register result);
1653 
1654 #ifdef _LP64
1655   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1656   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1657                              Register y, Register y_idx, Register z,
1658                              Register carry, Register product,
1659                              Register idx, Register kdx);
1660   void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1661                               Register yz_idx, Register idx,
1662                               Register carry, Register product, int offset);
1663   void multiply_128_x_128_bmi2_loop(Register y, Register z,
1664                                     Register carry, Register carry2,
1665                                     Register idx, Register jdx,
1666                                     Register yz_idx1, Register yz_idx2,
1667                                     Register tmp, Register tmp3, Register tmp4);
1668   void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1669                                Register yz_idx, Register idx, Register jdx,
1670                                Register carry, Register product,
1671                                Register carry2);
1672   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1673                        Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1674   void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1675                      Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1676   void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1677                             Register tmp2);
1678   void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1679                        Register rdxReg, Register raxReg);
1680   void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1681   void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1682                        Register tmp3, Register tmp4);
1683   void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1684                      Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1685 
1686   void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1687                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1688                Register raxReg);
1689   void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1690                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1691                Register raxReg);
1692   void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1693                            Register result, Register tmp1, Register tmp2,
1694                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1695 #endif
1696 
1697   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1698   void update_byte_crc32(Register crc, Register val, Register table);
1699   void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1700   // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1701   // Note on a naming convention:
1702   // Prefix w = register only used on a Westmere+ architecture
1703   // Prefix n = register only used on a Nehalem architecture
1704 #ifdef _LP64
1705   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1706                        Register tmp1, Register tmp2, Register tmp3);
1707 #else
1708   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1709                        Register tmp1, Register tmp2, Register tmp3,
1710                        XMMRegister xtmp1, XMMRegister xtmp2);
1711 #endif
1712   void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1713                         Register in_out,
1714                         uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1715                         XMMRegister w_xtmp2,
1716                         Register tmp1,
1717                         Register n_tmp2, Register n_tmp3);
1718   void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1719                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1720                        Register tmp1, Register tmp2,
1721                        Register n_tmp3);
1722   void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1723                          Register in_out1, Register in_out2, Register in_out3,
1724                          Register tmp1, Register tmp2, Register tmp3,
1725                          XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1726                          Register tmp4, Register tmp5,
1727                          Register n_tmp6);
1728   void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1729                             Register tmp1, Register tmp2, Register tmp3,
1730                             Register tmp4, Register tmp5, Register tmp6,
1731                             XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1732                             bool is_pclmulqdq_supported);
1733   // Fold 128-bit data chunk
1734   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1735   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1736   // Fold 8-bit data
1737   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1738   void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1739 
1740   // Compress char[] array to byte[].
1741   void char_array_compress(Register src, Register dst, Register len,
1742                            XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1743                            XMMRegister tmp4, Register tmp5, Register result);
1744 
1745   // Inflate byte[] array to char[].
1746   void byte_array_inflate(Register src, Register dst, Register len,
1747                           XMMRegister tmp1, Register tmp2);
1748 
1749 };
1750 
1751 /**
1752  * class SkipIfEqual:
1753  *
1754  * Instantiating this class will result in assembly code being output that will
1755  * jump around any code emitted between the creation of the instance and it's
1756  * automatic destruction at the end of a scope block, depending on the value of
1757  * the flag passed to the constructor, which will be checked at run-time.
1758  */
1759 class SkipIfEqual {
1760  private:
1761   MacroAssembler* _masm;
1762   Label _label;
1763 
1764  public:
1765    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1766    ~SkipIfEqual();
1767 };
1768 
1769 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP