# HG changeset patch # User Edward Nevill edward.nevill@linaro.org # Date 1427732188 -3600 # Mon Mar 30 17:16:28 2015 +0100 # Node ID 29ae29725b67848e5e949b67f5d38883cccbc680 # Parent 621ea7fae5f82f12030c85b28c8111c340ff4e70 Add aarch64 support for FramePointer diff --git a/src/cpu/aarch64/vm/aarch64.ad b/src/cpu/aarch64/vm/aarch64.ad --- a/src/cpu/aarch64/vm/aarch64.ad +++ b/src/cpu/aarch64/vm/aarch64.ad @@ -132,8 +132,8 @@ reg_def R27_H ( NS, SOE, Op_RegI, 27, r27->as_VMReg()->next()); reg_def R28 ( NS, SOE, Op_RegI, 28, r28->as_VMReg() ); // thread reg_def R28_H ( NS, SOE, Op_RegI, 28, r28->as_VMReg()->next()); -reg_def R29 ( NS, NS, Op_RegI, 29, r29->as_VMReg() ); // fp -reg_def R29_H ( NS, NS, Op_RegI, 29, r29->as_VMReg()->next()); +reg_def R29 ( NS, SOE, Op_RegI, 29, r29->as_VMReg() ); // fp +reg_def R29_H ( NS, SOE, Op_RegI, 29, r29->as_VMReg()->next()); reg_def R30 ( NS, NS, Op_RegI, 30, r30->as_VMReg() ); // lr reg_def R30_H ( NS, NS, Op_RegI, 30, r30->as_VMReg()->next()); reg_def R31 ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg() ); // sp @@ -421,7 +421,7 @@ ); // Class for all non-special integer registers -reg_class no_special_reg32( +reg_class no_special_reg32_no_fp( R0, R1, R2, @@ -454,8 +454,43 @@ /* R31 */ // sp ); +reg_class no_special_reg32_with_fp( + R0, + R1, + R2, + R3, + R4, + R5, + R6, + R7, + R10, + R11, + R12, // rmethod + R13, + R14, + R15, + R16, + R17, + R18, + R19, + R20, + R21, + R22, + R23, + R24, + R25, + R26 + /* R27, */ // heapbase + /* R28, */ // thread + R29, // fp + /* R30, */ // lr + /* R31 */ // sp +); + +reg_class_dynamic no_special_reg32(no_special_reg32_no_fp, no_special_reg32_with_fp, %{ FramePointer %}); + // Class for all non-special long integer registers -reg_class no_special_reg( +reg_class no_special_reg_no_fp( R0, R0_H, R1, R1_H, R2, R2_H, @@ -488,6 +523,41 @@ /* R31, R31_H */ // sp ); +reg_class no_special_reg_with_fp( + R0, R0_H, + R1, R1_H, + R2, R2_H, + R3, R3_H, + R4, R4_H, + R5, R5_H, + R6, R6_H, + R7, R7_H, + R10, R10_H, + R11, R11_H, + R12, R12_H, // rmethod + R13, R13_H, + R14, R14_H, + R15, R15_H, + R16, R16_H, + R17, R17_H, + R18, R18_H, + R19, R19_H, + R20, R20_H, + R21, R21_H, + R22, R22_H, + R23, R23_H, + R24, R24_H, + R25, R25_H, + R26, R26_H, + /* R27, R27_H, */ // heapbase + /* R28, R28_H, */ // thread + R29, R29_H, // fp + /* R30, R30_H, */ // lr + /* R31, R31_H */ // sp +); + +reg_class_dynamic no_special_reg(no_special_reg_no_fp, no_special_reg_with_fp, %{ FramePointer %}); + // Class for 64 bit register r0 reg_class r0_reg( R0, R0_H @@ -593,7 +663,7 @@ ); // Class for all non_special pointer registers -reg_class no_special_ptr_reg( +reg_class no_special_ptr_reg_no_fp( R0, R0_H, R1, R1_H, R2, R2_H, @@ -626,6 +696,41 @@ /* R31, R31_H */ // sp ); +reg_class no_special_ptr_reg_with_fp( + R0, R0_H, + R1, R1_H, + R2, R2_H, + R3, R3_H, + R4, R4_H, + R5, R5_H, + R6, R6_H, + R7, R7_H, + R10, R10_H, + R11, R11_H, + R12, R12_H, + R13, R13_H, + R14, R14_H, + R15, R15_H, + R16, R16_H, + R17, R17_H, + R18, R18_H, + R19, R19_H, + R20, R20_H, + R21, R21_H, + R22, R22_H, + R23, R23_H, + R24, R24_H, + R25, R25_H, + R26, R26_H, + /* R27, R27_H, */ // heapbase + /* R28, R28_H, */ // thread + R29, R29_H, // fp + /* R30, R30_H, */ // lr + /* R31, R31_H */ // sp +); + +reg_class_dynamic no_special_ptr_reg(no_special_ptr_reg_no_fp, no_special_ptr_reg_with_fp, %{ FramePointer %}); + // Class for all float registers reg_class float_reg( V0, @@ -844,12 +949,7 @@ int MachCallStaticJavaNode::ret_addr_offset() { // call should be a simple bl - // unless this is a method handle invoke in which case it is - // mov(rfp, sp), bl, mov(sp, rfp) int off = 4; - if (_method_handle_invoke) { - off += 4; - } return off; } @@ -966,8 +1066,10 @@ } else if (framesize < ((1 << 9) + 2 * wordSize)) { st->print("sub sp, sp, #%d\n\t", framesize); st->print("stp rfp, lr, [sp, #%d]", framesize - 2 * wordSize); + if (FramePointer) st->print("\n\tadd rfp, sp, #%d", framesize - 2 * wordSize); } else { st->print("stp lr, rfp, [sp, #%d]!\n\t", -(2 * wordSize)); + if (FramePointer) st->print("mov rfp, sp\n\t"); st->print("mov rscratch1, #%d\n\t", framesize - 2 * wordSize); st->print("sub sp, sp, rscratch1"); } @@ -2722,34 +2824,6 @@ } %} - enc_class aarch64_enc_java_handle_call(method meth) %{ - MacroAssembler _masm(&cbuf); - relocInfo::relocType reloc; - - // RFP is preserved across all calls, even compiled calls. - // Use it to preserve SP. - __ mov(rfp, sp); - - const int start_offset = __ offset(); - address addr = (address)$meth$$method; - if (!_method) { - // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap. - __ trampoline_call(Address(addr, relocInfo::runtime_call_type), &cbuf); - } else if (_optimized_virtual) { - __ trampoline_call(Address(addr, relocInfo::opt_virtual_call_type), &cbuf); - } else { - __ trampoline_call(Address(addr, relocInfo::static_call_type), &cbuf); - } - - if (_method) { - // Emit stub for static call - CompiledStaticCall::emit_to_interp_stub(cbuf); - } - - // now restore sp - __ mov(sp, rfp); - %} - enc_class aarch64_enc_java_dynamic_call(method meth) %{ MacroAssembler _masm(&cbuf); __ ic_call((address)$meth$$method); @@ -11710,8 +11784,6 @@ effect(USE meth); - predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke()); - ins_cost(CALL_COST); format %{ "call,static $meth \t// ==> " %} @@ -11724,26 +11796,6 @@ // TO HERE -// Call Java Static Instruction (method handle version) - -instruct CallStaticJavaDirectHandle(method meth, iRegP_FP reg_mh_save) -%{ - match(CallStaticJava); - - effect(USE meth); - - predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); - - ins_cost(CALL_COST); - - format %{ "call,static $meth \t// (methodhandle) ==> " %} - - ins_encode( aarch64_enc_java_handle_call(meth), - aarch64_enc_call_epilog ); - - ins_pipe(pipe_class_call); -%} - // Call Java Dynamic Instruction instruct CallDynamicJavaDirect(method meth) %{ diff --git a/src/cpu/aarch64/vm/c1_FrameMap_aarch64.cpp b/src/cpu/aarch64/vm/c1_FrameMap_aarch64.cpp --- a/src/cpu/aarch64/vm/c1_FrameMap_aarch64.cpp +++ b/src/cpu/aarch64/vm/c1_FrameMap_aarch64.cpp @@ -347,7 +347,7 @@ // JSR 292 LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() { // assert(rfp == rbp_mh_SP_save, "must be same register"); - return rfp_opr; + return LIR_OprFact::illegalOpr; // Not needed on aarch64 } diff --git a/src/cpu/aarch64/vm/frame_aarch64.inline.hpp b/src/cpu/aarch64/vm/frame_aarch64.inline.hpp --- a/src/cpu/aarch64/vm/frame_aarch64.inline.hpp +++ b/src/cpu/aarch64/vm/frame_aarch64.inline.hpp @@ -48,7 +48,7 @@ intptr_t a = intptr_t(sp); intptr_t b = intptr_t(fp); #ifndef PRODUCT - if (fp) + if (fp && FramePointer) if (sp > fp || (fp - sp > 0x100000)) for(;;) asm("nop"); @@ -78,7 +78,7 @@ intptr_t a = intptr_t(sp); intptr_t b = intptr_t(fp); #ifndef PRODUCT - if (fp) + if (fp && FramePointer) if (sp > fp || (fp - sp > 0x100000)) for(;;) asm("nop"); diff --git a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp --- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp +++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp @@ -3475,8 +3475,10 @@ } else if (framesize < ((1 << 9) + 2 * wordSize)) { sub(sp, sp, framesize); stp(rfp, lr, Address(sp, framesize - 2 * wordSize)); + if (FramePointer) add(rfp, sp, framesize - 2 * wordSize); } else { stp(rfp, lr, Address(pre(sp, -2 * wordSize))); + if (FramePointer) mov(rfp, sp); if (framesize < ((1 << 12) + 2 * wordSize)) sub(sp, sp, framesize - 2 * wordSize); else {