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src/cpu/aarch64/vm/aarch64.ad
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rev 8063 : 8075930: AARCH64: Use FP Register in C2
@@ -130,12 +130,12 @@
reg_def R26_H ( SOC, SOE, Op_RegI, 26, r26->as_VMReg()->next());
reg_def R27 ( NS, SOE, Op_RegI, 27, r27->as_VMReg() ); // heapbase
reg_def R27_H ( NS, SOE, Op_RegI, 27, r27->as_VMReg()->next());
reg_def R28 ( NS, SOE, Op_RegI, 28, r28->as_VMReg() ); // thread
reg_def R28_H ( NS, SOE, Op_RegI, 28, r28->as_VMReg()->next());
-reg_def R29 ( NS, NS, Op_RegI, 29, r29->as_VMReg() ); // fp
-reg_def R29_H ( NS, NS, Op_RegI, 29, r29->as_VMReg()->next());
+reg_def R29 ( NS, SOE, Op_RegI, 29, r29->as_VMReg() ); // fp
+reg_def R29_H ( NS, SOE, Op_RegI, 29, r29->as_VMReg()->next());
reg_def R30 ( NS, NS, Op_RegI, 30, r30->as_VMReg() ); // lr
reg_def R30_H ( NS, NS, Op_RegI, 30, r30->as_VMReg()->next());
reg_def R31 ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg() ); // sp
reg_def R31_H ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg()->next());
@@ -447,11 +447,11 @@
R24,
R25,
R26
/* R27, */ // heapbase
/* R28, */ // thread
- /* R29, */ // fp
+ R29, // fp
/* R30, */ // lr
/* R31 */ // sp
);
// Class for all non-special long integer registers
@@ -481,11 +481,11 @@
R24, R24_H,
R25, R25_H,
R26, R26_H,
/* R27, R27_H, */ // heapbase
/* R28, R28_H, */ // thread
- /* R29, R29_H, */ // fp
+ R29, R29_H, // fp
/* R30, R30_H, */ // lr
/* R31, R31_H */ // sp
);
// Class for 64 bit register r0
@@ -1742,11 +1742,11 @@
ShouldNotReachHere();
return RegMask();
}
const RegMask Matcher::method_handle_invoke_SP_save_mask() {
- return RegMask();
+ return FP_REG_mask();
}
// helper for encoding java_to_runtime calls on sim
//
// this is needed to compute the extra arguments required when
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