793 // count one adr and one far branch instruction
794 return 4 * NativeInstruction::instruction_size;
795 }
796 };
797
798 // graph traversal helpers
799 MemBarNode *has_parent_membar(const Node *n,
800 ProjNode *&ctl, ProjNode *&mem);
801 MemBarNode *has_child_membar(const MemBarNode *n,
802 ProjNode *&ctl, ProjNode *&mem);
803
804 // predicates controlling emit of ldr<x>/ldar<x> and associated dmb
805 bool unnecessary_acquire(const Node *barrier);
806 bool needs_acquiring_load(const Node *load);
807
808 // predicates controlling emit of str<x>/stlr<x> and associated dmbs
809 bool unnecessary_release(const Node *barrier);
810 bool unnecessary_volatile(const Node *barrier);
811 bool needs_releasing_store(const Node *store);
812
813 // Use barrier instructions rather than load acquire / store
814 // release.
815 const bool UseBarriersForVolatile = false;
816 // Use barrier instructions for unsafe volatile gets rather than
817 // trying to identify an exact signature for them
818 const bool UseBarriersForUnsafeVolatileGet = false;
819 %}
820
821 source %{
822
823 // AArch64 has ldar<x> and stlr<x> instructions which we can safely
824 // use to implement volatile reads and writes. For a volatile read
825 // we simply need
826 //
827 // ldar<x>
828 //
829 // and for a volatile write we need
830 //
831 // stlr<x>
832 //
833 // Alternatively, we can implement them by pairing a normal
834 // load/store with a memory barrier. For a volatile read we need
835 //
|
793 // count one adr and one far branch instruction
794 return 4 * NativeInstruction::instruction_size;
795 }
796 };
797
798 // graph traversal helpers
799 MemBarNode *has_parent_membar(const Node *n,
800 ProjNode *&ctl, ProjNode *&mem);
801 MemBarNode *has_child_membar(const MemBarNode *n,
802 ProjNode *&ctl, ProjNode *&mem);
803
804 // predicates controlling emit of ldr<x>/ldar<x> and associated dmb
805 bool unnecessary_acquire(const Node *barrier);
806 bool needs_acquiring_load(const Node *load);
807
808 // predicates controlling emit of str<x>/stlr<x> and associated dmbs
809 bool unnecessary_release(const Node *barrier);
810 bool unnecessary_volatile(const Node *barrier);
811 bool needs_releasing_store(const Node *store);
812
813 // Use barrier instructions for unsafe volatile gets rather than
814 // trying to identify an exact signature for them
815 const bool UseBarriersForUnsafeVolatileGet = false;
816 %}
817
818 source %{
819
820 // AArch64 has ldar<x> and stlr<x> instructions which we can safely
821 // use to implement volatile reads and writes. For a volatile read
822 // we simply need
823 //
824 // ldar<x>
825 //
826 // and for a volatile write we need
827 //
828 // stlr<x>
829 //
830 // Alternatively, we can implement them by pairing a normal
831 // load/store with a memory barrier. For a volatile read we need
832 //
|