1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30
31 // MacroAssembler extends Assembler by frequently used macros.
32 //
33 // Instructions for which a 'better' code sequence exists depending
34 // on arguments should also go in here.
35
36 class MacroAssembler: public Assembler {
37 friend class LIR_Assembler;
38
39 using Assembler::mov;
40
41 protected:
42
43 // Support for VM calls
44 //
45 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
46 // may customize this version by overriding it for its purposes (e.g., to save/restore
47 // additional registers when doing a VM call).
48 #ifdef CC_INTERP
49 // c++ interpreter never wants to use interp_masm version of call_VM
50 #define VIRTUAL
51 #else
52 #define VIRTUAL virtual
53 #endif
54
55 VIRTUAL void call_VM_leaf_base(
56 address entry_point, // the entry point
57 int number_of_arguments, // the number of arguments to pop after the call
58 Label *retaddr = NULL
59 );
60
61 VIRTUAL void call_VM_leaf_base(
62 address entry_point, // the entry point
63 int number_of_arguments, // the number of arguments to pop after the call
64 Label &retaddr) {
65 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
66 }
67
68 // This is the base routine called by the different versions of call_VM. The interpreter
69 // may customize this version by overriding it for its purposes (e.g., to save/restore
70 // additional registers when doing a VM call).
71 //
72 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
73 // returns the register which contains the thread upon return. If a thread register has been
74 // specified, the return value will correspond to that register. If no last_java_sp is specified
75 // (noreg) than rsp will be used instead.
76 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
77 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
78 Register java_thread, // the thread if computed before ; use noreg otherwise
79 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
80 address entry_point, // the entry point
81 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
82 bool check_exceptions // whether to check for pending exceptions after return
83 );
84
85 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
86 // The implementation is only non-empty for the InterpreterMacroAssembler,
87 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
88 virtual void check_and_handle_popframe(Register java_thread);
89 virtual void check_and_handle_earlyret(Register java_thread);
90
91 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
92
93 // Maximum size of class area in Metaspace when compressed
94 uint64_t use_XOR_for_compressed_class_base;
95
96 public:
97 MacroAssembler(CodeBuffer* code) : Assembler(code) {
98 use_XOR_for_compressed_class_base
99 = (operand_valid_for_logical_immediate(false /*is32*/,
100 (uint64_t)Universe::narrow_klass_base())
101 && ((uint64_t)Universe::narrow_klass_base()
102 > (1u << log2_intptr(CompressedClassSpaceSize))));
103 }
104
105 // Biased locking support
106 // lock_reg and obj_reg must be loaded up with the appropriate values.
107 // swap_reg is killed.
108 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
109 // be killed; if not supplied, push/pop will be used internally to
110 // allocate a temporary (inefficient, avoid if possible).
111 // Optional slow case is for implementations (interpreter and C1) which branch to
112 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
113 // Returns offset of first potentially-faulting instruction for null
114 // check info (currently consumed only by C1). If
115 // swap_reg_contains_mark is true then returns -1 as it is assumed
116 // the calling code has already passed any potential faults.
117 int biased_locking_enter(Register lock_reg, Register obj_reg,
118 Register swap_reg, Register tmp_reg,
119 bool swap_reg_contains_mark,
120 Label& done, Label* slow_case = NULL,
121 BiasedLockingCounters* counters = NULL);
122 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
123
124
125 // Helper functions for statistics gathering.
126 // Unconditional atomic increment.
127 void atomic_incw(Register counter_addr, Register tmp);
128 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2) {
129 lea(tmp1, counter_addr);
130 atomic_incw(tmp1, tmp2);
131 }
132 // Load Effective Address
133 void lea(Register r, const Address &a) {
134 InstructionMark im(this);
135 code_section()->relocate(inst_mark(), a.rspec());
136 a.lea(this, r);
137 }
138
139 void addmw(Address a, Register incr, Register scratch) {
140 ldrw(scratch, a);
141 addw(scratch, scratch, incr);
142 strw(scratch, a);
143 }
144
145 // Add constant to memory word
146 void addmw(Address a, int imm, Register scratch) {
147 ldrw(scratch, a);
148 if (imm > 0)
149 addw(scratch, scratch, (unsigned)imm);
150 else
151 subw(scratch, scratch, (unsigned)-imm);
152 strw(scratch, a);
153 }
154
155 // Frame creation and destruction shared between JITs.
156 void build_frame(int framesize);
157 void remove_frame(int framesize);
158
159 virtual void _call_Unimplemented(address call_site) {
160 mov(rscratch2, call_site);
161 haltsim();
162 }
163
164 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
165
166 virtual void notify(int type);
167
168 // aliases defined in AARCH64 spec
169
170
171 template<class T>
172 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
173 inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); }
174
175 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
176 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
177
178 void cset(Register Rd, Assembler::Condition cond) {
179 csinc(Rd, zr, zr, ~cond);
180 }
181 void csetw(Register Rd, Assembler::Condition cond) {
182 csincw(Rd, zr, zr, ~cond);
183 }
184
185 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
186 csneg(Rd, Rn, Rn, ~cond);
187 }
188 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
189 csnegw(Rd, Rn, Rn, ~cond);
190 }
191
192 inline void movw(Register Rd, Register Rn) {
193 if (Rd == sp || Rn == sp) {
194 addw(Rd, Rn, 0U);
195 } else {
196 orrw(Rd, zr, Rn);
197 }
198 }
199 inline void mov(Register Rd, Register Rn) {
200 assert(Rd != r31_sp && Rn != r31_sp, "should be");
201 if (Rd == Rn) {
202 } else if (Rd == sp || Rn == sp) {
203 add(Rd, Rn, 0U);
204 } else {
205 orr(Rd, zr, Rn);
206 }
207 }
208
209 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
210 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
211
212 inline void tstw(Register Rd, unsigned imm) { andsw(zr, Rd, imm); }
213 inline void tst(Register Rd, unsigned imm) { ands(zr, Rd, imm); }
214
215 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
216 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
217 }
218 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
219 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
220 }
221
222 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
223 bfmw(Rd, Rn, lsb, (lsb + width - 1));
224 }
225 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
226 bfm(Rd, Rn, lsb , (lsb + width - 1));
227 }
228
229 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
230 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
231 }
232 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
233 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
234 }
235
236 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
237 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
238 }
239 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
240 sbfm(Rd, Rn, lsb , (lsb + width - 1));
241 }
242
243 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
244 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
245 }
246 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
247 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
248 }
249
250 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
251 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
252 }
253 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
254 ubfm(Rd, Rn, lsb , (lsb + width - 1));
255 }
256
257 inline void asrw(Register Rd, Register Rn, unsigned imm) {
258 sbfmw(Rd, Rn, imm, 31);
259 }
260
261 inline void asr(Register Rd, Register Rn, unsigned imm) {
262 sbfm(Rd, Rn, imm, 63);
263 }
264
265 inline void lslw(Register Rd, Register Rn, unsigned imm) {
266 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
267 }
268
269 inline void lsl(Register Rd, Register Rn, unsigned imm) {
270 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
271 }
272
273 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
274 ubfmw(Rd, Rn, imm, 31);
275 }
276
277 inline void lsr(Register Rd, Register Rn, unsigned imm) {
278 ubfm(Rd, Rn, imm, 63);
279 }
280
281 inline void rorw(Register Rd, Register Rn, unsigned imm) {
282 extrw(Rd, Rn, Rn, imm);
283 }
284
285 inline void ror(Register Rd, Register Rn, unsigned imm) {
286 extr(Rd, Rn, Rn, imm);
287 }
288
289 inline void sxtbw(Register Rd, Register Rn) {
290 sbfmw(Rd, Rn, 0, 7);
291 }
292 inline void sxthw(Register Rd, Register Rn) {
293 sbfmw(Rd, Rn, 0, 15);
294 }
295 inline void sxtb(Register Rd, Register Rn) {
296 sbfm(Rd, Rn, 0, 7);
297 }
298 inline void sxth(Register Rd, Register Rn) {
299 sbfm(Rd, Rn, 0, 15);
300 }
301 inline void sxtw(Register Rd, Register Rn) {
302 sbfm(Rd, Rn, 0, 31);
303 }
304
305 inline void uxtbw(Register Rd, Register Rn) {
306 ubfmw(Rd, Rn, 0, 7);
307 }
308 inline void uxthw(Register Rd, Register Rn) {
309 ubfmw(Rd, Rn, 0, 15);
310 }
311 inline void uxtb(Register Rd, Register Rn) {
312 ubfm(Rd, Rn, 0, 7);
313 }
314 inline void uxth(Register Rd, Register Rn) {
315 ubfm(Rd, Rn, 0, 15);
316 }
317 inline void uxtw(Register Rd, Register Rn) {
318 ubfm(Rd, Rn, 0, 31);
319 }
320
321 inline void cmnw(Register Rn, Register Rm) {
322 addsw(zr, Rn, Rm);
323 }
324 inline void cmn(Register Rn, Register Rm) {
325 adds(zr, Rn, Rm);
326 }
327
328 inline void cmpw(Register Rn, Register Rm) {
329 subsw(zr, Rn, Rm);
330 }
331 inline void cmp(Register Rn, Register Rm) {
332 subs(zr, Rn, Rm);
333 }
334
335 inline void negw(Register Rd, Register Rn) {
336 subw(Rd, zr, Rn);
337 }
338
339 inline void neg(Register Rd, Register Rn) {
340 sub(Rd, zr, Rn);
341 }
342
343 inline void negsw(Register Rd, Register Rn) {
344 subsw(Rd, zr, Rn);
345 }
346
347 inline void negs(Register Rd, Register Rn) {
348 subs(Rd, zr, Rn);
349 }
350
351 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
352 addsw(zr, Rn, Rm, kind, shift);
353 }
354 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
355 adds(zr, Rn, Rm, kind, shift);
356 }
357
358 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
359 subsw(zr, Rn, Rm, kind, shift);
360 }
361 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
362 subs(zr, Rn, Rm, kind, shift);
363 }
364
365 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
366 subw(Rd, zr, Rn, kind, shift);
367 }
368
369 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
370 sub(Rd, zr, Rn, kind, shift);
371 }
372
373 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
374 subsw(Rd, zr, Rn, kind, shift);
375 }
376
377 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
378 subs(Rd, zr, Rn, kind, shift);
379 }
380
381 inline void mnegw(Register Rd, Register Rn, Register Rm) {
382 msubw(Rd, Rn, Rm, zr);
383 }
384 inline void mneg(Register Rd, Register Rn, Register Rm) {
385 msub(Rd, Rn, Rm, zr);
386 }
387
388 inline void mulw(Register Rd, Register Rn, Register Rm) {
389 maddw(Rd, Rn, Rm, zr);
390 }
391 inline void mul(Register Rd, Register Rn, Register Rm) {
392 madd(Rd, Rn, Rm, zr);
393 }
394
395 inline void smnegl(Register Rd, Register Rn, Register Rm) {
396 smsubl(Rd, Rn, Rm, zr);
397 }
398 inline void smull(Register Rd, Register Rn, Register Rm) {
399 smaddl(Rd, Rn, Rm, zr);
400 }
401
402 inline void umnegl(Register Rd, Register Rn, Register Rm) {
403 umsubl(Rd, Rn, Rm, zr);
404 }
405 inline void umull(Register Rd, Register Rn, Register Rm) {
406 umaddl(Rd, Rn, Rm, zr);
407 }
408
409 // macro assembly operations needed for aarch64
410
411 // first two private routines for loading 32 bit or 64 bit constants
412 private:
413
414 void mov_immediate64(Register dst, u_int64_t imm64);
415 void mov_immediate32(Register dst, u_int32_t imm32);
416
417 int push(unsigned int bitset, Register stack);
418 int pop(unsigned int bitset, Register stack);
419
420 void mov(Register dst, Address a);
421
422 public:
423 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
424 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
425
426 // now mov instructions for loading absolute addresses and 32 or
427 // 64 bit integers
428
429 inline void mov(Register dst, address addr)
430 {
431 mov_immediate64(dst, (u_int64_t)addr);
432 }
433
434 inline void mov(Register dst, u_int64_t imm64)
435 {
436 mov_immediate64(dst, imm64);
437 }
438
439 inline void movw(Register dst, u_int32_t imm32)
440 {
441 mov_immediate32(dst, imm32);
442 }
443
444 inline void mov(Register dst, long l)
445 {
446 mov(dst, (u_int64_t)l);
447 }
448
449 inline void mov(Register dst, int i)
450 {
451 mov(dst, (long)i);
452 }
453
454 void movptr(Register r, uintptr_t imm64);
455
456 // macro instructions for accessing and updating floating point
457 // status register
458 //
459 // FPSR : op1 == 011
460 // CRn == 0100
461 // CRm == 0100
462 // op2 == 001
463
464 inline void get_fpsr(Register reg)
465 {
466 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
467 }
468
469 inline void set_fpsr(Register reg)
470 {
471 msr(0b011, 0b0100, 0b0100, 0b001, reg);
472 }
473
474 inline void clear_fpsr()
475 {
476 msr(0b011, 0b0100, 0b0100, 0b001, zr);
477 }
478
479 // idiv variant which deals with MINLONG as dividend and -1 as divisor
480 int corrected_idivl(Register result, Register ra, Register rb,
481 bool want_remainder, Register tmp = rscratch1);
482 int corrected_idivq(Register result, Register ra, Register rb,
483 bool want_remainder, Register tmp = rscratch1);
484
485 // Support for NULL-checks
486 //
487 // Generates code that causes a NULL OS exception if the content of reg is NULL.
488 // If the accessed location is M[reg + offset] and the offset is known, provide the
489 // offset. No explicit code generation is needed if the offset is within a certain
490 // range (0 <= offset <= page_size).
491
492 virtual void null_check(Register reg, int offset = -1);
493 static bool needs_explicit_null_check(intptr_t offset);
494
495 static address target_addr_for_insn(address insn_addr, unsigned insn);
496 static address target_addr_for_insn(address insn_addr) {
497 unsigned insn = *(unsigned*)insn_addr;
498 return target_addr_for_insn(insn_addr, insn);
499 }
500
501 // Required platform-specific helpers for Label::patch_instructions.
502 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
503 static int pd_patch_instruction_size(address branch, address target);
504 static void pd_patch_instruction(address branch, address target) {
505 pd_patch_instruction_size(branch, target);
506 }
507 static address pd_call_destination(address branch) {
508 return target_addr_for_insn(branch);
509 }
510 #ifndef PRODUCT
511 static void pd_print_patched_instruction(address branch);
512 #endif
513
514 static int patch_oop(address insn_addr, address o);
515
516 void emit_trampoline_stub(int insts_call_instruction_offset, address target);
517
518 // The following 4 methods return the offset of the appropriate move instruction
519
520 // Support for fast byte/short loading with zero extension (depending on particular CPU)
521 int load_unsigned_byte(Register dst, Address src);
522 int load_unsigned_short(Register dst, Address src);
523
524 // Support for fast byte/short loading with sign extension (depending on particular CPU)
525 int load_signed_byte(Register dst, Address src);
526 int load_signed_short(Register dst, Address src);
527
528 int load_signed_byte32(Register dst, Address src);
529 int load_signed_short32(Register dst, Address src);
530
531 // Support for sign-extension (hi:lo = extend_sign(lo))
532 void extend_sign(Register hi, Register lo);
533
534 // Load and store values by size and signed-ness
535 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
536 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
537
538 // Support for inc/dec with optimal instruction selection depending on value
539
540 // x86_64 aliases an unqualified register/address increment and
541 // decrement to call incrementq and decrementq but also supports
542 // explicitly sized calls to incrementq/decrementq or
543 // incrementl/decrementl
544
545 // for aarch64 the proper convention would be to use
546 // increment/decrement for 64 bit operatons and
547 // incrementw/decrementw for 32 bit operations. so when porting
548 // x86_64 code we can leave calls to increment/decrement as is,
549 // replace incrementq/decrementq with increment/decrement and
550 // replace incrementl/decrementl with incrementw/decrementw.
551
552 // n.b. increment/decrement calls with an Address destination will
553 // need to use a scratch register to load the value to be
554 // incremented. increment/decrement calls which add or subtract a
555 // constant value greater than 2^12 will need to use a 2nd scratch
556 // register to hold the constant. so, a register increment/decrement
557 // may trash rscratch2 and an address increment/decrement trash
558 // rscratch and rscratch2
559
560 void decrementw(Address dst, int value = 1);
561 void decrementw(Register reg, int value = 1);
562
563 void decrement(Register reg, int value = 1);
564 void decrement(Address dst, int value = 1);
565
566 void incrementw(Address dst, int value = 1);
567 void incrementw(Register reg, int value = 1);
568
569 void increment(Register reg, int value = 1);
570 void increment(Address dst, int value = 1);
571
572
573 // Alignment
574 void align(int modulus);
575
576 // Stack frame creation/removal
577 void enter()
578 {
579 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
580 mov(rfp, sp);
581 }
582 void leave()
583 {
584 mov(sp, rfp);
585 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
586 }
587
588 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
589 // The pointer will be loaded into the thread register.
590 void get_thread(Register thread);
591
592
593 // Support for VM calls
594 //
595 // It is imperative that all calls into the VM are handled via the call_VM macros.
596 // They make sure that the stack linkage is setup correctly. call_VM's correspond
597 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
598
599
600 void call_VM(Register oop_result,
601 address entry_point,
602 bool check_exceptions = true);
603 void call_VM(Register oop_result,
604 address entry_point,
605 Register arg_1,
606 bool check_exceptions = true);
607 void call_VM(Register oop_result,
608 address entry_point,
609 Register arg_1, Register arg_2,
610 bool check_exceptions = true);
611 void call_VM(Register oop_result,
612 address entry_point,
613 Register arg_1, Register arg_2, Register arg_3,
614 bool check_exceptions = true);
615
616 // Overloadings with last_Java_sp
617 void call_VM(Register oop_result,
618 Register last_java_sp,
619 address entry_point,
620 int number_of_arguments = 0,
621 bool check_exceptions = true);
622 void call_VM(Register oop_result,
623 Register last_java_sp,
624 address entry_point,
625 Register arg_1, bool
626 check_exceptions = true);
627 void call_VM(Register oop_result,
628 Register last_java_sp,
629 address entry_point,
630 Register arg_1, Register arg_2,
631 bool check_exceptions = true);
632 void call_VM(Register oop_result,
633 Register last_java_sp,
634 address entry_point,
635 Register arg_1, Register arg_2, Register arg_3,
636 bool check_exceptions = true);
637
638 void get_vm_result (Register oop_result, Register thread);
639 void get_vm_result_2(Register metadata_result, Register thread);
640
641 // These always tightly bind to MacroAssembler::call_VM_base
642 // bypassing the virtual implementation
643 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
644 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
645 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
646 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
647 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
648
649 void call_VM_leaf(address entry_point,
650 int number_of_arguments = 0);
651 void call_VM_leaf(address entry_point,
652 Register arg_1);
653 void call_VM_leaf(address entry_point,
654 Register arg_1, Register arg_2);
655 void call_VM_leaf(address entry_point,
656 Register arg_1, Register arg_2, Register arg_3);
657
658 // These always tightly bind to MacroAssembler::call_VM_leaf_base
659 // bypassing the virtual implementation
660 void super_call_VM_leaf(address entry_point);
661 void super_call_VM_leaf(address entry_point, Register arg_1);
662 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
663 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
664 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
665
666 // last Java Frame (fills frame anchor)
667 void set_last_Java_frame(Register last_java_sp,
668 Register last_java_fp,
669 address last_java_pc,
670 Register scratch);
671
672 void set_last_Java_frame(Register last_java_sp,
673 Register last_java_fp,
674 Label &last_java_pc,
675 Register scratch);
676
677 void set_last_Java_frame(Register last_java_sp,
678 Register last_java_fp,
679 Register last_java_pc,
680 Register scratch);
681
682 void reset_last_Java_frame(Register thread, bool clearfp, bool clear_pc);
683
684 // thread in the default location (r15_thread on 64bit)
685 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
686
687 // Stores
688 void store_check(Register obj); // store check for obj - register is destroyed afterwards
689 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
690
691 #if INCLUDE_ALL_GCS
692
693 void g1_write_barrier_pre(Register obj,
694 Register pre_val,
695 Register thread,
696 Register tmp,
697 bool tosca_live,
698 bool expand_call);
699
700 void g1_write_barrier_post(Register store_addr,
701 Register new_val,
702 Register thread,
703 Register tmp,
704 Register tmp2);
705
706 #endif // INCLUDE_ALL_GCS
707
708 // split store_check(Register obj) to enhance instruction interleaving
709 void store_check_part_1(Register obj);
710 void store_check_part_2(Register obj);
711
712 // oop manipulations
713 void load_klass(Register dst, Register src);
714 void store_klass(Register dst, Register src);
715 void cmp_klass(Register oop, Register trial_klass, Register tmp);
716
717 void load_heap_oop(Register dst, Address src);
718
719 void load_heap_oop_not_null(Register dst, Address src);
720 void store_heap_oop(Address dst, Register src);
721
722 // currently unimplemented
723 // Used for storing NULL. All other oop constants should be
724 // stored using routines that take a jobject.
725 void store_heap_oop_null(Address dst);
726
727 void load_prototype_header(Register dst, Register src);
728
729 void store_klass_gap(Register dst, Register src);
730
731 // This dummy is to prevent a call to store_heap_oop from
732 // converting a zero (like NULL) into a Register by giving
733 // the compiler two choices it can't resolve
734
735 void store_heap_oop(Address dst, void* dummy);
736
737 void encode_heap_oop(Register d, Register s);
738 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
739 void decode_heap_oop(Register d, Register s);
740 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
741 void encode_heap_oop_not_null(Register r);
742 void decode_heap_oop_not_null(Register r);
743 void encode_heap_oop_not_null(Register dst, Register src);
744 void decode_heap_oop_not_null(Register dst, Register src);
745
746 void set_narrow_oop(Register dst, jobject obj);
747
748 void encode_klass_not_null(Register r);
749 void decode_klass_not_null(Register r);
750 void encode_klass_not_null(Register dst, Register src);
751 void decode_klass_not_null(Register dst, Register src);
752
753 void set_narrow_klass(Register dst, Klass* k);
754
755 // if heap base register is used - reinit it with the correct value
756 void reinit_heapbase();
757
758 DEBUG_ONLY(void verify_heapbase(const char* msg);)
759
760 void push_CPU_state();
761 void pop_CPU_state() ;
762
763 // Round up to a power of two
764 void round_to(Register reg, int modulus);
765
766 // allocation
767 void eden_allocate(
768 Register obj, // result: pointer to object after successful allocation
769 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
770 int con_size_in_bytes, // object size in bytes if known at compile time
771 Register t1, // temp register
772 Label& slow_case // continuation point if fast allocation fails
773 );
774 void tlab_allocate(
775 Register obj, // result: pointer to object after successful allocation
776 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
777 int con_size_in_bytes, // object size in bytes if known at compile time
778 Register t1, // temp register
779 Register t2, // temp register
780 Label& slow_case // continuation point if fast allocation fails
781 );
782 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
783 void verify_tlab();
784
785 void incr_allocated_bytes(Register thread,
786 Register var_size_in_bytes, int con_size_in_bytes,
787 Register t1 = noreg);
788
789 // interface method calling
790 void lookup_interface_method(Register recv_klass,
791 Register intf_klass,
792 RegisterOrConstant itable_index,
793 Register method_result,
794 Register scan_temp,
795 Label& no_such_interface);
796
797 // virtual method calling
798 // n.b. x86 allows RegisterOrConstant for vtable_index
799 void lookup_virtual_method(Register recv_klass,
800 RegisterOrConstant vtable_index,
801 Register method_result);
802
803 // Test sub_klass against super_klass, with fast and slow paths.
804
805 // The fast path produces a tri-state answer: yes / no / maybe-slow.
806 // One of the three labels can be NULL, meaning take the fall-through.
807 // If super_check_offset is -1, the value is loaded up from super_klass.
808 // No registers are killed, except temp_reg.
809 void check_klass_subtype_fast_path(Register sub_klass,
810 Register super_klass,
811 Register temp_reg,
812 Label* L_success,
813 Label* L_failure,
814 Label* L_slow_path,
815 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
816
817 // The rest of the type check; must be wired to a corresponding fast path.
818 // It does not repeat the fast path logic, so don't use it standalone.
819 // The temp_reg and temp2_reg can be noreg, if no temps are available.
820 // Updates the sub's secondary super cache as necessary.
821 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
822 void check_klass_subtype_slow_path(Register sub_klass,
823 Register super_klass,
824 Register temp_reg,
825 Register temp2_reg,
826 Label* L_success,
827 Label* L_failure,
828 bool set_cond_codes = false);
829
830 // Simplified, combined version, good for typical uses.
831 // Falls through on failure.
832 void check_klass_subtype(Register sub_klass,
833 Register super_klass,
834 Register temp_reg,
835 Label& L_success);
836
837 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
838
839
840 // Debugging
841
842 // only if +VerifyOops
843 void verify_oop(Register reg, const char* s = "broken oop");
844 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
845
846 // TODO: verify method and klass metadata (compare against vptr?)
847 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
848 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
849
850 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
851 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
852
853 // only if +VerifyFPU
854 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
855
856 // prints msg, dumps registers and stops execution
857 void stop(const char* msg);
858
859 // prints msg and continues
860 void warn(const char* msg);
861
862 static void debug64(char* msg, int64_t pc, int64_t regs[]);
863
864 void untested() { stop("untested"); }
865
866 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
867
868 void should_not_reach_here() { stop("should not reach here"); }
869
870 // Stack overflow checking
871 void bang_stack_with_offset(int offset) {
872 // stack grows down, caller passes positive offset
873 assert(offset > 0, "must bang with negative offset");
874 mov(rscratch2, -offset);
875 str(zr, Address(sp, rscratch2));
876 }
877
878 // Writes to stack successive pages until offset reached to check for
879 // stack overflow + shadow pages. Also, clobbers tmp
880 void bang_stack_size(Register size, Register tmp);
881
882 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
883 Register tmp,
884 int offset);
885
886 // Support for serializing memory accesses between threads
887 void serialize_memory(Register thread, Register tmp);
888
889 // Arithmetics
890
891 void addptr(Address dst, int32_t src) {
892 lea(rscratch2, dst);
893 ldr(rscratch1, Address(rscratch2));
894 add(rscratch1, rscratch1, src);
895 str(rscratch1, Address(rscratch2));
896 }
897
898 void cmpptr(Register src1, Address src2);
899
900 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
901 Label &suceed, Label *fail);
902
903 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
904 Label &suceed, Label *fail);
905
906 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
907 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
908
909 void atomic_xchg(Register prev, Register newv, Register addr);
910 void atomic_xchgw(Register prev, Register newv, Register addr);
911
912 void orptr(Address adr, RegisterOrConstant src) {
913 ldr(rscratch2, adr);
914 if (src.is_register())
915 orr(rscratch2, rscratch2, src.as_register());
916 else
917 orr(rscratch2, rscratch2, src.as_constant());
918 str(rscratch2, adr);
919 }
920
921 // Calls
922
923 void trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
924
925 static bool far_branches() {
926 return ReservedCodeCacheSize > branch_range;
927 }
928
929 // Jumps that can reach anywhere in the code cache.
930 // Trashes tmp.
931 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
932 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
933
934 static int far_branch_size() {
935 if (far_branches()) {
936 return 3 * 4; // adrp, add, br
937 } else {
938 return 4;
939 }
940 }
941
942 // Emit the CompiledIC call idiom
943 void ic_call(address entry);
944
945 public:
946
947 // Data
948
949 void mov_metadata(Register dst, Metadata* obj);
950 Address allocate_metadata_address(Metadata* obj);
951 Address constant_oop_address(jobject obj);
952
953 void movoop(Register dst, jobject obj, bool immediate = false);
954
955 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
956 void kernel_crc32(Register crc, Register buf, Register len,
957 Register table0, Register table1, Register table2, Register table3,
958 Register tmp, Register tmp2, Register tmp3);
959
960 #undef VIRTUAL
961
962 // Stack push and pop individual 64 bit registers
963 void push(Register src);
964 void pop(Register dst);
965
966 // push all registers onto the stack
967 void pusha();
968 void popa();
969
970 void repne_scan(Register addr, Register value, Register count,
971 Register scratch);
972 void repne_scanw(Register addr, Register value, Register count,
973 Register scratch);
974
975 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
976 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
977
978 // If a constant does not fit in an immediate field, generate some
979 // number of MOV instructions and then perform the operation
980 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
981 add_sub_imm_insn insn1,
982 add_sub_reg_insn insn2);
983 // Seperate vsn which sets the flags
984 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
985 add_sub_imm_insn insn1,
986 add_sub_reg_insn insn2);
987
988 #define WRAP(INSN) \
989 void INSN(Register Rd, Register Rn, unsigned imm) { \
990 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
991 } \
992 \
993 void INSN(Register Rd, Register Rn, Register Rm, \
994 enum shift_kind kind, unsigned shift = 0) { \
995 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
996 } \
997 \
998 void INSN(Register Rd, Register Rn, Register Rm) { \
999 Assembler::INSN(Rd, Rn, Rm); \
1000 } \
1001 \
1002 void INSN(Register Rd, Register Rn, Register Rm, \
1003 ext::operation option, int amount = 0) { \
1004 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1005 }
1006
1007 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1008
1009 #undef WRAP
1010 #define WRAP(INSN) \
1011 void INSN(Register Rd, Register Rn, unsigned imm) { \
1012 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1013 } \
1014 \
1015 void INSN(Register Rd, Register Rn, Register Rm, \
1016 enum shift_kind kind, unsigned shift = 0) { \
1017 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1018 } \
1019 \
1020 void INSN(Register Rd, Register Rn, Register Rm) { \
1021 Assembler::INSN(Rd, Rn, Rm); \
1022 } \
1023 \
1024 void INSN(Register Rd, Register Rn, Register Rm, \
1025 ext::operation option, int amount = 0) { \
1026 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1027 }
1028
1029 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1030
1031 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1032 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1033
1034 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1035
1036 void tableswitch(Register index, jint lowbound, jint highbound,
1037 Label &jumptable, Label &jumptable_end, int stride = 1) {
1038 adr(rscratch1, jumptable);
1039 subsw(rscratch2, index, lowbound);
1040 subsw(zr, rscratch2, highbound - lowbound);
1041 br(Assembler::HS, jumptable_end);
1042 add(rscratch1, rscratch1, rscratch2,
1043 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1044 br(rscratch1);
1045 }
1046
1047 // Form an address from base + offset in Rd. Rd may or may not
1048 // actually be used: you must use the Address that is returned. It
1049 // is up to you to ensure that the shift provided matches the size
1050 // of your data.
1051 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1052
1053 // Prolog generator routines to support switch between x86 code and
1054 // generated ARM code
1055
1056 // routine to generate an x86 prolog for a stub function which
1057 // bootstraps into the generated ARM code which directly follows the
1058 // stub
1059 //
1060
1061 public:
1062 // enum used for aarch64--x86 linkage to define return type of x86 function
1063 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1064
1065 #ifdef BUILTIN_SIM
1066 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1067 #else
1068 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1069 #endif
1070
1071 // special version of call_VM_leaf_base needed for aarch64 simulator
1072 // where we need to specify both the gp and fp arg counts and the
1073 // return type so that the linkage routine from aarch64 to x86 and
1074 // back knows which aarch64 registers to copy to x86 registers and
1075 // which x86 result register to copy back to an aarch64 register
1076
1077 void call_VM_leaf_base1(
1078 address entry_point, // the entry point
1079 int number_of_gp_arguments, // the number of gp reg arguments to pass
1080 int number_of_fp_arguments, // the number of fp reg arguments to pass
1081 ret_type type, // the return type for the call
1082 Label* retaddr = NULL
1083 );
1084
1085 void ldr_constant(Register dest, const Address &const_addr) {
1086 if (NearCpool) {
1087 ldr(dest, const_addr);
1088 } else {
1089 unsigned long offset;
1090 adrp(dest, InternalAddress(const_addr.target()), offset);
1091 ldr(dest, Address(dest, offset));
1092 }
1093 }
1094
1095 address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1096 address read_polling_page(Register r, relocInfo::relocType rtype);
1097
1098 // Used by aarch64.ad to control code generation
1099 static bool use_acq_rel_for_volatile_fields();
1100
1101 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1102 void update_byte_crc32(Register crc, Register val, Register table);
1103 void update_word_crc32(Register crc, Register v, Register tmp,
1104 Register table0, Register table1, Register table2, Register table3,
1105 bool upper = false);
1106
1107 void string_compare(Register str1, Register str2,
1108 Register cnt1, Register cnt2, Register result,
1109 Register tmp1);
1110 void string_equals(Register str1, Register str2,
1111 Register cnt, Register result,
1112 Register tmp1);
1113 void char_arrays_equals(Register ary1, Register ary2,
1114 Register result, Register tmp1);
1115 void encode_iso_array(Register src, Register dst,
1116 Register len, Register result,
1117 FloatRegister Vtmp1, FloatRegister Vtmp2,
1118 FloatRegister Vtmp3, FloatRegister Vtmp4);
1119 void string_indexof(Register str1, Register str2,
1120 Register cnt1, Register cnt2,
1121 Register tmp1, Register tmp2,
1122 Register tmp3, Register tmp4,
1123 int int_cnt1, Register result);
1124
1125 // ISB may be needed because of a safepoint
1126 void maybe_isb() { isb(); }
1127 };
1128
1129 // Used by aarch64.ad to control code generation
1130 #define treat_as_volatile(MEM_NODE) \
1131 (MacroAssembler::use_acq_rel_for_volatile_fields() ? (MEM_NODE)->is_volatile() : false)
1132
1133 #ifdef ASSERT
1134 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1135 #endif
1136
1137 /**
1138 * class SkipIfEqual:
1139 *
1140 * Instantiating this class will result in assembly code being output that will
1141 * jump around any code emitted between the creation of the instance and it's
1142 * automatic destruction at the end of a scope block, depending on the value of
1143 * the flag passed to the constructor, which will be checked at run-time.
1144 */
1145 class SkipIfEqual {
1146 private:
1147 MacroAssembler* _masm;
1148 Label _label;
1149
1150 public:
1151 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1152 ~SkipIfEqual();
1153 };
1154
1155 struct tableswitch {
1156 Register _reg;
1157 int _insn_index; jint _first_key; jint _last_key;
1158 Label _after;
1159 Label _branches;
1160 };
1161
1162 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP