1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_aarch64.hpp"
33 #ifdef TARGET_OS_FAMILY_linux
34 # include "os_linux.inline.hpp"
35 #endif
36
37 #ifndef BUILTIN_SIM
38 #include <sys/auxv.h>
39 #include <asm/hwcap.h>
40 #else
41 #define getauxval(hwcap) 0
42 #endif
43
44 #ifndef HWCAP_AES
45 #define HWCAP_AES (1<<3)
46 #endif
47
48 #ifndef HWCAP_SHA1
49 #define HWCAP_SHA1 (1<<5)
50 #endif
51
52 #ifndef HWCAP_SHA2
53 #define HWCAP_SHA2 (1<<6)
54 #endif
55
56 #ifndef HWCAP_CRC32
57 #define HWCAP_CRC32 (1<<7)
58 #endif
59
60 int VM_Version::_cpu;
61 int VM_Version::_model;
62 int VM_Version::_variant;
63 int VM_Version::_revision;
64 int VM_Version::_stepping;
65 int VM_Version::_cpuFeatures;
66 const char* VM_Version::_features_str = "";
67
68 static BufferBlob* stub_blob;
69 static const int stub_size = 550;
70
71 extern "C" {
72 typedef void (*getPsrInfo_stub_t)(void*);
73 }
74 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
75
76
77 class VM_Version_StubGenerator: public StubCodeGenerator {
78 public:
79
80 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
81
82 address generate_getPsrInfo() {
83 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
84 # define __ _masm->
85 address start = __ pc();
86
87 #ifdef BUILTIN_SIM
88 __ c_stub_prolog(1, 0, MacroAssembler::ret_type_void);
89 #endif
90
91 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
92
93 address entry = __ pc();
94
95 // TODO : redefine fields in CpuidInfo and generate
96 // code to fill them in
97
98 __ ret(lr);
99
100 # undef __
101
102 return start;
103 }
104 };
105
106
107 void VM_Version::get_processor_features() {
108 _supports_cx8 = true;
109 _supports_atomic_getset4 = true;
110 _supports_atomic_getadd4 = true;
111 _supports_atomic_getset8 = true;
112 _supports_atomic_getadd8 = true;
113
114 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
115 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
116 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
117 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, 64);
118 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 256);
119 FLAG_SET_DEFAULT(PrefetchFieldsAhead, 256);
120 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 256);
121 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
122
123 unsigned long auxv = getauxval(AT_HWCAP);
124
125 char buf[512];
126
127 strcpy(buf, "simd");
128 if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
129 if (auxv & HWCAP_AES) strcat(buf, ", aes");
130 if (auxv & HWCAP_SHA1) strcat(buf, ", sha1");
131 if (auxv & HWCAP_SHA2) strcat(buf, ", sha256");
132
133 _features_str = strdup(buf);
134 _cpuFeatures = auxv;
135
136 if (FILE *f = fopen("/proc/cpuinfo", "r")) {
137 char buf[128], *p;
138 while (fgets(buf, sizeof (buf), f) != NULL) {
139 if (p = strchr(buf, ':')) {
140 long v = strtol(p+1, NULL, 0);
141 if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
142 _cpu = v;
143 } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
144 _variant = v;
145 } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
146 _model = v;
147 } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
148 _revision = v;
149 }
150 }
151 }
152 fclose(f);
153 }
154
155 // Enable vendor specific features
156 if (_cpu == CPU_CAVIUM) _cpuFeatures |= CPU_DMB_ATOMICS;
157 if (_cpu == CPU_ARM) _cpuFeatures |= CPU_A53MAC;
158
159 if (FLAG_IS_DEFAULT(UseCRC32)) {
160 UseCRC32 = (auxv & HWCAP_CRC32) != 0;
161 }
162 if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
163 warning("UseCRC32 specified, but not supported on this CPU");
164 }
165 if (auxv & HWCAP_AES) {
166 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
167 UseAESIntrinsics =
168 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
169 if (UseAESIntrinsics && !UseAES) {
170 warning("UseAESIntrinsics enabled, but UseAES not, enabling");
171 UseAES = true;
172 }
173 } else {
174 if (UseAES) {
175 warning("UseAES specified, but not supported on this CPU");
176 }
177 if (UseAESIntrinsics) {
178 warning("UseAESIntrinsics specified, but not supported on this CPU");
179 }
180 }
181
182 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
183 UseCRC32Intrinsics = true;
184 }
185
186 if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
187 if (FLAG_IS_DEFAULT(UseSHA)) {
188 FLAG_SET_DEFAULT(UseSHA, true);
189 }
190 } else if (UseSHA) {
191 warning("SHA instructions are not available on this CPU");
192 FLAG_SET_DEFAULT(UseSHA, false);
193 }
194
195 if (!UseSHA) {
196 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
197 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
198 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
199 } else {
200 if (auxv & HWCAP_SHA1) {
201 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
202 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
203 }
204 } else if (UseSHA1Intrinsics) {
205 warning("SHA1 instruction is not available on this CPU.");
206 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
207 }
208 if (auxv & HWCAP_SHA2) {
209 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
210 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
211 }
212 } else if (UseSHA256Intrinsics) {
213 warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU.");
214 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
215 }
216 if (UseSHA512Intrinsics) {
217 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
218 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
219 }
220 }
221
222 if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) {
223 UseBarriersForVolatile = (_cpuFeatures & CPU_DMB_ATOMICS) != 0;
224 }
225
226 #ifdef COMPILER2
227 if (FLAG_IS_DEFAULT(OptoScheduling)) {
228 OptoScheduling = true;
229 }
230 #endif
231 }
232
233 void VM_Version::initialize() {
234 ResourceMark rm;
235
236 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
237 if (stub_blob == NULL) {
238 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
239 }
240
241 CodeBuffer c(stub_blob);
242 VM_Version_StubGenerator g(&c);
243 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
244 g.generate_getPsrInfo());
245
246 get_processor_features();
247 }