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src/cpu/aarch64/vm/vm_version_aarch64.cpp
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rev 8079 : 8079203: AARCH64: Need to cater for different partner implementations
Summary: Parse /proc/cpuinfo to derive implementation specific info
Reviewed-by: aph
@@ -57,10 +57,12 @@
#define HWCAP_CRC32 (1<<7)
#endif
int VM_Version::_cpu;
int VM_Version::_model;
+int VM_Version::_variant;
+int VM_Version::_revision;
int VM_Version::_stepping;
int VM_Version::_cpuFeatures;
const char* VM_Version::_features_str = "";
static BufferBlob* stub_blob;
@@ -127,10 +129,34 @@
if (auxv & HWCAP_AES) strcat(buf, ", aes");
if (auxv & HWCAP_SHA1) strcat(buf, ", sha1");
if (auxv & HWCAP_SHA2) strcat(buf, ", sha256");
_features_str = strdup(buf);
+ _cpuFeatures = auxv;
+
+ if (FILE *f = fopen("/proc/cpuinfo", "r")) {
+ char buf[128], *p;
+ while (fgets(buf, sizeof (buf), f) != NULL) {
+ if (p = strchr(buf, ':')) {
+ long v = strtol(p+1, NULL, 0);
+ if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
+ _cpu = v;
+ } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
+ _variant = v;
+ } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
+ _model = v;
+ } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
+ _revision = v;
+ }
+ }
+ }
+ fclose(f);
+ }
+
+ // Enable vendor specific features
+ if (_cpu == CPU_CAVIUM) _cpuFeatures |= CPU_DMB_ATOMICS;
+ if (_cpu == CPU_ARM) _cpuFeatures |= CPU_A53MAC;
if (FLAG_IS_DEFAULT(UseCRC32)) {
UseCRC32 = (auxv & HWCAP_CRC32) != 0;
}
if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
@@ -191,10 +217,14 @@
warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
}
}
+ if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) {
+ UseBarriersForVolatile = (_cpuFeatures & CPU_DMB_ATOMICS) != 0;
+ }
+
#ifdef COMPILER2
if (FLAG_IS_DEFAULT(OptoScheduling)) {
OptoScheduling = true;
}
#endif
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