1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30
31 // MacroAssembler extends Assembler by frequently used macros.
32 //
33 // Instructions for which a 'better' code sequence exists depending
34 // on arguments should also go in here.
35
36 class MacroAssembler: public Assembler {
37 friend class LIR_Assembler;
38
39 using Assembler::mov;
40
41 protected:
42
43 // Support for VM calls
44 //
45 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
46 // may customize this version by overriding it for its purposes (e.g., to save/restore
47 // additional registers when doing a VM call).
48 #ifdef CC_INTERP
49 // c++ interpreter never wants to use interp_masm version of call_VM
50 #define VIRTUAL
51 #else
52 #define VIRTUAL virtual
53 #endif
54
55 VIRTUAL void call_VM_leaf_base(
56 address entry_point, // the entry point
57 int number_of_arguments, // the number of arguments to pop after the call
58 Label *retaddr = NULL
59 );
60
61 VIRTUAL void call_VM_leaf_base(
62 address entry_point, // the entry point
63 int number_of_arguments, // the number of arguments to pop after the call
64 Label &retaddr) {
65 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
66 }
67
68 // This is the base routine called by the different versions of call_VM. The interpreter
69 // may customize this version by overriding it for its purposes (e.g., to save/restore
70 // additional registers when doing a VM call).
71 //
72 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
73 // returns the register which contains the thread upon return. If a thread register has been
74 // specified, the return value will correspond to that register. If no last_java_sp is specified
75 // (noreg) than rsp will be used instead.
76 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
77 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
78 Register java_thread, // the thread if computed before ; use noreg otherwise
79 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
80 address entry_point, // the entry point
81 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
82 bool check_exceptions // whether to check for pending exceptions after return
83 );
84
85 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
86 // The implementation is only non-empty for the InterpreterMacroAssembler,
87 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
88 virtual void check_and_handle_popframe(Register java_thread);
89 virtual void check_and_handle_earlyret(Register java_thread);
90
91 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
92
93 // Maximum size of class area in Metaspace when compressed
94 uint64_t use_XOR_for_compressed_class_base;
95
96 public:
97 MacroAssembler(CodeBuffer* code) : Assembler(code) {
98 use_XOR_for_compressed_class_base
99 = (operand_valid_for_logical_immediate(false /*is32*/,
100 (uint64_t)Universe::narrow_klass_base())
101 && ((uint64_t)Universe::narrow_klass_base()
102 > (1u << log2_intptr(CompressedClassSpaceSize))));
103 }
104
105 // Biased locking support
106 // lock_reg and obj_reg must be loaded up with the appropriate values.
107 // swap_reg is killed.
108 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
109 // be killed; if not supplied, push/pop will be used internally to
110 // allocate a temporary (inefficient, avoid if possible).
111 // Optional slow case is for implementations (interpreter and C1) which branch to
112 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
113 // Returns offset of first potentially-faulting instruction for null
114 // check info (currently consumed only by C1). If
115 // swap_reg_contains_mark is true then returns -1 as it is assumed
116 // the calling code has already passed any potential faults.
117 int biased_locking_enter(Register lock_reg, Register obj_reg,
118 Register swap_reg, Register tmp_reg,
119 bool swap_reg_contains_mark,
120 Label& done, Label* slow_case = NULL,
121 BiasedLockingCounters* counters = NULL);
122 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
123
124
125 // Helper functions for statistics gathering.
126 // Unconditional atomic increment.
127 void atomic_incw(Register counter_addr, Register tmp);
128 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2) {
129 lea(tmp1, counter_addr);
130 atomic_incw(tmp1, tmp2);
131 }
132 // Load Effective Address
133 void lea(Register r, const Address &a) {
134 InstructionMark im(this);
135 code_section()->relocate(inst_mark(), a.rspec());
136 a.lea(this, r);
137 }
138
139 void addmw(Address a, Register incr, Register scratch) {
140 ldrw(scratch, a);
141 addw(scratch, scratch, incr);
142 strw(scratch, a);
143 }
144
145 // Add constant to memory word
146 void addmw(Address a, int imm, Register scratch) {
147 ldrw(scratch, a);
148 if (imm > 0)
149 addw(scratch, scratch, (unsigned)imm);
150 else
151 subw(scratch, scratch, (unsigned)-imm);
152 strw(scratch, a);
153 }
154
155 // Frame creation and destruction shared between JITs.
156 void build_frame(int framesize);
157 void remove_frame(int framesize);
158
159 virtual void _call_Unimplemented(address call_site) {
160 mov(rscratch2, call_site);
161 haltsim();
162 }
163
164 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
165
166 virtual void notify(int type);
167
168 // aliases defined in AARCH64 spec
169
170 template<class T>
171 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
172 inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); }
173
174 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
175 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
176
177 void cset(Register Rd, Assembler::Condition cond) {
178 csinc(Rd, zr, zr, ~cond);
179 }
180 void csetw(Register Rd, Assembler::Condition cond) {
181 csincw(Rd, zr, zr, ~cond);
182 }
183
184 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
185 csneg(Rd, Rn, Rn, ~cond);
186 }
187 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
188 csnegw(Rd, Rn, Rn, ~cond);
189 }
190
191 inline void movw(Register Rd, Register Rn) {
192 if (Rd == sp || Rn == sp) {
193 addw(Rd, Rn, 0U);
194 } else {
195 orrw(Rd, zr, Rn);
196 }
197 }
198 inline void mov(Register Rd, Register Rn) {
199 assert(Rd != r31_sp && Rn != r31_sp, "should be");
200 if (Rd == Rn) {
201 } else if (Rd == sp || Rn == sp) {
202 add(Rd, Rn, 0U);
203 } else {
204 orr(Rd, zr, Rn);
205 }
206 }
207
208 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
209 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
210
211 inline void tstw(Register Rd, unsigned imm) { andsw(zr, Rd, imm); }
212 inline void tst(Register Rd, unsigned imm) { ands(zr, Rd, imm); }
213
214 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
215 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
216 }
217 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
218 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
219 }
220
221 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
222 bfmw(Rd, Rn, lsb, (lsb + width - 1));
223 }
224 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
225 bfm(Rd, Rn, lsb , (lsb + width - 1));
226 }
227
228 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
229 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
230 }
231 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
232 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
233 }
234
235 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
236 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
237 }
238 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
239 sbfm(Rd, Rn, lsb , (lsb + width - 1));
240 }
241
242 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
243 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
244 }
245 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
246 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
247 }
248
249 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
250 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
251 }
252 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
253 ubfm(Rd, Rn, lsb , (lsb + width - 1));
254 }
255
256 inline void asrw(Register Rd, Register Rn, unsigned imm) {
257 sbfmw(Rd, Rn, imm, 31);
258 }
259
260 inline void asr(Register Rd, Register Rn, unsigned imm) {
261 sbfm(Rd, Rn, imm, 63);
262 }
263
264 inline void lslw(Register Rd, Register Rn, unsigned imm) {
265 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
266 }
267
268 inline void lsl(Register Rd, Register Rn, unsigned imm) {
269 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
270 }
271
272 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
273 ubfmw(Rd, Rn, imm, 31);
274 }
275
276 inline void lsr(Register Rd, Register Rn, unsigned imm) {
277 ubfm(Rd, Rn, imm, 63);
278 }
279
280 inline void rorw(Register Rd, Register Rn, unsigned imm) {
281 extrw(Rd, Rn, Rn, imm);
282 }
283
284 inline void ror(Register Rd, Register Rn, unsigned imm) {
285 extr(Rd, Rn, Rn, imm);
286 }
287
288 inline void sxtbw(Register Rd, Register Rn) {
289 sbfmw(Rd, Rn, 0, 7);
290 }
291 inline void sxthw(Register Rd, Register Rn) {
292 sbfmw(Rd, Rn, 0, 15);
293 }
294 inline void sxtb(Register Rd, Register Rn) {
295 sbfm(Rd, Rn, 0, 7);
296 }
297 inline void sxth(Register Rd, Register Rn) {
298 sbfm(Rd, Rn, 0, 15);
299 }
300 inline void sxtw(Register Rd, Register Rn) {
301 sbfm(Rd, Rn, 0, 31);
302 }
303
304 inline void uxtbw(Register Rd, Register Rn) {
305 ubfmw(Rd, Rn, 0, 7);
306 }
307 inline void uxthw(Register Rd, Register Rn) {
308 ubfmw(Rd, Rn, 0, 15);
309 }
310 inline void uxtb(Register Rd, Register Rn) {
311 ubfm(Rd, Rn, 0, 7);
312 }
313 inline void uxth(Register Rd, Register Rn) {
314 ubfm(Rd, Rn, 0, 15);
315 }
316 inline void uxtw(Register Rd, Register Rn) {
317 ubfm(Rd, Rn, 0, 31);
318 }
319
320 inline void cmnw(Register Rn, Register Rm) {
321 addsw(zr, Rn, Rm);
322 }
323 inline void cmn(Register Rn, Register Rm) {
324 adds(zr, Rn, Rm);
325 }
326
327 inline void cmpw(Register Rn, Register Rm) {
328 subsw(zr, Rn, Rm);
329 }
330 inline void cmp(Register Rn, Register Rm) {
331 subs(zr, Rn, Rm);
332 }
333
334 inline void negw(Register Rd, Register Rn) {
335 subw(Rd, zr, Rn);
336 }
337
338 inline void neg(Register Rd, Register Rn) {
339 sub(Rd, zr, Rn);
340 }
341
342 inline void negsw(Register Rd, Register Rn) {
343 subsw(Rd, zr, Rn);
344 }
345
346 inline void negs(Register Rd, Register Rn) {
347 subs(Rd, zr, Rn);
348 }
349
350 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
351 addsw(zr, Rn, Rm, kind, shift);
352 }
353 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
354 adds(zr, Rn, Rm, kind, shift);
355 }
356
357 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
358 subsw(zr, Rn, Rm, kind, shift);
359 }
360 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
361 subs(zr, Rn, Rm, kind, shift);
362 }
363
364 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
365 subw(Rd, zr, Rn, kind, shift);
366 }
367
368 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
369 sub(Rd, zr, Rn, kind, shift);
370 }
371
372 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
373 subsw(Rd, zr, Rn, kind, shift);
374 }
375
376 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
377 subs(Rd, zr, Rn, kind, shift);
378 }
379
380 inline void mnegw(Register Rd, Register Rn, Register Rm) {
381 msubw(Rd, Rn, Rm, zr);
382 }
383 inline void mneg(Register Rd, Register Rn, Register Rm) {
384 msub(Rd, Rn, Rm, zr);
385 }
386
387 inline void mulw(Register Rd, Register Rn, Register Rm) {
388 maddw(Rd, Rn, Rm, zr);
389 }
390 inline void mul(Register Rd, Register Rn, Register Rm) {
391 madd(Rd, Rn, Rm, zr);
392 }
393
394 inline void smnegl(Register Rd, Register Rn, Register Rm) {
395 smsubl(Rd, Rn, Rm, zr);
396 }
397 inline void smull(Register Rd, Register Rn, Register Rm) {
398 smaddl(Rd, Rn, Rm, zr);
399 }
400
401 inline void umnegl(Register Rd, Register Rn, Register Rm) {
402 umsubl(Rd, Rn, Rm, zr);
403 }
404 inline void umull(Register Rd, Register Rn, Register Rm) {
405 umaddl(Rd, Rn, Rm, zr);
406 }
407
408 #define WRAP(INSN) \
409 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
410 if ((VM_Version::cpu_cpuFeatures() & VM_Version::CPU_A53MAC) && Ra != zr) \
411 nop(); \
412 Assembler::INSN(Rd, Rn, Rm, Ra); \
413 }
414
415 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
416 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
417 #undef WRAP
418
419
420 // macro assembly operations needed for aarch64
421
422 // first two private routines for loading 32 bit or 64 bit constants
423 private:
424
425 void mov_immediate64(Register dst, u_int64_t imm64);
426 void mov_immediate32(Register dst, u_int32_t imm32);
427
428 int push(unsigned int bitset, Register stack);
429 int pop(unsigned int bitset, Register stack);
430
431 void mov(Register dst, Address a);
432
433 public:
434 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
435 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
436
437 // now mov instructions for loading absolute addresses and 32 or
438 // 64 bit integers
439
440 inline void mov(Register dst, address addr)
441 {
442 mov_immediate64(dst, (u_int64_t)addr);
443 }
444
445 inline void mov(Register dst, u_int64_t imm64)
446 {
447 mov_immediate64(dst, imm64);
448 }
449
450 inline void movw(Register dst, u_int32_t imm32)
451 {
452 mov_immediate32(dst, imm32);
453 }
454
455 inline void mov(Register dst, long l)
456 {
457 mov(dst, (u_int64_t)l);
458 }
459
460 inline void mov(Register dst, int i)
461 {
462 mov(dst, (long)i);
463 }
464
465 void movptr(Register r, uintptr_t imm64);
466
467 // macro instructions for accessing and updating floating point
468 // status register
469 //
470 // FPSR : op1 == 011
471 // CRn == 0100
472 // CRm == 0100
473 // op2 == 001
474
475 inline void get_fpsr(Register reg)
476 {
477 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
478 }
479
480 inline void set_fpsr(Register reg)
481 {
482 msr(0b011, 0b0100, 0b0100, 0b001, reg);
483 }
484
485 inline void clear_fpsr()
486 {
487 msr(0b011, 0b0100, 0b0100, 0b001, zr);
488 }
489
490 // idiv variant which deals with MINLONG as dividend and -1 as divisor
491 int corrected_idivl(Register result, Register ra, Register rb,
492 bool want_remainder, Register tmp = rscratch1);
493 int corrected_idivq(Register result, Register ra, Register rb,
494 bool want_remainder, Register tmp = rscratch1);
495
496 // Support for NULL-checks
497 //
498 // Generates code that causes a NULL OS exception if the content of reg is NULL.
499 // If the accessed location is M[reg + offset] and the offset is known, provide the
500 // offset. No explicit code generation is needed if the offset is within a certain
501 // range (0 <= offset <= page_size).
502
503 virtual void null_check(Register reg, int offset = -1);
504 static bool needs_explicit_null_check(intptr_t offset);
505
506 static address target_addr_for_insn(address insn_addr, unsigned insn);
507 static address target_addr_for_insn(address insn_addr) {
508 unsigned insn = *(unsigned*)insn_addr;
509 return target_addr_for_insn(insn_addr, insn);
510 }
511
512 // Required platform-specific helpers for Label::patch_instructions.
513 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
514 static int pd_patch_instruction_size(address branch, address target);
515 static void pd_patch_instruction(address branch, address target) {
516 pd_patch_instruction_size(branch, target);
517 }
518 static address pd_call_destination(address branch) {
519 return target_addr_for_insn(branch);
520 }
521 #ifndef PRODUCT
522 static void pd_print_patched_instruction(address branch);
523 #endif
524
525 static int patch_oop(address insn_addr, address o);
526
527 void emit_trampoline_stub(int insts_call_instruction_offset, address target);
528
529 // The following 4 methods return the offset of the appropriate move instruction
530
531 // Support for fast byte/short loading with zero extension (depending on particular CPU)
532 int load_unsigned_byte(Register dst, Address src);
533 int load_unsigned_short(Register dst, Address src);
534
535 // Support for fast byte/short loading with sign extension (depending on particular CPU)
536 int load_signed_byte(Register dst, Address src);
537 int load_signed_short(Register dst, Address src);
538
539 int load_signed_byte32(Register dst, Address src);
540 int load_signed_short32(Register dst, Address src);
541
542 // Support for sign-extension (hi:lo = extend_sign(lo))
543 void extend_sign(Register hi, Register lo);
544
545 // Load and store values by size and signed-ness
546 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
547 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
548
549 // Support for inc/dec with optimal instruction selection depending on value
550
551 // x86_64 aliases an unqualified register/address increment and
552 // decrement to call incrementq and decrementq but also supports
553 // explicitly sized calls to incrementq/decrementq or
554 // incrementl/decrementl
555
556 // for aarch64 the proper convention would be to use
557 // increment/decrement for 64 bit operatons and
558 // incrementw/decrementw for 32 bit operations. so when porting
559 // x86_64 code we can leave calls to increment/decrement as is,
560 // replace incrementq/decrementq with increment/decrement and
561 // replace incrementl/decrementl with incrementw/decrementw.
562
563 // n.b. increment/decrement calls with an Address destination will
564 // need to use a scratch register to load the value to be
565 // incremented. increment/decrement calls which add or subtract a
566 // constant value greater than 2^12 will need to use a 2nd scratch
567 // register to hold the constant. so, a register increment/decrement
568 // may trash rscratch2 and an address increment/decrement trash
569 // rscratch and rscratch2
570
571 void decrementw(Address dst, int value = 1);
572 void decrementw(Register reg, int value = 1);
573
574 void decrement(Register reg, int value = 1);
575 void decrement(Address dst, int value = 1);
576
577 void incrementw(Address dst, int value = 1);
578 void incrementw(Register reg, int value = 1);
579
580 void increment(Register reg, int value = 1);
581 void increment(Address dst, int value = 1);
582
583
584 // Alignment
585 void align(int modulus);
586
587 // Stack frame creation/removal
588 void enter()
589 {
590 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
591 mov(rfp, sp);
592 }
593 void leave()
594 {
595 mov(sp, rfp);
596 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
597 }
598
599 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
600 // The pointer will be loaded into the thread register.
601 void get_thread(Register thread);
602
603
604 // Support for VM calls
605 //
606 // It is imperative that all calls into the VM are handled via the call_VM macros.
607 // They make sure that the stack linkage is setup correctly. call_VM's correspond
608 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
609
610
611 void call_VM(Register oop_result,
612 address entry_point,
613 bool check_exceptions = true);
614 void call_VM(Register oop_result,
615 address entry_point,
616 Register arg_1,
617 bool check_exceptions = true);
618 void call_VM(Register oop_result,
619 address entry_point,
620 Register arg_1, Register arg_2,
621 bool check_exceptions = true);
622 void call_VM(Register oop_result,
623 address entry_point,
624 Register arg_1, Register arg_2, Register arg_3,
625 bool check_exceptions = true);
626
627 // Overloadings with last_Java_sp
628 void call_VM(Register oop_result,
629 Register last_java_sp,
630 address entry_point,
631 int number_of_arguments = 0,
632 bool check_exceptions = true);
633 void call_VM(Register oop_result,
634 Register last_java_sp,
635 address entry_point,
636 Register arg_1, bool
637 check_exceptions = true);
638 void call_VM(Register oop_result,
639 Register last_java_sp,
640 address entry_point,
641 Register arg_1, Register arg_2,
642 bool check_exceptions = true);
643 void call_VM(Register oop_result,
644 Register last_java_sp,
645 address entry_point,
646 Register arg_1, Register arg_2, Register arg_3,
647 bool check_exceptions = true);
648
649 void get_vm_result (Register oop_result, Register thread);
650 void get_vm_result_2(Register metadata_result, Register thread);
651
652 // These always tightly bind to MacroAssembler::call_VM_base
653 // bypassing the virtual implementation
654 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
655 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
656 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
657 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
658 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
659
660 void call_VM_leaf(address entry_point,
661 int number_of_arguments = 0);
662 void call_VM_leaf(address entry_point,
663 Register arg_1);
664 void call_VM_leaf(address entry_point,
665 Register arg_1, Register arg_2);
666 void call_VM_leaf(address entry_point,
667 Register arg_1, Register arg_2, Register arg_3);
668
669 // These always tightly bind to MacroAssembler::call_VM_leaf_base
670 // bypassing the virtual implementation
671 void super_call_VM_leaf(address entry_point);
672 void super_call_VM_leaf(address entry_point, Register arg_1);
673 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
674 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
675 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
676
677 // last Java Frame (fills frame anchor)
678 void set_last_Java_frame(Register last_java_sp,
679 Register last_java_fp,
680 address last_java_pc,
681 Register scratch);
682
683 void set_last_Java_frame(Register last_java_sp,
684 Register last_java_fp,
685 Label &last_java_pc,
686 Register scratch);
687
688 void set_last_Java_frame(Register last_java_sp,
689 Register last_java_fp,
690 Register last_java_pc,
691 Register scratch);
692
693 void reset_last_Java_frame(Register thread, bool clearfp, bool clear_pc);
694
695 // thread in the default location (r15_thread on 64bit)
696 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
697
698 // Stores
699 void store_check(Register obj); // store check for obj - register is destroyed afterwards
700 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
701
702 #if INCLUDE_ALL_GCS
703
704 void g1_write_barrier_pre(Register obj,
705 Register pre_val,
706 Register thread,
707 Register tmp,
708 bool tosca_live,
709 bool expand_call);
710
711 void g1_write_barrier_post(Register store_addr,
712 Register new_val,
713 Register thread,
714 Register tmp,
715 Register tmp2);
716
717 #endif // INCLUDE_ALL_GCS
718
719 // split store_check(Register obj) to enhance instruction interleaving
720 void store_check_part_1(Register obj);
721 void store_check_part_2(Register obj);
722
723 // oop manipulations
724 void load_klass(Register dst, Register src);
725 void store_klass(Register dst, Register src);
726 void cmp_klass(Register oop, Register trial_klass, Register tmp);
727
728 void load_heap_oop(Register dst, Address src);
729
730 void load_heap_oop_not_null(Register dst, Address src);
731 void store_heap_oop(Address dst, Register src);
732
733 // currently unimplemented
734 // Used for storing NULL. All other oop constants should be
735 // stored using routines that take a jobject.
736 void store_heap_oop_null(Address dst);
737
738 void load_prototype_header(Register dst, Register src);
739
740 void store_klass_gap(Register dst, Register src);
741
742 // This dummy is to prevent a call to store_heap_oop from
743 // converting a zero (like NULL) into a Register by giving
744 // the compiler two choices it can't resolve
745
746 void store_heap_oop(Address dst, void* dummy);
747
748 void encode_heap_oop(Register d, Register s);
749 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
750 void decode_heap_oop(Register d, Register s);
751 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
752 void encode_heap_oop_not_null(Register r);
753 void decode_heap_oop_not_null(Register r);
754 void encode_heap_oop_not_null(Register dst, Register src);
755 void decode_heap_oop_not_null(Register dst, Register src);
756
757 void set_narrow_oop(Register dst, jobject obj);
758
759 void encode_klass_not_null(Register r);
760 void decode_klass_not_null(Register r);
761 void encode_klass_not_null(Register dst, Register src);
762 void decode_klass_not_null(Register dst, Register src);
763
764 void set_narrow_klass(Register dst, Klass* k);
765
766 // if heap base register is used - reinit it with the correct value
767 void reinit_heapbase();
768
769 DEBUG_ONLY(void verify_heapbase(const char* msg);)
770
771 void push_CPU_state();
772 void pop_CPU_state() ;
773
774 // Round up to a power of two
775 void round_to(Register reg, int modulus);
776
777 // allocation
778 void eden_allocate(
779 Register obj, // result: pointer to object after successful allocation
780 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
781 int con_size_in_bytes, // object size in bytes if known at compile time
782 Register t1, // temp register
783 Label& slow_case // continuation point if fast allocation fails
784 );
785 void tlab_allocate(
786 Register obj, // result: pointer to object after successful allocation
787 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
788 int con_size_in_bytes, // object size in bytes if known at compile time
789 Register t1, // temp register
790 Register t2, // temp register
791 Label& slow_case // continuation point if fast allocation fails
792 );
793 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
794 void verify_tlab();
795
796 void incr_allocated_bytes(Register thread,
797 Register var_size_in_bytes, int con_size_in_bytes,
798 Register t1 = noreg);
799
800 // interface method calling
801 void lookup_interface_method(Register recv_klass,
802 Register intf_klass,
803 RegisterOrConstant itable_index,
804 Register method_result,
805 Register scan_temp,
806 Label& no_such_interface);
807
808 // virtual method calling
809 // n.b. x86 allows RegisterOrConstant for vtable_index
810 void lookup_virtual_method(Register recv_klass,
811 RegisterOrConstant vtable_index,
812 Register method_result);
813
814 // Test sub_klass against super_klass, with fast and slow paths.
815
816 // The fast path produces a tri-state answer: yes / no / maybe-slow.
817 // One of the three labels can be NULL, meaning take the fall-through.
818 // If super_check_offset is -1, the value is loaded up from super_klass.
819 // No registers are killed, except temp_reg.
820 void check_klass_subtype_fast_path(Register sub_klass,
821 Register super_klass,
822 Register temp_reg,
823 Label* L_success,
824 Label* L_failure,
825 Label* L_slow_path,
826 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
827
828 // The rest of the type check; must be wired to a corresponding fast path.
829 // It does not repeat the fast path logic, so don't use it standalone.
830 // The temp_reg and temp2_reg can be noreg, if no temps are available.
831 // Updates the sub's secondary super cache as necessary.
832 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
833 void check_klass_subtype_slow_path(Register sub_klass,
834 Register super_klass,
835 Register temp_reg,
836 Register temp2_reg,
837 Label* L_success,
838 Label* L_failure,
839 bool set_cond_codes = false);
840
841 // Simplified, combined version, good for typical uses.
842 // Falls through on failure.
843 void check_klass_subtype(Register sub_klass,
844 Register super_klass,
845 Register temp_reg,
846 Label& L_success);
847
848 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
849
850
851 // Debugging
852
853 // only if +VerifyOops
854 void verify_oop(Register reg, const char* s = "broken oop");
855 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
856
857 // TODO: verify method and klass metadata (compare against vptr?)
858 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
859 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
860
861 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
862 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
863
864 // only if +VerifyFPU
865 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
866
867 // prints msg, dumps registers and stops execution
868 void stop(const char* msg);
869
870 // prints msg and continues
871 void warn(const char* msg);
872
873 static void debug64(char* msg, int64_t pc, int64_t regs[]);
874
875 void untested() { stop("untested"); }
876
877 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
878
879 void should_not_reach_here() { stop("should not reach here"); }
880
881 // Stack overflow checking
882 void bang_stack_with_offset(int offset) {
883 // stack grows down, caller passes positive offset
884 assert(offset > 0, "must bang with negative offset");
885 mov(rscratch2, -offset);
886 str(zr, Address(sp, rscratch2));
887 }
888
889 // Writes to stack successive pages until offset reached to check for
890 // stack overflow + shadow pages. Also, clobbers tmp
891 void bang_stack_size(Register size, Register tmp);
892
893 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
894 Register tmp,
895 int offset);
896
897 // Support for serializing memory accesses between threads
898 void serialize_memory(Register thread, Register tmp);
899
900 // Arithmetics
901
902 void addptr(Address dst, int32_t src) {
903 lea(rscratch2, dst);
904 ldr(rscratch1, Address(rscratch2));
905 add(rscratch1, rscratch1, src);
906 str(rscratch1, Address(rscratch2));
907 }
908
909 void cmpptr(Register src1, Address src2);
910
911 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
912 Label &suceed, Label *fail);
913
914 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
915 Label &suceed, Label *fail);
916
917 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
918 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
919
920 void atomic_xchg(Register prev, Register newv, Register addr);
921 void atomic_xchgw(Register prev, Register newv, Register addr);
922
923 void orptr(Address adr, RegisterOrConstant src) {
924 ldr(rscratch2, adr);
925 if (src.is_register())
926 orr(rscratch2, rscratch2, src.as_register());
927 else
928 orr(rscratch2, rscratch2, src.as_constant());
929 str(rscratch2, adr);
930 }
931
932 // Calls
933
934 void trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
935
936 static bool far_branches() {
937 return ReservedCodeCacheSize > branch_range;
938 }
939
940 // Jumps that can reach anywhere in the code cache.
941 // Trashes tmp.
942 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
943 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
944
945 static int far_branch_size() {
946 if (far_branches()) {
947 return 3 * 4; // adrp, add, br
948 } else {
949 return 4;
950 }
951 }
952
953 // Emit the CompiledIC call idiom
954 void ic_call(address entry);
955
956 public:
957
958 // Data
959
960 void mov_metadata(Register dst, Metadata* obj);
961 Address allocate_metadata_address(Metadata* obj);
962 Address constant_oop_address(jobject obj);
963
964 void movoop(Register dst, jobject obj, bool immediate = false);
965
966 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
967 void kernel_crc32(Register crc, Register buf, Register len,
968 Register table0, Register table1, Register table2, Register table3,
969 Register tmp, Register tmp2, Register tmp3);
970
971 #undef VIRTUAL
972
973 // Stack push and pop individual 64 bit registers
974 void push(Register src);
975 void pop(Register dst);
976
977 // push all registers onto the stack
978 void pusha();
979 void popa();
980
981 void repne_scan(Register addr, Register value, Register count,
982 Register scratch);
983 void repne_scanw(Register addr, Register value, Register count,
984 Register scratch);
985
986 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
987 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
988
989 // If a constant does not fit in an immediate field, generate some
990 // number of MOV instructions and then perform the operation
991 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
992 add_sub_imm_insn insn1,
993 add_sub_reg_insn insn2);
994 // Seperate vsn which sets the flags
995 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
996 add_sub_imm_insn insn1,
997 add_sub_reg_insn insn2);
998
999 #define WRAP(INSN) \
1000 void INSN(Register Rd, Register Rn, unsigned imm) { \
1001 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1002 } \
1003 \
1004 void INSN(Register Rd, Register Rn, Register Rm, \
1005 enum shift_kind kind, unsigned shift = 0) { \
1006 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1007 } \
1008 \
1009 void INSN(Register Rd, Register Rn, Register Rm) { \
1010 Assembler::INSN(Rd, Rn, Rm); \
1011 } \
1012 \
1013 void INSN(Register Rd, Register Rn, Register Rm, \
1014 ext::operation option, int amount = 0) { \
1015 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1016 }
1017
1018 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1019
1020 #undef WRAP
1021 #define WRAP(INSN) \
1022 void INSN(Register Rd, Register Rn, unsigned imm) { \
1023 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1024 } \
1025 \
1026 void INSN(Register Rd, Register Rn, Register Rm, \
1027 enum shift_kind kind, unsigned shift = 0) { \
1028 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1029 } \
1030 \
1031 void INSN(Register Rd, Register Rn, Register Rm) { \
1032 Assembler::INSN(Rd, Rn, Rm); \
1033 } \
1034 \
1035 void INSN(Register Rd, Register Rn, Register Rm, \
1036 ext::operation option, int amount = 0) { \
1037 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1038 }
1039
1040 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1041
1042 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1043 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1044
1045 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1046
1047 void tableswitch(Register index, jint lowbound, jint highbound,
1048 Label &jumptable, Label &jumptable_end, int stride = 1) {
1049 adr(rscratch1, jumptable);
1050 subsw(rscratch2, index, lowbound);
1051 subsw(zr, rscratch2, highbound - lowbound);
1052 br(Assembler::HS, jumptable_end);
1053 add(rscratch1, rscratch1, rscratch2,
1054 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1055 br(rscratch1);
1056 }
1057
1058 // Form an address from base + offset in Rd. Rd may or may not
1059 // actually be used: you must use the Address that is returned. It
1060 // is up to you to ensure that the shift provided matches the size
1061 // of your data.
1062 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1063
1064 // Prolog generator routines to support switch between x86 code and
1065 // generated ARM code
1066
1067 // routine to generate an x86 prolog for a stub function which
1068 // bootstraps into the generated ARM code which directly follows the
1069 // stub
1070 //
1071
1072 public:
1073 // enum used for aarch64--x86 linkage to define return type of x86 function
1074 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1075
1076 #ifdef BUILTIN_SIM
1077 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1078 #else
1079 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1080 #endif
1081
1082 // special version of call_VM_leaf_base needed for aarch64 simulator
1083 // where we need to specify both the gp and fp arg counts and the
1084 // return type so that the linkage routine from aarch64 to x86 and
1085 // back knows which aarch64 registers to copy to x86 registers and
1086 // which x86 result register to copy back to an aarch64 register
1087
1088 void call_VM_leaf_base1(
1089 address entry_point, // the entry point
1090 int number_of_gp_arguments, // the number of gp reg arguments to pass
1091 int number_of_fp_arguments, // the number of fp reg arguments to pass
1092 ret_type type, // the return type for the call
1093 Label* retaddr = NULL
1094 );
1095
1096 void ldr_constant(Register dest, const Address &const_addr) {
1097 if (NearCpool) {
1098 ldr(dest, const_addr);
1099 } else {
1100 unsigned long offset;
1101 adrp(dest, InternalAddress(const_addr.target()), offset);
1102 ldr(dest, Address(dest, offset));
1103 }
1104 }
1105
1106 address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1107 address read_polling_page(Register r, relocInfo::relocType rtype);
1108
1109 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1110 void update_byte_crc32(Register crc, Register val, Register table);
1111 void update_word_crc32(Register crc, Register v, Register tmp,
1112 Register table0, Register table1, Register table2, Register table3,
1113 bool upper = false);
1114
1115 void string_compare(Register str1, Register str2,
1116 Register cnt1, Register cnt2, Register result,
1117 Register tmp1);
1118 void string_equals(Register str1, Register str2,
1119 Register cnt, Register result,
1120 Register tmp1);
1121 void char_arrays_equals(Register ary1, Register ary2,
1122 Register result, Register tmp1);
1123 void encode_iso_array(Register src, Register dst,
1124 Register len, Register result,
1125 FloatRegister Vtmp1, FloatRegister Vtmp2,
1126 FloatRegister Vtmp3, FloatRegister Vtmp4);
1127 void string_indexof(Register str1, Register str2,
1128 Register cnt1, Register cnt2,
1129 Register tmp1, Register tmp2,
1130 Register tmp3, Register tmp4,
1131 int int_cnt1, Register result);
1132 private:
1133 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1134 Register src1, Register src2);
1135 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1136 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1137 }
1138 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1139 Register y, Register y_idx, Register z,
1140 Register carry, Register product,
1141 Register idx, Register kdx);
1142 void multiply_128_x_128_loop(Register y, Register z,
1143 Register carry, Register carry2,
1144 Register idx, Register jdx,
1145 Register yz_idx1, Register yz_idx2,
1146 Register tmp, Register tmp3, Register tmp4,
1147 Register tmp7, Register product_hi);
1148 public:
1149 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1150 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1151 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1152 // ISB may be needed because of a safepoint
1153 void maybe_isb() { isb(); }
1154
1155 private:
1156 // Return the effective address r + (r1 << ext) + offset.
1157 // Uses rscratch2.
1158 Address offsetted_address(Register r, Register r1, Address::extend ext,
1159 int offset, int size);
1160 };
1161
1162 #ifdef ASSERT
1163 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1164 #endif
1165
1166 /**
1167 * class SkipIfEqual:
1168 *
1169 * Instantiating this class will result in assembly code being output that will
1170 * jump around any code emitted between the creation of the instance and it's
1171 * automatic destruction at the end of a scope block, depending on the value of
1172 * the flag passed to the constructor, which will be checked at run-time.
1173 */
1174 class SkipIfEqual {
1175 private:
1176 MacroAssembler* _masm;
1177 Label _label;
1178
1179 public:
1180 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1181 ~SkipIfEqual();
1182 };
1183
1184 struct tableswitch {
1185 Register _reg;
1186 int _insn_index; jint _first_key; jint _last_key;
1187 Label _after;
1188 Label _branches;
1189 };
1190
1191 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP