1 /* 2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP 27 #define CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP 28 29 #include "asm/register.hpp" 30 31 // definitions of various symbolic names for machine registers 32 33 // First intercalls between C and Java which use 8 general registers 34 // and 8 floating registers 35 36 // we also have to copy between x86 and ARM registers but that's a 37 // secondary complication -- not all code employing C call convention 38 // executes as x86 code though -- we generate some of it 39 40 class Argument VALUE_OBJ_CLASS_SPEC { 41 public: 42 enum { 43 n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...) 44 n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... ) 45 46 n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ... 47 n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ... 48 }; 49 }; 50 51 REGISTER_DECLARATION(Register, c_rarg0, r0); 52 REGISTER_DECLARATION(Register, c_rarg1, r1); 53 REGISTER_DECLARATION(Register, c_rarg2, r2); 54 REGISTER_DECLARATION(Register, c_rarg3, r3); 55 REGISTER_DECLARATION(Register, c_rarg4, r4); 56 REGISTER_DECLARATION(Register, c_rarg5, r5); 57 REGISTER_DECLARATION(Register, c_rarg6, r6); 58 REGISTER_DECLARATION(Register, c_rarg7, r7); 59 60 REGISTER_DECLARATION(FloatRegister, c_farg0, v0); 61 REGISTER_DECLARATION(FloatRegister, c_farg1, v1); 62 REGISTER_DECLARATION(FloatRegister, c_farg2, v2); 63 REGISTER_DECLARATION(FloatRegister, c_farg3, v3); 64 REGISTER_DECLARATION(FloatRegister, c_farg4, v4); 65 REGISTER_DECLARATION(FloatRegister, c_farg5, v5); 66 REGISTER_DECLARATION(FloatRegister, c_farg6, v6); 67 REGISTER_DECLARATION(FloatRegister, c_farg7, v7); 68 69 // Symbolically name the register arguments used by the Java calling convention. 70 // We have control over the convention for java so we can do what we please. 71 // What pleases us is to offset the java calling convention so that when 72 // we call a suitable jni method the arguments are lined up and we don't 73 // have to do much shuffling. A suitable jni method is non-static and a 74 // small number of arguments 75 // 76 // |--------------------------------------------------------------------| 77 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 | 78 // |--------------------------------------------------------------------| 79 // | r0 r1 r2 r3 r4 r5 r6 r7 | 80 // |--------------------------------------------------------------------| 81 // | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 | 82 // |--------------------------------------------------------------------| 83 84 85 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); 86 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); 87 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); 88 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); 89 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); 90 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6); 91 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7); 92 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0); 93 94 // Java floating args are passed as per C 95 96 REGISTER_DECLARATION(FloatRegister, j_farg0, v0); 97 REGISTER_DECLARATION(FloatRegister, j_farg1, v1); 98 REGISTER_DECLARATION(FloatRegister, j_farg2, v2); 99 REGISTER_DECLARATION(FloatRegister, j_farg3, v3); 100 REGISTER_DECLARATION(FloatRegister, j_farg4, v4); 101 REGISTER_DECLARATION(FloatRegister, j_farg5, v5); 102 REGISTER_DECLARATION(FloatRegister, j_farg6, v6); 103 REGISTER_DECLARATION(FloatRegister, j_farg7, v7); 104 105 // registers used to hold VM data either temporarily within a method 106 // or across method calls 107 108 // volatile (caller-save) registers 109 110 // r8 is used for indirect result location return 111 // we use it and r9 as scratch registers 112 REGISTER_DECLARATION(Register, rscratch1, r8); 113 REGISTER_DECLARATION(Register, rscratch2, r9); 114 115 // current method -- must be in a call-clobbered register 116 REGISTER_DECLARATION(Register, rmethod, r12); 117 118 // non-volatile (callee-save) registers are r16-29 119 // of which the following are dedicated global state 120 121 // link register 122 REGISTER_DECLARATION(Register, lr, r30); 123 // frame pointer 124 REGISTER_DECLARATION(Register, rfp, r29); 125 // current thread 126 REGISTER_DECLARATION(Register, rthread, r28); 127 // base of heap 128 REGISTER_DECLARATION(Register, rheapbase, r27); 129 // constant pool cache 130 REGISTER_DECLARATION(Register, rcpool, r26); 131 // monitors allocated on stack 132 REGISTER_DECLARATION(Register, rmonitors, r25); 133 // locals on stack 134 REGISTER_DECLARATION(Register, rlocals, r24); 135 // bytecode pointer 136 REGISTER_DECLARATION(Register, rbcp, r22); 137 // Dispatch table base 138 REGISTER_DECLARATION(Register, rdispatch, r21); 139 // Java stack pointer 140 REGISTER_DECLARATION(Register, esp, r20); 141 142 // TODO : x86 uses rbp to save SP in method handle code 143 // we may need to do the same with fp 144 // JSR 292 fixed register usages: 145 //REGISTER_DECLARATION(Register, r_mh_SP_save, r29); 146 147 #define assert_cond(ARG1) assert(ARG1, #ARG1) 148 149 namespace asm_util { 150 uint32_t encode_logical_immediate(bool is32, uint64_t imm); 151 }; 152 153 using namespace asm_util; 154 155 156 class Assembler; 157 158 class Instruction_aarch64 { 159 unsigned insn; 160 #ifdef ASSERT 161 unsigned bits; 162 #endif 163 Assembler *assem; 164 165 public: 166 167 Instruction_aarch64(class Assembler *as) { 168 #ifdef ASSERT 169 bits = 0; 170 #endif 171 insn = 0; 172 assem = as; 173 } 174 175 inline ~Instruction_aarch64(); 176 177 unsigned &get_insn() { return insn; } 178 #ifdef ASSERT 179 unsigned &get_bits() { return bits; } 180 #endif 181 182 static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) { 183 union { 184 unsigned u; 185 int n; 186 }; 187 188 u = val << (31 - hi); 189 n = n >> (31 - hi + lo); 190 return n; 191 } 192 193 static inline uint32_t extract(uint32_t val, int msb, int lsb) { 194 int nbits = msb - lsb + 1; 195 assert_cond(msb >= lsb); 196 uint32_t mask = (1U << nbits) - 1; 197 uint32_t result = val >> lsb; 198 result &= mask; 199 return result; 200 } 201 202 static inline int32_t sextract(uint32_t val, int msb, int lsb) { 203 uint32_t uval = extract(val, msb, lsb); 204 return extend(uval, msb - lsb); 205 } 206 207 static void patch(address a, int msb, int lsb, unsigned long val) { 208 int nbits = msb - lsb + 1; 209 guarantee(val < (1U << nbits), "Field too big for insn"); 210 assert_cond(msb >= lsb); 211 unsigned mask = (1U << nbits) - 1; 212 val <<= lsb; 213 mask <<= lsb; 214 unsigned target = *(unsigned *)a; 215 target &= ~mask; 216 target |= val; 217 *(unsigned *)a = target; 218 } 219 220 static void spatch(address a, int msb, int lsb, long val) { 221 int nbits = msb - lsb + 1; 222 long chk = val >> (nbits - 1); 223 guarantee (chk == -1 || chk == 0, "Field too big for insn"); 224 unsigned uval = val; 225 unsigned mask = (1U << nbits) - 1; 226 uval &= mask; 227 uval <<= lsb; 228 mask <<= lsb; 229 unsigned target = *(unsigned *)a; 230 target &= ~mask; 231 target |= uval; 232 *(unsigned *)a = target; 233 } 234 235 void f(unsigned val, int msb, int lsb) { 236 int nbits = msb - lsb + 1; 237 guarantee(val < (1U << nbits), "Field too big for insn"); 238 assert_cond(msb >= lsb); 239 unsigned mask = (1U << nbits) - 1; 240 val <<= lsb; 241 mask <<= lsb; 242 insn |= val; 243 assert_cond((bits & mask) == 0); 244 #ifdef ASSERT 245 bits |= mask; 246 #endif 247 } 248 249 void f(unsigned val, int bit) { 250 f(val, bit, bit); 251 } 252 253 void sf(long val, int msb, int lsb) { 254 int nbits = msb - lsb + 1; 255 long chk = val >> (nbits - 1); 256 guarantee (chk == -1 || chk == 0, "Field too big for insn"); 257 unsigned uval = val; 258 unsigned mask = (1U << nbits) - 1; 259 uval &= mask; 260 f(uval, lsb + nbits - 1, lsb); 261 } 262 263 void rf(Register r, int lsb) { 264 f(r->encoding_nocheck(), lsb + 4, lsb); 265 } 266 267 // reg|ZR 268 void zrf(Register r, int lsb) { 269 f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb); 270 } 271 272 // reg|SP 273 void srf(Register r, int lsb) { 274 f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb); 275 } 276 277 void rf(FloatRegister r, int lsb) { 278 f(r->encoding_nocheck(), lsb + 4, lsb); 279 } 280 281 unsigned get(int msb = 31, int lsb = 0) { 282 int nbits = msb - lsb + 1; 283 unsigned mask = ((1U << nbits) - 1) << lsb; 284 assert_cond(bits & mask == mask); 285 return (insn & mask) >> lsb; 286 } 287 288 void fixed(unsigned value, unsigned mask) { 289 assert_cond ((mask & bits) == 0); 290 #ifdef ASSERT 291 bits |= mask; 292 #endif 293 insn |= value; 294 } 295 }; 296 297 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use) 298 299 class PrePost { 300 int _offset; 301 Register _r; 302 public: 303 PrePost(Register reg, int o) : _r(reg), _offset(o) { } 304 int offset() { return _offset; } 305 Register reg() { return _r; } 306 }; 307 308 class Pre : public PrePost { 309 public: 310 Pre(Register reg, int o) : PrePost(reg, o) { } 311 }; 312 class Post : public PrePost { 313 public: 314 Post(Register reg, int o) : PrePost(reg, o) { } 315 }; 316 317 namespace ext 318 { 319 enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx }; 320 }; 321 322 // abs methods which cannot overflow and so are well-defined across 323 // the entire domain of integer types. 324 static inline unsigned int uabs(unsigned int n) { 325 union { 326 unsigned int result; 327 int value; 328 }; 329 result = n; 330 if (value < 0) result = -result; 331 return result; 332 } 333 static inline unsigned long uabs(unsigned long n) { 334 union { 335 unsigned long result; 336 long value; 337 }; 338 result = n; 339 if (value < 0) result = -result; 340 return result; 341 } 342 static inline unsigned long uabs(long n) { return uabs((unsigned long)n); } 343 static inline unsigned long uabs(int n) { return uabs((unsigned int)n); } 344 345 // Addressing modes 346 class Address VALUE_OBJ_CLASS_SPEC { 347 public: 348 349 enum mode { no_mode, base_plus_offset, pre, post, pcrel, 350 base_plus_offset_reg, literal }; 351 352 // Shift and extend for base reg + reg offset addressing 353 class extend { 354 int _option, _shift; 355 ext::operation _op; 356 public: 357 extend() { } 358 extend(int s, int o, ext::operation op) : _shift(s), _option(o), _op(op) { } 359 int option() const{ return _option; } 360 int shift() const { return _shift; } 361 ext::operation op() const { return _op; } 362 }; 363 class uxtw : public extend { 364 public: 365 uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { } 366 }; 367 class lsl : public extend { 368 public: 369 lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { } 370 }; 371 class sxtw : public extend { 372 public: 373 sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { } 374 }; 375 class sxtx : public extend { 376 public: 377 sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { } 378 }; 379 380 private: 381 Register _base; 382 Register _index; 383 long _offset; 384 enum mode _mode; 385 extend _ext; 386 387 RelocationHolder _rspec; 388 389 // Typically we use AddressLiterals we want to use their rval 390 // However in some situations we want the lval (effect address) of 391 // the item. We provide a special factory for making those lvals. 392 bool _is_lval; 393 394 // If the target is far we'll need to load the ea of this to a 395 // register to reach it. Otherwise if near we can do PC-relative 396 // addressing. 397 address _target; 398 399 public: 400 Address() 401 : _mode(no_mode) { } 402 Address(Register r) 403 : _mode(base_plus_offset), _base(r), _offset(0), _index(noreg), _target(0) { } 404 Address(Register r, int o) 405 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { } 406 Address(Register r, long o) 407 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { } 408 Address(Register r, unsigned long o) 409 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { } 410 #ifdef ASSERT 411 Address(Register r, ByteSize disp) 412 : _mode(base_plus_offset), _base(r), _offset(in_bytes(disp)), 413 _index(noreg), _target(0) { } 414 #endif 415 Address(Register r, Register r1, extend ext = lsl()) 416 : _mode(base_plus_offset_reg), _base(r), _index(r1), 417 _ext(ext), _offset(0), _target(0) { } 418 Address(Pre p) 419 : _mode(pre), _base(p.reg()), _offset(p.offset()) { } 420 Address(Post p) 421 : _mode(post), _base(p.reg()), _offset(p.offset()), _target(0) { } 422 Address(address target, RelocationHolder const& rspec) 423 : _mode(literal), 424 _rspec(rspec), 425 _is_lval(false), 426 _target(target) { } 427 Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type); 428 Address(Register base, RegisterOrConstant index, extend ext = lsl()) 429 : _base (base), 430 _ext(ext), _offset(0), _target(0) { 431 if (index.is_register()) { 432 _mode = base_plus_offset_reg; 433 _index = index.as_register(); 434 } else { 435 guarantee(ext.option() == ext::uxtx, "should be"); 436 assert(index.is_constant(), "should be"); 437 _mode = base_plus_offset; 438 _offset = index.as_constant() << ext.shift(); 439 } 440 } 441 442 Register base() const { 443 guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg 444 | _mode == post), 445 "wrong mode"); 446 return _base; 447 } 448 long offset() const { 449 return _offset; 450 } 451 Register index() const { 452 return _index; 453 } 454 mode getMode() const { 455 return _mode; 456 } 457 bool uses(Register reg) const { return _base == reg || _index == reg; } 458 address target() const { return _target; } 459 const RelocationHolder& rspec() const { return _rspec; } 460 461 void encode(Instruction_aarch64 *i) const { 462 i->f(0b111, 29, 27); 463 i->srf(_base, 5); 464 465 switch(_mode) { 466 case base_plus_offset: 467 { 468 unsigned size = i->get(31, 30); 469 if (i->get(26, 26) && i->get(23, 23)) { 470 // SIMD Q Type - Size = 128 bits 471 assert(size == 0, "bad size"); 472 size = 0b100; 473 } 474 unsigned mask = (1 << size) - 1; 475 if (_offset < 0 || _offset & mask) 476 { 477 i->f(0b00, 25, 24); 478 i->f(0, 21), i->f(0b00, 11, 10); 479 i->sf(_offset, 20, 12); 480 } else { 481 i->f(0b01, 25, 24); 482 i->f(_offset >> size, 21, 10); 483 } 484 } 485 break; 486 487 case base_plus_offset_reg: 488 { 489 i->f(0b00, 25, 24); 490 i->f(1, 21); 491 i->rf(_index, 16); 492 i->f(_ext.option(), 15, 13); 493 unsigned size = i->get(31, 30); 494 if (size == 0) // It's a byte 495 i->f(_ext.shift() >= 0, 12); 496 else { 497 if (_ext.shift() > 0) 498 assert(_ext.shift() == (int)size, "bad shift"); 499 i->f(_ext.shift() > 0, 12); 500 } 501 i->f(0b10, 11, 10); 502 } 503 break; 504 505 case pre: 506 i->f(0b00, 25, 24); 507 i->f(0, 21), i->f(0b11, 11, 10); 508 i->sf(_offset, 20, 12); 509 break; 510 511 case post: 512 i->f(0b00, 25, 24); 513 i->f(0, 21), i->f(0b01, 11, 10); 514 i->sf(_offset, 20, 12); 515 break; 516 517 default: 518 ShouldNotReachHere(); 519 } 520 } 521 522 void encode_pair(Instruction_aarch64 *i) const { 523 switch(_mode) { 524 case base_plus_offset: 525 i->f(0b010, 25, 23); 526 break; 527 case pre: 528 i->f(0b011, 25, 23); 529 break; 530 case post: 531 i->f(0b001, 25, 23); 532 break; 533 default: 534 ShouldNotReachHere(); 535 } 536 537 unsigned size; // Operand shift in 32-bit words 538 539 if (i->get(26, 26)) { // float 540 switch(i->get(31, 30)) { 541 case 0b10: 542 size = 2; break; 543 case 0b01: 544 size = 1; break; 545 case 0b00: 546 size = 0; break; 547 default: 548 ShouldNotReachHere(); 549 } 550 } else { 551 size = i->get(31, 31); 552 } 553 554 size = 4 << size; 555 guarantee(_offset % size == 0, "bad offset"); 556 i->sf(_offset / size, 21, 15); 557 i->srf(_base, 5); 558 } 559 560 void encode_nontemporal_pair(Instruction_aarch64 *i) const { 561 // Only base + offset is allowed 562 i->f(0b000, 25, 23); 563 unsigned size = i->get(31, 31); 564 size = 4 << size; 565 guarantee(_offset % size == 0, "bad offset"); 566 i->sf(_offset / size, 21, 15); 567 i->srf(_base, 5); 568 guarantee(_mode == Address::base_plus_offset, 569 "Bad addressing mode for non-temporal op"); 570 } 571 572 void lea(MacroAssembler *, Register) const; 573 574 static bool offset_ok_for_immed(long offset, int shift = 0) { 575 unsigned mask = (1 << shift) - 1; 576 if (offset < 0 || offset & mask) { 577 return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset 578 } else { 579 return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset 580 } 581 } 582 }; 583 584 // Convience classes 585 class RuntimeAddress: public Address { 586 587 public: 588 589 RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {} 590 591 }; 592 593 class OopAddress: public Address { 594 595 public: 596 597 OopAddress(address target) : Address(target, relocInfo::oop_type){} 598 599 }; 600 601 class ExternalAddress: public Address { 602 private: 603 static relocInfo::relocType reloc_for_target(address target) { 604 // Sometimes ExternalAddress is used for values which aren't 605 // exactly addresses, like the card table base. 606 // external_word_type can't be used for values in the first page 607 // so just skip the reloc in that case. 608 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; 609 } 610 611 public: 612 613 ExternalAddress(address target) : Address(target, reloc_for_target(target)) {} 614 615 }; 616 617 class InternalAddress: public Address { 618 619 public: 620 621 InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {} 622 }; 623 624 const int FPUStateSizeInWords = 32 * 2; 625 typedef enum { 626 PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM, 627 PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM, 628 PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM 629 } prfop; 630 631 class Assembler : public AbstractAssembler { 632 633 #ifndef PRODUCT 634 static const unsigned long asm_bp; 635 636 void emit_long(jint x) { 637 if ((unsigned long)pc() == asm_bp) 638 asm volatile ("nop"); 639 AbstractAssembler::emit_int32(x); 640 } 641 #else 642 void emit_long(jint x) { 643 AbstractAssembler::emit_int32(x); 644 } 645 #endif 646 647 public: 648 649 enum { instruction_size = 4 }; 650 651 Address adjust(Register base, int offset, bool preIncrement) { 652 if (preIncrement) 653 return Address(Pre(base, offset)); 654 else 655 return Address(Post(base, offset)); 656 } 657 658 Address pre(Register base, int offset) { 659 return adjust(base, offset, true); 660 } 661 662 Address post (Register base, int offset) { 663 return adjust(base, offset, false); 664 } 665 666 Instruction_aarch64* current; 667 668 void set_current(Instruction_aarch64* i) { current = i; } 669 670 void f(unsigned val, int msb, int lsb) { 671 current->f(val, msb, lsb); 672 } 673 void f(unsigned val, int msb) { 674 current->f(val, msb, msb); 675 } 676 void sf(long val, int msb, int lsb) { 677 current->sf(val, msb, lsb); 678 } 679 void rf(Register reg, int lsb) { 680 current->rf(reg, lsb); 681 } 682 void srf(Register reg, int lsb) { 683 current->srf(reg, lsb); 684 } 685 void zrf(Register reg, int lsb) { 686 current->zrf(reg, lsb); 687 } 688 void rf(FloatRegister reg, int lsb) { 689 current->rf(reg, lsb); 690 } 691 void fixed(unsigned value, unsigned mask) { 692 current->fixed(value, mask); 693 } 694 695 void emit() { 696 emit_long(current->get_insn()); 697 assert_cond(current->get_bits() == 0xffffffff); 698 current = NULL; 699 } 700 701 typedef void (Assembler::* uncond_branch_insn)(address dest); 702 typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest); 703 typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest); 704 typedef void (Assembler::* prefetch_insn)(address target, prfop); 705 706 void wrap_label(Label &L, uncond_branch_insn insn); 707 void wrap_label(Register r, Label &L, compare_and_branch_insn insn); 708 void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn); 709 void wrap_label(Label &L, prfop, prefetch_insn insn); 710 711 // PC-rel. addressing 712 713 void adr(Register Rd, address dest); 714 void _adrp(Register Rd, address dest); 715 716 void adr(Register Rd, const Address &dest); 717 void _adrp(Register Rd, const Address &dest); 718 719 void adr(Register Rd, Label &L) { 720 wrap_label(Rd, L, &Assembler::Assembler::adr); 721 } 722 void _adrp(Register Rd, Label &L) { 723 wrap_label(Rd, L, &Assembler::_adrp); 724 } 725 726 void adrp(Register Rd, const Address &dest, unsigned long &offset); 727 728 #undef INSN 729 730 void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op, 731 int negated_op); 732 733 // Add/subtract (immediate) 734 #define INSN(NAME, decode, negated) \ 735 void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \ 736 starti; \ 737 f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \ 738 zrf(Rd, 0), srf(Rn, 5); \ 739 } \ 740 \ 741 void NAME(Register Rd, Register Rn, unsigned imm) { \ 742 starti; \ 743 add_sub_immediate(Rd, Rn, imm, decode, negated); \ 744 } 745 746 INSN(addsw, 0b001, 0b011); 747 INSN(subsw, 0b011, 0b001); 748 INSN(adds, 0b101, 0b111); 749 INSN(subs, 0b111, 0b101); 750 751 #undef INSN 752 753 #define INSN(NAME, decode, negated) \ 754 void NAME(Register Rd, Register Rn, unsigned imm) { \ 755 starti; \ 756 add_sub_immediate(Rd, Rn, imm, decode, negated); \ 757 } 758 759 INSN(addw, 0b000, 0b010); 760 INSN(subw, 0b010, 0b000); 761 INSN(add, 0b100, 0b110); 762 INSN(sub, 0b110, 0b100); 763 764 #undef INSN 765 766 // Logical (immediate) 767 #define INSN(NAME, decode, is32) \ 768 void NAME(Register Rd, Register Rn, uint64_t imm) { \ 769 starti; \ 770 uint32_t val = encode_logical_immediate(is32, imm); \ 771 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \ 772 srf(Rd, 0), zrf(Rn, 5); \ 773 } 774 775 INSN(andw, 0b000, true); 776 INSN(orrw, 0b001, true); 777 INSN(eorw, 0b010, true); 778 INSN(andr, 0b100, false); 779 INSN(orr, 0b101, false); 780 INSN(eor, 0b110, false); 781 782 #undef INSN 783 784 #define INSN(NAME, decode, is32) \ 785 void NAME(Register Rd, Register Rn, uint64_t imm) { \ 786 starti; \ 787 uint32_t val = encode_logical_immediate(is32, imm); \ 788 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \ 789 zrf(Rd, 0), zrf(Rn, 5); \ 790 } 791 792 INSN(ands, 0b111, false); 793 INSN(andsw, 0b011, true); 794 795 #undef INSN 796 797 // Move wide (immediate) 798 #define INSN(NAME, opcode) \ 799 void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \ 800 assert_cond((shift/16)*16 == shift); \ 801 starti; \ 802 f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \ 803 f(imm, 20, 5); \ 804 rf(Rd, 0); \ 805 } 806 807 INSN(movnw, 0b000); 808 INSN(movzw, 0b010); 809 INSN(movkw, 0b011); 810 INSN(movn, 0b100); 811 INSN(movz, 0b110); 812 INSN(movk, 0b111); 813 814 #undef INSN 815 816 // Bitfield 817 #define INSN(NAME, opcode) \ 818 void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \ 819 starti; \ 820 f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \ 821 rf(Rn, 5), rf(Rd, 0); \ 822 } 823 824 INSN(sbfmw, 0b0001001100); 825 INSN(bfmw, 0b0011001100); 826 INSN(ubfmw, 0b0101001100); 827 INSN(sbfm, 0b1001001101); 828 INSN(bfm, 0b1011001101); 829 INSN(ubfm, 0b1101001101); 830 831 #undef INSN 832 833 // Extract 834 #define INSN(NAME, opcode) \ 835 void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \ 836 starti; \ 837 f(opcode, 31, 21), f(imms, 15, 10); \ 838 rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \ 839 } 840 841 INSN(extrw, 0b00010011100); 842 INSN(extr, 0b10010011110); 843 844 #undef INSN 845 846 // The maximum range of a branch is fixed for the AArch64 847 // architecture. In debug mode we shrink it in order to test 848 // trampolines, but not so small that branches in the interpreter 849 // are out of range. 850 static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M); 851 852 static bool reachable_from_branch_at(address branch, address target) { 853 return uabs(target - branch) < branch_range; 854 } 855 856 // Unconditional branch (immediate) 857 #define INSN(NAME, opcode) \ 858 void NAME(address dest) { \ 859 starti; \ 860 long offset = (dest - pc()) >> 2; \ 861 DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \ 862 f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \ 863 } \ 864 void NAME(Label &L) { \ 865 wrap_label(L, &Assembler::NAME); \ 866 } \ 867 void NAME(const Address &dest); 868 869 INSN(b, 0); 870 INSN(bl, 1); 871 872 #undef INSN 873 874 // Compare & branch (immediate) 875 #define INSN(NAME, opcode) \ 876 void NAME(Register Rt, address dest) { \ 877 long offset = (dest - pc()) >> 2; \ 878 starti; \ 879 f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \ 880 } \ 881 void NAME(Register Rt, Label &L) { \ 882 wrap_label(Rt, L, &Assembler::NAME); \ 883 } 884 885 INSN(cbzw, 0b00110100); 886 INSN(cbnzw, 0b00110101); 887 INSN(cbz, 0b10110100); 888 INSN(cbnz, 0b10110101); 889 890 #undef INSN 891 892 // Test & branch (immediate) 893 #define INSN(NAME, opcode) \ 894 void NAME(Register Rt, int bitpos, address dest) { \ 895 long offset = (dest - pc()) >> 2; \ 896 int b5 = bitpos >> 5; \ 897 bitpos &= 0x1f; \ 898 starti; \ 899 f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \ 900 rf(Rt, 0); \ 901 } \ 902 void NAME(Register Rt, int bitpos, Label &L) { \ 903 wrap_label(Rt, bitpos, L, &Assembler::NAME); \ 904 } 905 906 INSN(tbz, 0b0110110); 907 INSN(tbnz, 0b0110111); 908 909 #undef INSN 910 911 // Conditional branch (immediate) 912 enum Condition 913 {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV}; 914 915 void br(Condition cond, address dest) { 916 long offset = (dest - pc()) >> 2; 917 starti; 918 f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0); 919 } 920 921 #define INSN(NAME, cond) \ 922 void NAME(address dest) { \ 923 br(cond, dest); \ 924 } 925 926 INSN(beq, EQ); 927 INSN(bne, NE); 928 INSN(bhs, HS); 929 INSN(bcs, CS); 930 INSN(blo, LO); 931 INSN(bcc, CC); 932 INSN(bmi, MI); 933 INSN(bpl, PL); 934 INSN(bvs, VS); 935 INSN(bvc, VC); 936 INSN(bhi, HI); 937 INSN(bls, LS); 938 INSN(bge, GE); 939 INSN(blt, LT); 940 INSN(bgt, GT); 941 INSN(ble, LE); 942 INSN(bal, AL); 943 INSN(bnv, NV); 944 945 void br(Condition cc, Label &L); 946 947 #undef INSN 948 949 // Exception generation 950 void generate_exception(int opc, int op2, int LL, unsigned imm) { 951 starti; 952 f(0b11010100, 31, 24); 953 f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0); 954 } 955 956 #define INSN(NAME, opc, op2, LL) \ 957 void NAME(unsigned imm) { \ 958 generate_exception(opc, op2, LL, imm); \ 959 } 960 961 INSN(svc, 0b000, 0, 0b01); 962 INSN(hvc, 0b000, 0, 0b10); 963 INSN(smc, 0b000, 0, 0b11); 964 INSN(brk, 0b001, 0, 0b00); 965 INSN(hlt, 0b010, 0, 0b00); 966 INSN(dpcs1, 0b101, 0, 0b01); 967 INSN(dpcs2, 0b101, 0, 0b10); 968 INSN(dpcs3, 0b101, 0, 0b11); 969 970 #undef INSN 971 972 // System 973 void system(int op0, int op1, int CRn, int CRm, int op2, 974 Register rt = (Register)0b11111) 975 { 976 starti; 977 f(0b11010101000, 31, 21); 978 f(op0, 20, 19); 979 f(op1, 18, 16); 980 f(CRn, 15, 12); 981 f(CRm, 11, 8); 982 f(op2, 7, 5); 983 rf(rt, 0); 984 } 985 986 void hint(int imm) { 987 system(0b00, 0b011, 0b0010, imm, 0b000); 988 } 989 990 void nop() { 991 hint(0); 992 } 993 // we only provide mrs and msr for the special purpose system 994 // registers where op1 (instr[20:19]) == 11 and, (currently) only 995 // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1 996 997 void msr(int op1, int CRn, int CRm, int op2, Register rt) { 998 starti; 999 f(0b1101010100011, 31, 19); 1000 f(op1, 18, 16); 1001 f(CRn, 15, 12); 1002 f(CRm, 11, 8); 1003 f(op2, 7, 5); 1004 // writing zr is ok 1005 zrf(rt, 0); 1006 } 1007 1008 void mrs(int op1, int CRn, int CRm, int op2, Register rt) { 1009 starti; 1010 f(0b1101010100111, 31, 19); 1011 f(op1, 18, 16); 1012 f(CRn, 15, 12); 1013 f(CRm, 11, 8); 1014 f(op2, 7, 5); 1015 // reading to zr is a mistake 1016 rf(rt, 0); 1017 } 1018 1019 enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH, 1020 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY}; 1021 1022 void dsb(barrier imm) { 1023 system(0b00, 0b011, 0b00011, imm, 0b100); 1024 } 1025 1026 void dmb(barrier imm) { 1027 system(0b00, 0b011, 0b00011, imm, 0b101); 1028 } 1029 1030 void isb() { 1031 system(0b00, 0b011, 0b00011, SY, 0b110); 1032 } 1033 1034 void dc(Register Rt) { 1035 system(0b01, 0b011, 0b0111, 0b1011, 0b001, Rt); 1036 } 1037 1038 void ic(Register Rt) { 1039 system(0b01, 0b011, 0b0111, 0b0101, 0b001, Rt); 1040 } 1041 1042 // A more convenient access to dmb for our purposes 1043 enum Membar_mask_bits { 1044 // We can use ISH for a barrier because the ARM ARM says "This 1045 // architecture assumes that all Processing Elements that use the 1046 // same operating system or hypervisor are in the same Inner 1047 // Shareable shareability domain." 1048 StoreStore = ISHST, 1049 LoadStore = ISHLD, 1050 LoadLoad = ISHLD, 1051 StoreLoad = ISH, 1052 AnyAny = ISH 1053 }; 1054 1055 void membar(Membar_mask_bits order_constraint) { 1056 dmb(Assembler::barrier(order_constraint)); 1057 } 1058 1059 // Unconditional branch (register) 1060 void branch_reg(Register R, int opc) { 1061 starti; 1062 f(0b1101011, 31, 25); 1063 f(opc, 24, 21); 1064 f(0b11111000000, 20, 10); 1065 rf(R, 5); 1066 f(0b00000, 4, 0); 1067 } 1068 1069 #define INSN(NAME, opc) \ 1070 void NAME(Register R) { \ 1071 branch_reg(R, opc); \ 1072 } 1073 1074 INSN(br, 0b0000); 1075 INSN(blr, 0b0001); 1076 INSN(ret, 0b0010); 1077 1078 void ret(void *p); // This forces a compile-time error for ret(0) 1079 1080 #undef INSN 1081 1082 #define INSN(NAME, opc) \ 1083 void NAME() { \ 1084 branch_reg((Register)0b11111, opc); \ 1085 } 1086 1087 INSN(eret, 0b0100); 1088 INSN(drps, 0b0101); 1089 1090 #undef INSN 1091 1092 // Load/store exclusive 1093 enum operand_size { byte, halfword, word, xword }; 1094 1095 void load_store_exclusive(Register Rs, Register Rt1, Register Rt2, 1096 Register Rn, enum operand_size sz, int op, int o0) { 1097 starti; 1098 f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21); 1099 rf(Rs, 16), f(o0, 15), rf(Rt2, 10), rf(Rn, 5), rf(Rt1, 0); 1100 } 1101 1102 #define INSN4(NAME, sz, op, o0) /* Four registers */ \ 1103 void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \ 1104 load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \ 1105 } 1106 1107 #define INSN3(NAME, sz, op, o0) /* Three registers */ \ 1108 void NAME(Register Rs, Register Rt, Register Rn) { \ 1109 load_store_exclusive(Rs, Rt, (Register)0b11111, Rn, sz, op, o0); \ 1110 } 1111 1112 #define INSN2(NAME, sz, op, o0) /* Two registers */ \ 1113 void NAME(Register Rt, Register Rn) { \ 1114 load_store_exclusive((Register)0b11111, Rt, (Register)0b11111, \ 1115 Rn, sz, op, o0); \ 1116 } 1117 1118 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \ 1119 void NAME(Register Rt1, Register Rt2, Register Rn) { \ 1120 load_store_exclusive((Register)0b11111, Rt1, Rt2, Rn, sz, op, o0); \ 1121 } 1122 1123 // bytes 1124 INSN3(stxrb, byte, 0b000, 0); 1125 INSN3(stlxrb, byte, 0b000, 1); 1126 INSN2(ldxrb, byte, 0b010, 0); 1127 INSN2(ldaxrb, byte, 0b010, 1); 1128 INSN2(stlrb, byte, 0b100, 1); 1129 INSN2(ldarb, byte, 0b110, 1); 1130 1131 // halfwords 1132 INSN3(stxrh, halfword, 0b000, 0); 1133 INSN3(stlxrh, halfword, 0b000, 1); 1134 INSN2(ldxrh, halfword, 0b010, 0); 1135 INSN2(ldaxrh, halfword, 0b010, 1); 1136 INSN2(stlrh, halfword, 0b100, 1); 1137 INSN2(ldarh, halfword, 0b110, 1); 1138 1139 // words 1140 INSN3(stxrw, word, 0b000, 0); 1141 INSN3(stlxrw, word, 0b000, 1); 1142 INSN4(stxpw, word, 0b001, 0); 1143 INSN4(stlxpw, word, 0b001, 1); 1144 INSN2(ldxrw, word, 0b010, 0); 1145 INSN2(ldaxrw, word, 0b010, 1); 1146 INSN_FOO(ldxpw, word, 0b011, 0); 1147 INSN_FOO(ldaxpw, word, 0b011, 1); 1148 INSN2(stlrw, word, 0b100, 1); 1149 INSN2(ldarw, word, 0b110, 1); 1150 1151 // xwords 1152 INSN3(stxr, xword, 0b000, 0); 1153 INSN3(stlxr, xword, 0b000, 1); 1154 INSN4(stxp, xword, 0b001, 0); 1155 INSN4(stlxp, xword, 0b001, 1); 1156 INSN2(ldxr, xword, 0b010, 0); 1157 INSN2(ldaxr, xword, 0b010, 1); 1158 INSN_FOO(ldxp, xword, 0b011, 0); 1159 INSN_FOO(ldaxp, xword, 0b011, 1); 1160 INSN2(stlr, xword, 0b100, 1); 1161 INSN2(ldar, xword, 0b110, 1); 1162 1163 #undef INSN2 1164 #undef INSN3 1165 #undef INSN4 1166 #undef INSN_FOO 1167 1168 // Load register (literal) 1169 #define INSN(NAME, opc, V) \ 1170 void NAME(Register Rt, address dest) { \ 1171 long offset = (dest - pc()) >> 2; \ 1172 starti; \ 1173 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ 1174 sf(offset, 23, 5); \ 1175 rf(Rt, 0); \ 1176 } \ 1177 void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \ 1178 InstructionMark im(this); \ 1179 guarantee(rtype == relocInfo::internal_word_type, \ 1180 "only internal_word_type relocs make sense here"); \ 1181 code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \ 1182 NAME(Rt, dest); \ 1183 } \ 1184 void NAME(Register Rt, Label &L) { \ 1185 wrap_label(Rt, L, &Assembler::NAME); \ 1186 } 1187 1188 INSN(ldrw, 0b00, 0); 1189 INSN(ldr, 0b01, 0); 1190 INSN(ldrsw, 0b10, 0); 1191 1192 #undef INSN 1193 1194 #define INSN(NAME, opc, V) \ 1195 void NAME(FloatRegister Rt, address dest) { \ 1196 long offset = (dest - pc()) >> 2; \ 1197 starti; \ 1198 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ 1199 sf(offset, 23, 5); \ 1200 rf((Register)Rt, 0); \ 1201 } 1202 1203 INSN(ldrs, 0b00, 1); 1204 INSN(ldrd, 0b01, 1); 1205 INSN(ldrq, 0x10, 1); 1206 1207 #undef INSN 1208 1209 #define INSN(NAME, opc, V) \ 1210 void NAME(address dest, prfop op = PLDL1KEEP) { \ 1211 long offset = (dest - pc()) >> 2; \ 1212 starti; \ 1213 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ 1214 sf(offset, 23, 5); \ 1215 f(op, 4, 0); \ 1216 } \ 1217 void NAME(Label &L, prfop op = PLDL1KEEP) { \ 1218 wrap_label(L, op, &Assembler::NAME); \ 1219 } 1220 1221 INSN(prfm, 0b11, 0); 1222 1223 #undef INSN 1224 1225 // Load/store 1226 void ld_st1(int opc, int p1, int V, int L, 1227 Register Rt1, Register Rt2, Address adr, bool no_allocate) { 1228 starti; 1229 f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22); 1230 zrf(Rt2, 10), zrf(Rt1, 0); 1231 if (no_allocate) { 1232 adr.encode_nontemporal_pair(current); 1233 } else { 1234 adr.encode_pair(current); 1235 } 1236 } 1237 1238 // Load/store register pair (offset) 1239 #define INSN(NAME, size, p1, V, L, no_allocate) \ 1240 void NAME(Register Rt1, Register Rt2, Address adr) { \ 1241 ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \ 1242 } 1243 1244 INSN(stpw, 0b00, 0b101, 0, 0, false); 1245 INSN(ldpw, 0b00, 0b101, 0, 1, false); 1246 INSN(ldpsw, 0b01, 0b101, 0, 1, false); 1247 INSN(stp, 0b10, 0b101, 0, 0, false); 1248 INSN(ldp, 0b10, 0b101, 0, 1, false); 1249 1250 // Load/store no-allocate pair (offset) 1251 INSN(stnpw, 0b00, 0b101, 0, 0, true); 1252 INSN(ldnpw, 0b00, 0b101, 0, 1, true); 1253 INSN(stnp, 0b10, 0b101, 0, 0, true); 1254 INSN(ldnp, 0b10, 0b101, 0, 1, true); 1255 1256 #undef INSN 1257 1258 #define INSN(NAME, size, p1, V, L, no_allocate) \ 1259 void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \ 1260 ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \ 1261 } 1262 1263 INSN(stps, 0b00, 0b101, 1, 0, false); 1264 INSN(ldps, 0b00, 0b101, 1, 1, false); 1265 INSN(stpd, 0b01, 0b101, 1, 0, false); 1266 INSN(ldpd, 0b01, 0b101, 1, 1, false); 1267 INSN(stpq, 0b10, 0b101, 1, 0, false); 1268 INSN(ldpq, 0b10, 0b101, 1, 1, false); 1269 1270 #undef INSN 1271 1272 // Load/store register (all modes) 1273 void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) { 1274 starti; 1275 1276 f(V, 26); // general reg? 1277 zrf(Rt, 0); 1278 1279 // Encoding for literal loads is done here (rather than pushed 1280 // down into Address::encode) because the encoding of this 1281 // instruction is too different from all of the other forms to 1282 // make it worth sharing. 1283 if (adr.getMode() == Address::literal) { 1284 assert(size == 0b10 || size == 0b11, "bad operand size in ldr"); 1285 assert(op == 0b01, "literal form can only be used with loads"); 1286 f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24); 1287 long offset = (adr.target() - pc()) >> 2; 1288 sf(offset, 23, 5); 1289 code_section()->relocate(pc(), adr.rspec()); 1290 return; 1291 } 1292 1293 f(size, 31, 30); 1294 f(op, 23, 22); // str 1295 adr.encode(current); 1296 } 1297 1298 #define INSN(NAME, size, op) \ 1299 void NAME(Register Rt, const Address &adr) { \ 1300 ld_st2(Rt, adr, size, op); \ 1301 } \ 1302 1303 INSN(str, 0b11, 0b00); 1304 INSN(strw, 0b10, 0b00); 1305 INSN(strb, 0b00, 0b00); 1306 INSN(strh, 0b01, 0b00); 1307 1308 INSN(ldr, 0b11, 0b01); 1309 INSN(ldrw, 0b10, 0b01); 1310 INSN(ldrb, 0b00, 0b01); 1311 INSN(ldrh, 0b01, 0b01); 1312 1313 INSN(ldrsb, 0b00, 0b10); 1314 INSN(ldrsbw, 0b00, 0b11); 1315 INSN(ldrsh, 0b01, 0b10); 1316 INSN(ldrshw, 0b01, 0b11); 1317 INSN(ldrsw, 0b10, 0b10); 1318 1319 #undef INSN 1320 1321 #define INSN(NAME, size, op) \ 1322 void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \ 1323 ld_st2((Register)pfop, adr, size, op); \ 1324 } 1325 1326 INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with 1327 // writeback modes, but the assembler 1328 // doesn't enfore that. 1329 1330 #undef INSN 1331 1332 #define INSN(NAME, size, op) \ 1333 void NAME(FloatRegister Rt, const Address &adr) { \ 1334 ld_st2((Register)Rt, adr, size, op, 1); \ 1335 } 1336 1337 INSN(strd, 0b11, 0b00); 1338 INSN(strs, 0b10, 0b00); 1339 INSN(ldrd, 0b11, 0b01); 1340 INSN(ldrs, 0b10, 0b01); 1341 INSN(strq, 0b00, 0b10); 1342 INSN(ldrq, 0x00, 0b11); 1343 1344 #undef INSN 1345 1346 enum shift_kind { LSL, LSR, ASR, ROR }; 1347 1348 void op_shifted_reg(unsigned decode, 1349 enum shift_kind kind, unsigned shift, 1350 unsigned size, unsigned op) { 1351 f(size, 31); 1352 f(op, 30, 29); 1353 f(decode, 28, 24); 1354 f(shift, 15, 10); 1355 f(kind, 23, 22); 1356 } 1357 1358 // Logical (shifted register) 1359 #define INSN(NAME, size, op, N) \ 1360 void NAME(Register Rd, Register Rn, Register Rm, \ 1361 enum shift_kind kind = LSL, unsigned shift = 0) { \ 1362 starti; \ 1363 f(N, 21); \ 1364 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \ 1365 op_shifted_reg(0b01010, kind, shift, size, op); \ 1366 } 1367 1368 INSN(andr, 1, 0b00, 0); 1369 INSN(orr, 1, 0b01, 0); 1370 INSN(eor, 1, 0b10, 0); 1371 INSN(ands, 1, 0b11, 0); 1372 INSN(andw, 0, 0b00, 0); 1373 INSN(orrw, 0, 0b01, 0); 1374 INSN(eorw, 0, 0b10, 0); 1375 INSN(andsw, 0, 0b11, 0); 1376 1377 INSN(bic, 1, 0b00, 1); 1378 INSN(orn, 1, 0b01, 1); 1379 INSN(eon, 1, 0b10, 1); 1380 INSN(bics, 1, 0b11, 1); 1381 INSN(bicw, 0, 0b00, 1); 1382 INSN(ornw, 0, 0b01, 1); 1383 INSN(eonw, 0, 0b10, 1); 1384 INSN(bicsw, 0, 0b11, 1); 1385 1386 #undef INSN 1387 1388 // Add/subtract (shifted register) 1389 #define INSN(NAME, size, op) \ 1390 void NAME(Register Rd, Register Rn, Register Rm, \ 1391 enum shift_kind kind, unsigned shift = 0) { \ 1392 starti; \ 1393 f(0, 21); \ 1394 assert_cond(kind != ROR); \ 1395 zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \ 1396 op_shifted_reg(0b01011, kind, shift, size, op); \ 1397 } 1398 1399 INSN(add, 1, 0b000); 1400 INSN(sub, 1, 0b10); 1401 INSN(addw, 0, 0b000); 1402 INSN(subw, 0, 0b10); 1403 1404 INSN(adds, 1, 0b001); 1405 INSN(subs, 1, 0b11); 1406 INSN(addsw, 0, 0b001); 1407 INSN(subsw, 0, 0b11); 1408 1409 #undef INSN 1410 1411 // Add/subtract (extended register) 1412 #define INSN(NAME, op) \ 1413 void NAME(Register Rd, Register Rn, Register Rm, \ 1414 ext::operation option, int amount = 0) { \ 1415 starti; \ 1416 zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \ 1417 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \ 1418 } 1419 1420 void add_sub_extended_reg(unsigned op, unsigned decode, 1421 Register Rd, Register Rn, Register Rm, 1422 unsigned opt, ext::operation option, unsigned imm) { 1423 guarantee(imm <= 4, "shift amount must be < 4"); 1424 f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21); 1425 f(option, 15, 13), f(imm, 12, 10); 1426 } 1427 1428 INSN(addw, 0b000); 1429 INSN(subw, 0b010); 1430 INSN(add, 0b100); 1431 INSN(sub, 0b110); 1432 1433 #undef INSN 1434 1435 #define INSN(NAME, op) \ 1436 void NAME(Register Rd, Register Rn, Register Rm, \ 1437 ext::operation option, int amount = 0) { \ 1438 starti; \ 1439 zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \ 1440 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \ 1441 } 1442 1443 INSN(addsw, 0b001); 1444 INSN(subsw, 0b011); 1445 INSN(adds, 0b101); 1446 INSN(subs, 0b111); 1447 1448 #undef INSN 1449 1450 // Aliases for short forms of add and sub 1451 #define INSN(NAME) \ 1452 void NAME(Register Rd, Register Rn, Register Rm) { \ 1453 if (Rd == sp || Rn == sp) \ 1454 NAME(Rd, Rn, Rm, ext::uxtx); \ 1455 else \ 1456 NAME(Rd, Rn, Rm, LSL); \ 1457 } 1458 1459 INSN(addw); 1460 INSN(subw); 1461 INSN(add); 1462 INSN(sub); 1463 1464 INSN(addsw); 1465 INSN(subsw); 1466 INSN(adds); 1467 INSN(subs); 1468 1469 #undef INSN 1470 1471 // Add/subtract (with carry) 1472 void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) { 1473 starti; 1474 f(op, 31, 29); 1475 f(0b11010000, 28, 21); 1476 f(0b000000, 15, 10); 1477 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); 1478 } 1479 1480 #define INSN(NAME, op) \ 1481 void NAME(Register Rd, Register Rn, Register Rm) { \ 1482 add_sub_carry(op, Rd, Rn, Rm); \ 1483 } 1484 1485 INSN(adcw, 0b000); 1486 INSN(adcsw, 0b001); 1487 INSN(sbcw, 0b010); 1488 INSN(sbcsw, 0b011); 1489 INSN(adc, 0b100); 1490 INSN(adcs, 0b101); 1491 INSN(sbc,0b110); 1492 INSN(sbcs, 0b111); 1493 1494 #undef INSN 1495 1496 // Conditional compare (both kinds) 1497 void conditional_compare(unsigned op, int o2, int o3, 1498 Register Rn, unsigned imm5, unsigned nzcv, 1499 unsigned cond) { 1500 f(op, 31, 29); 1501 f(0b11010010, 28, 21); 1502 f(cond, 15, 12); 1503 f(o2, 10); 1504 f(o3, 4); 1505 f(nzcv, 3, 0); 1506 f(imm5, 20, 16), rf(Rn, 5); 1507 } 1508 1509 #define INSN(NAME, op) \ 1510 void NAME(Register Rn, Register Rm, int imm, Condition cond) { \ 1511 starti; \ 1512 f(0, 11); \ 1513 conditional_compare(op, 0, 0, Rn, (uintptr_t)Rm, imm, cond); \ 1514 } \ 1515 \ 1516 void NAME(Register Rn, int imm5, int imm, Condition cond) { \ 1517 starti; \ 1518 f(1, 11); \ 1519 conditional_compare(op, 0, 0, Rn, imm5, imm, cond); \ 1520 } 1521 1522 INSN(ccmnw, 0b001); 1523 INSN(ccmpw, 0b011); 1524 INSN(ccmn, 0b101); 1525 INSN(ccmp, 0b111); 1526 1527 #undef INSN 1528 1529 // Conditional select 1530 void conditional_select(unsigned op, unsigned op2, 1531 Register Rd, Register Rn, Register Rm, 1532 unsigned cond) { 1533 starti; 1534 f(op, 31, 29); 1535 f(0b11010100, 28, 21); 1536 f(cond, 15, 12); 1537 f(op2, 11, 10); 1538 zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0); 1539 } 1540 1541 #define INSN(NAME, op, op2) \ 1542 void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \ 1543 conditional_select(op, op2, Rd, Rn, Rm, cond); \ 1544 } 1545 1546 INSN(cselw, 0b000, 0b00); 1547 INSN(csincw, 0b000, 0b01); 1548 INSN(csinvw, 0b010, 0b00); 1549 INSN(csnegw, 0b010, 0b01); 1550 INSN(csel, 0b100, 0b00); 1551 INSN(csinc, 0b100, 0b01); 1552 INSN(csinv, 0b110, 0b00); 1553 INSN(csneg, 0b110, 0b01); 1554 1555 #undef INSN 1556 1557 // Data processing 1558 void data_processing(unsigned op29, unsigned opcode, 1559 Register Rd, Register Rn) { 1560 f(op29, 31, 29), f(0b11010110, 28, 21); 1561 f(opcode, 15, 10); 1562 rf(Rn, 5), rf(Rd, 0); 1563 } 1564 1565 // (1 source) 1566 #define INSN(NAME, op29, opcode2, opcode) \ 1567 void NAME(Register Rd, Register Rn) { \ 1568 starti; \ 1569 f(opcode2, 20, 16); \ 1570 data_processing(op29, opcode, Rd, Rn); \ 1571 } 1572 1573 INSN(rbitw, 0b010, 0b00000, 0b00000); 1574 INSN(rev16w, 0b010, 0b00000, 0b00001); 1575 INSN(revw, 0b010, 0b00000, 0b00010); 1576 INSN(clzw, 0b010, 0b00000, 0b00100); 1577 INSN(clsw, 0b010, 0b00000, 0b00101); 1578 1579 INSN(rbit, 0b110, 0b00000, 0b00000); 1580 INSN(rev16, 0b110, 0b00000, 0b00001); 1581 INSN(rev32, 0b110, 0b00000, 0b00010); 1582 INSN(rev, 0b110, 0b00000, 0b00011); 1583 INSN(clz, 0b110, 0b00000, 0b00100); 1584 INSN(cls, 0b110, 0b00000, 0b00101); 1585 1586 #undef INSN 1587 1588 // (2 sources) 1589 #define INSN(NAME, op29, opcode) \ 1590 void NAME(Register Rd, Register Rn, Register Rm) { \ 1591 starti; \ 1592 rf(Rm, 16); \ 1593 data_processing(op29, opcode, Rd, Rn); \ 1594 } 1595 1596 INSN(udivw, 0b000, 0b000010); 1597 INSN(sdivw, 0b000, 0b000011); 1598 INSN(lslvw, 0b000, 0b001000); 1599 INSN(lsrvw, 0b000, 0b001001); 1600 INSN(asrvw, 0b000, 0b001010); 1601 INSN(rorvw, 0b000, 0b001011); 1602 1603 INSN(udiv, 0b100, 0b000010); 1604 INSN(sdiv, 0b100, 0b000011); 1605 INSN(lslv, 0b100, 0b001000); 1606 INSN(lsrv, 0b100, 0b001001); 1607 INSN(asrv, 0b100, 0b001010); 1608 INSN(rorv, 0b100, 0b001011); 1609 1610 #undef INSN 1611 1612 // (3 sources) 1613 void data_processing(unsigned op54, unsigned op31, unsigned o0, 1614 Register Rd, Register Rn, Register Rm, 1615 Register Ra) { 1616 starti; 1617 f(op54, 31, 29), f(0b11011, 28, 24); 1618 f(op31, 23, 21), f(o0, 15); 1619 zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0); 1620 } 1621 1622 #define INSN(NAME, op54, op31, o0) \ 1623 void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \ 1624 data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \ 1625 } 1626 1627 INSN(maddw, 0b000, 0b000, 0); 1628 INSN(msubw, 0b000, 0b000, 1); 1629 INSN(madd, 0b100, 0b000, 0); 1630 INSN(msub, 0b100, 0b000, 1); 1631 INSN(smaddl, 0b100, 0b001, 0); 1632 INSN(smsubl, 0b100, 0b001, 1); 1633 INSN(umaddl, 0b100, 0b101, 0); 1634 INSN(umsubl, 0b100, 0b101, 1); 1635 1636 #undef INSN 1637 1638 #define INSN(NAME, op54, op31, o0) \ 1639 void NAME(Register Rd, Register Rn, Register Rm) { \ 1640 data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \ 1641 } 1642 1643 INSN(smulh, 0b100, 0b010, 0); 1644 INSN(umulh, 0b100, 0b110, 0); 1645 1646 #undef INSN 1647 1648 // Floating-point data-processing (1 source) 1649 void data_processing(unsigned op31, unsigned type, unsigned opcode, 1650 FloatRegister Vd, FloatRegister Vn) { 1651 starti; 1652 f(op31, 31, 29); 1653 f(0b11110, 28, 24); 1654 f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10); 1655 rf(Vn, 5), rf(Vd, 0); 1656 } 1657 1658 #define INSN(NAME, op31, type, opcode) \ 1659 void NAME(FloatRegister Vd, FloatRegister Vn) { \ 1660 data_processing(op31, type, opcode, Vd, Vn); \ 1661 } 1662 1663 private: 1664 INSN(i_fmovs, 0b000, 0b00, 0b000000); 1665 public: 1666 INSN(fabss, 0b000, 0b00, 0b000001); 1667 INSN(fnegs, 0b000, 0b00, 0b000010); 1668 INSN(fsqrts, 0b000, 0b00, 0b000011); 1669 INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision 1670 1671 private: 1672 INSN(i_fmovd, 0b000, 0b01, 0b000000); 1673 public: 1674 INSN(fabsd, 0b000, 0b01, 0b000001); 1675 INSN(fnegd, 0b000, 0b01, 0b000010); 1676 INSN(fsqrtd, 0b000, 0b01, 0b000011); 1677 INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision 1678 1679 void fmovd(FloatRegister Vd, FloatRegister Vn) { 1680 assert(Vd != Vn, "should be"); 1681 i_fmovd(Vd, Vn); 1682 } 1683 1684 void fmovs(FloatRegister Vd, FloatRegister Vn) { 1685 assert(Vd != Vn, "should be"); 1686 i_fmovs(Vd, Vn); 1687 } 1688 1689 #undef INSN 1690 1691 // Floating-point data-processing (2 source) 1692 void data_processing(unsigned op31, unsigned type, unsigned opcode, 1693 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { 1694 starti; 1695 f(op31, 31, 29); 1696 f(0b11110, 28, 24); 1697 f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10); 1698 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); 1699 } 1700 1701 #define INSN(NAME, op31, type, opcode) \ 1702 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \ 1703 data_processing(op31, type, opcode, Vd, Vn, Vm); \ 1704 } 1705 1706 INSN(fmuls, 0b000, 0b00, 0b0000); 1707 INSN(fdivs, 0b000, 0b00, 0b0001); 1708 INSN(fadds, 0b000, 0b00, 0b0010); 1709 INSN(fsubs, 0b000, 0b00, 0b0011); 1710 INSN(fnmuls, 0b000, 0b00, 0b1000); 1711 1712 INSN(fmuld, 0b000, 0b01, 0b0000); 1713 INSN(fdivd, 0b000, 0b01, 0b0001); 1714 INSN(faddd, 0b000, 0b01, 0b0010); 1715 INSN(fsubd, 0b000, 0b01, 0b0011); 1716 INSN(fnmuld, 0b000, 0b01, 0b1000); 1717 1718 #undef INSN 1719 1720 // Floating-point data-processing (3 source) 1721 void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0, 1722 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, 1723 FloatRegister Va) { 1724 starti; 1725 f(op31, 31, 29); 1726 f(0b11111, 28, 24); 1727 f(type, 23, 22), f(o1, 21), f(o0, 15); 1728 rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0); 1729 } 1730 1731 #define INSN(NAME, op31, type, o1, o0) \ 1732 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \ 1733 FloatRegister Va) { \ 1734 data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \ 1735 } 1736 1737 INSN(fmadds, 0b000, 0b00, 0, 0); 1738 INSN(fmsubs, 0b000, 0b00, 0, 1); 1739 INSN(fnmadds, 0b000, 0b00, 1, 0); 1740 INSN(fnmsubs, 0b000, 0b00, 1, 1); 1741 1742 INSN(fmaddd, 0b000, 0b01, 0, 0); 1743 INSN(fmsubd, 0b000, 0b01, 0, 1); 1744 INSN(fnmaddd, 0b000, 0b01, 1, 0); 1745 INSN(fnmsub, 0b000, 0b01, 1, 1); 1746 1747 #undef INSN 1748 1749 // Floating-point conditional select 1750 void fp_conditional_select(unsigned op31, unsigned type, 1751 unsigned op1, unsigned op2, 1752 Condition cond, FloatRegister Vd, 1753 FloatRegister Vn, FloatRegister Vm) { 1754 starti; 1755 f(op31, 31, 29); 1756 f(0b11110, 28, 24); 1757 f(type, 23, 22); 1758 f(op1, 21, 21); 1759 f(op2, 11, 10); 1760 f(cond, 15, 12); 1761 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); 1762 } 1763 1764 #define INSN(NAME, op31, type, op1, op2) \ 1765 void NAME(FloatRegister Vd, FloatRegister Vn, \ 1766 FloatRegister Vm, Condition cond) { \ 1767 fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \ 1768 } 1769 1770 INSN(fcsels, 0b000, 0b00, 0b1, 0b11); 1771 INSN(fcseld, 0b000, 0b01, 0b1, 0b11); 1772 1773 #undef INSN 1774 1775 // Floating-point<->integer conversions 1776 void float_int_convert(unsigned op31, unsigned type, 1777 unsigned rmode, unsigned opcode, 1778 Register Rd, Register Rn) { 1779 starti; 1780 f(op31, 31, 29); 1781 f(0b11110, 28, 24); 1782 f(type, 23, 22), f(1, 21), f(rmode, 20, 19); 1783 f(opcode, 18, 16), f(0b000000, 15, 10); 1784 zrf(Rn, 5), zrf(Rd, 0); 1785 } 1786 1787 #define INSN(NAME, op31, type, rmode, opcode) \ 1788 void NAME(Register Rd, FloatRegister Vn) { \ 1789 float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \ 1790 } 1791 1792 INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000); 1793 INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000); 1794 INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000); 1795 INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000); 1796 1797 INSN(fmovs, 0b000, 0b00, 0b00, 0b110); 1798 INSN(fmovd, 0b100, 0b01, 0b00, 0b110); 1799 1800 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110); 1801 1802 #undef INSN 1803 1804 #define INSN(NAME, op31, type, rmode, opcode) \ 1805 void NAME(FloatRegister Vd, Register Rn) { \ 1806 float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \ 1807 } 1808 1809 INSN(fmovs, 0b000, 0b00, 0b00, 0b111); 1810 INSN(fmovd, 0b100, 0b01, 0b00, 0b111); 1811 1812 INSN(scvtfws, 0b000, 0b00, 0b00, 0b010); 1813 INSN(scvtfs, 0b100, 0b00, 0b00, 0b010); 1814 INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010); 1815 INSN(scvtfd, 0b100, 0b01, 0b00, 0b010); 1816 1817 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111); 1818 1819 #undef INSN 1820 1821 // Floating-point compare 1822 void float_compare(unsigned op31, unsigned type, 1823 unsigned op, unsigned op2, 1824 FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) { 1825 starti; 1826 f(op31, 31, 29); 1827 f(0b11110, 28, 24); 1828 f(type, 23, 22), f(1, 21); 1829 f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0); 1830 rf(Vn, 5), rf(Vm, 16); 1831 } 1832 1833 1834 #define INSN(NAME, op31, type, op, op2) \ 1835 void NAME(FloatRegister Vn, FloatRegister Vm) { \ 1836 float_compare(op31, type, op, op2, Vn, Vm); \ 1837 } 1838 1839 #define INSN1(NAME, op31, type, op, op2) \ 1840 void NAME(FloatRegister Vn, double d) { \ 1841 assert_cond(d == 0.0); \ 1842 float_compare(op31, type, op, op2, Vn); \ 1843 } 1844 1845 INSN(fcmps, 0b000, 0b00, 0b00, 0b00000); 1846 INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000); 1847 // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000); 1848 // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000); 1849 1850 INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000); 1851 INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000); 1852 // INSN(fcmped, 0b000, 0b01, 0b00, 0b10000); 1853 // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000); 1854 1855 #undef INSN 1856 #undef INSN1 1857 1858 // Floating-point Move (immediate) 1859 private: 1860 unsigned pack(double value); 1861 1862 void fmov_imm(FloatRegister Vn, double value, unsigned size) { 1863 starti; 1864 f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21); 1865 f(pack(value), 20, 13), f(0b10000000, 12, 5); 1866 rf(Vn, 0); 1867 } 1868 1869 public: 1870 1871 void fmovs(FloatRegister Vn, double value) { 1872 if (value) 1873 fmov_imm(Vn, value, 0b00); 1874 else 1875 fmovs(Vn, zr); 1876 } 1877 void fmovd(FloatRegister Vn, double value) { 1878 if (value) 1879 fmov_imm(Vn, value, 0b01); 1880 else 1881 fmovd(Vn, zr); 1882 } 1883 1884 /* SIMD extensions 1885 * 1886 * We just use FloatRegister in the following. They are exactly the same 1887 * as SIMD registers. 1888 */ 1889 public: 1890 1891 enum SIMD_Arrangement { 1892 T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D 1893 }; 1894 1895 enum SIMD_RegVariant { 1896 B, H, S, D, Q 1897 }; 1898 1899 #define INSN(NAME, op) \ 1900 void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \ 1901 ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \ 1902 } \ 1903 1904 INSN(ldr, 1); 1905 INSN(str, 0); 1906 1907 #undef INSN 1908 1909 private: 1910 1911 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) { 1912 starti; 1913 f(0,31), f((int)T & 1, 30); 1914 f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12); 1915 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0); 1916 } 1917 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, 1918 int imm, int op1, int op2) { 1919 starti; 1920 f(0,31), f((int)T & 1, 30); 1921 f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12); 1922 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0); 1923 } 1924 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, 1925 Register Xm, int op1, int op2) { 1926 starti; 1927 f(0,31), f((int)T & 1, 30); 1928 f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12); 1929 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0); 1930 } 1931 1932 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2) { 1933 switch (a.getMode()) { 1934 case Address::base_plus_offset: 1935 guarantee(a.offset() == 0, "no offset allowed here"); 1936 ld_st(Vt, T, a.base(), op1, op2); 1937 break; 1938 case Address::post: 1939 ld_st(Vt, T, a.base(), a.offset(), op1, op2); 1940 break; 1941 case Address::base_plus_offset_reg: 1942 ld_st(Vt, T, a.base(), a.index(), op1, op2); 1943 break; 1944 default: 1945 ShouldNotReachHere(); 1946 } 1947 } 1948 1949 public: 1950 1951 #define INSN1(NAME, op1, op2) \ 1952 void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \ 1953 ld_st(Vt, T, a, op1, op2); \ 1954 } 1955 1956 #define INSN2(NAME, op1, op2) \ 1957 void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \ 1958 assert(Vt->successor() == Vt2, "Registers must be ordered"); \ 1959 ld_st(Vt, T, a, op1, op2); \ 1960 } 1961 1962 #define INSN3(NAME, op1, op2) \ 1963 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \ 1964 SIMD_Arrangement T, const Address &a) { \ 1965 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \ 1966 "Registers must be ordered"); \ 1967 ld_st(Vt, T, a, op1, op2); \ 1968 } 1969 1970 #define INSN4(NAME, op1, op2) \ 1971 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \ 1972 FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \ 1973 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \ 1974 Vt3->successor() == Vt4, "Registers must be ordered"); \ 1975 ld_st(Vt, T, a, op1, op2); \ 1976 } 1977 1978 INSN1(ld1, 0b001100010, 0b0111); 1979 INSN2(ld1, 0b001100010, 0b1010); 1980 INSN3(ld1, 0b001100010, 0b0110); 1981 INSN4(ld1, 0b001100010, 0b0010); 1982 1983 INSN2(ld2, 0b001100010, 0b1000); 1984 INSN3(ld3, 0b001100010, 0b0100); 1985 INSN4(ld4, 0b001100010, 0b0000); 1986 1987 INSN1(st1, 0b001100000, 0b0111); 1988 INSN2(st1, 0b001100000, 0b1010); 1989 INSN3(st1, 0b001100000, 0b0110); 1990 INSN4(st1, 0b001100000, 0b0010); 1991 1992 INSN2(st2, 0b001100000, 0b1000); 1993 INSN3(st3, 0b001100000, 0b0100); 1994 INSN4(st4, 0b001100000, 0b0000); 1995 1996 INSN1(ld1r, 0b001101010, 0b1100); 1997 INSN2(ld2r, 0b001101011, 0b1100); 1998 INSN3(ld3r, 0b001101010, 0b1110); 1999 INSN4(ld4r, 0b001101011, 0b1110); 2000 2001 #undef INSN1 2002 #undef INSN2 2003 #undef INSN3 2004 #undef INSN4 2005 2006 #define INSN(NAME, opc) \ 2007 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2008 starti; \ 2009 assert(T == T8B || T == T16B, "must be T8B or T16B"); \ 2010 f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \ 2011 rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2012 } 2013 2014 INSN(eor, 0b101110001); 2015 INSN(orr, 0b001110101); 2016 INSN(andr, 0b001110001); 2017 INSN(bic, 0b001110011); 2018 INSN(bif, 0b101110111); 2019 INSN(bit, 0b101110101); 2020 INSN(bsl, 0b101110011); 2021 INSN(orn, 0b001110111); 2022 2023 #undef INSN 2024 2025 #define INSN(NAME, opc, opc2) \ 2026 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2027 starti; \ 2028 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \ 2029 f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \ 2030 rf(Vn, 5), rf(Vd, 0); \ 2031 } 2032 2033 INSN(addv, 0, 0b100001); 2034 INSN(subv, 1, 0b100001); 2035 INSN(mulv, 0, 0b100111); 2036 INSN(sshl, 0, 0b010001); 2037 INSN(ushl, 1, 0b010001); 2038 2039 #undef INSN 2040 2041 #define INSN(NAME, opc, opc2) \ 2042 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ 2043 starti; \ 2044 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \ 2045 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \ 2046 rf(Vn, 5), rf(Vd, 0); \ 2047 } 2048 2049 INSN(absr, 0, 0b100000101110); 2050 INSN(negr, 1, 0b100000101110); 2051 INSN(notr, 1, 0b100000010110); 2052 INSN(addv, 0, 0b110001101110); 2053 2054 #undef INSN 2055 2056 #define INSN(NAME, op0, cmode0) \ 2057 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \ 2058 unsigned cmode = cmode0; \ 2059 unsigned op = op0; \ 2060 starti; \ 2061 assert(lsl == 0 || \ 2062 ((T == T4H || T == T8H) && lsl == 8) || \ 2063 ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \ 2064 cmode |= lsl >> 2; \ 2065 if (T == T4H || T == T8H) cmode |= 0b1000; \ 2066 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \ 2067 assert(op == 0 && cmode0 == 0, "must be MOVI"); \ 2068 cmode = 0b1110; \ 2069 if (T == T1D || T == T2D) op = 1; \ 2070 } \ 2071 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \ 2072 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \ 2073 rf(Vd, 0); \ 2074 } 2075 2076 INSN(movi, 0, 0); 2077 INSN(orri, 0, 1); 2078 INSN(mvni, 1, 0); 2079 INSN(bici, 1, 1); 2080 2081 #undef INSN 2082 2083 #define INSN(NAME, op1, op2, op3) \ 2084 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2085 starti; \ 2086 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \ 2087 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \ 2088 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2089 } 2090 2091 INSN(fadd, 0, 0, 0b110101); 2092 INSN(fdiv, 1, 0, 0b111111); 2093 INSN(fmul, 1, 0, 0b110111); 2094 INSN(fsub, 0, 1, 0b110101); 2095 2096 #undef INSN 2097 2098 #define INSN(NAME, opc) \ 2099 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2100 starti; \ 2101 assert(T == T4S, "arrangement must be T4S"); \ 2102 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2103 } 2104 2105 INSN(sha1c, 0b000000); 2106 INSN(sha1m, 0b001000); 2107 INSN(sha1p, 0b000100); 2108 INSN(sha1su0, 0b001100); 2109 INSN(sha256h2, 0b010100); 2110 INSN(sha256h, 0b010000); 2111 INSN(sha256su1, 0b011000); 2112 2113 #undef INSN 2114 2115 #define INSN(NAME, opc) \ 2116 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ 2117 starti; \ 2118 assert(T == T4S, "arrangement must be T4S"); \ 2119 f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2120 } 2121 2122 INSN(sha1h, 0b000010); 2123 INSN(sha1su1, 0b000110); 2124 INSN(sha256su0, 0b001010); 2125 2126 #undef INSN 2127 2128 #define INSN(NAME, opc) \ 2129 void NAME(FloatRegister Vd, FloatRegister Vn) { \ 2130 starti; \ 2131 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \ 2132 } 2133 2134 INSN(aese, 0b0100111000101000010010); 2135 INSN(aesd, 0b0100111000101000010110); 2136 INSN(aesmc, 0b0100111000101000011010); 2137 INSN(aesimc, 0b0100111000101000011110); 2138 2139 #undef INSN 2140 2141 void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) { 2142 starti; 2143 assert(T != Q, "invalid register variant"); 2144 f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15); 2145 f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0); 2146 } 2147 2148 void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) { 2149 starti; 2150 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21); 2151 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10); 2152 rf(Vn, 5), rf(Rd, 0); 2153 } 2154 2155 #define INSN(NAME, opc, opc2) \ 2156 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \ 2157 starti; \ 2158 /* The encodings for the immh:immb fields (bits 22:16) are \ 2159 * 0001 xxx 8B/16B, shift = xxx \ 2160 * 001x xxx 4H/8H, shift = xxxx \ 2161 * 01xx xxx 2S/4S, shift = xxxxx \ 2162 * 1xxx xxx 1D/2D, shift = xxxxxx (1D is RESERVED) \ 2163 */ \ 2164 assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \ 2165 f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \ 2166 f((1 << ((T>>1)+3))|shift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2167 } 2168 2169 INSN(shl, 0, 0b010101); 2170 INSN(sshr, 0, 0b000001); 2171 INSN(ushr, 1, 0b000001); 2172 2173 #undef INSN 2174 2175 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { 2176 starti; 2177 /* The encodings for the immh:immb fields (bits 22:16) are 2178 * 0001 xxx 8H, 8B/16b shift = xxx 2179 * 001x xxx 4S, 4H/8H shift = xxxx 2180 * 01xx xxx 2D, 2S/4S shift = xxxxx 2181 * 1xxx xxx RESERVED 2182 */ 2183 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement"); 2184 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value"); 2185 f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16); 2186 f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0); 2187 } 2188 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { 2189 ushll(Vd, Ta, Vn, Tb, shift); 2190 } 2191 2192 void uzp1(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T, int op = 0){ 2193 starti; 2194 f(0, 31), f((T & 0x1), 30), f(0b001110, 29, 24), f((T >> 1), 23, 22), f(0, 21); 2195 rf(Vm, 16), f(0, 15), f(op, 14), f(0b0110, 13, 10), rf(Vn, 5), rf(Vd, 0); 2196 } 2197 void uzp2(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T){ 2198 uzp1(Vd, Vn, Vm, T, 1); 2199 } 2200 2201 // Move from general purpose register 2202 // mov Vd.T[index], Rn 2203 void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) { 2204 starti; 2205 f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); 2206 f(0b000111, 15, 10), rf(Xn, 5), rf(Vd, 0); 2207 } 2208 2209 // Move to general purpose register 2210 // mov Rd, Vn.T[index] 2211 void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) { 2212 starti; 2213 f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21); 2214 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); 2215 f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0); 2216 } 2217 2218 // We do not handle the 1Q arrangement. 2219 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) { 2220 starti; 2221 assert(Ta == T8H && (Tb == T8B || Tb == T16B), "Invalid Size specifier"); 2222 f(0, 31), f(Tb & 1, 30), f(0b001110001, 29, 21), rf(Vm, 16), f(0b111000, 15, 10); 2223 rf(Vn, 5), rf(Vd, 0); 2224 } 2225 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) { 2226 pmull(Vd, Ta, Vn, Vm, Tb); 2227 } 2228 2229 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) { 2230 starti; 2231 int size_b = (int)Tb >> 1; 2232 int size_a = (int)Ta >> 1; 2233 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier"); 2234 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22); 2235 f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0); 2236 } 2237 2238 void rev32(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) 2239 { 2240 starti; 2241 assert(T <= T8H, "must be one of T8B, T16B, T4H, T8H"); 2242 f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24); 2243 f(T <= T16B ? 0b00 : 0b01, 23, 22), f(0b100000000010, 21, 10); 2244 rf(Vn, 5), rf(Vd, 0); 2245 } 2246 2247 void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs) 2248 { 2249 starti; 2250 assert(T != T1D, "reserved encoding"); 2251 f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21); 2252 f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), rf(Xs, 5), rf(Vd, 0); 2253 } 2254 2255 void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0) 2256 { 2257 starti; 2258 assert(T != T1D, "reserved encoding"); 2259 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21); 2260 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); 2261 f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0); 2262 } 2263 2264 // CRC32 instructions 2265 #define INSN(NAME, sf, sz) \ 2266 void NAME(Register Rd, Register Rn, Register Rm) { \ 2267 starti; \ 2268 f(sf, 31), f(0b0011010110, 30, 21), f(0b0100, 15, 12), f(sz, 11, 10); \ 2269 rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \ 2270 } 2271 2272 INSN(crc32b, 0, 0b00); 2273 INSN(crc32h, 0, 0b01); 2274 INSN(crc32w, 0, 0b10); 2275 INSN(crc32x, 1, 0b11); 2276 2277 #undef INSN 2278 2279 2280 /* Simulator extensions to the ISA 2281 2282 haltsim 2283 2284 takes no arguments, causes the sim to enter a debug break and then 2285 return from the simulator run() call with STATUS_HALT? The linking 2286 code will call fatal() when it sees STATUS_HALT. 2287 2288 blrt Xn, Wm 2289 blrt Xn, #gpargs, #fpargs, #type 2290 Xn holds the 64 bit x86 branch_address 2291 call format is encoded either as immediate data in the call 2292 or in register Wm. In the latter case 2293 Wm[13..6] = #gpargs, 2294 Wm[5..2] = #fpargs, 2295 Wm[1,0] = #type 2296 2297 calls the x86 code address 'branch_address' supplied in Xn passing 2298 arguments taken from the general and floating point registers according 2299 to the supplied counts 'gpargs' and 'fpargs'. may return a result in r0 2300 or v0 according to the the return type #type' where 2301 2302 address branch_address; 2303 uimm4 gpargs; 2304 uimm4 fpargs; 2305 enum ReturnType type; 2306 2307 enum ReturnType 2308 { 2309 void_ret = 0, 2310 int_ret = 1, 2311 long_ret = 1, 2312 obj_ret = 1, // i.e. same as long 2313 float_ret = 2, 2314 double_ret = 3 2315 } 2316 2317 notify 2318 2319 notifies the simulator of a transfer of control. instr[14:0] 2320 identifies the type of change of control. 2321 2322 0 ==> initial entry to a method. 2323 2324 1 ==> return into a method from a submethod call. 2325 2326 2 ==> exit out of Java method code. 2327 2328 3 ==> start execution for a new bytecode. 2329 2330 in cases 1 and 2 the simulator is expected to use a JVM callback to 2331 identify the name of the specific method being executed. in case 4 2332 the simulator is expected to use a JVM callback to identify the 2333 bytecode index. 2334 2335 Instruction encodings 2336 --------------------- 2337 2338 These are encoded in the space with instr[28:25] = 00 which is 2339 unallocated. Encodings are 2340 2341 10987654321098765432109876543210 2342 PSEUDO_HALT = 0x11100000000000000000000000000000 2343 PSEUDO_BLRT = 0x11000000000000000_______________ 2344 PSEUDO_BLRTR = 0x1100000000000000100000__________ 2345 PSEUDO_NOTIFY = 0x10100000000000000_______________ 2346 2347 instr[31,29] = op1 : 111 ==> HALT, 110 ==> BLRT/BLRTR, 101 ==> NOTIFY 2348 2349 for BLRT 2350 instr[14,11] = #gpargs, instr[10,7] = #fpargs 2351 instr[6,5] = #type, instr[4,0] = Rn 2352 for BLRTR 2353 instr[9,5] = Rm, instr[4,0] = Rn 2354 for NOTIFY 2355 instr[14:0] = type : 0 ==> entry, 1 ==> reentry, 2 ==> exit, 3 ==> bcstart 2356 */ 2357 2358 enum NotifyType { method_entry, method_reentry, method_exit, bytecode_start }; 2359 2360 virtual void notify(int type) { 2361 if (UseBuiltinSim) { 2362 starti; 2363 // 109 2364 f(0b101, 31, 29); 2365 // 87654321098765 2366 f(0b00000000000000, 28, 15); 2367 f(type, 14, 0); 2368 } 2369 } 2370 2371 void blrt(Register Rn, int gpargs, int fpargs, int type) { 2372 if (UseBuiltinSim) { 2373 starti; 2374 f(0b110, 31 ,29); 2375 f(0b00, 28, 25); 2376 // 4321098765 2377 f(0b0000000000, 24, 15); 2378 f(gpargs, 14, 11); 2379 f(fpargs, 10, 7); 2380 f(type, 6, 5); 2381 rf(Rn, 0); 2382 } else { 2383 blr(Rn); 2384 } 2385 } 2386 2387 void blrt(Register Rn, Register Rm) { 2388 if (UseBuiltinSim) { 2389 starti; 2390 f(0b110, 31 ,29); 2391 f(0b00, 28, 25); 2392 // 4321098765 2393 f(0b0000000001, 24, 15); 2394 // 43210 2395 f(0b00000, 14, 10); 2396 rf(Rm, 5); 2397 rf(Rn, 0); 2398 } else { 2399 blr(Rn); 2400 } 2401 } 2402 2403 void haltsim() { 2404 starti; 2405 f(0b111, 31 ,29); 2406 f(0b00, 28, 27); 2407 // 654321098765432109876543210 2408 f(0b000000000000000000000000000, 26, 0); 2409 } 2410 2411 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 2412 } 2413 2414 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 2415 Register tmp, 2416 int offset) { 2417 ShouldNotCallThis(); 2418 return RegisterOrConstant(); 2419 } 2420 2421 // Stack overflow checking 2422 virtual void bang_stack_with_offset(int offset); 2423 2424 static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm); 2425 static bool operand_valid_for_add_sub_immediate(long imm); 2426 static bool operand_valid_for_float_immediate(double imm); 2427 2428 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); 2429 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); 2430 }; 2431 2432 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a, 2433 Assembler::Membar_mask_bits b) { 2434 return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b)); 2435 } 2436 2437 Instruction_aarch64::~Instruction_aarch64() { 2438 assem->emit(); 2439 } 2440 2441 #undef starti 2442 2443 // Invert a condition 2444 inline const Assembler::Condition operator~(const Assembler::Condition cond) { 2445 return Assembler::Condition(int(cond) ^ 1); 2446 } 2447 2448 class BiasedLockingCounters; 2449 2450 extern "C" void das(uint64_t start, int len); 2451 2452 #endif // CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP