1 /* 2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP 27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP 28 29 #include "asm/assembler.hpp" 30 31 // MacroAssembler extends Assembler by frequently used macros. 32 // 33 // Instructions for which a 'better' code sequence exists depending 34 // on arguments should also go in here. 35 36 class MacroAssembler: public Assembler { 37 friend class LIR_Assembler; 38 39 using Assembler::mov; 40 using Assembler::movi; 41 42 protected: 43 44 // Support for VM calls 45 // 46 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 47 // may customize this version by overriding it for its purposes (e.g., to save/restore 48 // additional registers when doing a VM call). 49 #ifdef CC_INTERP 50 // c++ interpreter never wants to use interp_masm version of call_VM 51 #define VIRTUAL 52 #else 53 #define VIRTUAL virtual 54 #endif 55 56 VIRTUAL void call_VM_leaf_base( 57 address entry_point, // the entry point 58 int number_of_arguments, // the number of arguments to pop after the call 59 Label *retaddr = NULL 60 ); 61 62 VIRTUAL void call_VM_leaf_base( 63 address entry_point, // the entry point 64 int number_of_arguments, // the number of arguments to pop after the call 65 Label &retaddr) { 66 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr); 67 } 68 69 // This is the base routine called by the different versions of call_VM. The interpreter 70 // may customize this version by overriding it for its purposes (e.g., to save/restore 71 // additional registers when doing a VM call). 72 // 73 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base 74 // returns the register which contains the thread upon return. If a thread register has been 75 // specified, the return value will correspond to that register. If no last_java_sp is specified 76 // (noreg) than rsp will be used instead. 77 VIRTUAL void call_VM_base( // returns the register containing the thread upon return 78 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 79 Register java_thread, // the thread if computed before ; use noreg otherwise 80 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 81 address entry_point, // the entry point 82 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 83 bool check_exceptions // whether to check for pending exceptions after return 84 ); 85 86 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 87 // The implementation is only non-empty for the InterpreterMacroAssembler, 88 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 89 virtual void check_and_handle_popframe(Register java_thread); 90 virtual void check_and_handle_earlyret(Register java_thread); 91 92 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 93 94 // Maximum size of class area in Metaspace when compressed 95 uint64_t use_XOR_for_compressed_class_base; 96 97 public: 98 MacroAssembler(CodeBuffer* code) : Assembler(code) { 99 use_XOR_for_compressed_class_base 100 = (operand_valid_for_logical_immediate(false /*is32*/, 101 (uint64_t)Universe::narrow_klass_base()) 102 && ((uint64_t)Universe::narrow_klass_base() 103 > (1u << log2_intptr(CompressedClassSpaceSize)))); 104 } 105 106 // Biased locking support 107 // lock_reg and obj_reg must be loaded up with the appropriate values. 108 // swap_reg is killed. 109 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will 110 // be killed; if not supplied, push/pop will be used internally to 111 // allocate a temporary (inefficient, avoid if possible). 112 // Optional slow case is for implementations (interpreter and C1) which branch to 113 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. 114 // Returns offset of first potentially-faulting instruction for null 115 // check info (currently consumed only by C1). If 116 // swap_reg_contains_mark is true then returns -1 as it is assumed 117 // the calling code has already passed any potential faults. 118 int biased_locking_enter(Register lock_reg, Register obj_reg, 119 Register swap_reg, Register tmp_reg, 120 bool swap_reg_contains_mark, 121 Label& done, Label* slow_case = NULL, 122 BiasedLockingCounters* counters = NULL); 123 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); 124 125 126 // Helper functions for statistics gathering. 127 // Unconditional atomic increment. 128 void atomic_incw(Register counter_addr, Register tmp); 129 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2) { 130 lea(tmp1, counter_addr); 131 atomic_incw(tmp1, tmp2); 132 } 133 // Load Effective Address 134 void lea(Register r, const Address &a) { 135 InstructionMark im(this); 136 code_section()->relocate(inst_mark(), a.rspec()); 137 a.lea(this, r); 138 } 139 140 void addmw(Address a, Register incr, Register scratch) { 141 ldrw(scratch, a); 142 addw(scratch, scratch, incr); 143 strw(scratch, a); 144 } 145 146 // Add constant to memory word 147 void addmw(Address a, int imm, Register scratch) { 148 ldrw(scratch, a); 149 if (imm > 0) 150 addw(scratch, scratch, (unsigned)imm); 151 else 152 subw(scratch, scratch, (unsigned)-imm); 153 strw(scratch, a); 154 } 155 156 // Frame creation and destruction shared between JITs. 157 void build_frame(int framesize); 158 void remove_frame(int framesize); 159 160 virtual void _call_Unimplemented(address call_site) { 161 mov(rscratch2, call_site); 162 haltsim(); 163 } 164 165 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__) 166 167 virtual void notify(int type); 168 169 // aliases defined in AARCH64 spec 170 171 template<class T> 172 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); } 173 inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); } 174 175 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); } 176 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); } 177 178 void cset(Register Rd, Assembler::Condition cond) { 179 csinc(Rd, zr, zr, ~cond); 180 } 181 void csetw(Register Rd, Assembler::Condition cond) { 182 csincw(Rd, zr, zr, ~cond); 183 } 184 185 void cneg(Register Rd, Register Rn, Assembler::Condition cond) { 186 csneg(Rd, Rn, Rn, ~cond); 187 } 188 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) { 189 csnegw(Rd, Rn, Rn, ~cond); 190 } 191 192 inline void movw(Register Rd, Register Rn) { 193 if (Rd == sp || Rn == sp) { 194 addw(Rd, Rn, 0U); 195 } else { 196 orrw(Rd, zr, Rn); 197 } 198 } 199 inline void mov(Register Rd, Register Rn) { 200 assert(Rd != r31_sp && Rn != r31_sp, "should be"); 201 if (Rd == Rn) { 202 } else if (Rd == sp || Rn == sp) { 203 add(Rd, Rn, 0U); 204 } else { 205 orr(Rd, zr, Rn); 206 } 207 } 208 209 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); } 210 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); } 211 212 inline void tstw(Register Rd, unsigned imm) { andsw(zr, Rd, imm); } 213 inline void tst(Register Rd, unsigned imm) { ands(zr, Rd, imm); } 214 215 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 216 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 217 } 218 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) { 219 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 220 } 221 222 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 223 bfmw(Rd, Rn, lsb, (lsb + width - 1)); 224 } 225 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) { 226 bfm(Rd, Rn, lsb , (lsb + width - 1)); 227 } 228 229 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 230 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 231 } 232 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 233 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 234 } 235 236 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 237 sbfmw(Rd, Rn, lsb, (lsb + width - 1)); 238 } 239 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 240 sbfm(Rd, Rn, lsb , (lsb + width - 1)); 241 } 242 243 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 244 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 245 } 246 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 247 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 248 } 249 250 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 251 ubfmw(Rd, Rn, lsb, (lsb + width - 1)); 252 } 253 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 254 ubfm(Rd, Rn, lsb , (lsb + width - 1)); 255 } 256 257 inline void asrw(Register Rd, Register Rn, unsigned imm) { 258 sbfmw(Rd, Rn, imm, 31); 259 } 260 261 inline void asr(Register Rd, Register Rn, unsigned imm) { 262 sbfm(Rd, Rn, imm, 63); 263 } 264 265 inline void lslw(Register Rd, Register Rn, unsigned imm) { 266 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm)); 267 } 268 269 inline void lsl(Register Rd, Register Rn, unsigned imm) { 270 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm)); 271 } 272 273 inline void lsrw(Register Rd, Register Rn, unsigned imm) { 274 ubfmw(Rd, Rn, imm, 31); 275 } 276 277 inline void lsr(Register Rd, Register Rn, unsigned imm) { 278 ubfm(Rd, Rn, imm, 63); 279 } 280 281 inline void rorw(Register Rd, Register Rn, unsigned imm) { 282 extrw(Rd, Rn, Rn, imm); 283 } 284 285 inline void ror(Register Rd, Register Rn, unsigned imm) { 286 extr(Rd, Rn, Rn, imm); 287 } 288 289 inline void sxtbw(Register Rd, Register Rn) { 290 sbfmw(Rd, Rn, 0, 7); 291 } 292 inline void sxthw(Register Rd, Register Rn) { 293 sbfmw(Rd, Rn, 0, 15); 294 } 295 inline void sxtb(Register Rd, Register Rn) { 296 sbfm(Rd, Rn, 0, 7); 297 } 298 inline void sxth(Register Rd, Register Rn) { 299 sbfm(Rd, Rn, 0, 15); 300 } 301 inline void sxtw(Register Rd, Register Rn) { 302 sbfm(Rd, Rn, 0, 31); 303 } 304 305 inline void uxtbw(Register Rd, Register Rn) { 306 ubfmw(Rd, Rn, 0, 7); 307 } 308 inline void uxthw(Register Rd, Register Rn) { 309 ubfmw(Rd, Rn, 0, 15); 310 } 311 inline void uxtb(Register Rd, Register Rn) { 312 ubfm(Rd, Rn, 0, 7); 313 } 314 inline void uxth(Register Rd, Register Rn) { 315 ubfm(Rd, Rn, 0, 15); 316 } 317 inline void uxtw(Register Rd, Register Rn) { 318 ubfm(Rd, Rn, 0, 31); 319 } 320 321 inline void cmnw(Register Rn, Register Rm) { 322 addsw(zr, Rn, Rm); 323 } 324 inline void cmn(Register Rn, Register Rm) { 325 adds(zr, Rn, Rm); 326 } 327 328 inline void cmpw(Register Rn, Register Rm) { 329 subsw(zr, Rn, Rm); 330 } 331 inline void cmp(Register Rn, Register Rm) { 332 subs(zr, Rn, Rm); 333 } 334 335 inline void negw(Register Rd, Register Rn) { 336 subw(Rd, zr, Rn); 337 } 338 339 inline void neg(Register Rd, Register Rn) { 340 sub(Rd, zr, Rn); 341 } 342 343 inline void negsw(Register Rd, Register Rn) { 344 subsw(Rd, zr, Rn); 345 } 346 347 inline void negs(Register Rd, Register Rn) { 348 subs(Rd, zr, Rn); 349 } 350 351 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 352 addsw(zr, Rn, Rm, kind, shift); 353 } 354 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 355 adds(zr, Rn, Rm, kind, shift); 356 } 357 358 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 359 subsw(zr, Rn, Rm, kind, shift); 360 } 361 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 362 subs(zr, Rn, Rm, kind, shift); 363 } 364 365 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 366 subw(Rd, zr, Rn, kind, shift); 367 } 368 369 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 370 sub(Rd, zr, Rn, kind, shift); 371 } 372 373 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 374 subsw(Rd, zr, Rn, kind, shift); 375 } 376 377 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 378 subs(Rd, zr, Rn, kind, shift); 379 } 380 381 inline void mnegw(Register Rd, Register Rn, Register Rm) { 382 msubw(Rd, Rn, Rm, zr); 383 } 384 inline void mneg(Register Rd, Register Rn, Register Rm) { 385 msub(Rd, Rn, Rm, zr); 386 } 387 388 inline void mulw(Register Rd, Register Rn, Register Rm) { 389 maddw(Rd, Rn, Rm, zr); 390 } 391 inline void mul(Register Rd, Register Rn, Register Rm) { 392 madd(Rd, Rn, Rm, zr); 393 } 394 395 inline void smnegl(Register Rd, Register Rn, Register Rm) { 396 smsubl(Rd, Rn, Rm, zr); 397 } 398 inline void smull(Register Rd, Register Rn, Register Rm) { 399 smaddl(Rd, Rn, Rm, zr); 400 } 401 402 inline void umnegl(Register Rd, Register Rn, Register Rm) { 403 umsubl(Rd, Rn, Rm, zr); 404 } 405 inline void umull(Register Rd, Register Rn, Register Rm) { 406 umaddl(Rd, Rn, Rm, zr); 407 } 408 409 #define WRAP(INSN) \ 410 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \ 411 if ((VM_Version::cpu_cpuFeatures() & VM_Version::CPU_A53MAC) && Ra != zr) \ 412 nop(); \ 413 Assembler::INSN(Rd, Rn, Rm, Ra); \ 414 } 415 416 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw) 417 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl) 418 #undef WRAP 419 420 421 // macro assembly operations needed for aarch64 422 423 // first two private routines for loading 32 bit or 64 bit constants 424 private: 425 426 void mov_immediate64(Register dst, u_int64_t imm64); 427 void mov_immediate32(Register dst, u_int32_t imm32); 428 429 int push(unsigned int bitset, Register stack); 430 int pop(unsigned int bitset, Register stack); 431 432 void mov(Register dst, Address a); 433 434 public: 435 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); } 436 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); } 437 438 // now mov instructions for loading absolute addresses and 32 or 439 // 64 bit integers 440 441 inline void mov(Register dst, address addr) 442 { 443 mov_immediate64(dst, (u_int64_t)addr); 444 } 445 446 inline void mov(Register dst, u_int64_t imm64) 447 { 448 mov_immediate64(dst, imm64); 449 } 450 451 inline void movw(Register dst, u_int32_t imm32) 452 { 453 mov_immediate32(dst, imm32); 454 } 455 456 inline void mov(Register dst, long l) 457 { 458 mov(dst, (u_int64_t)l); 459 } 460 461 inline void mov(Register dst, int i) 462 { 463 mov(dst, (long)i); 464 } 465 466 void movptr(Register r, uintptr_t imm64); 467 468 // Macro to mov replicated immediate to vector register. 469 // Where imm32 == hex abcdefgh, Vd will get the following values 470 // for different arrangements in T 471 // T8B: Vd = ghghghghghghghgh 472 // T16B: Vd = ghghghghghghghghghghghghghghghgh 473 // T4H: Vd = efghefghefghefgh 474 // T8H: Vd = efghefghefghefghefghefghefghefgh 475 // T2S: Vd = abcdefghabcdefgh 476 // T4S: Vd = abcdefghabcdefghabcdefghabcdefgh 477 // T1D/T2D: invalid 478 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) { 479 assert(T != T1D && T != T2D, "invalid arrangement"); 480 u_int32_t nimm32 = ~imm32; 481 if (T == T8B || T == T16B) { imm32 &= 0xff; nimm32 &= 0xff; } 482 if (T == T4H || T == T8H) { imm32 &= 0xffff; nimm32 &= 0xffff; } 483 u_int32_t x = imm32; 484 int movi_cnt = 0; 485 int movn_cnt = 0; 486 while (x) { if (x & 0xff) movi_cnt++; x >>= 8; } 487 x = nimm32; 488 while (x) { if (x & 0xff) movn_cnt++; x >>= 8; } 489 if (movn_cnt < movi_cnt) imm32 = nimm32; 490 unsigned lsl = 0; 491 while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } 492 if (movn_cnt < movi_cnt) 493 mvni(Vd, T, imm32 & 0xff, lsl); 494 else 495 movi(Vd, T, imm32 & 0xff, lsl); 496 imm32 >>= 8; lsl += 8; 497 while (imm32) { 498 while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } 499 if (movn_cnt < movi_cnt) 500 bici(Vd, T, imm32 & 0xff, lsl); 501 else 502 orri(Vd, T, imm32 & 0xff, lsl); 503 lsl += 8; imm32 >>= 8; 504 } 505 } 506 507 // macro instructions for accessing and updating floating point 508 // status register 509 // 510 // FPSR : op1 == 011 511 // CRn == 0100 512 // CRm == 0100 513 // op2 == 001 514 515 inline void get_fpsr(Register reg) 516 { 517 mrs(0b11, 0b0100, 0b0100, 0b001, reg); 518 } 519 520 inline void set_fpsr(Register reg) 521 { 522 msr(0b011, 0b0100, 0b0100, 0b001, reg); 523 } 524 525 inline void clear_fpsr() 526 { 527 msr(0b011, 0b0100, 0b0100, 0b001, zr); 528 } 529 530 // idiv variant which deals with MINLONG as dividend and -1 as divisor 531 int corrected_idivl(Register result, Register ra, Register rb, 532 bool want_remainder, Register tmp = rscratch1); 533 int corrected_idivq(Register result, Register ra, Register rb, 534 bool want_remainder, Register tmp = rscratch1); 535 536 // Support for NULL-checks 537 // 538 // Generates code that causes a NULL OS exception if the content of reg is NULL. 539 // If the accessed location is M[reg + offset] and the offset is known, provide the 540 // offset. No explicit code generation is needed if the offset is within a certain 541 // range (0 <= offset <= page_size). 542 543 virtual void null_check(Register reg, int offset = -1); 544 static bool needs_explicit_null_check(intptr_t offset); 545 546 static address target_addr_for_insn(address insn_addr, unsigned insn); 547 static address target_addr_for_insn(address insn_addr) { 548 unsigned insn = *(unsigned*)insn_addr; 549 return target_addr_for_insn(insn_addr, insn); 550 } 551 552 // Required platform-specific helpers for Label::patch_instructions. 553 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 554 static int pd_patch_instruction_size(address branch, address target); 555 static void pd_patch_instruction(address branch, address target) { 556 pd_patch_instruction_size(branch, target); 557 } 558 static address pd_call_destination(address branch) { 559 return target_addr_for_insn(branch); 560 } 561 #ifndef PRODUCT 562 static void pd_print_patched_instruction(address branch); 563 #endif 564 565 static int patch_oop(address insn_addr, address o); 566 567 void emit_trampoline_stub(int insts_call_instruction_offset, address target); 568 569 // The following 4 methods return the offset of the appropriate move instruction 570 571 // Support for fast byte/short loading with zero extension (depending on particular CPU) 572 int load_unsigned_byte(Register dst, Address src); 573 int load_unsigned_short(Register dst, Address src); 574 575 // Support for fast byte/short loading with sign extension (depending on particular CPU) 576 int load_signed_byte(Register dst, Address src); 577 int load_signed_short(Register dst, Address src); 578 579 int load_signed_byte32(Register dst, Address src); 580 int load_signed_short32(Register dst, Address src); 581 582 // Support for sign-extension (hi:lo = extend_sign(lo)) 583 void extend_sign(Register hi, Register lo); 584 585 // Load and store values by size and signed-ness 586 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); 587 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); 588 589 // Support for inc/dec with optimal instruction selection depending on value 590 591 // x86_64 aliases an unqualified register/address increment and 592 // decrement to call incrementq and decrementq but also supports 593 // explicitly sized calls to incrementq/decrementq or 594 // incrementl/decrementl 595 596 // for aarch64 the proper convention would be to use 597 // increment/decrement for 64 bit operatons and 598 // incrementw/decrementw for 32 bit operations. so when porting 599 // x86_64 code we can leave calls to increment/decrement as is, 600 // replace incrementq/decrementq with increment/decrement and 601 // replace incrementl/decrementl with incrementw/decrementw. 602 603 // n.b. increment/decrement calls with an Address destination will 604 // need to use a scratch register to load the value to be 605 // incremented. increment/decrement calls which add or subtract a 606 // constant value greater than 2^12 will need to use a 2nd scratch 607 // register to hold the constant. so, a register increment/decrement 608 // may trash rscratch2 and an address increment/decrement trash 609 // rscratch and rscratch2 610 611 void decrementw(Address dst, int value = 1); 612 void decrementw(Register reg, int value = 1); 613 614 void decrement(Register reg, int value = 1); 615 void decrement(Address dst, int value = 1); 616 617 void incrementw(Address dst, int value = 1); 618 void incrementw(Register reg, int value = 1); 619 620 void increment(Register reg, int value = 1); 621 void increment(Address dst, int value = 1); 622 623 624 // Alignment 625 void align(int modulus); 626 627 // Stack frame creation/removal 628 void enter() 629 { 630 stp(rfp, lr, Address(pre(sp, -2 * wordSize))); 631 mov(rfp, sp); 632 } 633 void leave() 634 { 635 mov(sp, rfp); 636 ldp(rfp, lr, Address(post(sp, 2 * wordSize))); 637 } 638 639 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 640 // The pointer will be loaded into the thread register. 641 void get_thread(Register thread); 642 643 644 // Support for VM calls 645 // 646 // It is imperative that all calls into the VM are handled via the call_VM macros. 647 // They make sure that the stack linkage is setup correctly. call_VM's correspond 648 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 649 650 651 void call_VM(Register oop_result, 652 address entry_point, 653 bool check_exceptions = true); 654 void call_VM(Register oop_result, 655 address entry_point, 656 Register arg_1, 657 bool check_exceptions = true); 658 void call_VM(Register oop_result, 659 address entry_point, 660 Register arg_1, Register arg_2, 661 bool check_exceptions = true); 662 void call_VM(Register oop_result, 663 address entry_point, 664 Register arg_1, Register arg_2, Register arg_3, 665 bool check_exceptions = true); 666 667 // Overloadings with last_Java_sp 668 void call_VM(Register oop_result, 669 Register last_java_sp, 670 address entry_point, 671 int number_of_arguments = 0, 672 bool check_exceptions = true); 673 void call_VM(Register oop_result, 674 Register last_java_sp, 675 address entry_point, 676 Register arg_1, bool 677 check_exceptions = true); 678 void call_VM(Register oop_result, 679 Register last_java_sp, 680 address entry_point, 681 Register arg_1, Register arg_2, 682 bool check_exceptions = true); 683 void call_VM(Register oop_result, 684 Register last_java_sp, 685 address entry_point, 686 Register arg_1, Register arg_2, Register arg_3, 687 bool check_exceptions = true); 688 689 void get_vm_result (Register oop_result, Register thread); 690 void get_vm_result_2(Register metadata_result, Register thread); 691 692 // These always tightly bind to MacroAssembler::call_VM_base 693 // bypassing the virtual implementation 694 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 695 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 696 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 697 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 698 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); 699 700 void call_VM_leaf(address entry_point, 701 int number_of_arguments = 0); 702 void call_VM_leaf(address entry_point, 703 Register arg_1); 704 void call_VM_leaf(address entry_point, 705 Register arg_1, Register arg_2); 706 void call_VM_leaf(address entry_point, 707 Register arg_1, Register arg_2, Register arg_3); 708 709 // These always tightly bind to MacroAssembler::call_VM_leaf_base 710 // bypassing the virtual implementation 711 void super_call_VM_leaf(address entry_point); 712 void super_call_VM_leaf(address entry_point, Register arg_1); 713 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 714 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 715 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); 716 717 // last Java Frame (fills frame anchor) 718 void set_last_Java_frame(Register last_java_sp, 719 Register last_java_fp, 720 address last_java_pc, 721 Register scratch); 722 723 void set_last_Java_frame(Register last_java_sp, 724 Register last_java_fp, 725 Label &last_java_pc, 726 Register scratch); 727 728 void set_last_Java_frame(Register last_java_sp, 729 Register last_java_fp, 730 Register last_java_pc, 731 Register scratch); 732 733 void reset_last_Java_frame(Register thread, bool clearfp, bool clear_pc); 734 735 // thread in the default location (r15_thread on 64bit) 736 void reset_last_Java_frame(bool clear_fp, bool clear_pc); 737 738 // Stores 739 void store_check(Register obj); // store check for obj - register is destroyed afterwards 740 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 741 742 #if INCLUDE_ALL_GCS 743 744 void g1_write_barrier_pre(Register obj, 745 Register pre_val, 746 Register thread, 747 Register tmp, 748 bool tosca_live, 749 bool expand_call); 750 751 void g1_write_barrier_post(Register store_addr, 752 Register new_val, 753 Register thread, 754 Register tmp, 755 Register tmp2); 756 757 #endif // INCLUDE_ALL_GCS 758 759 // split store_check(Register obj) to enhance instruction interleaving 760 void store_check_part_1(Register obj); 761 void store_check_part_2(Register obj); 762 763 // oop manipulations 764 void load_klass(Register dst, Register src); 765 void store_klass(Register dst, Register src); 766 void cmp_klass(Register oop, Register trial_klass, Register tmp); 767 768 void load_heap_oop(Register dst, Address src); 769 770 void load_heap_oop_not_null(Register dst, Address src); 771 void store_heap_oop(Address dst, Register src); 772 773 // currently unimplemented 774 // Used for storing NULL. All other oop constants should be 775 // stored using routines that take a jobject. 776 void store_heap_oop_null(Address dst); 777 778 void load_prototype_header(Register dst, Register src); 779 780 void store_klass_gap(Register dst, Register src); 781 782 // This dummy is to prevent a call to store_heap_oop from 783 // converting a zero (like NULL) into a Register by giving 784 // the compiler two choices it can't resolve 785 786 void store_heap_oop(Address dst, void* dummy); 787 788 void encode_heap_oop(Register d, Register s); 789 void encode_heap_oop(Register r) { encode_heap_oop(r, r); } 790 void decode_heap_oop(Register d, Register s); 791 void decode_heap_oop(Register r) { decode_heap_oop(r, r); } 792 void encode_heap_oop_not_null(Register r); 793 void decode_heap_oop_not_null(Register r); 794 void encode_heap_oop_not_null(Register dst, Register src); 795 void decode_heap_oop_not_null(Register dst, Register src); 796 797 void set_narrow_oop(Register dst, jobject obj); 798 799 void encode_klass_not_null(Register r); 800 void decode_klass_not_null(Register r); 801 void encode_klass_not_null(Register dst, Register src); 802 void decode_klass_not_null(Register dst, Register src); 803 804 void set_narrow_klass(Register dst, Klass* k); 805 806 // if heap base register is used - reinit it with the correct value 807 void reinit_heapbase(); 808 809 DEBUG_ONLY(void verify_heapbase(const char* msg);) 810 811 void push_CPU_state(); 812 void pop_CPU_state() ; 813 814 // Round up to a power of two 815 void round_to(Register reg, int modulus); 816 817 // allocation 818 void eden_allocate( 819 Register obj, // result: pointer to object after successful allocation 820 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 821 int con_size_in_bytes, // object size in bytes if known at compile time 822 Register t1, // temp register 823 Label& slow_case // continuation point if fast allocation fails 824 ); 825 void tlab_allocate( 826 Register obj, // result: pointer to object after successful allocation 827 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 828 int con_size_in_bytes, // object size in bytes if known at compile time 829 Register t1, // temp register 830 Register t2, // temp register 831 Label& slow_case // continuation point if fast allocation fails 832 ); 833 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address 834 void verify_tlab(); 835 836 void incr_allocated_bytes(Register thread, 837 Register var_size_in_bytes, int con_size_in_bytes, 838 Register t1 = noreg); 839 840 // interface method calling 841 void lookup_interface_method(Register recv_klass, 842 Register intf_klass, 843 RegisterOrConstant itable_index, 844 Register method_result, 845 Register scan_temp, 846 Label& no_such_interface); 847 848 // virtual method calling 849 // n.b. x86 allows RegisterOrConstant for vtable_index 850 void lookup_virtual_method(Register recv_klass, 851 RegisterOrConstant vtable_index, 852 Register method_result); 853 854 // Test sub_klass against super_klass, with fast and slow paths. 855 856 // The fast path produces a tri-state answer: yes / no / maybe-slow. 857 // One of the three labels can be NULL, meaning take the fall-through. 858 // If super_check_offset is -1, the value is loaded up from super_klass. 859 // No registers are killed, except temp_reg. 860 void check_klass_subtype_fast_path(Register sub_klass, 861 Register super_klass, 862 Register temp_reg, 863 Label* L_success, 864 Label* L_failure, 865 Label* L_slow_path, 866 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 867 868 // The rest of the type check; must be wired to a corresponding fast path. 869 // It does not repeat the fast path logic, so don't use it standalone. 870 // The temp_reg and temp2_reg can be noreg, if no temps are available. 871 // Updates the sub's secondary super cache as necessary. 872 // If set_cond_codes, condition codes will be Z on success, NZ on failure. 873 void check_klass_subtype_slow_path(Register sub_klass, 874 Register super_klass, 875 Register temp_reg, 876 Register temp2_reg, 877 Label* L_success, 878 Label* L_failure, 879 bool set_cond_codes = false); 880 881 // Simplified, combined version, good for typical uses. 882 // Falls through on failure. 883 void check_klass_subtype(Register sub_klass, 884 Register super_klass, 885 Register temp_reg, 886 Label& L_success); 887 888 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); 889 890 891 // Debugging 892 893 // only if +VerifyOops 894 void verify_oop(Register reg, const char* s = "broken oop"); 895 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); 896 897 // TODO: verify method and klass metadata (compare against vptr?) 898 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} 899 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} 900 901 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 902 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 903 904 // only if +VerifyFPU 905 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); 906 907 // prints msg, dumps registers and stops execution 908 void stop(const char* msg); 909 910 // prints msg and continues 911 void warn(const char* msg); 912 913 static void debug64(char* msg, int64_t pc, int64_t regs[]); 914 915 void untested() { stop("untested"); } 916 917 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } 918 919 void should_not_reach_here() { stop("should not reach here"); } 920 921 // Stack overflow checking 922 void bang_stack_with_offset(int offset) { 923 // stack grows down, caller passes positive offset 924 assert(offset > 0, "must bang with negative offset"); 925 mov(rscratch2, -offset); 926 str(zr, Address(sp, rscratch2)); 927 } 928 929 // Writes to stack successive pages until offset reached to check for 930 // stack overflow + shadow pages. Also, clobbers tmp 931 void bang_stack_size(Register size, Register tmp); 932 933 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 934 Register tmp, 935 int offset); 936 937 // Support for serializing memory accesses between threads 938 void serialize_memory(Register thread, Register tmp); 939 940 // Arithmetics 941 942 void addptr(Address dst, int32_t src) { 943 lea(rscratch2, dst); 944 ldr(rscratch1, Address(rscratch2)); 945 add(rscratch1, rscratch1, src); 946 str(rscratch1, Address(rscratch2)); 947 } 948 949 void cmpptr(Register src1, Address src2); 950 951 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, 952 Label &suceed, Label *fail); 953 954 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, 955 Label &suceed, Label *fail); 956 957 void atomic_add(Register prev, RegisterOrConstant incr, Register addr); 958 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr); 959 960 void atomic_xchg(Register prev, Register newv, Register addr); 961 void atomic_xchgw(Register prev, Register newv, Register addr); 962 963 void orptr(Address adr, RegisterOrConstant src) { 964 ldr(rscratch2, adr); 965 if (src.is_register()) 966 orr(rscratch2, rscratch2, src.as_register()); 967 else 968 orr(rscratch2, rscratch2, src.as_constant()); 969 str(rscratch2, adr); 970 } 971 972 // Calls 973 974 void trampoline_call(Address entry, CodeBuffer *cbuf = NULL); 975 976 static bool far_branches() { 977 return ReservedCodeCacheSize > branch_range; 978 } 979 980 // Jumps that can reach anywhere in the code cache. 981 // Trashes tmp. 982 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1); 983 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1); 984 985 static int far_branch_size() { 986 if (far_branches()) { 987 return 3 * 4; // adrp, add, br 988 } else { 989 return 4; 990 } 991 } 992 993 // Emit the CompiledIC call idiom 994 void ic_call(address entry); 995 996 public: 997 998 // Data 999 1000 void mov_metadata(Register dst, Metadata* obj); 1001 Address allocate_metadata_address(Metadata* obj); 1002 Address constant_oop_address(jobject obj); 1003 1004 void movoop(Register dst, jobject obj, bool immediate = false); 1005 1006 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic. 1007 void kernel_crc32(Register crc, Register buf, Register len, 1008 Register table0, Register table1, Register table2, Register table3, 1009 Register tmp, Register tmp2, Register tmp3); 1010 1011 #undef VIRTUAL 1012 1013 // Stack push and pop individual 64 bit registers 1014 void push(Register src); 1015 void pop(Register dst); 1016 1017 // push all registers onto the stack 1018 void pusha(); 1019 void popa(); 1020 1021 void repne_scan(Register addr, Register value, Register count, 1022 Register scratch); 1023 void repne_scanw(Register addr, Register value, Register count, 1024 Register scratch); 1025 1026 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm); 1027 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift); 1028 1029 // If a constant does not fit in an immediate field, generate some 1030 // number of MOV instructions and then perform the operation 1031 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm, 1032 add_sub_imm_insn insn1, 1033 add_sub_reg_insn insn2); 1034 // Seperate vsn which sets the flags 1035 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm, 1036 add_sub_imm_insn insn1, 1037 add_sub_reg_insn insn2); 1038 1039 #define WRAP(INSN) \ 1040 void INSN(Register Rd, Register Rn, unsigned imm) { \ 1041 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \ 1042 } \ 1043 \ 1044 void INSN(Register Rd, Register Rn, Register Rm, \ 1045 enum shift_kind kind, unsigned shift = 0) { \ 1046 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 1047 } \ 1048 \ 1049 void INSN(Register Rd, Register Rn, Register Rm) { \ 1050 Assembler::INSN(Rd, Rn, Rm); \ 1051 } \ 1052 \ 1053 void INSN(Register Rd, Register Rn, Register Rm, \ 1054 ext::operation option, int amount = 0) { \ 1055 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1056 } 1057 1058 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw) 1059 1060 #undef WRAP 1061 #define WRAP(INSN) \ 1062 void INSN(Register Rd, Register Rn, unsigned imm) { \ 1063 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \ 1064 } \ 1065 \ 1066 void INSN(Register Rd, Register Rn, Register Rm, \ 1067 enum shift_kind kind, unsigned shift = 0) { \ 1068 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 1069 } \ 1070 \ 1071 void INSN(Register Rd, Register Rn, Register Rm) { \ 1072 Assembler::INSN(Rd, Rn, Rm); \ 1073 } \ 1074 \ 1075 void INSN(Register Rd, Register Rn, Register Rm, \ 1076 ext::operation option, int amount = 0) { \ 1077 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1078 } 1079 1080 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw) 1081 1082 void add(Register Rd, Register Rn, RegisterOrConstant increment); 1083 void addw(Register Rd, Register Rn, RegisterOrConstant increment); 1084 1085 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset); 1086 1087 void tableswitch(Register index, jint lowbound, jint highbound, 1088 Label &jumptable, Label &jumptable_end, int stride = 1) { 1089 adr(rscratch1, jumptable); 1090 subsw(rscratch2, index, lowbound); 1091 subsw(zr, rscratch2, highbound - lowbound); 1092 br(Assembler::HS, jumptable_end); 1093 add(rscratch1, rscratch1, rscratch2, 1094 ext::sxtw, exact_log2(stride * Assembler::instruction_size)); 1095 br(rscratch1); 1096 } 1097 1098 // Form an address from base + offset in Rd. Rd may or may not 1099 // actually be used: you must use the Address that is returned. It 1100 // is up to you to ensure that the shift provided matches the size 1101 // of your data. 1102 Address form_address(Register Rd, Register base, long byte_offset, int shift); 1103 1104 // Prolog generator routines to support switch between x86 code and 1105 // generated ARM code 1106 1107 // routine to generate an x86 prolog for a stub function which 1108 // bootstraps into the generated ARM code which directly follows the 1109 // stub 1110 // 1111 1112 public: 1113 // enum used for aarch64--x86 linkage to define return type of x86 function 1114 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double}; 1115 1116 #ifdef BUILTIN_SIM 1117 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL); 1118 #else 1119 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { } 1120 #endif 1121 1122 // special version of call_VM_leaf_base needed for aarch64 simulator 1123 // where we need to specify both the gp and fp arg counts and the 1124 // return type so that the linkage routine from aarch64 to x86 and 1125 // back knows which aarch64 registers to copy to x86 registers and 1126 // which x86 result register to copy back to an aarch64 register 1127 1128 void call_VM_leaf_base1( 1129 address entry_point, // the entry point 1130 int number_of_gp_arguments, // the number of gp reg arguments to pass 1131 int number_of_fp_arguments, // the number of fp reg arguments to pass 1132 ret_type type, // the return type for the call 1133 Label* retaddr = NULL 1134 ); 1135 1136 void ldr_constant(Register dest, const Address &const_addr) { 1137 if (NearCpool) { 1138 ldr(dest, const_addr); 1139 } else { 1140 unsigned long offset; 1141 adrp(dest, InternalAddress(const_addr.target()), offset); 1142 ldr(dest, Address(dest, offset)); 1143 } 1144 } 1145 1146 address read_polling_page(Register r, address page, relocInfo::relocType rtype); 1147 address read_polling_page(Register r, relocInfo::relocType rtype); 1148 1149 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic. 1150 void update_byte_crc32(Register crc, Register val, Register table); 1151 void update_word_crc32(Register crc, Register v, Register tmp, 1152 Register table0, Register table1, Register table2, Register table3, 1153 bool upper = false); 1154 1155 void string_compare(Register str1, Register str2, 1156 Register cnt1, Register cnt2, Register result, 1157 Register tmp1); 1158 void string_equals(Register str1, Register str2, 1159 Register cnt, Register result, 1160 Register tmp1); 1161 void char_arrays_equals(Register ary1, Register ary2, 1162 Register result, Register tmp1); 1163 void encode_iso_array(Register src, Register dst, 1164 Register len, Register result, 1165 FloatRegister Vtmp1, FloatRegister Vtmp2, 1166 FloatRegister Vtmp3, FloatRegister Vtmp4); 1167 void string_indexof(Register str1, Register str2, 1168 Register cnt1, Register cnt2, 1169 Register tmp1, Register tmp2, 1170 Register tmp3, Register tmp4, 1171 int int_cnt1, Register result); 1172 private: 1173 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, 1174 Register src1, Register src2); 1175 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 1176 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2); 1177 } 1178 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 1179 Register y, Register y_idx, Register z, 1180 Register carry, Register product, 1181 Register idx, Register kdx); 1182 void multiply_128_x_128_loop(Register y, Register z, 1183 Register carry, Register carry2, 1184 Register idx, Register jdx, 1185 Register yz_idx1, Register yz_idx2, 1186 Register tmp, Register tmp3, Register tmp4, 1187 Register tmp7, Register product_hi); 1188 public: 1189 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, 1190 Register zlen, Register tmp1, Register tmp2, Register tmp3, 1191 Register tmp4, Register tmp5, Register tmp6, Register tmp7); 1192 // ISB may be needed because of a safepoint 1193 void maybe_isb() { isb(); } 1194 1195 private: 1196 // Return the effective address r + (r1 << ext) + offset. 1197 // Uses rscratch2. 1198 Address offsetted_address(Register r, Register r1, Address::extend ext, 1199 int offset, int size); 1200 }; 1201 1202 #ifdef ASSERT 1203 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } 1204 #endif 1205 1206 /** 1207 * class SkipIfEqual: 1208 * 1209 * Instantiating this class will result in assembly code being output that will 1210 * jump around any code emitted between the creation of the instance and it's 1211 * automatic destruction at the end of a scope block, depending on the value of 1212 * the flag passed to the constructor, which will be checked at run-time. 1213 */ 1214 class SkipIfEqual { 1215 private: 1216 MacroAssembler* _masm; 1217 Label _label; 1218 1219 public: 1220 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); 1221 ~SkipIfEqual(); 1222 }; 1223 1224 struct tableswitch { 1225 Register _reg; 1226 int _insn_index; jint _first_key; jint _last_key; 1227 Label _after; 1228 Label _branches; 1229 }; 1230 1231 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP