2033 INSN(addv, 0, 0b100001);
2034 INSN(subv, 1, 0b100001);
2035 INSN(mulv, 0, 0b100111);
2036 INSN(sshl, 0, 0b010001);
2037 INSN(ushl, 1, 0b010001);
2038
2039 #undef INSN
2040
2041 #define INSN(NAME, opc, opc2) \
2042 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2043 starti; \
2044 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2045 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
2046 rf(Vn, 5), rf(Vd, 0); \
2047 }
2048
2049 INSN(absr, 0, 0b100000101110);
2050 INSN(negr, 1, 0b100000101110);
2051 INSN(notr, 1, 0b100000010110);
2052 INSN(addv, 0, 0b110001101110);
2053
2054 #undef INSN
2055
2056 #define INSN(NAME, op0, cmode0) \
2057 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \
2058 unsigned cmode = cmode0; \
2059 unsigned op = op0; \
2060 starti; \
2061 assert(lsl == 0 || \
2062 ((T == T4H || T == T8H) && lsl == 8) || \
2063 ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \
2064 cmode |= lsl >> 2; \
2065 if (T == T4H || T == T8H) cmode |= 0b1000; \
2066 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
2067 assert(op == 0 && cmode0 == 0, "must be MOVI"); \
2068 cmode = 0b1110; \
2069 if (T == T1D || T == T2D) op = 1; \
2070 } \
2071 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \
2072 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
|
2033 INSN(addv, 0, 0b100001);
2034 INSN(subv, 1, 0b100001);
2035 INSN(mulv, 0, 0b100111);
2036 INSN(sshl, 0, 0b010001);
2037 INSN(ushl, 1, 0b010001);
2038
2039 #undef INSN
2040
2041 #define INSN(NAME, opc, opc2) \
2042 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2043 starti; \
2044 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2045 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
2046 rf(Vn, 5), rf(Vd, 0); \
2047 }
2048
2049 INSN(absr, 0, 0b100000101110);
2050 INSN(negr, 1, 0b100000101110);
2051 INSN(notr, 1, 0b100000010110);
2052 INSN(addv, 0, 0b110001101110);
2053 INSN(cls, 0, 0b100000010010);
2054 INSN(clz, 1, 0b100000010010);
2055 INSN(cnt, 0, 0b100000010110);
2056
2057 #undef INSN
2058
2059 #define INSN(NAME, op0, cmode0) \
2060 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \
2061 unsigned cmode = cmode0; \
2062 unsigned op = op0; \
2063 starti; \
2064 assert(lsl == 0 || \
2065 ((T == T4H || T == T8H) && lsl == 8) || \
2066 ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \
2067 cmode |= lsl >> 2; \
2068 if (T == T4H || T == T8H) cmode |= 0b1000; \
2069 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
2070 assert(op == 0 && cmode0 == 0, "must be MOVI"); \
2071 cmode = 0b1110; \
2072 if (T == T1D || T == T2D) op = 1; \
2073 } \
2074 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \
2075 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
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