1 /* 2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP 27 #define CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP 28 29 #include "asm/register.hpp" 30 31 // definitions of various symbolic names for machine registers 32 33 // First intercalls between C and Java which use 8 general registers 34 // and 8 floating registers 35 36 // we also have to copy between x86 and ARM registers but that's a 37 // secondary complication -- not all code employing C call convention 38 // executes as x86 code though -- we generate some of it 39 40 class Argument VALUE_OBJ_CLASS_SPEC { 41 public: 42 enum { 43 n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...) 44 n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... ) 45 46 n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ... 47 n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ... 48 }; 49 }; 50 51 REGISTER_DECLARATION(Register, c_rarg0, r0); 52 REGISTER_DECLARATION(Register, c_rarg1, r1); 53 REGISTER_DECLARATION(Register, c_rarg2, r2); 54 REGISTER_DECLARATION(Register, c_rarg3, r3); 55 REGISTER_DECLARATION(Register, c_rarg4, r4); 56 REGISTER_DECLARATION(Register, c_rarg5, r5); 57 REGISTER_DECLARATION(Register, c_rarg6, r6); 58 REGISTER_DECLARATION(Register, c_rarg7, r7); 59 60 REGISTER_DECLARATION(FloatRegister, c_farg0, v0); 61 REGISTER_DECLARATION(FloatRegister, c_farg1, v1); 62 REGISTER_DECLARATION(FloatRegister, c_farg2, v2); 63 REGISTER_DECLARATION(FloatRegister, c_farg3, v3); 64 REGISTER_DECLARATION(FloatRegister, c_farg4, v4); 65 REGISTER_DECLARATION(FloatRegister, c_farg5, v5); 66 REGISTER_DECLARATION(FloatRegister, c_farg6, v6); 67 REGISTER_DECLARATION(FloatRegister, c_farg7, v7); 68 69 // Symbolically name the register arguments used by the Java calling convention. 70 // We have control over the convention for java so we can do what we please. 71 // What pleases us is to offset the java calling convention so that when 72 // we call a suitable jni method the arguments are lined up and we don't 73 // have to do much shuffling. A suitable jni method is non-static and a 74 // small number of arguments 75 // 76 // |--------------------------------------------------------------------| 77 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 | 78 // |--------------------------------------------------------------------| 79 // | r0 r1 r2 r3 r4 r5 r6 r7 | 80 // |--------------------------------------------------------------------| 81 // | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 | 82 // |--------------------------------------------------------------------| 83 84 85 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); 86 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); 87 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); 88 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); 89 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); 90 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6); 91 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7); 92 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0); 93 94 // Java floating args are passed as per C 95 96 REGISTER_DECLARATION(FloatRegister, j_farg0, v0); 97 REGISTER_DECLARATION(FloatRegister, j_farg1, v1); 98 REGISTER_DECLARATION(FloatRegister, j_farg2, v2); 99 REGISTER_DECLARATION(FloatRegister, j_farg3, v3); 100 REGISTER_DECLARATION(FloatRegister, j_farg4, v4); 101 REGISTER_DECLARATION(FloatRegister, j_farg5, v5); 102 REGISTER_DECLARATION(FloatRegister, j_farg6, v6); 103 REGISTER_DECLARATION(FloatRegister, j_farg7, v7); 104 105 // registers used to hold VM data either temporarily within a method 106 // or across method calls 107 108 // volatile (caller-save) registers 109 110 // r8 is used for indirect result location return 111 // we use it and r9 as scratch registers 112 REGISTER_DECLARATION(Register, rscratch1, r8); 113 REGISTER_DECLARATION(Register, rscratch2, r9); 114 115 // current method -- must be in a call-clobbered register 116 REGISTER_DECLARATION(Register, rmethod, r12); 117 118 // non-volatile (callee-save) registers are r16-29 119 // of which the following are dedicated global state 120 121 // link register 122 REGISTER_DECLARATION(Register, lr, r30); 123 // frame pointer 124 REGISTER_DECLARATION(Register, rfp, r29); 125 // current thread 126 REGISTER_DECLARATION(Register, rthread, r28); 127 // base of heap 128 REGISTER_DECLARATION(Register, rheapbase, r27); 129 // constant pool cache 130 REGISTER_DECLARATION(Register, rcpool, r26); 131 // monitors allocated on stack 132 REGISTER_DECLARATION(Register, rmonitors, r25); 133 // locals on stack 134 REGISTER_DECLARATION(Register, rlocals, r24); 135 // bytecode pointer 136 REGISTER_DECLARATION(Register, rbcp, r22); 137 // Dispatch table base 138 REGISTER_DECLARATION(Register, rdispatch, r21); 139 // Java stack pointer 140 REGISTER_DECLARATION(Register, esp, r20); 141 142 // TODO : x86 uses rbp to save SP in method handle code 143 // we may need to do the same with fp 144 // JSR 292 fixed register usages: 145 //REGISTER_DECLARATION(Register, r_mh_SP_save, r29); 146 147 #define assert_cond(ARG1) assert(ARG1, #ARG1) 148 149 namespace asm_util { 150 uint32_t encode_logical_immediate(bool is32, uint64_t imm); 151 }; 152 153 using namespace asm_util; 154 155 156 class Assembler; 157 158 class Instruction_aarch64 { 159 unsigned insn; 160 #ifdef ASSERT 161 unsigned bits; 162 #endif 163 Assembler *assem; 164 165 public: 166 167 Instruction_aarch64(class Assembler *as) { 168 #ifdef ASSERT 169 bits = 0; 170 #endif 171 insn = 0; 172 assem = as; 173 } 174 175 inline ~Instruction_aarch64(); 176 177 unsigned &get_insn() { return insn; } 178 #ifdef ASSERT 179 unsigned &get_bits() { return bits; } 180 #endif 181 182 static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) { 183 union { 184 unsigned u; 185 int n; 186 }; 187 188 u = val << (31 - hi); 189 n = n >> (31 - hi + lo); 190 return n; 191 } 192 193 static inline uint32_t extract(uint32_t val, int msb, int lsb) { 194 int nbits = msb - lsb + 1; 195 assert_cond(msb >= lsb); 196 uint32_t mask = (1U << nbits) - 1; 197 uint32_t result = val >> lsb; 198 result &= mask; 199 return result; 200 } 201 202 static inline int32_t sextract(uint32_t val, int msb, int lsb) { 203 uint32_t uval = extract(val, msb, lsb); 204 return extend(uval, msb - lsb); 205 } 206 207 static void patch(address a, int msb, int lsb, unsigned long val) { 208 int nbits = msb - lsb + 1; 209 guarantee(val < (1U << nbits), "Field too big for insn"); 210 assert_cond(msb >= lsb); 211 unsigned mask = (1U << nbits) - 1; 212 val <<= lsb; 213 mask <<= lsb; 214 unsigned target = *(unsigned *)a; 215 target &= ~mask; 216 target |= val; 217 *(unsigned *)a = target; 218 } 219 220 static void spatch(address a, int msb, int lsb, long val) { 221 int nbits = msb - lsb + 1; 222 long chk = val >> (nbits - 1); 223 guarantee (chk == -1 || chk == 0, "Field too big for insn"); 224 unsigned uval = val; 225 unsigned mask = (1U << nbits) - 1; 226 uval &= mask; 227 uval <<= lsb; 228 mask <<= lsb; 229 unsigned target = *(unsigned *)a; 230 target &= ~mask; 231 target |= uval; 232 *(unsigned *)a = target; 233 } 234 235 void f(unsigned val, int msb, int lsb) { 236 int nbits = msb - lsb + 1; 237 guarantee(val < (1U << nbits), "Field too big for insn"); 238 assert_cond(msb >= lsb); 239 unsigned mask = (1U << nbits) - 1; 240 val <<= lsb; 241 mask <<= lsb; 242 insn |= val; 243 assert_cond((bits & mask) == 0); 244 #ifdef ASSERT 245 bits |= mask; 246 #endif 247 } 248 249 void f(unsigned val, int bit) { 250 f(val, bit, bit); 251 } 252 253 void sf(long val, int msb, int lsb) { 254 int nbits = msb - lsb + 1; 255 long chk = val >> (nbits - 1); 256 guarantee (chk == -1 || chk == 0, "Field too big for insn"); 257 unsigned uval = val; 258 unsigned mask = (1U << nbits) - 1; 259 uval &= mask; 260 f(uval, lsb + nbits - 1, lsb); 261 } 262 263 void rf(Register r, int lsb) { 264 f(r->encoding_nocheck(), lsb + 4, lsb); 265 } 266 267 // reg|ZR 268 void zrf(Register r, int lsb) { 269 f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb); 270 } 271 272 // reg|SP 273 void srf(Register r, int lsb) { 274 f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb); 275 } 276 277 void rf(FloatRegister r, int lsb) { 278 f(r->encoding_nocheck(), lsb + 4, lsb); 279 } 280 281 unsigned get(int msb = 31, int lsb = 0) { 282 int nbits = msb - lsb + 1; 283 unsigned mask = ((1U << nbits) - 1) << lsb; 284 assert_cond(bits & mask == mask); 285 return (insn & mask) >> lsb; 286 } 287 288 void fixed(unsigned value, unsigned mask) { 289 assert_cond ((mask & bits) == 0); 290 #ifdef ASSERT 291 bits |= mask; 292 #endif 293 insn |= value; 294 } 295 }; 296 297 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use) 298 299 class PrePost { 300 int _offset; 301 Register _r; 302 public: 303 PrePost(Register reg, int o) : _r(reg), _offset(o) { } 304 int offset() { return _offset; } 305 Register reg() { return _r; } 306 }; 307 308 class Pre : public PrePost { 309 public: 310 Pre(Register reg, int o) : PrePost(reg, o) { } 311 }; 312 class Post : public PrePost { 313 public: 314 Post(Register reg, int o) : PrePost(reg, o) { } 315 }; 316 317 namespace ext 318 { 319 enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx }; 320 }; 321 322 // abs methods which cannot overflow and so are well-defined across 323 // the entire domain of integer types. 324 static inline unsigned int uabs(unsigned int n) { 325 union { 326 unsigned int result; 327 int value; 328 }; 329 result = n; 330 if (value < 0) result = -result; 331 return result; 332 } 333 static inline unsigned long uabs(unsigned long n) { 334 union { 335 unsigned long result; 336 long value; 337 }; 338 result = n; 339 if (value < 0) result = -result; 340 return result; 341 } 342 static inline unsigned long uabs(long n) { return uabs((unsigned long)n); } 343 static inline unsigned long uabs(int n) { return uabs((unsigned int)n); } 344 345 // Addressing modes 346 class Address VALUE_OBJ_CLASS_SPEC { 347 public: 348 349 enum mode { no_mode, base_plus_offset, pre, post, pcrel, 350 base_plus_offset_reg, literal }; 351 352 // Shift and extend for base reg + reg offset addressing 353 class extend { 354 int _option, _shift; 355 ext::operation _op; 356 public: 357 extend() { } 358 extend(int s, int o, ext::operation op) : _shift(s), _option(o), _op(op) { } 359 int option() const{ return _option; } 360 int shift() const { return _shift; } 361 ext::operation op() const { return _op; } 362 }; 363 class uxtw : public extend { 364 public: 365 uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { } 366 }; 367 class lsl : public extend { 368 public: 369 lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { } 370 }; 371 class sxtw : public extend { 372 public: 373 sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { } 374 }; 375 class sxtx : public extend { 376 public: 377 sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { } 378 }; 379 380 private: 381 Register _base; 382 Register _index; 383 long _offset; 384 enum mode _mode; 385 extend _ext; 386 387 RelocationHolder _rspec; 388 389 // Typically we use AddressLiterals we want to use their rval 390 // However in some situations we want the lval (effect address) of 391 // the item. We provide a special factory for making those lvals. 392 bool _is_lval; 393 394 // If the target is far we'll need to load the ea of this to a 395 // register to reach it. Otherwise if near we can do PC-relative 396 // addressing. 397 address _target; 398 399 public: 400 Address() 401 : _mode(no_mode) { } 402 Address(Register r) 403 : _mode(base_plus_offset), _base(r), _offset(0), _index(noreg), _target(0) { } 404 Address(Register r, int o) 405 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { } 406 Address(Register r, long o) 407 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { } 408 Address(Register r, unsigned long o) 409 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { } 410 #ifdef ASSERT 411 Address(Register r, ByteSize disp) 412 : _mode(base_plus_offset), _base(r), _offset(in_bytes(disp)), 413 _index(noreg), _target(0) { } 414 #endif 415 Address(Register r, Register r1, extend ext = lsl()) 416 : _mode(base_plus_offset_reg), _base(r), _index(r1), 417 _ext(ext), _offset(0), _target(0) { } 418 Address(Pre p) 419 : _mode(pre), _base(p.reg()), _offset(p.offset()) { } 420 Address(Post p) 421 : _mode(post), _base(p.reg()), _offset(p.offset()), _target(0) { } 422 Address(address target, RelocationHolder const& rspec) 423 : _mode(literal), 424 _rspec(rspec), 425 _is_lval(false), 426 _target(target) { } 427 Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type); 428 Address(Register base, RegisterOrConstant index, extend ext = lsl()) 429 : _base (base), 430 _ext(ext), _offset(0), _target(0) { 431 if (index.is_register()) { 432 _mode = base_plus_offset_reg; 433 _index = index.as_register(); 434 } else { 435 guarantee(ext.option() == ext::uxtx, "should be"); 436 assert(index.is_constant(), "should be"); 437 _mode = base_plus_offset; 438 _offset = index.as_constant() << ext.shift(); 439 } 440 } 441 442 Register base() const { 443 guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg 444 | _mode == post), 445 "wrong mode"); 446 return _base; 447 } 448 long offset() const { 449 return _offset; 450 } 451 Register index() const { 452 return _index; 453 } 454 mode getMode() const { 455 return _mode; 456 } 457 bool uses(Register reg) const { return _base == reg || _index == reg; } 458 address target() const { return _target; } 459 const RelocationHolder& rspec() const { return _rspec; } 460 461 void encode(Instruction_aarch64 *i) const { 462 i->f(0b111, 29, 27); 463 i->srf(_base, 5); 464 465 switch(_mode) { 466 case base_plus_offset: 467 { 468 unsigned size = i->get(31, 30); 469 if (i->get(26, 26) && i->get(23, 23)) { 470 // SIMD Q Type - Size = 128 bits 471 assert(size == 0, "bad size"); 472 size = 0b100; 473 } 474 unsigned mask = (1 << size) - 1; 475 if (_offset < 0 || _offset & mask) 476 { 477 i->f(0b00, 25, 24); 478 i->f(0, 21), i->f(0b00, 11, 10); 479 i->sf(_offset, 20, 12); 480 } else { 481 i->f(0b01, 25, 24); 482 i->f(_offset >> size, 21, 10); 483 } 484 } 485 break; 486 487 case base_plus_offset_reg: 488 { 489 i->f(0b00, 25, 24); 490 i->f(1, 21); 491 i->rf(_index, 16); 492 i->f(_ext.option(), 15, 13); 493 unsigned size = i->get(31, 30); 494 if (i->get(26, 26) && i->get(23, 23)) { 495 // SIMD Q Type - Size = 128 bits 496 assert(size == 0, "bad size"); 497 size = 0b100; 498 } 499 if (size == 0) // It's a byte 500 i->f(_ext.shift() >= 0, 12); 501 else { 502 if (_ext.shift() > 0) 503 assert(_ext.shift() == (int)size, "bad shift"); 504 i->f(_ext.shift() > 0, 12); 505 } 506 i->f(0b10, 11, 10); 507 } 508 break; 509 510 case pre: 511 i->f(0b00, 25, 24); 512 i->f(0, 21), i->f(0b11, 11, 10); 513 i->sf(_offset, 20, 12); 514 break; 515 516 case post: 517 i->f(0b00, 25, 24); 518 i->f(0, 21), i->f(0b01, 11, 10); 519 i->sf(_offset, 20, 12); 520 break; 521 522 default: 523 ShouldNotReachHere(); 524 } 525 } 526 527 void encode_pair(Instruction_aarch64 *i) const { 528 switch(_mode) { 529 case base_plus_offset: 530 i->f(0b010, 25, 23); 531 break; 532 case pre: 533 i->f(0b011, 25, 23); 534 break; 535 case post: 536 i->f(0b001, 25, 23); 537 break; 538 default: 539 ShouldNotReachHere(); 540 } 541 542 unsigned size; // Operand shift in 32-bit words 543 544 if (i->get(26, 26)) { // float 545 switch(i->get(31, 30)) { 546 case 0b10: 547 size = 2; break; 548 case 0b01: 549 size = 1; break; 550 case 0b00: 551 size = 0; break; 552 default: 553 ShouldNotReachHere(); 554 } 555 } else { 556 size = i->get(31, 31); 557 } 558 559 size = 4 << size; 560 guarantee(_offset % size == 0, "bad offset"); 561 i->sf(_offset / size, 21, 15); 562 i->srf(_base, 5); 563 } 564 565 void encode_nontemporal_pair(Instruction_aarch64 *i) const { 566 // Only base + offset is allowed 567 i->f(0b000, 25, 23); 568 unsigned size = i->get(31, 31); 569 size = 4 << size; 570 guarantee(_offset % size == 0, "bad offset"); 571 i->sf(_offset / size, 21, 15); 572 i->srf(_base, 5); 573 guarantee(_mode == Address::base_plus_offset, 574 "Bad addressing mode for non-temporal op"); 575 } 576 577 void lea(MacroAssembler *, Register) const; 578 579 static bool offset_ok_for_immed(long offset, int shift = 0) { 580 unsigned mask = (1 << shift) - 1; 581 if (offset < 0 || offset & mask) { 582 return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset 583 } else { 584 return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset 585 } 586 } 587 }; 588 589 // Convience classes 590 class RuntimeAddress: public Address { 591 592 public: 593 594 RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {} 595 596 }; 597 598 class OopAddress: public Address { 599 600 public: 601 602 OopAddress(address target) : Address(target, relocInfo::oop_type){} 603 604 }; 605 606 class ExternalAddress: public Address { 607 private: 608 static relocInfo::relocType reloc_for_target(address target) { 609 // Sometimes ExternalAddress is used for values which aren't 610 // exactly addresses, like the card table base. 611 // external_word_type can't be used for values in the first page 612 // so just skip the reloc in that case. 613 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; 614 } 615 616 public: 617 618 ExternalAddress(address target) : Address(target, reloc_for_target(target)) {} 619 620 }; 621 622 class InternalAddress: public Address { 623 624 public: 625 626 InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {} 627 }; 628 629 const int FPUStateSizeInWords = 32 * 2; 630 typedef enum { 631 PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM, 632 PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM, 633 PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM 634 } prfop; 635 636 class Assembler : public AbstractAssembler { 637 638 #ifndef PRODUCT 639 static const unsigned long asm_bp; 640 641 void emit_long(jint x) { 642 if ((unsigned long)pc() == asm_bp) 643 asm volatile ("nop"); 644 AbstractAssembler::emit_int32(x); 645 } 646 #else 647 void emit_long(jint x) { 648 AbstractAssembler::emit_int32(x); 649 } 650 #endif 651 652 public: 653 654 enum { instruction_size = 4 }; 655 656 Address adjust(Register base, int offset, bool preIncrement) { 657 if (preIncrement) 658 return Address(Pre(base, offset)); 659 else 660 return Address(Post(base, offset)); 661 } 662 663 Address pre(Register base, int offset) { 664 return adjust(base, offset, true); 665 } 666 667 Address post (Register base, int offset) { 668 return adjust(base, offset, false); 669 } 670 671 Instruction_aarch64* current; 672 673 void set_current(Instruction_aarch64* i) { current = i; } 674 675 void f(unsigned val, int msb, int lsb) { 676 current->f(val, msb, lsb); 677 } 678 void f(unsigned val, int msb) { 679 current->f(val, msb, msb); 680 } 681 void sf(long val, int msb, int lsb) { 682 current->sf(val, msb, lsb); 683 } 684 void rf(Register reg, int lsb) { 685 current->rf(reg, lsb); 686 } 687 void srf(Register reg, int lsb) { 688 current->srf(reg, lsb); 689 } 690 void zrf(Register reg, int lsb) { 691 current->zrf(reg, lsb); 692 } 693 void rf(FloatRegister reg, int lsb) { 694 current->rf(reg, lsb); 695 } 696 void fixed(unsigned value, unsigned mask) { 697 current->fixed(value, mask); 698 } 699 700 void emit() { 701 emit_long(current->get_insn()); 702 assert_cond(current->get_bits() == 0xffffffff); 703 current = NULL; 704 } 705 706 typedef void (Assembler::* uncond_branch_insn)(address dest); 707 typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest); 708 typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest); 709 typedef void (Assembler::* prefetch_insn)(address target, prfop); 710 711 void wrap_label(Label &L, uncond_branch_insn insn); 712 void wrap_label(Register r, Label &L, compare_and_branch_insn insn); 713 void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn); 714 void wrap_label(Label &L, prfop, prefetch_insn insn); 715 716 // PC-rel. addressing 717 718 void adr(Register Rd, address dest); 719 void _adrp(Register Rd, address dest); 720 721 void adr(Register Rd, const Address &dest); 722 void _adrp(Register Rd, const Address &dest); 723 724 void adr(Register Rd, Label &L) { 725 wrap_label(Rd, L, &Assembler::Assembler::adr); 726 } 727 void _adrp(Register Rd, Label &L) { 728 wrap_label(Rd, L, &Assembler::_adrp); 729 } 730 731 void adrp(Register Rd, const Address &dest, unsigned long &offset); 732 733 #undef INSN 734 735 void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op, 736 int negated_op); 737 738 // Add/subtract (immediate) 739 #define INSN(NAME, decode, negated) \ 740 void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \ 741 starti; \ 742 f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \ 743 zrf(Rd, 0), srf(Rn, 5); \ 744 } \ 745 \ 746 void NAME(Register Rd, Register Rn, unsigned imm) { \ 747 starti; \ 748 add_sub_immediate(Rd, Rn, imm, decode, negated); \ 749 } 750 751 INSN(addsw, 0b001, 0b011); 752 INSN(subsw, 0b011, 0b001); 753 INSN(adds, 0b101, 0b111); 754 INSN(subs, 0b111, 0b101); 755 756 #undef INSN 757 758 #define INSN(NAME, decode, negated) \ 759 void NAME(Register Rd, Register Rn, unsigned imm) { \ 760 starti; \ 761 add_sub_immediate(Rd, Rn, imm, decode, negated); \ 762 } 763 764 INSN(addw, 0b000, 0b010); 765 INSN(subw, 0b010, 0b000); 766 INSN(add, 0b100, 0b110); 767 INSN(sub, 0b110, 0b100); 768 769 #undef INSN 770 771 // Logical (immediate) 772 #define INSN(NAME, decode, is32) \ 773 void NAME(Register Rd, Register Rn, uint64_t imm) { \ 774 starti; \ 775 uint32_t val = encode_logical_immediate(is32, imm); \ 776 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \ 777 srf(Rd, 0), zrf(Rn, 5); \ 778 } 779 780 INSN(andw, 0b000, true); 781 INSN(orrw, 0b001, true); 782 INSN(eorw, 0b010, true); 783 INSN(andr, 0b100, false); 784 INSN(orr, 0b101, false); 785 INSN(eor, 0b110, false); 786 787 #undef INSN 788 789 #define INSN(NAME, decode, is32) \ 790 void NAME(Register Rd, Register Rn, uint64_t imm) { \ 791 starti; \ 792 uint32_t val = encode_logical_immediate(is32, imm); \ 793 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \ 794 zrf(Rd, 0), zrf(Rn, 5); \ 795 } 796 797 INSN(ands, 0b111, false); 798 INSN(andsw, 0b011, true); 799 800 #undef INSN 801 802 // Move wide (immediate) 803 #define INSN(NAME, opcode) \ 804 void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \ 805 assert_cond((shift/16)*16 == shift); \ 806 starti; \ 807 f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \ 808 f(imm, 20, 5); \ 809 rf(Rd, 0); \ 810 } 811 812 INSN(movnw, 0b000); 813 INSN(movzw, 0b010); 814 INSN(movkw, 0b011); 815 INSN(movn, 0b100); 816 INSN(movz, 0b110); 817 INSN(movk, 0b111); 818 819 #undef INSN 820 821 // Bitfield 822 #define INSN(NAME, opcode) \ 823 void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \ 824 starti; \ 825 f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \ 826 rf(Rn, 5), rf(Rd, 0); \ 827 } 828 829 INSN(sbfmw, 0b0001001100); 830 INSN(bfmw, 0b0011001100); 831 INSN(ubfmw, 0b0101001100); 832 INSN(sbfm, 0b1001001101); 833 INSN(bfm, 0b1011001101); 834 INSN(ubfm, 0b1101001101); 835 836 #undef INSN 837 838 // Extract 839 #define INSN(NAME, opcode) \ 840 void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \ 841 starti; \ 842 f(opcode, 31, 21), f(imms, 15, 10); \ 843 rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \ 844 } 845 846 INSN(extrw, 0b00010011100); 847 INSN(extr, 0b10010011110); 848 849 #undef INSN 850 851 // The maximum range of a branch is fixed for the AArch64 852 // architecture. In debug mode we shrink it in order to test 853 // trampolines, but not so small that branches in the interpreter 854 // are out of range. 855 static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M); 856 857 static bool reachable_from_branch_at(address branch, address target) { 858 return uabs(target - branch) < branch_range; 859 } 860 861 // Unconditional branch (immediate) 862 #define INSN(NAME, opcode) \ 863 void NAME(address dest) { \ 864 starti; \ 865 long offset = (dest - pc()) >> 2; \ 866 DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \ 867 f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \ 868 } \ 869 void NAME(Label &L) { \ 870 wrap_label(L, &Assembler::NAME); \ 871 } \ 872 void NAME(const Address &dest); 873 874 INSN(b, 0); 875 INSN(bl, 1); 876 877 #undef INSN 878 879 // Compare & branch (immediate) 880 #define INSN(NAME, opcode) \ 881 void NAME(Register Rt, address dest) { \ 882 long offset = (dest - pc()) >> 2; \ 883 starti; \ 884 f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \ 885 } \ 886 void NAME(Register Rt, Label &L) { \ 887 wrap_label(Rt, L, &Assembler::NAME); \ 888 } 889 890 INSN(cbzw, 0b00110100); 891 INSN(cbnzw, 0b00110101); 892 INSN(cbz, 0b10110100); 893 INSN(cbnz, 0b10110101); 894 895 #undef INSN 896 897 // Test & branch (immediate) 898 #define INSN(NAME, opcode) \ 899 void NAME(Register Rt, int bitpos, address dest) { \ 900 long offset = (dest - pc()) >> 2; \ 901 int b5 = bitpos >> 5; \ 902 bitpos &= 0x1f; \ 903 starti; \ 904 f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \ 905 rf(Rt, 0); \ 906 } \ 907 void NAME(Register Rt, int bitpos, Label &L) { \ 908 wrap_label(Rt, bitpos, L, &Assembler::NAME); \ 909 } 910 911 INSN(tbz, 0b0110110); 912 INSN(tbnz, 0b0110111); 913 914 #undef INSN 915 916 // Conditional branch (immediate) 917 enum Condition 918 {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV}; 919 920 void br(Condition cond, address dest) { 921 long offset = (dest - pc()) >> 2; 922 starti; 923 f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0); 924 } 925 926 #define INSN(NAME, cond) \ 927 void NAME(address dest) { \ 928 br(cond, dest); \ 929 } 930 931 INSN(beq, EQ); 932 INSN(bne, NE); 933 INSN(bhs, HS); 934 INSN(bcs, CS); 935 INSN(blo, LO); 936 INSN(bcc, CC); 937 INSN(bmi, MI); 938 INSN(bpl, PL); 939 INSN(bvs, VS); 940 INSN(bvc, VC); 941 INSN(bhi, HI); 942 INSN(bls, LS); 943 INSN(bge, GE); 944 INSN(blt, LT); 945 INSN(bgt, GT); 946 INSN(ble, LE); 947 INSN(bal, AL); 948 INSN(bnv, NV); 949 950 void br(Condition cc, Label &L); 951 952 #undef INSN 953 954 // Exception generation 955 void generate_exception(int opc, int op2, int LL, unsigned imm) { 956 starti; 957 f(0b11010100, 31, 24); 958 f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0); 959 } 960 961 #define INSN(NAME, opc, op2, LL) \ 962 void NAME(unsigned imm) { \ 963 generate_exception(opc, op2, LL, imm); \ 964 } 965 966 INSN(svc, 0b000, 0, 0b01); 967 INSN(hvc, 0b000, 0, 0b10); 968 INSN(smc, 0b000, 0, 0b11); 969 INSN(brk, 0b001, 0, 0b00); 970 INSN(hlt, 0b010, 0, 0b00); 971 INSN(dpcs1, 0b101, 0, 0b01); 972 INSN(dpcs2, 0b101, 0, 0b10); 973 INSN(dpcs3, 0b101, 0, 0b11); 974 975 #undef INSN 976 977 // System 978 void system(int op0, int op1, int CRn, int CRm, int op2, 979 Register rt = (Register)0b11111) 980 { 981 starti; 982 f(0b11010101000, 31, 21); 983 f(op0, 20, 19); 984 f(op1, 18, 16); 985 f(CRn, 15, 12); 986 f(CRm, 11, 8); 987 f(op2, 7, 5); 988 rf(rt, 0); 989 } 990 991 void hint(int imm) { 992 system(0b00, 0b011, 0b0010, imm, 0b000); 993 } 994 995 void nop() { 996 hint(0); 997 } 998 // we only provide mrs and msr for the special purpose system 999 // registers where op1 (instr[20:19]) == 11 and, (currently) only 1000 // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1 1001 1002 void msr(int op1, int CRn, int CRm, int op2, Register rt) { 1003 starti; 1004 f(0b1101010100011, 31, 19); 1005 f(op1, 18, 16); 1006 f(CRn, 15, 12); 1007 f(CRm, 11, 8); 1008 f(op2, 7, 5); 1009 // writing zr is ok 1010 zrf(rt, 0); 1011 } 1012 1013 void mrs(int op1, int CRn, int CRm, int op2, Register rt) { 1014 starti; 1015 f(0b1101010100111, 31, 19); 1016 f(op1, 18, 16); 1017 f(CRn, 15, 12); 1018 f(CRm, 11, 8); 1019 f(op2, 7, 5); 1020 // reading to zr is a mistake 1021 rf(rt, 0); 1022 } 1023 1024 enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH, 1025 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY}; 1026 1027 void dsb(barrier imm) { 1028 system(0b00, 0b011, 0b00011, imm, 0b100); 1029 } 1030 1031 void dmb(barrier imm) { 1032 system(0b00, 0b011, 0b00011, imm, 0b101); 1033 } 1034 1035 void isb() { 1036 system(0b00, 0b011, 0b00011, SY, 0b110); 1037 } 1038 1039 void dc(Register Rt) { 1040 system(0b01, 0b011, 0b0111, 0b1011, 0b001, Rt); 1041 } 1042 1043 void ic(Register Rt) { 1044 system(0b01, 0b011, 0b0111, 0b0101, 0b001, Rt); 1045 } 1046 1047 // A more convenient access to dmb for our purposes 1048 enum Membar_mask_bits { 1049 // We can use ISH for a barrier because the ARM ARM says "This 1050 // architecture assumes that all Processing Elements that use the 1051 // same operating system or hypervisor are in the same Inner 1052 // Shareable shareability domain." 1053 StoreStore = ISHST, 1054 LoadStore = ISHLD, 1055 LoadLoad = ISHLD, 1056 StoreLoad = ISH, 1057 AnyAny = ISH 1058 }; 1059 1060 void membar(Membar_mask_bits order_constraint) { 1061 dmb(Assembler::barrier(order_constraint)); 1062 } 1063 1064 // Unconditional branch (register) 1065 void branch_reg(Register R, int opc) { 1066 starti; 1067 f(0b1101011, 31, 25); 1068 f(opc, 24, 21); 1069 f(0b11111000000, 20, 10); 1070 rf(R, 5); 1071 f(0b00000, 4, 0); 1072 } 1073 1074 #define INSN(NAME, opc) \ 1075 void NAME(Register R) { \ 1076 branch_reg(R, opc); \ 1077 } 1078 1079 INSN(br, 0b0000); 1080 INSN(blr, 0b0001); 1081 INSN(ret, 0b0010); 1082 1083 void ret(void *p); // This forces a compile-time error for ret(0) 1084 1085 #undef INSN 1086 1087 #define INSN(NAME, opc) \ 1088 void NAME() { \ 1089 branch_reg((Register)0b11111, opc); \ 1090 } 1091 1092 INSN(eret, 0b0100); 1093 INSN(drps, 0b0101); 1094 1095 #undef INSN 1096 1097 // Load/store exclusive 1098 enum operand_size { byte, halfword, word, xword }; 1099 1100 void load_store_exclusive(Register Rs, Register Rt1, Register Rt2, 1101 Register Rn, enum operand_size sz, int op, int o0) { 1102 starti; 1103 f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21); 1104 rf(Rs, 16), f(o0, 15), rf(Rt2, 10), rf(Rn, 5), rf(Rt1, 0); 1105 } 1106 1107 #define INSN4(NAME, sz, op, o0) /* Four registers */ \ 1108 void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \ 1109 assert(Rs != Rn, "unpredictable instruction"); \ 1110 load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \ 1111 } 1112 1113 #define INSN3(NAME, sz, op, o0) /* Three registers */ \ 1114 void NAME(Register Rs, Register Rt, Register Rn) { \ 1115 assert(Rs != Rn, "unpredictable instruction"); \ 1116 load_store_exclusive(Rs, Rt, (Register)0b11111, Rn, sz, op, o0); \ 1117 } 1118 1119 #define INSN2(NAME, sz, op, o0) /* Two registers */ \ 1120 void NAME(Register Rt, Register Rn) { \ 1121 load_store_exclusive((Register)0b11111, Rt, (Register)0b11111, \ 1122 Rn, sz, op, o0); \ 1123 } 1124 1125 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \ 1126 void NAME(Register Rt1, Register Rt2, Register Rn) { \ 1127 load_store_exclusive((Register)0b11111, Rt1, Rt2, Rn, sz, op, o0); \ 1128 } 1129 1130 // bytes 1131 INSN3(stxrb, byte, 0b000, 0); 1132 INSN3(stlxrb, byte, 0b000, 1); 1133 INSN2(ldxrb, byte, 0b010, 0); 1134 INSN2(ldaxrb, byte, 0b010, 1); 1135 INSN2(stlrb, byte, 0b100, 1); 1136 INSN2(ldarb, byte, 0b110, 1); 1137 1138 // halfwords 1139 INSN3(stxrh, halfword, 0b000, 0); 1140 INSN3(stlxrh, halfword, 0b000, 1); 1141 INSN2(ldxrh, halfword, 0b010, 0); 1142 INSN2(ldaxrh, halfword, 0b010, 1); 1143 INSN2(stlrh, halfword, 0b100, 1); 1144 INSN2(ldarh, halfword, 0b110, 1); 1145 1146 // words 1147 INSN3(stxrw, word, 0b000, 0); 1148 INSN3(stlxrw, word, 0b000, 1); 1149 INSN4(stxpw, word, 0b001, 0); 1150 INSN4(stlxpw, word, 0b001, 1); 1151 INSN2(ldxrw, word, 0b010, 0); 1152 INSN2(ldaxrw, word, 0b010, 1); 1153 INSN_FOO(ldxpw, word, 0b011, 0); 1154 INSN_FOO(ldaxpw, word, 0b011, 1); 1155 INSN2(stlrw, word, 0b100, 1); 1156 INSN2(ldarw, word, 0b110, 1); 1157 1158 // xwords 1159 INSN3(stxr, xword, 0b000, 0); 1160 INSN3(stlxr, xword, 0b000, 1); 1161 INSN4(stxp, xword, 0b001, 0); 1162 INSN4(stlxp, xword, 0b001, 1); 1163 INSN2(ldxr, xword, 0b010, 0); 1164 INSN2(ldaxr, xword, 0b010, 1); 1165 INSN_FOO(ldxp, xword, 0b011, 0); 1166 INSN_FOO(ldaxp, xword, 0b011, 1); 1167 INSN2(stlr, xword, 0b100, 1); 1168 INSN2(ldar, xword, 0b110, 1); 1169 1170 #undef INSN2 1171 #undef INSN3 1172 #undef INSN4 1173 #undef INSN_FOO 1174 1175 // Load register (literal) 1176 #define INSN(NAME, opc, V) \ 1177 void NAME(Register Rt, address dest) { \ 1178 long offset = (dest - pc()) >> 2; \ 1179 starti; \ 1180 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ 1181 sf(offset, 23, 5); \ 1182 rf(Rt, 0); \ 1183 } \ 1184 void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \ 1185 InstructionMark im(this); \ 1186 guarantee(rtype == relocInfo::internal_word_type, \ 1187 "only internal_word_type relocs make sense here"); \ 1188 code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \ 1189 NAME(Rt, dest); \ 1190 } \ 1191 void NAME(Register Rt, Label &L) { \ 1192 wrap_label(Rt, L, &Assembler::NAME); \ 1193 } 1194 1195 INSN(ldrw, 0b00, 0); 1196 INSN(ldr, 0b01, 0); 1197 INSN(ldrsw, 0b10, 0); 1198 1199 #undef INSN 1200 1201 #define INSN(NAME, opc, V) \ 1202 void NAME(FloatRegister Rt, address dest) { \ 1203 long offset = (dest - pc()) >> 2; \ 1204 starti; \ 1205 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ 1206 sf(offset, 23, 5); \ 1207 rf((Register)Rt, 0); \ 1208 } 1209 1210 INSN(ldrs, 0b00, 1); 1211 INSN(ldrd, 0b01, 1); 1212 INSN(ldrq, 0x10, 1); 1213 1214 #undef INSN 1215 1216 #define INSN(NAME, opc, V) \ 1217 void NAME(address dest, prfop op = PLDL1KEEP) { \ 1218 long offset = (dest - pc()) >> 2; \ 1219 starti; \ 1220 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ 1221 sf(offset, 23, 5); \ 1222 f(op, 4, 0); \ 1223 } \ 1224 void NAME(Label &L, prfop op = PLDL1KEEP) { \ 1225 wrap_label(L, op, &Assembler::NAME); \ 1226 } 1227 1228 INSN(prfm, 0b11, 0); 1229 1230 #undef INSN 1231 1232 // Load/store 1233 void ld_st1(int opc, int p1, int V, int L, 1234 Register Rt1, Register Rt2, Address adr, bool no_allocate) { 1235 starti; 1236 f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22); 1237 zrf(Rt2, 10), zrf(Rt1, 0); 1238 if (no_allocate) { 1239 adr.encode_nontemporal_pair(current); 1240 } else { 1241 adr.encode_pair(current); 1242 } 1243 } 1244 1245 // Load/store register pair (offset) 1246 #define INSN(NAME, size, p1, V, L, no_allocate) \ 1247 void NAME(Register Rt1, Register Rt2, Address adr) { \ 1248 ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \ 1249 } 1250 1251 INSN(stpw, 0b00, 0b101, 0, 0, false); 1252 INSN(ldpw, 0b00, 0b101, 0, 1, false); 1253 INSN(ldpsw, 0b01, 0b101, 0, 1, false); 1254 INSN(stp, 0b10, 0b101, 0, 0, false); 1255 INSN(ldp, 0b10, 0b101, 0, 1, false); 1256 1257 // Load/store no-allocate pair (offset) 1258 INSN(stnpw, 0b00, 0b101, 0, 0, true); 1259 INSN(ldnpw, 0b00, 0b101, 0, 1, true); 1260 INSN(stnp, 0b10, 0b101, 0, 0, true); 1261 INSN(ldnp, 0b10, 0b101, 0, 1, true); 1262 1263 #undef INSN 1264 1265 #define INSN(NAME, size, p1, V, L, no_allocate) \ 1266 void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \ 1267 ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \ 1268 } 1269 1270 INSN(stps, 0b00, 0b101, 1, 0, false); 1271 INSN(ldps, 0b00, 0b101, 1, 1, false); 1272 INSN(stpd, 0b01, 0b101, 1, 0, false); 1273 INSN(ldpd, 0b01, 0b101, 1, 1, false); 1274 INSN(stpq, 0b10, 0b101, 1, 0, false); 1275 INSN(ldpq, 0b10, 0b101, 1, 1, false); 1276 1277 #undef INSN 1278 1279 // Load/store register (all modes) 1280 void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) { 1281 starti; 1282 1283 f(V, 26); // general reg? 1284 zrf(Rt, 0); 1285 1286 // Encoding for literal loads is done here (rather than pushed 1287 // down into Address::encode) because the encoding of this 1288 // instruction is too different from all of the other forms to 1289 // make it worth sharing. 1290 if (adr.getMode() == Address::literal) { 1291 assert(size == 0b10 || size == 0b11, "bad operand size in ldr"); 1292 assert(op == 0b01, "literal form can only be used with loads"); 1293 f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24); 1294 long offset = (adr.target() - pc()) >> 2; 1295 sf(offset, 23, 5); 1296 code_section()->relocate(pc(), adr.rspec()); 1297 return; 1298 } 1299 1300 f(size, 31, 30); 1301 f(op, 23, 22); // str 1302 adr.encode(current); 1303 } 1304 1305 #define INSN(NAME, size, op) \ 1306 void NAME(Register Rt, const Address &adr) { \ 1307 ld_st2(Rt, adr, size, op); \ 1308 } \ 1309 1310 INSN(str, 0b11, 0b00); 1311 INSN(strw, 0b10, 0b00); 1312 INSN(strb, 0b00, 0b00); 1313 INSN(strh, 0b01, 0b00); 1314 1315 INSN(ldr, 0b11, 0b01); 1316 INSN(ldrw, 0b10, 0b01); 1317 INSN(ldrb, 0b00, 0b01); 1318 INSN(ldrh, 0b01, 0b01); 1319 1320 INSN(ldrsb, 0b00, 0b10); 1321 INSN(ldrsbw, 0b00, 0b11); 1322 INSN(ldrsh, 0b01, 0b10); 1323 INSN(ldrshw, 0b01, 0b11); 1324 INSN(ldrsw, 0b10, 0b10); 1325 1326 #undef INSN 1327 1328 #define INSN(NAME, size, op) \ 1329 void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \ 1330 ld_st2((Register)pfop, adr, size, op); \ 1331 } 1332 1333 INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with 1334 // writeback modes, but the assembler 1335 // doesn't enfore that. 1336 1337 #undef INSN 1338 1339 #define INSN(NAME, size, op) \ 1340 void NAME(FloatRegister Rt, const Address &adr) { \ 1341 ld_st2((Register)Rt, adr, size, op, 1); \ 1342 } 1343 1344 INSN(strd, 0b11, 0b00); 1345 INSN(strs, 0b10, 0b00); 1346 INSN(ldrd, 0b11, 0b01); 1347 INSN(ldrs, 0b10, 0b01); 1348 INSN(strq, 0b00, 0b10); 1349 INSN(ldrq, 0x00, 0b11); 1350 1351 #undef INSN 1352 1353 enum shift_kind { LSL, LSR, ASR, ROR }; 1354 1355 void op_shifted_reg(unsigned decode, 1356 enum shift_kind kind, unsigned shift, 1357 unsigned size, unsigned op) { 1358 f(size, 31); 1359 f(op, 30, 29); 1360 f(decode, 28, 24); 1361 f(shift, 15, 10); 1362 f(kind, 23, 22); 1363 } 1364 1365 // Logical (shifted register) 1366 #define INSN(NAME, size, op, N) \ 1367 void NAME(Register Rd, Register Rn, Register Rm, \ 1368 enum shift_kind kind = LSL, unsigned shift = 0) { \ 1369 starti; \ 1370 f(N, 21); \ 1371 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \ 1372 op_shifted_reg(0b01010, kind, shift, size, op); \ 1373 } 1374 1375 INSN(andr, 1, 0b00, 0); 1376 INSN(orr, 1, 0b01, 0); 1377 INSN(eor, 1, 0b10, 0); 1378 INSN(ands, 1, 0b11, 0); 1379 INSN(andw, 0, 0b00, 0); 1380 INSN(orrw, 0, 0b01, 0); 1381 INSN(eorw, 0, 0b10, 0); 1382 INSN(andsw, 0, 0b11, 0); 1383 1384 INSN(bic, 1, 0b00, 1); 1385 INSN(orn, 1, 0b01, 1); 1386 INSN(eon, 1, 0b10, 1); 1387 INSN(bics, 1, 0b11, 1); 1388 INSN(bicw, 0, 0b00, 1); 1389 INSN(ornw, 0, 0b01, 1); 1390 INSN(eonw, 0, 0b10, 1); 1391 INSN(bicsw, 0, 0b11, 1); 1392 1393 #undef INSN 1394 1395 // Add/subtract (shifted register) 1396 #define INSN(NAME, size, op) \ 1397 void NAME(Register Rd, Register Rn, Register Rm, \ 1398 enum shift_kind kind, unsigned shift = 0) { \ 1399 starti; \ 1400 f(0, 21); \ 1401 assert_cond(kind != ROR); \ 1402 zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \ 1403 op_shifted_reg(0b01011, kind, shift, size, op); \ 1404 } 1405 1406 INSN(add, 1, 0b000); 1407 INSN(sub, 1, 0b10); 1408 INSN(addw, 0, 0b000); 1409 INSN(subw, 0, 0b10); 1410 1411 INSN(adds, 1, 0b001); 1412 INSN(subs, 1, 0b11); 1413 INSN(addsw, 0, 0b001); 1414 INSN(subsw, 0, 0b11); 1415 1416 #undef INSN 1417 1418 // Add/subtract (extended register) 1419 #define INSN(NAME, op) \ 1420 void NAME(Register Rd, Register Rn, Register Rm, \ 1421 ext::operation option, int amount = 0) { \ 1422 starti; \ 1423 zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \ 1424 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \ 1425 } 1426 1427 void add_sub_extended_reg(unsigned op, unsigned decode, 1428 Register Rd, Register Rn, Register Rm, 1429 unsigned opt, ext::operation option, unsigned imm) { 1430 guarantee(imm <= 4, "shift amount must be < 4"); 1431 f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21); 1432 f(option, 15, 13), f(imm, 12, 10); 1433 } 1434 1435 INSN(addw, 0b000); 1436 INSN(subw, 0b010); 1437 INSN(add, 0b100); 1438 INSN(sub, 0b110); 1439 1440 #undef INSN 1441 1442 #define INSN(NAME, op) \ 1443 void NAME(Register Rd, Register Rn, Register Rm, \ 1444 ext::operation option, int amount = 0) { \ 1445 starti; \ 1446 zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \ 1447 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \ 1448 } 1449 1450 INSN(addsw, 0b001); 1451 INSN(subsw, 0b011); 1452 INSN(adds, 0b101); 1453 INSN(subs, 0b111); 1454 1455 #undef INSN 1456 1457 // Aliases for short forms of add and sub 1458 #define INSN(NAME) \ 1459 void NAME(Register Rd, Register Rn, Register Rm) { \ 1460 if (Rd == sp || Rn == sp) \ 1461 NAME(Rd, Rn, Rm, ext::uxtx); \ 1462 else \ 1463 NAME(Rd, Rn, Rm, LSL); \ 1464 } 1465 1466 INSN(addw); 1467 INSN(subw); 1468 INSN(add); 1469 INSN(sub); 1470 1471 INSN(addsw); 1472 INSN(subsw); 1473 INSN(adds); 1474 INSN(subs); 1475 1476 #undef INSN 1477 1478 // Add/subtract (with carry) 1479 void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) { 1480 starti; 1481 f(op, 31, 29); 1482 f(0b11010000, 28, 21); 1483 f(0b000000, 15, 10); 1484 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); 1485 } 1486 1487 #define INSN(NAME, op) \ 1488 void NAME(Register Rd, Register Rn, Register Rm) { \ 1489 add_sub_carry(op, Rd, Rn, Rm); \ 1490 } 1491 1492 INSN(adcw, 0b000); 1493 INSN(adcsw, 0b001); 1494 INSN(sbcw, 0b010); 1495 INSN(sbcsw, 0b011); 1496 INSN(adc, 0b100); 1497 INSN(adcs, 0b101); 1498 INSN(sbc,0b110); 1499 INSN(sbcs, 0b111); 1500 1501 #undef INSN 1502 1503 // Conditional compare (both kinds) 1504 void conditional_compare(unsigned op, int o2, int o3, 1505 Register Rn, unsigned imm5, unsigned nzcv, 1506 unsigned cond) { 1507 f(op, 31, 29); 1508 f(0b11010010, 28, 21); 1509 f(cond, 15, 12); 1510 f(o2, 10); 1511 f(o3, 4); 1512 f(nzcv, 3, 0); 1513 f(imm5, 20, 16), rf(Rn, 5); 1514 } 1515 1516 #define INSN(NAME, op) \ 1517 void NAME(Register Rn, Register Rm, int imm, Condition cond) { \ 1518 starti; \ 1519 f(0, 11); \ 1520 conditional_compare(op, 0, 0, Rn, (uintptr_t)Rm, imm, cond); \ 1521 } \ 1522 \ 1523 void NAME(Register Rn, int imm5, int imm, Condition cond) { \ 1524 starti; \ 1525 f(1, 11); \ 1526 conditional_compare(op, 0, 0, Rn, imm5, imm, cond); \ 1527 } 1528 1529 INSN(ccmnw, 0b001); 1530 INSN(ccmpw, 0b011); 1531 INSN(ccmn, 0b101); 1532 INSN(ccmp, 0b111); 1533 1534 #undef INSN 1535 1536 // Conditional select 1537 void conditional_select(unsigned op, unsigned op2, 1538 Register Rd, Register Rn, Register Rm, 1539 unsigned cond) { 1540 starti; 1541 f(op, 31, 29); 1542 f(0b11010100, 28, 21); 1543 f(cond, 15, 12); 1544 f(op2, 11, 10); 1545 zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0); 1546 } 1547 1548 #define INSN(NAME, op, op2) \ 1549 void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \ 1550 conditional_select(op, op2, Rd, Rn, Rm, cond); \ 1551 } 1552 1553 INSN(cselw, 0b000, 0b00); 1554 INSN(csincw, 0b000, 0b01); 1555 INSN(csinvw, 0b010, 0b00); 1556 INSN(csnegw, 0b010, 0b01); 1557 INSN(csel, 0b100, 0b00); 1558 INSN(csinc, 0b100, 0b01); 1559 INSN(csinv, 0b110, 0b00); 1560 INSN(csneg, 0b110, 0b01); 1561 1562 #undef INSN 1563 1564 // Data processing 1565 void data_processing(unsigned op29, unsigned opcode, 1566 Register Rd, Register Rn) { 1567 f(op29, 31, 29), f(0b11010110, 28, 21); 1568 f(opcode, 15, 10); 1569 rf(Rn, 5), rf(Rd, 0); 1570 } 1571 1572 // (1 source) 1573 #define INSN(NAME, op29, opcode2, opcode) \ 1574 void NAME(Register Rd, Register Rn) { \ 1575 starti; \ 1576 f(opcode2, 20, 16); \ 1577 data_processing(op29, opcode, Rd, Rn); \ 1578 } 1579 1580 INSN(rbitw, 0b010, 0b00000, 0b00000); 1581 INSN(rev16w, 0b010, 0b00000, 0b00001); 1582 INSN(revw, 0b010, 0b00000, 0b00010); 1583 INSN(clzw, 0b010, 0b00000, 0b00100); 1584 INSN(clsw, 0b010, 0b00000, 0b00101); 1585 1586 INSN(rbit, 0b110, 0b00000, 0b00000); 1587 INSN(rev16, 0b110, 0b00000, 0b00001); 1588 INSN(rev32, 0b110, 0b00000, 0b00010); 1589 INSN(rev, 0b110, 0b00000, 0b00011); 1590 INSN(clz, 0b110, 0b00000, 0b00100); 1591 INSN(cls, 0b110, 0b00000, 0b00101); 1592 1593 #undef INSN 1594 1595 // (2 sources) 1596 #define INSN(NAME, op29, opcode) \ 1597 void NAME(Register Rd, Register Rn, Register Rm) { \ 1598 starti; \ 1599 rf(Rm, 16); \ 1600 data_processing(op29, opcode, Rd, Rn); \ 1601 } 1602 1603 INSN(udivw, 0b000, 0b000010); 1604 INSN(sdivw, 0b000, 0b000011); 1605 INSN(lslvw, 0b000, 0b001000); 1606 INSN(lsrvw, 0b000, 0b001001); 1607 INSN(asrvw, 0b000, 0b001010); 1608 INSN(rorvw, 0b000, 0b001011); 1609 1610 INSN(udiv, 0b100, 0b000010); 1611 INSN(sdiv, 0b100, 0b000011); 1612 INSN(lslv, 0b100, 0b001000); 1613 INSN(lsrv, 0b100, 0b001001); 1614 INSN(asrv, 0b100, 0b001010); 1615 INSN(rorv, 0b100, 0b001011); 1616 1617 #undef INSN 1618 1619 // (3 sources) 1620 void data_processing(unsigned op54, unsigned op31, unsigned o0, 1621 Register Rd, Register Rn, Register Rm, 1622 Register Ra) { 1623 starti; 1624 f(op54, 31, 29), f(0b11011, 28, 24); 1625 f(op31, 23, 21), f(o0, 15); 1626 zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0); 1627 } 1628 1629 #define INSN(NAME, op54, op31, o0) \ 1630 void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \ 1631 data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \ 1632 } 1633 1634 INSN(maddw, 0b000, 0b000, 0); 1635 INSN(msubw, 0b000, 0b000, 1); 1636 INSN(madd, 0b100, 0b000, 0); 1637 INSN(msub, 0b100, 0b000, 1); 1638 INSN(smaddl, 0b100, 0b001, 0); 1639 INSN(smsubl, 0b100, 0b001, 1); 1640 INSN(umaddl, 0b100, 0b101, 0); 1641 INSN(umsubl, 0b100, 0b101, 1); 1642 1643 #undef INSN 1644 1645 #define INSN(NAME, op54, op31, o0) \ 1646 void NAME(Register Rd, Register Rn, Register Rm) { \ 1647 data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \ 1648 } 1649 1650 INSN(smulh, 0b100, 0b010, 0); 1651 INSN(umulh, 0b100, 0b110, 0); 1652 1653 #undef INSN 1654 1655 // Floating-point data-processing (1 source) 1656 void data_processing(unsigned op31, unsigned type, unsigned opcode, 1657 FloatRegister Vd, FloatRegister Vn) { 1658 starti; 1659 f(op31, 31, 29); 1660 f(0b11110, 28, 24); 1661 f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10); 1662 rf(Vn, 5), rf(Vd, 0); 1663 } 1664 1665 #define INSN(NAME, op31, type, opcode) \ 1666 void NAME(FloatRegister Vd, FloatRegister Vn) { \ 1667 data_processing(op31, type, opcode, Vd, Vn); \ 1668 } 1669 1670 private: 1671 INSN(i_fmovs, 0b000, 0b00, 0b000000); 1672 public: 1673 INSN(fabss, 0b000, 0b00, 0b000001); 1674 INSN(fnegs, 0b000, 0b00, 0b000010); 1675 INSN(fsqrts, 0b000, 0b00, 0b000011); 1676 INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision 1677 1678 private: 1679 INSN(i_fmovd, 0b000, 0b01, 0b000000); 1680 public: 1681 INSN(fabsd, 0b000, 0b01, 0b000001); 1682 INSN(fnegd, 0b000, 0b01, 0b000010); 1683 INSN(fsqrtd, 0b000, 0b01, 0b000011); 1684 INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision 1685 1686 void fmovd(FloatRegister Vd, FloatRegister Vn) { 1687 assert(Vd != Vn, "should be"); 1688 i_fmovd(Vd, Vn); 1689 } 1690 1691 void fmovs(FloatRegister Vd, FloatRegister Vn) { 1692 assert(Vd != Vn, "should be"); 1693 i_fmovs(Vd, Vn); 1694 } 1695 1696 #undef INSN 1697 1698 // Floating-point data-processing (2 source) 1699 void data_processing(unsigned op31, unsigned type, unsigned opcode, 1700 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { 1701 starti; 1702 f(op31, 31, 29); 1703 f(0b11110, 28, 24); 1704 f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10); 1705 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); 1706 } 1707 1708 #define INSN(NAME, op31, type, opcode) \ 1709 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \ 1710 data_processing(op31, type, opcode, Vd, Vn, Vm); \ 1711 } 1712 1713 INSN(fmuls, 0b000, 0b00, 0b0000); 1714 INSN(fdivs, 0b000, 0b00, 0b0001); 1715 INSN(fadds, 0b000, 0b00, 0b0010); 1716 INSN(fsubs, 0b000, 0b00, 0b0011); 1717 INSN(fnmuls, 0b000, 0b00, 0b1000); 1718 1719 INSN(fmuld, 0b000, 0b01, 0b0000); 1720 INSN(fdivd, 0b000, 0b01, 0b0001); 1721 INSN(faddd, 0b000, 0b01, 0b0010); 1722 INSN(fsubd, 0b000, 0b01, 0b0011); 1723 INSN(fnmuld, 0b000, 0b01, 0b1000); 1724 1725 #undef INSN 1726 1727 // Floating-point data-processing (3 source) 1728 void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0, 1729 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, 1730 FloatRegister Va) { 1731 starti; 1732 f(op31, 31, 29); 1733 f(0b11111, 28, 24); 1734 f(type, 23, 22), f(o1, 21), f(o0, 15); 1735 rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0); 1736 } 1737 1738 #define INSN(NAME, op31, type, o1, o0) \ 1739 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \ 1740 FloatRegister Va) { \ 1741 data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \ 1742 } 1743 1744 INSN(fmadds, 0b000, 0b00, 0, 0); 1745 INSN(fmsubs, 0b000, 0b00, 0, 1); 1746 INSN(fnmadds, 0b000, 0b00, 1, 0); 1747 INSN(fnmsubs, 0b000, 0b00, 1, 1); 1748 1749 INSN(fmaddd, 0b000, 0b01, 0, 0); 1750 INSN(fmsubd, 0b000, 0b01, 0, 1); 1751 INSN(fnmaddd, 0b000, 0b01, 1, 0); 1752 INSN(fnmsub, 0b000, 0b01, 1, 1); 1753 1754 #undef INSN 1755 1756 // Floating-point conditional select 1757 void fp_conditional_select(unsigned op31, unsigned type, 1758 unsigned op1, unsigned op2, 1759 Condition cond, FloatRegister Vd, 1760 FloatRegister Vn, FloatRegister Vm) { 1761 starti; 1762 f(op31, 31, 29); 1763 f(0b11110, 28, 24); 1764 f(type, 23, 22); 1765 f(op1, 21, 21); 1766 f(op2, 11, 10); 1767 f(cond, 15, 12); 1768 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); 1769 } 1770 1771 #define INSN(NAME, op31, type, op1, op2) \ 1772 void NAME(FloatRegister Vd, FloatRegister Vn, \ 1773 FloatRegister Vm, Condition cond) { \ 1774 fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \ 1775 } 1776 1777 INSN(fcsels, 0b000, 0b00, 0b1, 0b11); 1778 INSN(fcseld, 0b000, 0b01, 0b1, 0b11); 1779 1780 #undef INSN 1781 1782 // Floating-point<->integer conversions 1783 void float_int_convert(unsigned op31, unsigned type, 1784 unsigned rmode, unsigned opcode, 1785 Register Rd, Register Rn) { 1786 starti; 1787 f(op31, 31, 29); 1788 f(0b11110, 28, 24); 1789 f(type, 23, 22), f(1, 21), f(rmode, 20, 19); 1790 f(opcode, 18, 16), f(0b000000, 15, 10); 1791 zrf(Rn, 5), zrf(Rd, 0); 1792 } 1793 1794 #define INSN(NAME, op31, type, rmode, opcode) \ 1795 void NAME(Register Rd, FloatRegister Vn) { \ 1796 float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \ 1797 } 1798 1799 INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000); 1800 INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000); 1801 INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000); 1802 INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000); 1803 1804 INSN(fmovs, 0b000, 0b00, 0b00, 0b110); 1805 INSN(fmovd, 0b100, 0b01, 0b00, 0b110); 1806 1807 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110); 1808 1809 #undef INSN 1810 1811 #define INSN(NAME, op31, type, rmode, opcode) \ 1812 void NAME(FloatRegister Vd, Register Rn) { \ 1813 float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \ 1814 } 1815 1816 INSN(fmovs, 0b000, 0b00, 0b00, 0b111); 1817 INSN(fmovd, 0b100, 0b01, 0b00, 0b111); 1818 1819 INSN(scvtfws, 0b000, 0b00, 0b00, 0b010); 1820 INSN(scvtfs, 0b100, 0b00, 0b00, 0b010); 1821 INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010); 1822 INSN(scvtfd, 0b100, 0b01, 0b00, 0b010); 1823 1824 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111); 1825 1826 #undef INSN 1827 1828 // Floating-point compare 1829 void float_compare(unsigned op31, unsigned type, 1830 unsigned op, unsigned op2, 1831 FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) { 1832 starti; 1833 f(op31, 31, 29); 1834 f(0b11110, 28, 24); 1835 f(type, 23, 22), f(1, 21); 1836 f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0); 1837 rf(Vn, 5), rf(Vm, 16); 1838 } 1839 1840 1841 #define INSN(NAME, op31, type, op, op2) \ 1842 void NAME(FloatRegister Vn, FloatRegister Vm) { \ 1843 float_compare(op31, type, op, op2, Vn, Vm); \ 1844 } 1845 1846 #define INSN1(NAME, op31, type, op, op2) \ 1847 void NAME(FloatRegister Vn, double d) { \ 1848 assert_cond(d == 0.0); \ 1849 float_compare(op31, type, op, op2, Vn); \ 1850 } 1851 1852 INSN(fcmps, 0b000, 0b00, 0b00, 0b00000); 1853 INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000); 1854 // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000); 1855 // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000); 1856 1857 INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000); 1858 INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000); 1859 // INSN(fcmped, 0b000, 0b01, 0b00, 0b10000); 1860 // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000); 1861 1862 #undef INSN 1863 #undef INSN1 1864 1865 // Floating-point Move (immediate) 1866 private: 1867 unsigned pack(double value); 1868 1869 void fmov_imm(FloatRegister Vn, double value, unsigned size) { 1870 starti; 1871 f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21); 1872 f(pack(value), 20, 13), f(0b10000000, 12, 5); 1873 rf(Vn, 0); 1874 } 1875 1876 public: 1877 1878 void fmovs(FloatRegister Vn, double value) { 1879 if (value) 1880 fmov_imm(Vn, value, 0b00); 1881 else 1882 fmovs(Vn, zr); 1883 } 1884 void fmovd(FloatRegister Vn, double value) { 1885 if (value) 1886 fmov_imm(Vn, value, 0b01); 1887 else 1888 fmovd(Vn, zr); 1889 } 1890 1891 /* SIMD extensions 1892 * 1893 * We just use FloatRegister in the following. They are exactly the same 1894 * as SIMD registers. 1895 */ 1896 public: 1897 1898 enum SIMD_Arrangement { 1899 T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D 1900 }; 1901 1902 enum SIMD_RegVariant { 1903 B, H, S, D, Q 1904 }; 1905 1906 #define INSN(NAME, op) \ 1907 void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \ 1908 ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \ 1909 } \ 1910 1911 INSN(ldr, 1); 1912 INSN(str, 0); 1913 1914 #undef INSN 1915 1916 private: 1917 1918 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) { 1919 starti; 1920 f(0,31), f((int)T & 1, 30); 1921 f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12); 1922 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0); 1923 } 1924 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, 1925 int imm, int op1, int op2) { 1926 starti; 1927 f(0,31), f((int)T & 1, 30); 1928 f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12); 1929 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0); 1930 } 1931 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, 1932 Register Xm, int op1, int op2) { 1933 starti; 1934 f(0,31), f((int)T & 1, 30); 1935 f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12); 1936 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0); 1937 } 1938 1939 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2) { 1940 switch (a.getMode()) { 1941 case Address::base_plus_offset: 1942 guarantee(a.offset() == 0, "no offset allowed here"); 1943 ld_st(Vt, T, a.base(), op1, op2); 1944 break; 1945 case Address::post: 1946 ld_st(Vt, T, a.base(), a.offset(), op1, op2); 1947 break; 1948 case Address::base_plus_offset_reg: 1949 ld_st(Vt, T, a.base(), a.index(), op1, op2); 1950 break; 1951 default: 1952 ShouldNotReachHere(); 1953 } 1954 } 1955 1956 public: 1957 1958 #define INSN1(NAME, op1, op2) \ 1959 void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \ 1960 ld_st(Vt, T, a, op1, op2); \ 1961 } 1962 1963 #define INSN2(NAME, op1, op2) \ 1964 void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \ 1965 assert(Vt->successor() == Vt2, "Registers must be ordered"); \ 1966 ld_st(Vt, T, a, op1, op2); \ 1967 } 1968 1969 #define INSN3(NAME, op1, op2) \ 1970 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \ 1971 SIMD_Arrangement T, const Address &a) { \ 1972 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \ 1973 "Registers must be ordered"); \ 1974 ld_st(Vt, T, a, op1, op2); \ 1975 } 1976 1977 #define INSN4(NAME, op1, op2) \ 1978 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \ 1979 FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \ 1980 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \ 1981 Vt3->successor() == Vt4, "Registers must be ordered"); \ 1982 ld_st(Vt, T, a, op1, op2); \ 1983 } 1984 1985 INSN1(ld1, 0b001100010, 0b0111); 1986 INSN2(ld1, 0b001100010, 0b1010); 1987 INSN3(ld1, 0b001100010, 0b0110); 1988 INSN4(ld1, 0b001100010, 0b0010); 1989 1990 INSN2(ld2, 0b001100010, 0b1000); 1991 INSN3(ld3, 0b001100010, 0b0100); 1992 INSN4(ld4, 0b001100010, 0b0000); 1993 1994 INSN1(st1, 0b001100000, 0b0111); 1995 INSN2(st1, 0b001100000, 0b1010); 1996 INSN3(st1, 0b001100000, 0b0110); 1997 INSN4(st1, 0b001100000, 0b0010); 1998 1999 INSN2(st2, 0b001100000, 0b1000); 2000 INSN3(st3, 0b001100000, 0b0100); 2001 INSN4(st4, 0b001100000, 0b0000); 2002 2003 INSN1(ld1r, 0b001101010, 0b1100); 2004 INSN2(ld2r, 0b001101011, 0b1100); 2005 INSN3(ld3r, 0b001101010, 0b1110); 2006 INSN4(ld4r, 0b001101011, 0b1110); 2007 2008 #undef INSN1 2009 #undef INSN2 2010 #undef INSN3 2011 #undef INSN4 2012 2013 #define INSN(NAME, opc) \ 2014 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2015 starti; \ 2016 assert(T == T8B || T == T16B, "must be T8B or T16B"); \ 2017 f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \ 2018 rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2019 } 2020 2021 INSN(eor, 0b101110001); 2022 INSN(orr, 0b001110101); 2023 INSN(andr, 0b001110001); 2024 INSN(bic, 0b001110011); 2025 INSN(bif, 0b101110111); 2026 INSN(bit, 0b101110101); 2027 INSN(bsl, 0b101110011); 2028 INSN(orn, 0b001110111); 2029 2030 #undef INSN 2031 2032 #define INSN(NAME, opc, opc2) \ 2033 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2034 starti; \ 2035 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \ 2036 f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \ 2037 rf(Vn, 5), rf(Vd, 0); \ 2038 } 2039 2040 INSN(addv, 0, 0b100001); 2041 INSN(subv, 1, 0b100001); 2042 INSN(mulv, 0, 0b100111); 2043 INSN(sshl, 0, 0b010001); 2044 INSN(ushl, 1, 0b010001); 2045 2046 #undef INSN 2047 2048 #define INSN(NAME, opc, opc2) \ 2049 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ 2050 starti; \ 2051 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \ 2052 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \ 2053 rf(Vn, 5), rf(Vd, 0); \ 2054 } 2055 2056 INSN(absr, 0, 0b100000101110); 2057 INSN(negr, 1, 0b100000101110); 2058 INSN(notr, 1, 0b100000010110); 2059 INSN(addv, 0, 0b110001101110); 2060 INSN(cls, 0, 0b100000010010); 2061 INSN(clz, 1, 0b100000010010); 2062 INSN(cnt, 0, 0b100000010110); 2063 2064 #undef INSN 2065 2066 #define INSN(NAME, op0, cmode0) \ 2067 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \ 2068 unsigned cmode = cmode0; \ 2069 unsigned op = op0; \ 2070 starti; \ 2071 assert(lsl == 0 || \ 2072 ((T == T4H || T == T8H) && lsl == 8) || \ 2073 ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \ 2074 cmode |= lsl >> 2; \ 2075 if (T == T4H || T == T8H) cmode |= 0b1000; \ 2076 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \ 2077 assert(op == 0 && cmode0 == 0, "must be MOVI"); \ 2078 cmode = 0b1110; \ 2079 if (T == T1D || T == T2D) op = 1; \ 2080 } \ 2081 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \ 2082 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \ 2083 rf(Vd, 0); \ 2084 } 2085 2086 INSN(movi, 0, 0); 2087 INSN(orri, 0, 1); 2088 INSN(mvni, 1, 0); 2089 INSN(bici, 1, 1); 2090 2091 #undef INSN 2092 2093 #define INSN(NAME, op1, op2, op3) \ 2094 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2095 starti; \ 2096 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \ 2097 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \ 2098 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2099 } 2100 2101 INSN(fadd, 0, 0, 0b110101); 2102 INSN(fdiv, 1, 0, 0b111111); 2103 INSN(fmul, 1, 0, 0b110111); 2104 INSN(fsub, 0, 1, 0b110101); 2105 2106 #undef INSN 2107 2108 #define INSN(NAME, opc) \ 2109 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2110 starti; \ 2111 assert(T == T4S, "arrangement must be T4S"); \ 2112 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2113 } 2114 2115 INSN(sha1c, 0b000000); 2116 INSN(sha1m, 0b001000); 2117 INSN(sha1p, 0b000100); 2118 INSN(sha1su0, 0b001100); 2119 INSN(sha256h2, 0b010100); 2120 INSN(sha256h, 0b010000); 2121 INSN(sha256su1, 0b011000); 2122 2123 #undef INSN 2124 2125 #define INSN(NAME, opc) \ 2126 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ 2127 starti; \ 2128 assert(T == T4S, "arrangement must be T4S"); \ 2129 f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2130 } 2131 2132 INSN(sha1h, 0b000010); 2133 INSN(sha1su1, 0b000110); 2134 INSN(sha256su0, 0b001010); 2135 2136 #undef INSN 2137 2138 #define INSN(NAME, opc) \ 2139 void NAME(FloatRegister Vd, FloatRegister Vn) { \ 2140 starti; \ 2141 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \ 2142 } 2143 2144 INSN(aese, 0b0100111000101000010010); 2145 INSN(aesd, 0b0100111000101000010110); 2146 INSN(aesmc, 0b0100111000101000011010); 2147 INSN(aesimc, 0b0100111000101000011110); 2148 2149 #undef INSN 2150 2151 void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) { 2152 starti; 2153 assert(T != Q, "invalid register variant"); 2154 f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15); 2155 f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0); 2156 } 2157 2158 void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) { 2159 starti; 2160 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21); 2161 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10); 2162 rf(Vn, 5), rf(Rd, 0); 2163 } 2164 2165 #define INSN(NAME, opc, opc2) \ 2166 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \ 2167 starti; \ 2168 /* The encodings for the immh:immb fields (bits 22:16) are \ 2169 * 0001 xxx 8B/16B, shift = xxx \ 2170 * 001x xxx 4H/8H, shift = xxxx \ 2171 * 01xx xxx 2S/4S, shift = xxxxx \ 2172 * 1xxx xxx 1D/2D, shift = xxxxxx (1D is RESERVED) \ 2173 */ \ 2174 assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \ 2175 f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \ 2176 f((1 << ((T>>1)+3))|shift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2177 } 2178 2179 INSN(shl, 0, 0b010101); 2180 INSN(sshr, 0, 0b000001); 2181 INSN(ushr, 1, 0b000001); 2182 2183 #undef INSN 2184 2185 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { 2186 starti; 2187 /* The encodings for the immh:immb fields (bits 22:16) are 2188 * 0001 xxx 8H, 8B/16b shift = xxx 2189 * 001x xxx 4S, 4H/8H shift = xxxx 2190 * 01xx xxx 2D, 2S/4S shift = xxxxx 2191 * 1xxx xxx RESERVED 2192 */ 2193 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement"); 2194 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value"); 2195 f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16); 2196 f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0); 2197 } 2198 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { 2199 ushll(Vd, Ta, Vn, Tb, shift); 2200 } 2201 2202 void uzp1(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T, int op = 0){ 2203 starti; 2204 f(0, 31), f((T & 0x1), 30), f(0b001110, 29, 24), f((T >> 1), 23, 22), f(0, 21); 2205 rf(Vm, 16), f(0, 15), f(op, 14), f(0b0110, 13, 10), rf(Vn, 5), rf(Vd, 0); 2206 } 2207 void uzp2(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T){ 2208 uzp1(Vd, Vn, Vm, T, 1); 2209 } 2210 2211 // Move from general purpose register 2212 // mov Vd.T[index], Rn 2213 void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) { 2214 starti; 2215 f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); 2216 f(0b000111, 15, 10), rf(Xn, 5), rf(Vd, 0); 2217 } 2218 2219 // Move to general purpose register 2220 // mov Rd, Vn.T[index] 2221 void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) { 2222 starti; 2223 f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21); 2224 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); 2225 f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0); 2226 } 2227 2228 // We do not handle the 1Q arrangement. 2229 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) { 2230 starti; 2231 assert(Ta == T8H && (Tb == T8B || Tb == T16B), "Invalid Size specifier"); 2232 f(0, 31), f(Tb & 1, 30), f(0b001110001, 29, 21), rf(Vm, 16), f(0b111000, 15, 10); 2233 rf(Vn, 5), rf(Vd, 0); 2234 } 2235 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) { 2236 pmull(Vd, Ta, Vn, Vm, Tb); 2237 } 2238 2239 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) { 2240 starti; 2241 int size_b = (int)Tb >> 1; 2242 int size_a = (int)Ta >> 1; 2243 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier"); 2244 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22); 2245 f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0); 2246 } 2247 2248 void rev32(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) 2249 { 2250 starti; 2251 assert(T <= T8H, "must be one of T8B, T16B, T4H, T8H"); 2252 f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24); 2253 f(T <= T16B ? 0b00 : 0b01, 23, 22), f(0b100000000010, 21, 10); 2254 rf(Vn, 5), rf(Vd, 0); 2255 } 2256 2257 void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs) 2258 { 2259 starti; 2260 assert(T != T1D, "reserved encoding"); 2261 f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21); 2262 f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), rf(Xs, 5), rf(Vd, 0); 2263 } 2264 2265 void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0) 2266 { 2267 starti; 2268 assert(T != T1D, "reserved encoding"); 2269 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21); 2270 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); 2271 f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0); 2272 } 2273 2274 // CRC32 instructions 2275 #define INSN(NAME, c, sf, sz) \ 2276 void NAME(Register Rd, Register Rn, Register Rm) { \ 2277 starti; \ 2278 f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12); \ 2279 f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \ 2280 } 2281 2282 INSN(crc32b, 0, 0, 0b00); 2283 INSN(crc32h, 0, 0, 0b01); 2284 INSN(crc32w, 0, 0, 0b10); 2285 INSN(crc32x, 0, 1, 0b11); 2286 INSN(crc32cb, 1, 0, 0b00); 2287 INSN(crc32ch, 1, 0, 0b01); 2288 INSN(crc32cw, 1, 0, 0b10); 2289 INSN(crc32cx, 1, 1, 0b11); 2290 2291 #undef INSN 2292 2293 2294 /* Simulator extensions to the ISA 2295 2296 haltsim 2297 2298 takes no arguments, causes the sim to enter a debug break and then 2299 return from the simulator run() call with STATUS_HALT? The linking 2300 code will call fatal() when it sees STATUS_HALT. 2301 2302 blrt Xn, Wm 2303 blrt Xn, #gpargs, #fpargs, #type 2304 Xn holds the 64 bit x86 branch_address 2305 call format is encoded either as immediate data in the call 2306 or in register Wm. In the latter case 2307 Wm[13..6] = #gpargs, 2308 Wm[5..2] = #fpargs, 2309 Wm[1,0] = #type 2310 2311 calls the x86 code address 'branch_address' supplied in Xn passing 2312 arguments taken from the general and floating point registers according 2313 to the supplied counts 'gpargs' and 'fpargs'. may return a result in r0 2314 or v0 according to the the return type #type' where 2315 2316 address branch_address; 2317 uimm4 gpargs; 2318 uimm4 fpargs; 2319 enum ReturnType type; 2320 2321 enum ReturnType 2322 { 2323 void_ret = 0, 2324 int_ret = 1, 2325 long_ret = 1, 2326 obj_ret = 1, // i.e. same as long 2327 float_ret = 2, 2328 double_ret = 3 2329 } 2330 2331 notify 2332 2333 notifies the simulator of a transfer of control. instr[14:0] 2334 identifies the type of change of control. 2335 2336 0 ==> initial entry to a method. 2337 2338 1 ==> return into a method from a submethod call. 2339 2340 2 ==> exit out of Java method code. 2341 2342 3 ==> start execution for a new bytecode. 2343 2344 in cases 1 and 2 the simulator is expected to use a JVM callback to 2345 identify the name of the specific method being executed. in case 4 2346 the simulator is expected to use a JVM callback to identify the 2347 bytecode index. 2348 2349 Instruction encodings 2350 --------------------- 2351 2352 These are encoded in the space with instr[28:25] = 00 which is 2353 unallocated. Encodings are 2354 2355 10987654321098765432109876543210 2356 PSEUDO_HALT = 0x11100000000000000000000000000000 2357 PSEUDO_BLRT = 0x11000000000000000_______________ 2358 PSEUDO_BLRTR = 0x1100000000000000100000__________ 2359 PSEUDO_NOTIFY = 0x10100000000000000_______________ 2360 2361 instr[31,29] = op1 : 111 ==> HALT, 110 ==> BLRT/BLRTR, 101 ==> NOTIFY 2362 2363 for BLRT 2364 instr[14,11] = #gpargs, instr[10,7] = #fpargs 2365 instr[6,5] = #type, instr[4,0] = Rn 2366 for BLRTR 2367 instr[9,5] = Rm, instr[4,0] = Rn 2368 for NOTIFY 2369 instr[14:0] = type : 0 ==> entry, 1 ==> reentry, 2 ==> exit, 3 ==> bcstart 2370 */ 2371 2372 enum NotifyType { method_entry, method_reentry, method_exit, bytecode_start }; 2373 2374 virtual void notify(int type) { 2375 if (UseBuiltinSim) { 2376 starti; 2377 // 109 2378 f(0b101, 31, 29); 2379 // 87654321098765 2380 f(0b00000000000000, 28, 15); 2381 f(type, 14, 0); 2382 } 2383 } 2384 2385 void blrt(Register Rn, int gpargs, int fpargs, int type) { 2386 if (UseBuiltinSim) { 2387 starti; 2388 f(0b110, 31 ,29); 2389 f(0b00, 28, 25); 2390 // 4321098765 2391 f(0b0000000000, 24, 15); 2392 f(gpargs, 14, 11); 2393 f(fpargs, 10, 7); 2394 f(type, 6, 5); 2395 rf(Rn, 0); 2396 } else { 2397 blr(Rn); 2398 } 2399 } 2400 2401 void blrt(Register Rn, Register Rm) { 2402 if (UseBuiltinSim) { 2403 starti; 2404 f(0b110, 31 ,29); 2405 f(0b00, 28, 25); 2406 // 4321098765 2407 f(0b0000000001, 24, 15); 2408 // 43210 2409 f(0b00000, 14, 10); 2410 rf(Rm, 5); 2411 rf(Rn, 0); 2412 } else { 2413 blr(Rn); 2414 } 2415 } 2416 2417 void haltsim() { 2418 starti; 2419 f(0b111, 31 ,29); 2420 f(0b00, 28, 27); 2421 // 654321098765432109876543210 2422 f(0b000000000000000000000000000, 26, 0); 2423 } 2424 2425 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 2426 } 2427 2428 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 2429 Register tmp, 2430 int offset) { 2431 ShouldNotCallThis(); 2432 return RegisterOrConstant(); 2433 } 2434 2435 // Stack overflow checking 2436 virtual void bang_stack_with_offset(int offset); 2437 2438 static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm); 2439 static bool operand_valid_for_add_sub_immediate(long imm); 2440 static bool operand_valid_for_float_immediate(double imm); 2441 2442 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); 2443 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); 2444 }; 2445 2446 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a, 2447 Assembler::Membar_mask_bits b) { 2448 return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b)); 2449 } 2450 2451 Instruction_aarch64::~Instruction_aarch64() { 2452 assem->emit(); 2453 } 2454 2455 #undef starti 2456 2457 // Invert a condition 2458 inline const Assembler::Condition operator~(const Assembler::Condition cond) { 2459 return Assembler::Condition(int(cond) ^ 1); 2460 } 2461 2462 class BiasedLockingCounters; 2463 2464 extern "C" void das(uint64_t start, int len); 2465 2466 #endif // CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP