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src/cpu/aarch64/vm/assembler_aarch64.hpp
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rev 8720 : 8131062: aarch64: add support for GHASH acceleration
Summary: Add support for GHASH using pmull
Reviewed-by: duke
Contributed-by: alexander.alexeev@caviumnetworks.com
*** 1894,1904 ****
* as SIMD registers.
*/
public:
enum SIMD_Arrangement {
! T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D
};
enum SIMD_RegVariant {
B, H, S, D, Q
};
--- 1894,1904 ----
* as SIMD registers.
*/
public:
enum SIMD_Arrangement {
! T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
};
enum SIMD_RegVariant {
B, H, S, D, Q
};
*** 2223,2240 ****
f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
}
- // We do not handle the 1Q arrangement.
void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
starti;
! assert(Ta == T8H && (Tb == T8B || Tb == T16B), "Invalid Size specifier");
! f(0, 31), f(Tb & 1, 30), f(0b001110001, 29, 21), rf(Vm, 16), f(0b111000, 15, 10);
! rf(Vn, 5), rf(Vd, 0);
}
void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
pmull(Vd, Ta, Vn, Vm, Tb);
}
void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
starti;
--- 2223,2242 ----
f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
}
void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
starti;
! assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
! (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
! int size = (Ta == T1Q) ? 0b11 : 0b00;
! f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
! f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
}
void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
+ assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
pmull(Vd, Ta, Vn, Vm, Tb);
}
void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
starti;
*** 2243,2261 ****
assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
}
- void rev32(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn)
- {
- starti;
- assert(T <= T8H, "must be one of T8B, T16B, T4H, T8H");
- f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24);
- f(T <= T16B ? 0b00 : 0b01, 23, 22), f(0b100000000010, 21, 10);
- rf(Vn, 5), rf(Vd, 0);
- }
-
void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
{
starti;
assert(T != T1D, "reserved encoding");
f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
--- 2245,2254 ----
*** 2288,2297 ****
--- 2281,2341 ----
INSN(crc32cw, 1, 0, 0b10);
INSN(crc32cx, 1, 1, 0b11);
#undef INSN
+ // Table vector lookup
+ #define INSN(NAME, op) \
+ void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \
+ starti; \
+ assert(T == T8B || T == T16B, "invalid arrangement"); \
+ assert(0 < registers && registers <= 4, "invalid number of registers"); \
+ f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \
+ f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \
+ }
+
+ INSN(tbl, 0);
+ INSN(tbx, 1);
+
+ #undef INSN
+
+ #define INSN(NAME, U, opcode) \
+ void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
+ starti; \
+ assert((ASSERTION), MSG); \
+ f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24); \
+ f((int)(T >> 1), 23, 22), f(0b10000, 21, 17), f(opcode, 16, 12); \
+ f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0); \
+ }
+
+ #define MSG "invalid arrangement"
+
+ #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
+ INSN(rev64, 0, 0b00000);
+ #undef ASSERTION
+
+ #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
+ INSN(rev32, 1, 0b00000);
+ #undef ASSERTION
+
+ #define ASSERTION (T == T8B || T == T16B)
+ INSN(rev16, 0, 0b00001);
+ #undef ASSERTION
+
+ #undef MSG
+
+ #undef INSN
+
+ void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
+ {
+ starti;
+ assert(T == T8B || T == T16B, "invalid arrangement");
+ assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
+ f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
+ rf(Vm, 16), f(0, 15), f(index, 14, 11);
+ f(0, 10), rf(Vn, 5), rf(Vd, 0);
+ }
/* Simulator extensions to the ISA
haltsim
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