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src/cpu/aarch64/vm/aarch64.ad

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rev 8690 : 8131358: aarch64: test compiler/loopopts/superword/ProdRed_Float.java fails when run with debug VM
Summary: fix typo in match rule in vsub2f
Reviewed-by: duke


14084   ins_pipe(pipe_class_default);
14085 %}
14086 
14087 instruct vsub2L(vecX dst, vecX src1, vecX src2)
14088 %{
14089   predicate(n->as_Vector()->length() == 2);
14090   match(Set dst (SubVL src1 src2));
14091   ins_cost(INSN_COST);
14092   format %{ "subv  $dst,$src1,$src2\t# vector (2L)" %}
14093   ins_encode %{
14094     __ subv(as_FloatRegister($dst$$reg), __ T2D,
14095             as_FloatRegister($src1$$reg),
14096             as_FloatRegister($src2$$reg));
14097   %}
14098   ins_pipe(pipe_class_default);
14099 %}
14100 
14101 instruct vsub2F(vecD dst, vecD src1, vecD src2)
14102 %{
14103   predicate(n->as_Vector()->length() == 2);
14104   match(Set dst (AddVF src1 src2));
14105   ins_cost(INSN_COST);
14106   format %{ "fsub  $dst,$src1,$src2\t# vector (2S)" %}
14107   ins_encode %{
14108     __ fsub(as_FloatRegister($dst$$reg), __ T2S,
14109             as_FloatRegister($src1$$reg),
14110             as_FloatRegister($src2$$reg));
14111   %}
14112   ins_pipe(pipe_class_default);
14113 %}
14114 
14115 instruct vsub4F(vecX dst, vecX src1, vecX src2)
14116 %{
14117   predicate(n->as_Vector()->length() == 4);
14118   match(Set dst (SubVF src1 src2));
14119   ins_cost(INSN_COST);
14120   format %{ "fsub  $dst,$src1,$src2\t# vector (4S)" %}
14121   ins_encode %{
14122     __ fsub(as_FloatRegister($dst$$reg), __ T4S,
14123             as_FloatRegister($src1$$reg),
14124             as_FloatRegister($src2$$reg));




14084   ins_pipe(pipe_class_default);
14085 %}
14086 
14087 instruct vsub2L(vecX dst, vecX src1, vecX src2)
14088 %{
14089   predicate(n->as_Vector()->length() == 2);
14090   match(Set dst (SubVL src1 src2));
14091   ins_cost(INSN_COST);
14092   format %{ "subv  $dst,$src1,$src2\t# vector (2L)" %}
14093   ins_encode %{
14094     __ subv(as_FloatRegister($dst$$reg), __ T2D,
14095             as_FloatRegister($src1$$reg),
14096             as_FloatRegister($src2$$reg));
14097   %}
14098   ins_pipe(pipe_class_default);
14099 %}
14100 
14101 instruct vsub2F(vecD dst, vecD src1, vecD src2)
14102 %{
14103   predicate(n->as_Vector()->length() == 2);
14104   match(Set dst (SubVF src1 src2));
14105   ins_cost(INSN_COST);
14106   format %{ "fsub  $dst,$src1,$src2\t# vector (2S)" %}
14107   ins_encode %{
14108     __ fsub(as_FloatRegister($dst$$reg), __ T2S,
14109             as_FloatRegister($src1$$reg),
14110             as_FloatRegister($src2$$reg));
14111   %}
14112   ins_pipe(pipe_class_default);
14113 %}
14114 
14115 instruct vsub4F(vecX dst, vecX src1, vecX src2)
14116 %{
14117   predicate(n->as_Vector()->length() == 4);
14118   match(Set dst (SubVF src1 src2));
14119   ins_cost(INSN_COST);
14120   format %{ "fsub  $dst,$src1,$src2\t# vector (4S)" %}
14121   ins_encode %{
14122     __ fsub(as_FloatRegister($dst$$reg), __ T4S,
14123             as_FloatRegister($src1$$reg),
14124             as_FloatRegister($src2$$reg));


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