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src/cpu/aarch64/vm/aarch64.ad

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rev 8694 : 8131362: aarch64: C2 does not handle large stack offsets
Summary: change spill code to allow large offsets
Reviewed-by: kvn, aph


2150   OptoReg::Name dst_hi = ra_->get_reg_second(this);
2151   OptoReg::Name dst_lo = ra_->get_reg_first(this);
2152 
2153   enum RC src_hi_rc = rc_class(src_hi);
2154   enum RC src_lo_rc = rc_class(src_lo);
2155   enum RC dst_hi_rc = rc_class(dst_hi);
2156   enum RC dst_lo_rc = rc_class(dst_lo);
2157 
2158   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
2159 
2160   if (src_hi != OptoReg::Bad) {
2161     assert((src_lo&1)==0 && src_lo+1==src_hi &&
2162            (dst_lo&1)==0 && dst_lo+1==dst_hi,
2163            "expected aligned-adjacent pairs");
2164   }
2165 
2166   if (src_lo == dst_lo && src_hi == dst_hi) {
2167     return 0;            // Self copy, no move.
2168   }
2169 





2170   if (bottom_type()->isa_vect() != NULL) {
2171     uint len = 4;
2172     uint ireg = ideal_reg();
2173     assert(ireg == Op_VecD || ireg == Op_VecX, "must be 64 bit or 128 bit vector");
2174     if (cbuf) {
2175       MacroAssembler _masm(cbuf);
2176       assert((src_lo_rc != rc_int && dst_lo_rc != rc_int), "sanity");
2177       if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
2178         // stack->stack
2179         int src_offset = ra_->reg2offset(src_lo);
2180         int dst_offset = ra_->reg2offset(dst_lo);
2181         assert((src_offset & 7) && (dst_offset & 7), "unaligned stack offset");
2182         len = 8;
2183         if (ireg == Op_VecD) {
2184           __ ldr(rscratch1, Address(sp, src_offset));
2185           __ str(rscratch1, Address(sp, dst_offset));
2186         } else {
2187           if (src_offset < 512) {
2188             __ ldp(rscratch1, rscratch2, Address(sp, src_offset));
2189           } else {
2190             __ ldr(rscratch1, Address(sp, src_offset));
2191             __ ldr(rscratch2, Address(sp, src_offset+4));
2192             len += 4;
2193           }
2194           if (dst_offset < 512) {
2195             __ stp(rscratch1, rscratch2, Address(sp, dst_offset));
2196           } else {
2197             __ str(rscratch1, Address(sp, dst_offset));
2198             __ str(rscratch2, Address(sp, dst_offset+4));
2199             len += 4;
2200           }
2201         }
2202       } else if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
2203         __ orr(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2204                ireg == Op_VecD ? __ T8B : __ T16B,
2205                as_FloatRegister(Matcher::_regEncode[src_lo]),
2206                as_FloatRegister(Matcher::_regEncode[src_lo]));
2207       } else if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
2208         __ str(as_FloatRegister(Matcher::_regEncode[src_lo]),
2209                ireg == Op_VecD ? __ D : __ Q,
2210                Address(sp, ra_->reg2offset(dst_lo)));
2211       } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_float) {
2212         __ ldr(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2213                ireg == Op_VecD ? __ D : __ Q,
2214                Address(sp, ra_->reg2offset(src_lo)));
2215       } else {
2216         ShouldNotReachHere();
2217       }
2218     } else if (st) {
2219       if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
2220         // stack->stack
2221         int src_offset = ra_->reg2offset(src_lo);
2222         int dst_offset = ra_->reg2offset(dst_lo);
2223         if (ireg == Op_VecD) {
2224           st->print("ldr  rscratch1, [sp, #%d]", src_offset);
2225           st->print("str  rscratch1, [sp, #%d]", dst_offset);
2226         } else {
2227           if (src_offset < 512) {
2228             st->print("ldp  rscratch1, rscratch2, [sp, #%d]", src_offset);
2229           } else {
2230             st->print("ldr  rscratch1, [sp, #%d]", src_offset);
2231             st->print("\nldr  rscratch2, [sp, #%d]", src_offset+4);
2232           }
2233           if (dst_offset < 512) {
2234             st->print("\nstp  rscratch1, rscratch2, [sp, #%d]", dst_offset);
2235           } else {
2236             st->print("\nstr  rscratch1, [sp, #%d]", dst_offset);
2237             st->print("\nstr  rscratch2, [sp, #%d]", dst_offset+4);
2238           }
2239         }
2240         st->print("\t# vector spill, stack to stack");
2241       } else if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
2242         st->print("mov  %s, %s\t# vector spill, reg to reg",
2243                    Matcher::regName[dst_lo], Matcher::regName[src_lo]);
2244       } else if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
2245         st->print("str  %s, [sp, #%d]\t# vector spill, reg to stack",
2246                    Matcher::regName[src_lo], ra_->reg2offset(dst_lo));
2247       } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_float) {
2248         st->print("ldr  %s, [sp, #%d]\t# vector spill, stack to reg",
2249                    Matcher::regName[dst_lo], ra_->reg2offset(src_lo));
2250       }
2251     }
2252     return len;
2253   }
2254 
2255   switch (src_lo_rc) {
2256   case rc_int:
2257     if (dst_lo_rc == rc_int) {  // gpr --> gpr copy
2258       if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
2259           (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
2260           // 64 bit
2261         if (cbuf) {
2262           MacroAssembler _masm(cbuf);
2263           __ mov(as_Register(Matcher::_regEncode[dst_lo]),
2264                  as_Register(Matcher::_regEncode[src_lo]));
2265         } else if (st) {
2266           st->print("mov  %s, %s\t# shuffle",
2267                     Matcher::regName[dst_lo],
2268                     Matcher::regName[src_lo]);
2269         }
2270       } else {
2271         // 32 bit
2272         if (cbuf) {
2273           MacroAssembler _masm(cbuf);
2274           __ movw(as_Register(Matcher::_regEncode[dst_lo]),
2275                   as_Register(Matcher::_regEncode[src_lo]));
2276         } else if (st) {
2277           st->print("movw  %s, %s\t# shuffle",
2278                     Matcher::regName[dst_lo],
2279                     Matcher::regName[src_lo]);
2280         }
2281       }
2282     } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
2283       if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
2284           (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
2285           // 64 bit
2286         if (cbuf) {
2287           MacroAssembler _masm(cbuf);
2288           __ fmovd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2289                    as_Register(Matcher::_regEncode[src_lo]));
2290         } else if (st) {
2291           st->print("fmovd  %s, %s\t# shuffle",
2292                     Matcher::regName[dst_lo],
2293                     Matcher::regName[src_lo]);
2294         }
2295       } else {
2296         // 32 bit
2297         if (cbuf) {
2298           MacroAssembler _masm(cbuf);
2299           __ fmovs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2300                    as_Register(Matcher::_regEncode[src_lo]));
2301         } else if (st) {
2302           st->print("fmovs  %s, %s\t# shuffle",
2303                     Matcher::regName[dst_lo],
2304                     Matcher::regName[src_lo]);
2305         }
2306       }
2307     } else {                    // gpr --> stack spill
2308       assert(dst_lo_rc == rc_stack, "spill to bad register class");
2309       int dst_offset = ra_->reg2offset(dst_lo);
2310       if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
2311           (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
2312           // 64 bit
2313         if (cbuf) {
2314           MacroAssembler _masm(cbuf);
2315           __ str(as_Register(Matcher::_regEncode[src_lo]),
2316                  Address(sp, dst_offset));
2317         } else if (st) {
2318           st->print("str  %s, [sp, #%d]\t# spill",
2319                     Matcher::regName[src_lo],
2320                     dst_offset);
2321         }
2322       } else {
2323         // 32 bit
2324         if (cbuf) {
2325           MacroAssembler _masm(cbuf);
2326           __ strw(as_Register(Matcher::_regEncode[src_lo]),
2327                  Address(sp, dst_offset));
2328         } else if (st) {
2329           st->print("strw  %s, [sp, #%d]\t# spill",
2330                     Matcher::regName[src_lo],
2331                     dst_offset);
2332         }
2333       }
2334     }
2335     return 4;
2336   case rc_float:
2337     if (dst_lo_rc == rc_int) {  // fpr --> gpr copy
2338       if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
2339           (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
2340           // 64 bit
2341         if (cbuf) {
2342           MacroAssembler _masm(cbuf);
2343           __ fmovd(as_Register(Matcher::_regEncode[dst_lo]),
2344                    as_FloatRegister(Matcher::_regEncode[src_lo]));
2345         } else if (st) {
2346           st->print("fmovd  %s, %s\t# shuffle",
2347                     Matcher::regName[dst_lo],
2348                     Matcher::regName[src_lo]);
2349         }
2350       } else {
2351         // 32 bit
2352         if (cbuf) {
2353           MacroAssembler _masm(cbuf);
2354           __ fmovs(as_Register(Matcher::_regEncode[dst_lo]),
2355                    as_FloatRegister(Matcher::_regEncode[src_lo]));
2356         } else if (st) {
2357           st->print("fmovs  %s, %s\t# shuffle",
2358                     Matcher::regName[dst_lo],
2359                     Matcher::regName[src_lo]);
2360         }
2361       }
2362     } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
2363       if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
2364           (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
2365           // 64 bit
2366         if (cbuf) {
2367           MacroAssembler _masm(cbuf);
2368           __ fmovd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2369                    as_FloatRegister(Matcher::_regEncode[src_lo]));
2370         } else if (st) {
2371           st->print("fmovd  %s, %s\t# shuffle",
2372                     Matcher::regName[dst_lo],
2373                     Matcher::regName[src_lo]);
2374         }
2375       } else {
2376         // 32 bit
2377         if (cbuf) {
2378           MacroAssembler _masm(cbuf);
2379           __ fmovs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2380                    as_FloatRegister(Matcher::_regEncode[src_lo]));
2381         } else if (st) {
2382           st->print("fmovs  %s, %s\t# shuffle",
2383                     Matcher::regName[dst_lo],
2384                     Matcher::regName[src_lo]);
2385         }
2386       }
2387     } else {                    // fpr --> stack spill
2388       assert(dst_lo_rc == rc_stack, "spill to bad register class");
2389       int dst_offset = ra_->reg2offset(dst_lo);
2390       if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
2391           (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
2392           // 64 bit
2393         if (cbuf) {
2394           MacroAssembler _masm(cbuf);
2395           __ strd(as_FloatRegister(Matcher::_regEncode[src_lo]),
2396                  Address(sp, dst_offset));
2397         } else if (st) {
2398           st->print("strd  %s, [sp, #%d]\t# spill",
2399                     Matcher::regName[src_lo],
2400                     dst_offset);
2401         }
2402       } else {
2403         // 32 bit
2404         if (cbuf) {
2405           MacroAssembler _masm(cbuf);
2406           __ strs(as_FloatRegister(Matcher::_regEncode[src_lo]),
2407                  Address(sp, dst_offset));
2408         } else if (st) {
2409           st->print("strs  %s, [sp, #%d]\t# spill",
2410                     Matcher::regName[src_lo],
2411                     dst_offset);
2412         }
2413       }
2414     }
2415     return 4;
2416   case rc_stack:
2417     int src_offset = ra_->reg2offset(src_lo);
2418     if (dst_lo_rc == rc_int) {  // stack --> gpr load
2419       if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
2420           (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
2421           // 64 bit
2422         if (cbuf) {
2423           MacroAssembler _masm(cbuf);
2424           __ ldr(as_Register(Matcher::_regEncode[dst_lo]),
2425                  Address(sp, src_offset));
2426         } else if (st) {
2427           st->print("ldr  %s, [sp, %d]\t# restore",
2428                     Matcher::regName[dst_lo],
2429                     src_offset);
2430         }
2431       } else {
2432         // 32 bit
2433         if (cbuf) {
2434           MacroAssembler _masm(cbuf);
2435           __ ldrw(as_Register(Matcher::_regEncode[dst_lo]),
2436                   Address(sp, src_offset));
2437         } else if (st) {
2438           st->print("ldr  %s, [sp, %d]\t# restore",
2439                     Matcher::regName[dst_lo],
2440                    src_offset);
2441         }
2442       }
2443       return 4;
2444     } else if (dst_lo_rc == rc_float) { // stack --> fpr load
2445       if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
2446           (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
2447           // 64 bit
2448         if (cbuf) {
2449           MacroAssembler _masm(cbuf);
2450           __ ldrd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2451                  Address(sp, src_offset));
2452         } else if (st) {
2453           st->print("ldrd  %s, [sp, %d]\t# restore",
2454                     Matcher::regName[dst_lo],
2455                     src_offset);
2456         }
2457       } else {
2458         // 32 bit
2459         if (cbuf) {
2460           MacroAssembler _masm(cbuf);
2461           __ ldrs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2462                   Address(sp, src_offset));
2463         } else if (st) {
2464           st->print("ldrs  %s, [sp, %d]\t# restore",
2465                     Matcher::regName[dst_lo],
2466                    src_offset);
2467         }
2468       }
2469       return 4;
2470     } else {                    // stack --> stack copy
2471       assert(dst_lo_rc == rc_stack, "spill to bad register class");
2472       int dst_offset = ra_->reg2offset(dst_lo);
2473       if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
2474           (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
2475           // 64 bit
2476         if (cbuf) {
2477           MacroAssembler _masm(cbuf);
2478           __ ldr(rscratch1, Address(sp, src_offset));
2479           __ str(rscratch1, Address(sp, dst_offset));
2480         } else if (st) {
2481           st->print("ldr  rscratch1, [sp, %d]\t# mem-mem spill",
2482                     src_offset);
2483           st->print("\n\t");
2484           st->print("str  rscratch1, [sp, %d]",
2485                     dst_offset);
2486         }





2487       } else {
2488         // 32 bit
2489         if (cbuf) {
2490           MacroAssembler _masm(cbuf);
2491           __ ldrw(rscratch1, Address(sp, src_offset));
2492           __ strw(rscratch1, Address(sp, dst_offset));
2493         } else if (st) {
2494           st->print("ldrw  rscratch1, [sp, %d]\t# mem-mem spill",
2495                     src_offset);
2496           st->print("\n\t");
2497           st->print("strw  rscratch1, [sp, %d]",
2498                     dst_offset);
2499         }




2500       }
2501       return 8;



2502     }
2503   }
2504 
2505   assert(false," bad rc_class for spill ");
2506   Unimplemented();
2507   return 0;
2508 
2509 }
2510 
2511 #ifndef PRODUCT
2512 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
2513   if (!ra_)
2514     st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
2515   else
2516     implementation(NULL, ra_, false, st);
2517 }
2518 #endif
2519 
2520 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
2521   implementation(&cbuf, ra_, false, NULL);
2522 }
2523 
2524 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
2525   return implementation(NULL, ra_, true, NULL);
2526 }
2527 
2528 //=============================================================================
2529 
2530 #ifndef PRODUCT
2531 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
2532   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
2533   int reg = ra_->get_reg_first(this);
2534   st->print("add %s, rsp, #%d]\t# box lock",
2535             Matcher::regName[reg], offset);
2536 }
2537 #endif
2538 
2539 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
2540   MacroAssembler _masm(&cbuf);
2541 
2542   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
2543   int reg    = ra_->get_encode(this);
2544 
2545   if (Assembler::operand_valid_for_add_sub_immediate(offset)) {




2150   OptoReg::Name dst_hi = ra_->get_reg_second(this);
2151   OptoReg::Name dst_lo = ra_->get_reg_first(this);
2152 
2153   enum RC src_hi_rc = rc_class(src_hi);
2154   enum RC src_lo_rc = rc_class(src_lo);
2155   enum RC dst_hi_rc = rc_class(dst_hi);
2156   enum RC dst_lo_rc = rc_class(dst_lo);
2157 
2158   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
2159 
2160   if (src_hi != OptoReg::Bad) {
2161     assert((src_lo&1)==0 && src_lo+1==src_hi &&
2162            (dst_lo&1)==0 && dst_lo+1==dst_hi,
2163            "expected aligned-adjacent pairs");
2164   }
2165 
2166   if (src_lo == dst_lo && src_hi == dst_hi) {
2167     return 0;            // Self copy, no move.
2168   }
2169 
2170   bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
2171               (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
2172   int src_offset = ra_->reg2offset(src_lo);
2173   int dst_offset = ra_->reg2offset(dst_lo);
2174 
2175   if (bottom_type()->isa_vect() != NULL) {

2176     uint ireg = ideal_reg();
2177     assert(ireg == Op_VecD || ireg == Op_VecX, "must be 64 bit or 128 bit vector");
2178     if (cbuf) {
2179       MacroAssembler _masm(cbuf);
2180       assert((src_lo_rc != rc_int && dst_lo_rc != rc_int), "sanity");
2181       if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
2182         // stack->stack


2183         assert((src_offset & 7) && (dst_offset & 7), "unaligned stack offset");

2184         if (ireg == Op_VecD) {
2185           __ unspill(rscratch1, true, src_offset);
2186           __ spill(rscratch1, true, dst_offset);



2187         } else {
2188           __ spill_copy128(src_offset, dst_offset);










2189         }
2190       } else if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
2191         __ mov(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2192                ireg == Op_VecD ? __ T8B : __ T16B,

2193                as_FloatRegister(Matcher::_regEncode[src_lo]));
2194       } else if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
2195         __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
2196                        ireg == Op_VecD ? __ D : __ Q,
2197                        ra_->reg2offset(dst_lo));
2198       } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_float) {
2199         __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2200                        ireg == Op_VecD ? __ D : __ Q,
2201                        ra_->reg2offset(src_lo));
2202       } else {
2203         ShouldNotReachHere();
2204       }

































2205     }
2206   } else if (cbuf) {
2207     MacroAssembler _masm(cbuf);

2208     switch (src_lo_rc) {
2209     case rc_int:
2210       if (dst_lo_rc == rc_int) {  // gpr --> gpr copy
2211         if (is64) {




2212             __ mov(as_Register(Matcher::_regEncode[dst_lo]),
2213                    as_Register(Matcher::_regEncode[src_lo]));





2214         } else {


2215             MacroAssembler _masm(cbuf);
2216             __ movw(as_Register(Matcher::_regEncode[dst_lo]),
2217                     as_Register(Matcher::_regEncode[src_lo]));





2218         }
2219       } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
2220         if (is64) {




2221             __ fmovd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2222                      as_Register(Matcher::_regEncode[src_lo]));





2223         } else {



2224             __ fmovs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2225                      as_Register(Matcher::_regEncode[src_lo]));





2226         }
2227       } else {                    // gpr --> stack spill
2228         assert(dst_lo_rc == rc_stack, "spill to bad register class");
2229         __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);






















2230       }
2231       break;


2232     case rc_float:
2233       if (dst_lo_rc == rc_int) {  // fpr --> gpr copy
2234         if (is64) {




2235             __ fmovd(as_Register(Matcher::_regEncode[dst_lo]),
2236                      as_FloatRegister(Matcher::_regEncode[src_lo]));





2237         } else {



2238             __ fmovs(as_Register(Matcher::_regEncode[dst_lo]),
2239                      as_FloatRegister(Matcher::_regEncode[src_lo]));





2240         }
2241       } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy



2242           if (cbuf) {

2243             __ fmovd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2244                      as_FloatRegister(Matcher::_regEncode[src_lo]));





2245         } else {



2246             __ fmovs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2247                      as_FloatRegister(Matcher::_regEncode[src_lo]));





2248         }
2249       } else {                    // fpr --> stack spill
2250         assert(dst_lo_rc == rc_stack, "spill to bad register class");
2251         __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
2252                  is64 ? __ D : __ S, dst_offset);






















2253       }
2254       break;

2255     case rc_stack:

2256       if (dst_lo_rc == rc_int) {  // stack --> gpr load
2257         __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
























2258       } else if (dst_lo_rc == rc_float) { // stack --> fpr load
2259         __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2260                    is64 ? __ D : __ S, src_offset);























2261       } else {                    // stack --> stack copy
2262         assert(dst_lo_rc == rc_stack, "spill to bad register class");
2263         __ unspill(rscratch1, is64, src_offset);
2264         __ spill(rscratch1, is64, dst_offset);
2265       }
2266       break;
2267     default:
2268       assert(false, "bad rc_class for spill");
2269       ShouldNotReachHere();
2270     }






2271   }
2272 
2273   if (st) {
2274     st->print("spill ");
2275     if (src_lo_rc == rc_stack) {
2276       st->print("[sp, #%d] -> ", ra_->reg2offset(src_lo));
2277     } else {
2278       st->print("%s -> ", Matcher::regName[src_lo]);










2279     }
2280     if (dst_lo_rc == rc_stack) {
2281       st->print("[sp, #%d]", ra_->reg2offset(dst_lo));
2282     } else {
2283       st->print("%s", Matcher::regName[dst_lo]);
2284     }
2285     if (bottom_type()->isa_vect() != NULL) {
2286       st->print("\t# vector spill size = %d", ideal_reg()==Op_VecD ? 64:128);
2287     } else {
2288       st->print("\t# spill size = %d", is64 ? 64:32);
2289     }
2290   }
2291 


2292   return 0;
2293 
2294 }
2295 
2296 #ifndef PRODUCT
2297 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
2298   if (!ra_)
2299     st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
2300   else
2301     implementation(NULL, ra_, false, st);
2302 }
2303 #endif
2304 
2305 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
2306   implementation(&cbuf, ra_, false, NULL);
2307 }
2308 
2309 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
2310   return MachNode::size(ra_);
2311 }
2312 
2313 //=============================================================================
2314 
2315 #ifndef PRODUCT
2316 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
2317   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
2318   int reg = ra_->get_reg_first(this);
2319   st->print("add %s, rsp, #%d]\t# box lock",
2320             Matcher::regName[reg], offset);
2321 }
2322 #endif
2323 
2324 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
2325   MacroAssembler _masm(&cbuf);
2326 
2327   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
2328   int reg    = ra_->get_encode(this);
2329 
2330   if (Assembler::operand_valid_for_add_sub_immediate(offset)) {


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