1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30
31 // MacroAssembler extends Assembler by frequently used macros.
32 //
33 // Instructions for which a 'better' code sequence exists depending
34 // on arguments should also go in here.
35
36 class MacroAssembler: public Assembler {
37 friend class LIR_Assembler;
38
39 public:
40 using Assembler::mov;
41 using Assembler::movi;
42
43 protected:
44
45 // Support for VM calls
46 //
47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
48 // may customize this version by overriding it for its purposes (e.g., to save/restore
49 // additional registers when doing a VM call).
50 #ifdef CC_INTERP
51 // c++ interpreter never wants to use interp_masm version of call_VM
52 #define VIRTUAL
53 #else
54 #define VIRTUAL virtual
55 #endif
56
57 VIRTUAL void call_VM_leaf_base(
58 address entry_point, // the entry point
59 int number_of_arguments, // the number of arguments to pop after the call
60 Label *retaddr = NULL
61 );
62
63 VIRTUAL void call_VM_leaf_base(
64 address entry_point, // the entry point
65 int number_of_arguments, // the number of arguments to pop after the call
66 Label &retaddr) {
67 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
68 }
69
70 // This is the base routine called by the different versions of call_VM. The interpreter
71 // may customize this version by overriding it for its purposes (e.g., to save/restore
72 // additional registers when doing a VM call).
73 //
74 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
75 // returns the register which contains the thread upon return. If a thread register has been
76 // specified, the return value will correspond to that register. If no last_java_sp is specified
77 // (noreg) than rsp will be used instead.
78 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
79 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
80 Register java_thread, // the thread if computed before ; use noreg otherwise
81 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
82 address entry_point, // the entry point
83 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
84 bool check_exceptions // whether to check for pending exceptions after return
85 );
86
87 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
88 // The implementation is only non-empty for the InterpreterMacroAssembler,
89 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
90 virtual void check_and_handle_popframe(Register java_thread);
91 virtual void check_and_handle_earlyret(Register java_thread);
92
93 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
94
95 // Maximum size of class area in Metaspace when compressed
96 uint64_t use_XOR_for_compressed_class_base;
97
98 public:
99 MacroAssembler(CodeBuffer* code) : Assembler(code) {
100 use_XOR_for_compressed_class_base
101 = (operand_valid_for_logical_immediate(false /*is32*/,
102 (uint64_t)Universe::narrow_klass_base())
103 && ((uint64_t)Universe::narrow_klass_base()
104 > (1u << log2_intptr(CompressedClassSpaceSize))));
105 }
106
107 // Biased locking support
108 // lock_reg and obj_reg must be loaded up with the appropriate values.
109 // swap_reg is killed.
110 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
111 // be killed; if not supplied, push/pop will be used internally to
112 // allocate a temporary (inefficient, avoid if possible).
113 // Optional slow case is for implementations (interpreter and C1) which branch to
114 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
115 // Returns offset of first potentially-faulting instruction for null
116 // check info (currently consumed only by C1). If
117 // swap_reg_contains_mark is true then returns -1 as it is assumed
118 // the calling code has already passed any potential faults.
119 int biased_locking_enter(Register lock_reg, Register obj_reg,
120 Register swap_reg, Register tmp_reg,
121 bool swap_reg_contains_mark,
122 Label& done, Label* slow_case = NULL,
123 BiasedLockingCounters* counters = NULL);
124 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
125
126
127 // Helper functions for statistics gathering.
128 // Unconditional atomic increment.
129 void atomic_incw(Register counter_addr, Register tmp);
130 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2) {
131 lea(tmp1, counter_addr);
132 atomic_incw(tmp1, tmp2);
133 }
134 // Load Effective Address
135 void lea(Register r, const Address &a) {
136 InstructionMark im(this);
137 code_section()->relocate(inst_mark(), a.rspec());
138 a.lea(this, r);
139 }
140
141 void addmw(Address a, Register incr, Register scratch) {
142 ldrw(scratch, a);
143 addw(scratch, scratch, incr);
144 strw(scratch, a);
145 }
146
147 // Add constant to memory word
148 void addmw(Address a, int imm, Register scratch) {
149 ldrw(scratch, a);
150 if (imm > 0)
151 addw(scratch, scratch, (unsigned)imm);
152 else
153 subw(scratch, scratch, (unsigned)-imm);
154 strw(scratch, a);
155 }
156
157 // Frame creation and destruction shared between JITs.
158 void build_frame(int framesize);
159 void remove_frame(int framesize);
160
161 virtual void _call_Unimplemented(address call_site) {
162 mov(rscratch2, call_site);
163 haltsim();
164 }
165
166 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
167
168 virtual void notify(int type);
169
170 // aliases defined in AARCH64 spec
171
172 template<class T>
173 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
174 inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); }
175
176 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
177 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
178
179 void cset(Register Rd, Assembler::Condition cond) {
180 csinc(Rd, zr, zr, ~cond);
181 }
182 void csetw(Register Rd, Assembler::Condition cond) {
183 csincw(Rd, zr, zr, ~cond);
184 }
185
186 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
187 csneg(Rd, Rn, Rn, ~cond);
188 }
189 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
190 csnegw(Rd, Rn, Rn, ~cond);
191 }
192
193 inline void movw(Register Rd, Register Rn) {
194 if (Rd == sp || Rn == sp) {
195 addw(Rd, Rn, 0U);
196 } else {
197 orrw(Rd, zr, Rn);
198 }
199 }
200 inline void mov(Register Rd, Register Rn) {
201 assert(Rd != r31_sp && Rn != r31_sp, "should be");
202 if (Rd == Rn) {
203 } else if (Rd == sp || Rn == sp) {
204 add(Rd, Rn, 0U);
205 } else {
206 orr(Rd, zr, Rn);
207 }
208 }
209
210 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
211 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
212
213 inline void tstw(Register Rd, unsigned imm) { andsw(zr, Rd, imm); }
214 inline void tst(Register Rd, unsigned imm) { ands(zr, Rd, imm); }
215
216 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
217 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
218 }
219 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
220 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
221 }
222
223 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
224 bfmw(Rd, Rn, lsb, (lsb + width - 1));
225 }
226 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
227 bfm(Rd, Rn, lsb , (lsb + width - 1));
228 }
229
230 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
231 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
232 }
233 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
234 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
235 }
236
237 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
238 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
239 }
240 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
241 sbfm(Rd, Rn, lsb , (lsb + width - 1));
242 }
243
244 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
245 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
246 }
247 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
248 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
249 }
250
251 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
252 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
253 }
254 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
255 ubfm(Rd, Rn, lsb , (lsb + width - 1));
256 }
257
258 inline void asrw(Register Rd, Register Rn, unsigned imm) {
259 sbfmw(Rd, Rn, imm, 31);
260 }
261
262 inline void asr(Register Rd, Register Rn, unsigned imm) {
263 sbfm(Rd, Rn, imm, 63);
264 }
265
266 inline void lslw(Register Rd, Register Rn, unsigned imm) {
267 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
268 }
269
270 inline void lsl(Register Rd, Register Rn, unsigned imm) {
271 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
272 }
273
274 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
275 ubfmw(Rd, Rn, imm, 31);
276 }
277
278 inline void lsr(Register Rd, Register Rn, unsigned imm) {
279 ubfm(Rd, Rn, imm, 63);
280 }
281
282 inline void rorw(Register Rd, Register Rn, unsigned imm) {
283 extrw(Rd, Rn, Rn, imm);
284 }
285
286 inline void ror(Register Rd, Register Rn, unsigned imm) {
287 extr(Rd, Rn, Rn, imm);
288 }
289
290 inline void sxtbw(Register Rd, Register Rn) {
291 sbfmw(Rd, Rn, 0, 7);
292 }
293 inline void sxthw(Register Rd, Register Rn) {
294 sbfmw(Rd, Rn, 0, 15);
295 }
296 inline void sxtb(Register Rd, Register Rn) {
297 sbfm(Rd, Rn, 0, 7);
298 }
299 inline void sxth(Register Rd, Register Rn) {
300 sbfm(Rd, Rn, 0, 15);
301 }
302 inline void sxtw(Register Rd, Register Rn) {
303 sbfm(Rd, Rn, 0, 31);
304 }
305
306 inline void uxtbw(Register Rd, Register Rn) {
307 ubfmw(Rd, Rn, 0, 7);
308 }
309 inline void uxthw(Register Rd, Register Rn) {
310 ubfmw(Rd, Rn, 0, 15);
311 }
312 inline void uxtb(Register Rd, Register Rn) {
313 ubfm(Rd, Rn, 0, 7);
314 }
315 inline void uxth(Register Rd, Register Rn) {
316 ubfm(Rd, Rn, 0, 15);
317 }
318 inline void uxtw(Register Rd, Register Rn) {
319 ubfm(Rd, Rn, 0, 31);
320 }
321
322 inline void cmnw(Register Rn, Register Rm) {
323 addsw(zr, Rn, Rm);
324 }
325 inline void cmn(Register Rn, Register Rm) {
326 adds(zr, Rn, Rm);
327 }
328
329 inline void cmpw(Register Rn, Register Rm) {
330 subsw(zr, Rn, Rm);
331 }
332 inline void cmp(Register Rn, Register Rm) {
333 subs(zr, Rn, Rm);
334 }
335
336 inline void negw(Register Rd, Register Rn) {
337 subw(Rd, zr, Rn);
338 }
339
340 inline void neg(Register Rd, Register Rn) {
341 sub(Rd, zr, Rn);
342 }
343
344 inline void negsw(Register Rd, Register Rn) {
345 subsw(Rd, zr, Rn);
346 }
347
348 inline void negs(Register Rd, Register Rn) {
349 subs(Rd, zr, Rn);
350 }
351
352 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
353 addsw(zr, Rn, Rm, kind, shift);
354 }
355 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
356 adds(zr, Rn, Rm, kind, shift);
357 }
358
359 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
360 subsw(zr, Rn, Rm, kind, shift);
361 }
362 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
363 subs(zr, Rn, Rm, kind, shift);
364 }
365
366 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
367 subw(Rd, zr, Rn, kind, shift);
368 }
369
370 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
371 sub(Rd, zr, Rn, kind, shift);
372 }
373
374 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
375 subsw(Rd, zr, Rn, kind, shift);
376 }
377
378 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
379 subs(Rd, zr, Rn, kind, shift);
380 }
381
382 inline void mnegw(Register Rd, Register Rn, Register Rm) {
383 msubw(Rd, Rn, Rm, zr);
384 }
385 inline void mneg(Register Rd, Register Rn, Register Rm) {
386 msub(Rd, Rn, Rm, zr);
387 }
388
389 inline void mulw(Register Rd, Register Rn, Register Rm) {
390 maddw(Rd, Rn, Rm, zr);
391 }
392 inline void mul(Register Rd, Register Rn, Register Rm) {
393 madd(Rd, Rn, Rm, zr);
394 }
395
396 inline void smnegl(Register Rd, Register Rn, Register Rm) {
397 smsubl(Rd, Rn, Rm, zr);
398 }
399 inline void smull(Register Rd, Register Rn, Register Rm) {
400 smaddl(Rd, Rn, Rm, zr);
401 }
402
403 inline void umnegl(Register Rd, Register Rn, Register Rm) {
404 umsubl(Rd, Rn, Rm, zr);
405 }
406 inline void umull(Register Rd, Register Rn, Register Rm) {
407 umaddl(Rd, Rn, Rm, zr);
408 }
409
410 #define WRAP(INSN) \
411 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
412 if ((VM_Version::cpu_cpuFeatures() & VM_Version::CPU_A53MAC) && Ra != zr) \
413 nop(); \
414 Assembler::INSN(Rd, Rn, Rm, Ra); \
415 }
416
417 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
418 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
419 #undef WRAP
420
421
422 // macro assembly operations needed for aarch64
423
424 // first two private routines for loading 32 bit or 64 bit constants
425 private:
426
427 void mov_immediate64(Register dst, u_int64_t imm64);
428 void mov_immediate32(Register dst, u_int32_t imm32);
429
430 int push(unsigned int bitset, Register stack);
431 int pop(unsigned int bitset, Register stack);
432
433 void mov(Register dst, Address a);
434
435 public:
436 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
437 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
438
439 // now mov instructions for loading absolute addresses and 32 or
440 // 64 bit integers
441
442 inline void mov(Register dst, address addr)
443 {
444 mov_immediate64(dst, (u_int64_t)addr);
445 }
446
447 inline void mov(Register dst, u_int64_t imm64)
448 {
449 mov_immediate64(dst, imm64);
450 }
451
452 inline void movw(Register dst, u_int32_t imm32)
453 {
454 mov_immediate32(dst, imm32);
455 }
456
457 inline void mov(Register dst, long l)
458 {
459 mov(dst, (u_int64_t)l);
460 }
461
462 inline void mov(Register dst, int i)
463 {
464 mov(dst, (long)i);
465 }
466
467 void movptr(Register r, uintptr_t imm64);
468
469 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
470
471 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
472 orr(Vd, T, Vn, Vn);
473 }
474
475 // macro instructions for accessing and updating floating point
476 // status register
477 //
478 // FPSR : op1 == 011
479 // CRn == 0100
480 // CRm == 0100
481 // op2 == 001
482
483 inline void get_fpsr(Register reg)
484 {
485 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
486 }
487
488 inline void set_fpsr(Register reg)
489 {
490 msr(0b011, 0b0100, 0b0100, 0b001, reg);
491 }
492
493 inline void clear_fpsr()
494 {
495 msr(0b011, 0b0100, 0b0100, 0b001, zr);
496 }
497
498 // idiv variant which deals with MINLONG as dividend and -1 as divisor
499 int corrected_idivl(Register result, Register ra, Register rb,
500 bool want_remainder, Register tmp = rscratch1);
501 int corrected_idivq(Register result, Register ra, Register rb,
502 bool want_remainder, Register tmp = rscratch1);
503
504 // Support for NULL-checks
505 //
506 // Generates code that causes a NULL OS exception if the content of reg is NULL.
507 // If the accessed location is M[reg + offset] and the offset is known, provide the
508 // offset. No explicit code generation is needed if the offset is within a certain
509 // range (0 <= offset <= page_size).
510
511 virtual void null_check(Register reg, int offset = -1);
512 static bool needs_explicit_null_check(intptr_t offset);
513
514 static address target_addr_for_insn(address insn_addr, unsigned insn);
515 static address target_addr_for_insn(address insn_addr) {
516 unsigned insn = *(unsigned*)insn_addr;
517 return target_addr_for_insn(insn_addr, insn);
518 }
519
520 // Required platform-specific helpers for Label::patch_instructions.
521 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
522 static int pd_patch_instruction_size(address branch, address target);
523 static void pd_patch_instruction(address branch, address target) {
524 pd_patch_instruction_size(branch, target);
525 }
526 static address pd_call_destination(address branch) {
527 return target_addr_for_insn(branch);
528 }
529 #ifndef PRODUCT
530 static void pd_print_patched_instruction(address branch);
531 #endif
532
533 static int patch_oop(address insn_addr, address o);
534
535 void emit_trampoline_stub(int insts_call_instruction_offset, address target);
536
537 // The following 4 methods return the offset of the appropriate move instruction
538
539 // Support for fast byte/short loading with zero extension (depending on particular CPU)
540 int load_unsigned_byte(Register dst, Address src);
541 int load_unsigned_short(Register dst, Address src);
542
543 // Support for fast byte/short loading with sign extension (depending on particular CPU)
544 int load_signed_byte(Register dst, Address src);
545 int load_signed_short(Register dst, Address src);
546
547 int load_signed_byte32(Register dst, Address src);
548 int load_signed_short32(Register dst, Address src);
549
550 // Support for sign-extension (hi:lo = extend_sign(lo))
551 void extend_sign(Register hi, Register lo);
552
553 // Load and store values by size and signed-ness
554 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
555 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
556
557 // Support for inc/dec with optimal instruction selection depending on value
558
559 // x86_64 aliases an unqualified register/address increment and
560 // decrement to call incrementq and decrementq but also supports
561 // explicitly sized calls to incrementq/decrementq or
562 // incrementl/decrementl
563
564 // for aarch64 the proper convention would be to use
565 // increment/decrement for 64 bit operatons and
566 // incrementw/decrementw for 32 bit operations. so when porting
567 // x86_64 code we can leave calls to increment/decrement as is,
568 // replace incrementq/decrementq with increment/decrement and
569 // replace incrementl/decrementl with incrementw/decrementw.
570
571 // n.b. increment/decrement calls with an Address destination will
572 // need to use a scratch register to load the value to be
573 // incremented. increment/decrement calls which add or subtract a
574 // constant value greater than 2^12 will need to use a 2nd scratch
575 // register to hold the constant. so, a register increment/decrement
576 // may trash rscratch2 and an address increment/decrement trash
577 // rscratch and rscratch2
578
579 void decrementw(Address dst, int value = 1);
580 void decrementw(Register reg, int value = 1);
581
582 void decrement(Register reg, int value = 1);
583 void decrement(Address dst, int value = 1);
584
585 void incrementw(Address dst, int value = 1);
586 void incrementw(Register reg, int value = 1);
587
588 void increment(Register reg, int value = 1);
589 void increment(Address dst, int value = 1);
590
591
592 // Alignment
593 void align(int modulus);
594
595 // Stack frame creation/removal
596 void enter()
597 {
598 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
599 mov(rfp, sp);
600 }
601 void leave()
602 {
603 mov(sp, rfp);
604 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
605 }
606
607 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
608 // The pointer will be loaded into the thread register.
609 void get_thread(Register thread);
610
611
612 // Support for VM calls
613 //
614 // It is imperative that all calls into the VM are handled via the call_VM macros.
615 // They make sure that the stack linkage is setup correctly. call_VM's correspond
616 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
617
618
619 void call_VM(Register oop_result,
620 address entry_point,
621 bool check_exceptions = true);
622 void call_VM(Register oop_result,
623 address entry_point,
624 Register arg_1,
625 bool check_exceptions = true);
626 void call_VM(Register oop_result,
627 address entry_point,
628 Register arg_1, Register arg_2,
629 bool check_exceptions = true);
630 void call_VM(Register oop_result,
631 address entry_point,
632 Register arg_1, Register arg_2, Register arg_3,
633 bool check_exceptions = true);
634
635 // Overloadings with last_Java_sp
636 void call_VM(Register oop_result,
637 Register last_java_sp,
638 address entry_point,
639 int number_of_arguments = 0,
640 bool check_exceptions = true);
641 void call_VM(Register oop_result,
642 Register last_java_sp,
643 address entry_point,
644 Register arg_1, bool
645 check_exceptions = true);
646 void call_VM(Register oop_result,
647 Register last_java_sp,
648 address entry_point,
649 Register arg_1, Register arg_2,
650 bool check_exceptions = true);
651 void call_VM(Register oop_result,
652 Register last_java_sp,
653 address entry_point,
654 Register arg_1, Register arg_2, Register arg_3,
655 bool check_exceptions = true);
656
657 void get_vm_result (Register oop_result, Register thread);
658 void get_vm_result_2(Register metadata_result, Register thread);
659
660 // These always tightly bind to MacroAssembler::call_VM_base
661 // bypassing the virtual implementation
662 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
663 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
664 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
665 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
666 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
667
668 void call_VM_leaf(address entry_point,
669 int number_of_arguments = 0);
670 void call_VM_leaf(address entry_point,
671 Register arg_1);
672 void call_VM_leaf(address entry_point,
673 Register arg_1, Register arg_2);
674 void call_VM_leaf(address entry_point,
675 Register arg_1, Register arg_2, Register arg_3);
676
677 // These always tightly bind to MacroAssembler::call_VM_leaf_base
678 // bypassing the virtual implementation
679 void super_call_VM_leaf(address entry_point);
680 void super_call_VM_leaf(address entry_point, Register arg_1);
681 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
682 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
683 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
684
685 // last Java Frame (fills frame anchor)
686 void set_last_Java_frame(Register last_java_sp,
687 Register last_java_fp,
688 address last_java_pc,
689 Register scratch);
690
691 void set_last_Java_frame(Register last_java_sp,
692 Register last_java_fp,
693 Label &last_java_pc,
694 Register scratch);
695
696 void set_last_Java_frame(Register last_java_sp,
697 Register last_java_fp,
698 Register last_java_pc,
699 Register scratch);
700
701 void reset_last_Java_frame(Register thread, bool clearfp, bool clear_pc);
702
703 // thread in the default location (r15_thread on 64bit)
704 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
705
706 // Stores
707 void store_check(Register obj); // store check for obj - register is destroyed afterwards
708 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
709
710 #if INCLUDE_ALL_GCS
711
712 void g1_write_barrier_pre(Register obj,
713 Register pre_val,
714 Register thread,
715 Register tmp,
716 bool tosca_live,
717 bool expand_call);
718
719 void g1_write_barrier_post(Register store_addr,
720 Register new_val,
721 Register thread,
722 Register tmp,
723 Register tmp2);
724
725 #endif // INCLUDE_ALL_GCS
726
727 // oop manipulations
728 void load_klass(Register dst, Register src);
729 void store_klass(Register dst, Register src);
730 void cmp_klass(Register oop, Register trial_klass, Register tmp);
731
732 void load_heap_oop(Register dst, Address src);
733
734 void load_heap_oop_not_null(Register dst, Address src);
735 void store_heap_oop(Address dst, Register src);
736
737 // currently unimplemented
738 // Used for storing NULL. All other oop constants should be
739 // stored using routines that take a jobject.
740 void store_heap_oop_null(Address dst);
741
742 void load_prototype_header(Register dst, Register src);
743
744 void store_klass_gap(Register dst, Register src);
745
746 // This dummy is to prevent a call to store_heap_oop from
747 // converting a zero (like NULL) into a Register by giving
748 // the compiler two choices it can't resolve
749
750 void store_heap_oop(Address dst, void* dummy);
751
752 void encode_heap_oop(Register d, Register s);
753 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
754 void decode_heap_oop(Register d, Register s);
755 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
756 void encode_heap_oop_not_null(Register r);
757 void decode_heap_oop_not_null(Register r);
758 void encode_heap_oop_not_null(Register dst, Register src);
759 void decode_heap_oop_not_null(Register dst, Register src);
760
761 void set_narrow_oop(Register dst, jobject obj);
762
763 void encode_klass_not_null(Register r);
764 void decode_klass_not_null(Register r);
765 void encode_klass_not_null(Register dst, Register src);
766 void decode_klass_not_null(Register dst, Register src);
767
768 void set_narrow_klass(Register dst, Klass* k);
769
770 // if heap base register is used - reinit it with the correct value
771 void reinit_heapbase();
772
773 DEBUG_ONLY(void verify_heapbase(const char* msg);)
774
775 void push_CPU_state();
776 void pop_CPU_state() ;
777
778 // Round up to a power of two
779 void round_to(Register reg, int modulus);
780
781 // allocation
782 void eden_allocate(
783 Register obj, // result: pointer to object after successful allocation
784 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
785 int con_size_in_bytes, // object size in bytes if known at compile time
786 Register t1, // temp register
787 Label& slow_case // continuation point if fast allocation fails
788 );
789 void tlab_allocate(
790 Register obj, // result: pointer to object after successful allocation
791 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
792 int con_size_in_bytes, // object size in bytes if known at compile time
793 Register t1, // temp register
794 Register t2, // temp register
795 Label& slow_case // continuation point if fast allocation fails
796 );
797 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
798 void verify_tlab();
799
800 void incr_allocated_bytes(Register thread,
801 Register var_size_in_bytes, int con_size_in_bytes,
802 Register t1 = noreg);
803
804 // interface method calling
805 void lookup_interface_method(Register recv_klass,
806 Register intf_klass,
807 RegisterOrConstant itable_index,
808 Register method_result,
809 Register scan_temp,
810 Label& no_such_interface);
811
812 // virtual method calling
813 // n.b. x86 allows RegisterOrConstant for vtable_index
814 void lookup_virtual_method(Register recv_klass,
815 RegisterOrConstant vtable_index,
816 Register method_result);
817
818 // Test sub_klass against super_klass, with fast and slow paths.
819
820 // The fast path produces a tri-state answer: yes / no / maybe-slow.
821 // One of the three labels can be NULL, meaning take the fall-through.
822 // If super_check_offset is -1, the value is loaded up from super_klass.
823 // No registers are killed, except temp_reg.
824 void check_klass_subtype_fast_path(Register sub_klass,
825 Register super_klass,
826 Register temp_reg,
827 Label* L_success,
828 Label* L_failure,
829 Label* L_slow_path,
830 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
831
832 // The rest of the type check; must be wired to a corresponding fast path.
833 // It does not repeat the fast path logic, so don't use it standalone.
834 // The temp_reg and temp2_reg can be noreg, if no temps are available.
835 // Updates the sub's secondary super cache as necessary.
836 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
837 void check_klass_subtype_slow_path(Register sub_klass,
838 Register super_klass,
839 Register temp_reg,
840 Register temp2_reg,
841 Label* L_success,
842 Label* L_failure,
843 bool set_cond_codes = false);
844
845 // Simplified, combined version, good for typical uses.
846 // Falls through on failure.
847 void check_klass_subtype(Register sub_klass,
848 Register super_klass,
849 Register temp_reg,
850 Label& L_success);
851
852 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
853
854
855 // Debugging
856
857 // only if +VerifyOops
858 void verify_oop(Register reg, const char* s = "broken oop");
859 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
860
861 // TODO: verify method and klass metadata (compare against vptr?)
862 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
863 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
864
865 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
866 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
867
868 // only if +VerifyFPU
869 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
870
871 // prints msg, dumps registers and stops execution
872 void stop(const char* msg);
873
874 // prints msg and continues
875 void warn(const char* msg);
876
877 static void debug64(char* msg, int64_t pc, int64_t regs[]);
878
879 void untested() { stop("untested"); }
880
881 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
882
883 void should_not_reach_here() { stop("should not reach here"); }
884
885 // Stack overflow checking
886 void bang_stack_with_offset(int offset) {
887 // stack grows down, caller passes positive offset
888 assert(offset > 0, "must bang with negative offset");
889 mov(rscratch2, -offset);
890 str(zr, Address(sp, rscratch2));
891 }
892
893 // Writes to stack successive pages until offset reached to check for
894 // stack overflow + shadow pages. Also, clobbers tmp
895 void bang_stack_size(Register size, Register tmp);
896
897 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
898 Register tmp,
899 int offset);
900
901 // Support for serializing memory accesses between threads
902 void serialize_memory(Register thread, Register tmp);
903
904 // Arithmetics
905
906 void addptr(Address dst, int32_t src) {
907 lea(rscratch2, dst);
908 ldr(rscratch1, Address(rscratch2));
909 add(rscratch1, rscratch1, src);
910 str(rscratch1, Address(rscratch2));
911 }
912
913 void cmpptr(Register src1, Address src2);
914
915 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
916 Label &suceed, Label *fail);
917
918 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
919 Label &suceed, Label *fail);
920
921 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
922 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
923
924 void atomic_xchg(Register prev, Register newv, Register addr);
925 void atomic_xchgw(Register prev, Register newv, Register addr);
926
927 void orptr(Address adr, RegisterOrConstant src) {
928 ldr(rscratch2, adr);
929 if (src.is_register())
930 orr(rscratch2, rscratch2, src.as_register());
931 else
932 orr(rscratch2, rscratch2, src.as_constant());
933 str(rscratch2, adr);
934 }
935
936 // Calls
937
938 void trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
939
940 static bool far_branches() {
941 return ReservedCodeCacheSize > branch_range;
942 }
943
944 // Jumps that can reach anywhere in the code cache.
945 // Trashes tmp.
946 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
947 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
948
949 static int far_branch_size() {
950 if (far_branches()) {
951 return 3 * 4; // adrp, add, br
952 } else {
953 return 4;
954 }
955 }
956
957 // Emit the CompiledIC call idiom
958 void ic_call(address entry);
959
960 public:
961
962 // Data
963
964 void mov_metadata(Register dst, Metadata* obj);
965 Address allocate_metadata_address(Metadata* obj);
966 Address constant_oop_address(jobject obj);
967
968 void movoop(Register dst, jobject obj, bool immediate = false);
969
970 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
971 void kernel_crc32(Register crc, Register buf, Register len,
972 Register table0, Register table1, Register table2, Register table3,
973 Register tmp, Register tmp2, Register tmp3);
974 // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
975 void kernel_crc32c(Register crc, Register buf, Register len,
976 Register table0, Register table1, Register table2, Register table3,
977 Register tmp, Register tmp2, Register tmp3);
978
979 #undef VIRTUAL
980
981 // Stack push and pop individual 64 bit registers
982 void push(Register src);
983 void pop(Register dst);
984
985 // push all registers onto the stack
986 void pusha();
987 void popa();
988
989 void repne_scan(Register addr, Register value, Register count,
990 Register scratch);
991 void repne_scanw(Register addr, Register value, Register count,
992 Register scratch);
993
994 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
995 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
996
997 // If a constant does not fit in an immediate field, generate some
998 // number of MOV instructions and then perform the operation
999 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1000 add_sub_imm_insn insn1,
1001 add_sub_reg_insn insn2);
1002 // Seperate vsn which sets the flags
1003 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1004 add_sub_imm_insn insn1,
1005 add_sub_reg_insn insn2);
1006
1007 #define WRAP(INSN) \
1008 void INSN(Register Rd, Register Rn, unsigned imm) { \
1009 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1010 } \
1011 \
1012 void INSN(Register Rd, Register Rn, Register Rm, \
1013 enum shift_kind kind, unsigned shift = 0) { \
1014 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1015 } \
1016 \
1017 void INSN(Register Rd, Register Rn, Register Rm) { \
1018 Assembler::INSN(Rd, Rn, Rm); \
1019 } \
1020 \
1021 void INSN(Register Rd, Register Rn, Register Rm, \
1022 ext::operation option, int amount = 0) { \
1023 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1024 }
1025
1026 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1027
1028 #undef WRAP
1029 #define WRAP(INSN) \
1030 void INSN(Register Rd, Register Rn, unsigned imm) { \
1031 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1032 } \
1033 \
1034 void INSN(Register Rd, Register Rn, Register Rm, \
1035 enum shift_kind kind, unsigned shift = 0) { \
1036 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1037 } \
1038 \
1039 void INSN(Register Rd, Register Rn, Register Rm) { \
1040 Assembler::INSN(Rd, Rn, Rm); \
1041 } \
1042 \
1043 void INSN(Register Rd, Register Rn, Register Rm, \
1044 ext::operation option, int amount = 0) { \
1045 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1046 }
1047
1048 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1049
1050 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1051 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1052
1053 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1054
1055 void tableswitch(Register index, jint lowbound, jint highbound,
1056 Label &jumptable, Label &jumptable_end, int stride = 1) {
1057 adr(rscratch1, jumptable);
1058 subsw(rscratch2, index, lowbound);
1059 subsw(zr, rscratch2, highbound - lowbound);
1060 br(Assembler::HS, jumptable_end);
1061 add(rscratch1, rscratch1, rscratch2,
1062 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1063 br(rscratch1);
1064 }
1065
1066 // Form an address from base + offset in Rd. Rd may or may not
1067 // actually be used: you must use the Address that is returned. It
1068 // is up to you to ensure that the shift provided matches the size
1069 // of your data.
1070 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1071
1072 // Prolog generator routines to support switch between x86 code and
1073 // generated ARM code
1074
1075 // routine to generate an x86 prolog for a stub function which
1076 // bootstraps into the generated ARM code which directly follows the
1077 // stub
1078 //
1079
1080 public:
1081 // enum used for aarch64--x86 linkage to define return type of x86 function
1082 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1083
1084 #ifdef BUILTIN_SIM
1085 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1086 #else
1087 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1088 #endif
1089
1090 // special version of call_VM_leaf_base needed for aarch64 simulator
1091 // where we need to specify both the gp and fp arg counts and the
1092 // return type so that the linkage routine from aarch64 to x86 and
1093 // back knows which aarch64 registers to copy to x86 registers and
1094 // which x86 result register to copy back to an aarch64 register
1095
1096 void call_VM_leaf_base1(
1097 address entry_point, // the entry point
1098 int number_of_gp_arguments, // the number of gp reg arguments to pass
1099 int number_of_fp_arguments, // the number of fp reg arguments to pass
1100 ret_type type, // the return type for the call
1101 Label* retaddr = NULL
1102 );
1103
1104 void ldr_constant(Register dest, const Address &const_addr) {
1105 if (NearCpool) {
1106 ldr(dest, const_addr);
1107 } else {
1108 unsigned long offset;
1109 adrp(dest, InternalAddress(const_addr.target()), offset);
1110 ldr(dest, Address(dest, offset));
1111 }
1112 }
1113
1114 address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1115 address read_polling_page(Register r, relocInfo::relocType rtype);
1116
1117 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1118 void update_byte_crc32(Register crc, Register val, Register table);
1119 void update_word_crc32(Register crc, Register v, Register tmp,
1120 Register table0, Register table1, Register table2, Register table3,
1121 bool upper = false);
1122
1123 void string_compare(Register str1, Register str2,
1124 Register cnt1, Register cnt2, Register result,
1125 Register tmp1);
1126 void string_equals(Register str1, Register str2,
1127 Register cnt, Register result,
1128 Register tmp1);
1129 void char_arrays_equals(Register ary1, Register ary2,
1130 Register result, Register tmp1);
1131 void encode_iso_array(Register src, Register dst,
1132 Register len, Register result,
1133 FloatRegister Vtmp1, FloatRegister Vtmp2,
1134 FloatRegister Vtmp3, FloatRegister Vtmp4);
1135 void string_indexof(Register str1, Register str2,
1136 Register cnt1, Register cnt2,
1137 Register tmp1, Register tmp2,
1138 Register tmp3, Register tmp4,
1139 int int_cnt1, Register result);
1140 private:
1141 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1142 Register src1, Register src2);
1143 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1144 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1145 }
1146 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1147 Register y, Register y_idx, Register z,
1148 Register carry, Register product,
1149 Register idx, Register kdx);
1150 void multiply_128_x_128_loop(Register y, Register z,
1151 Register carry, Register carry2,
1152 Register idx, Register jdx,
1153 Register yz_idx1, Register yz_idx2,
1154 Register tmp, Register tmp3, Register tmp4,
1155 Register tmp7, Register product_hi);
1156 public:
1157 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1158 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1159 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1160 // ISB may be needed because of a safepoint
1161 void maybe_isb() { isb(); }
1162
1163 private:
1164 // Return the effective address r + (r1 << ext) + offset.
1165 // Uses rscratch2.
1166 Address offsetted_address(Register r, Register r1, Address::extend ext,
1167 int offset, int size);
1168
1169 private:
1170 // Returns an address on the stack which is reachable with a ldr/str of size
1171 // Uses rscratch2 if the address is not directly reachable
1172 Address spill_address(int size, int offset, Register tmp=rscratch2);
1173
1174 public:
1175 void spill(Register Rx, bool is64, int offset) {
1176 if (is64) {
1177 str(Rx, spill_address(8, offset));
1178 } else {
1179 strw(Rx, spill_address(4, offset));
1180 }
1181 }
1182 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1183 str(Vx, T, spill_address(1 << (int)T, offset));
1184 }
1185 void unspill(Register Rx, bool is64, int offset) {
1186 if (is64) {
1187 ldr(Rx, spill_address(8, offset));
1188 } else {
1189 ldrw(Rx, spill_address(4, offset));
1190 }
1191 }
1192 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1193 ldr(Vx, T, spill_address(1 << (int)T, offset));
1194 }
1195 void spill_copy128(int src_offset, int dst_offset,
1196 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1197 if (src_offset < 512 && (src_offset & 7) == 0 &&
1198 dst_offset < 512 && (dst_offset & 7) == 0) {
1199 ldp(tmp1, tmp2, Address(sp, src_offset));
1200 stp(tmp1, tmp2, Address(sp, dst_offset));
1201 } else {
1202 unspill(tmp1, true, src_offset);
1203 spill(tmp1, true, dst_offset);
1204 unspill(tmp1, true, src_offset+8);
1205 spill(tmp1, true, dst_offset+8);
1206 }
1207 }
1208 };
1209
1210 #ifdef ASSERT
1211 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1212 #endif
1213
1214 /**
1215 * class SkipIfEqual:
1216 *
1217 * Instantiating this class will result in assembly code being output that will
1218 * jump around any code emitted between the creation of the instance and it's
1219 * automatic destruction at the end of a scope block, depending on the value of
1220 * the flag passed to the constructor, which will be checked at run-time.
1221 */
1222 class SkipIfEqual {
1223 private:
1224 MacroAssembler* _masm;
1225 Label _label;
1226
1227 public:
1228 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1229 ~SkipIfEqual();
1230 };
1231
1232 struct tableswitch {
1233 Register _reg;
1234 int _insn_index; jint _first_key; jint _last_key;
1235 Label _after;
1236 Label _branches;
1237 };
1238
1239 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP