1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights All rights reserved.
3 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
4 * reserved. DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE
5 * HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #include <stdio.h>
28 #include <sys/types.h>
29
30 #include "precompiled.hpp"
31 #include "asm/assembler.hpp"
32 #include "asm/assembler.inline.hpp"
33 #include "interpreter/interpreter.hpp"
34
35 #ifndef PRODUCT
36 const unsigned long Assembler::asm_bp = 0x00007fffee09ac88;
37 #endif
38
39 #include "compiler/disassembler.hpp"
40 #include "memory/resourceArea.hpp"
41 #include "runtime/interfaceSupport.hpp"
42 #include "runtime/sharedRuntime.hpp"
43
44 // for the moment we reuse the logical/floating point immediate encode
45 // and decode functiosn provided by the simulator. when we move to
46 // real hardware we will need to pull taht code into here
47
48 #include "immediate_aarch64.hpp"
49
50 extern "C" void entry(CodeBuffer *cb);
51
52 #define __ _masm.
53 #ifdef PRODUCT
54 #define BLOCK_COMMENT(str) /* nothing */
55 #else
56 #define BLOCK_COMMENT(str) block_comment(str)
57 #endif
58
59 #define BIND(label) bind(label); __ BLOCK_COMMENT(#label ":")
60
61 static float unpack(unsigned value);
62
63 void entry(CodeBuffer *cb) {
64
65 // {
66 // for (int i = 0; i < 256; i+=16)
67 // {
68 // printf("\"%20.20g\", ", unpack(i));
69 // printf("\"%20.20g\", ", unpack(i+1));
70 // }
71 // printf("\n");
72 // }
73
74 Assembler _masm(cb);
75 address entry = __ pc();
76
77 // Smoke test for assembler
78
79 #ifdef ASSERT
80 // BEGIN Generated code -- do not edit
81 // Generated by aarch64-asmtest.py
82 Label back, forth;
83 __ bind(back);
84
85 // ArithOp
86 __ add(r19, r22, r7, Assembler::LSL, 28); // add x19, x22, x7, LSL #28
87 __ sub(r16, r11, r10, Assembler::LSR, 13); // sub x16, x11, x10, LSR #13
88 __ adds(r27, r13, r28, Assembler::ASR, 2); // adds x27, x13, x28, ASR #2
89 __ subs(r20, r28, r26, Assembler::ASR, 41); // subs x20, x28, x26, ASR #41
90 __ addw(r8, r19, r19, Assembler::ASR, 19); // add w8, w19, w19, ASR #19
91 __ subw(r4, r9, r10, Assembler::LSL, 14); // sub w4, w9, w10, LSL #14
92 __ addsw(r8, r11, r30, Assembler::LSL, 13); // adds w8, w11, w30, LSL #13
93 __ subsw(r0, r25, r19, Assembler::LSL, 9); // subs w0, w25, w19, LSL #9
94 __ andr(r20, r0, r21, Assembler::LSL, 19); // and x20, x0, x21, LSL #19
95 __ orr(r21, r14, r20, Assembler::LSL, 17); // orr x21, x14, x20, LSL #17
96 __ eor(r25, r28, r1, Assembler::LSL, 51); // eor x25, x28, x1, LSL #51
97 __ ands(r10, r27, r11, Assembler::ASR, 15); // ands x10, x27, x11, ASR #15
98 __ andw(r25, r5, r12, Assembler::ASR, 23); // and w25, w5, w12, ASR #23
99 __ orrw(r18, r14, r10, Assembler::LSR, 4); // orr w18, w14, w10, LSR #4
100 __ eorw(r4, r21, r5, Assembler::ASR, 22); // eor w4, w21, w5, ASR #22
101 __ andsw(r21, r0, r5, Assembler::ASR, 29); // ands w21, w0, w5, ASR #29
102 __ bic(r26, r30, r6, Assembler::ASR, 37); // bic x26, x30, x6, ASR #37
103 __ orn(r3, r1, r13, Assembler::LSR, 29); // orn x3, x1, x13, LSR #29
104 __ eon(r0, r28, r9, Assembler::LSL, 47); // eon x0, x28, x9, LSL #47
105 __ bics(r29, r5, r28, Assembler::LSL, 46); // bics x29, x5, x28, LSL #46
106 __ bicw(r9, r18, r7, Assembler::LSR, 20); // bic w9, w18, w7, LSR #20
107 __ ornw(r26, r13, r25, Assembler::ASR, 24); // orn w26, w13, w25, ASR #24
108 __ eonw(r25, r4, r19, Assembler::LSL, 6); // eon w25, w4, w19, LSL #6
109 __ bicsw(r5, r26, r4, Assembler::LSR, 24); // bics w5, w26, w4, LSR #24
110
111 // AddSubImmOp
112 __ addw(r7, r19, 340u); // add w7, w19, #340
113 __ addsw(r8, r0, 401u); // adds w8, w0, #401
114 __ subw(r29, r20, 163u); // sub w29, w20, #163
115 __ subsw(r8, r23, 759u); // subs w8, w23, #759
116 __ add(r1, r12, 523u); // add x1, x12, #523
117 __ adds(r2, r11, 426u); // adds x2, x11, #426
118 __ sub(r14, r29, 716u); // sub x14, x29, #716
119 __ subs(r11, r5, 582u); // subs x11, x5, #582
120
121 // LogicalImmOp
122 __ andw(r23, r22, 32768ul); // and w23, w22, #0x8000
123 __ orrw(r4, r10, 4042322160ul); // orr w4, w10, #0xf0f0f0f0
124 __ eorw(r0, r24, 4042322160ul); // eor w0, w24, #0xf0f0f0f0
125 __ andsw(r19, r29, 2139127680ul); // ands w19, w29, #0x7f807f80
126 __ andr(r5, r10, 4503599627354112ul); // and x5, x10, #0xfffffffffc000
127 __ orr(r12, r30, 18445618178097414144ul); // orr x12, x30, #0xfffc0000fffc0000
128 __ eor(r30, r5, 262128ul); // eor x30, x5, #0x3fff0
129 __ ands(r26, r23, 4194300ul); // ands x26, x23, #0x3ffffc
130
131 // AbsOp
132 __ b(__ pc()); // b .
133 __ b(back); // b back
134 __ b(forth); // b forth
135 __ bl(__ pc()); // bl .
136 __ bl(back); // bl back
137 __ bl(forth); // bl forth
138
139 // RegAndAbsOp
140 __ cbzw(r12, __ pc()); // cbz w12, .
141 __ cbzw(r12, back); // cbz w12, back
142 __ cbzw(r12, forth); // cbz w12, forth
143 __ cbnzw(r20, __ pc()); // cbnz w20, .
144 __ cbnzw(r20, back); // cbnz w20, back
145 __ cbnzw(r20, forth); // cbnz w20, forth
146 __ cbz(r12, __ pc()); // cbz x12, .
147 __ cbz(r12, back); // cbz x12, back
148 __ cbz(r12, forth); // cbz x12, forth
149 __ cbnz(r24, __ pc()); // cbnz x24, .
150 __ cbnz(r24, back); // cbnz x24, back
151 __ cbnz(r24, forth); // cbnz x24, forth
152 __ adr(r6, __ pc()); // adr x6, .
153 __ adr(r6, back); // adr x6, back
154 __ adr(r6, forth); // adr x6, forth
155 __ _adrp(r21, __ pc()); // adrp x21, .
156
157 // RegImmAbsOp
158 __ tbz(r1, 1, __ pc()); // tbz x1, #1, .
159 __ tbz(r1, 1, back); // tbz x1, #1, back
160 __ tbz(r1, 1, forth); // tbz x1, #1, forth
161 __ tbnz(r8, 9, __ pc()); // tbnz x8, #9, .
162 __ tbnz(r8, 9, back); // tbnz x8, #9, back
163 __ tbnz(r8, 9, forth); // tbnz x8, #9, forth
164
165 // MoveWideImmOp
166 __ movnw(r12, 23175, 0); // movn w12, #23175, lsl 0
167 __ movzw(r11, 20476, 16); // movz w11, #20476, lsl 16
168 __ movkw(r21, 3716, 0); // movk w21, #3716, lsl 0
169 __ movn(r29, 28661, 48); // movn x29, #28661, lsl 48
170 __ movz(r3, 6927, 0); // movz x3, #6927, lsl 0
171 __ movk(r22, 9828, 16); // movk x22, #9828, lsl 16
172
173 // BitfieldOp
174 __ sbfm(r12, r8, 6, 22); // sbfm x12, x8, #6, #22
175 __ bfmw(r19, r25, 25, 19); // bfm w19, w25, #25, #19
176 __ ubfmw(r9, r12, 29, 15); // ubfm w9, w12, #29, #15
177 __ sbfm(r28, r25, 16, 16); // sbfm x28, x25, #16, #16
178 __ bfm(r12, r5, 4, 25); // bfm x12, x5, #4, #25
179 __ ubfm(r0, r10, 6, 8); // ubfm x0, x10, #6, #8
180
181 // ExtractOp
182 __ extrw(r4, r13, r26, 24); // extr w4, w13, w26, #24
183 __ extr(r23, r30, r24, 31); // extr x23, x30, x24, #31
184
185 // CondBranchOp
186 __ br(Assembler::EQ, __ pc()); // b.EQ .
187 __ br(Assembler::EQ, back); // b.EQ back
188 __ br(Assembler::EQ, forth); // b.EQ forth
189 __ br(Assembler::NE, __ pc()); // b.NE .
190 __ br(Assembler::NE, back); // b.NE back
191 __ br(Assembler::NE, forth); // b.NE forth
192 __ br(Assembler::HS, __ pc()); // b.HS .
193 __ br(Assembler::HS, back); // b.HS back
194 __ br(Assembler::HS, forth); // b.HS forth
195 __ br(Assembler::CS, __ pc()); // b.CS .
196 __ br(Assembler::CS, back); // b.CS back
197 __ br(Assembler::CS, forth); // b.CS forth
198 __ br(Assembler::LO, __ pc()); // b.LO .
199 __ br(Assembler::LO, back); // b.LO back
200 __ br(Assembler::LO, forth); // b.LO forth
201 __ br(Assembler::CC, __ pc()); // b.CC .
202 __ br(Assembler::CC, back); // b.CC back
203 __ br(Assembler::CC, forth); // b.CC forth
204 __ br(Assembler::MI, __ pc()); // b.MI .
205 __ br(Assembler::MI, back); // b.MI back
206 __ br(Assembler::MI, forth); // b.MI forth
207 __ br(Assembler::PL, __ pc()); // b.PL .
208 __ br(Assembler::PL, back); // b.PL back
209 __ br(Assembler::PL, forth); // b.PL forth
210 __ br(Assembler::VS, __ pc()); // b.VS .
211 __ br(Assembler::VS, back); // b.VS back
212 __ br(Assembler::VS, forth); // b.VS forth
213 __ br(Assembler::VC, __ pc()); // b.VC .
214 __ br(Assembler::VC, back); // b.VC back
215 __ br(Assembler::VC, forth); // b.VC forth
216 __ br(Assembler::HI, __ pc()); // b.HI .
217 __ br(Assembler::HI, back); // b.HI back
218 __ br(Assembler::HI, forth); // b.HI forth
219 __ br(Assembler::LS, __ pc()); // b.LS .
220 __ br(Assembler::LS, back); // b.LS back
221 __ br(Assembler::LS, forth); // b.LS forth
222 __ br(Assembler::GE, __ pc()); // b.GE .
223 __ br(Assembler::GE, back); // b.GE back
224 __ br(Assembler::GE, forth); // b.GE forth
225 __ br(Assembler::LT, __ pc()); // b.LT .
226 __ br(Assembler::LT, back); // b.LT back
227 __ br(Assembler::LT, forth); // b.LT forth
228 __ br(Assembler::GT, __ pc()); // b.GT .
229 __ br(Assembler::GT, back); // b.GT back
230 __ br(Assembler::GT, forth); // b.GT forth
231 __ br(Assembler::LE, __ pc()); // b.LE .
232 __ br(Assembler::LE, back); // b.LE back
233 __ br(Assembler::LE, forth); // b.LE forth
234 __ br(Assembler::AL, __ pc()); // b.AL .
235 __ br(Assembler::AL, back); // b.AL back
236 __ br(Assembler::AL, forth); // b.AL forth
237 __ br(Assembler::NV, __ pc()); // b.NV .
238 __ br(Assembler::NV, back); // b.NV back
239 __ br(Assembler::NV, forth); // b.NV forth
240
241 // ImmOp
242 __ svc(12729); // svc #12729
243 __ hvc(6788); // hvc #6788
244 __ smc(1535); // smc #1535
245 __ brk(16766); // brk #16766
246 __ hlt(9753); // hlt #9753
247
248 // Op
249 __ nop(); // nop
250 __ eret(); // eret
251 __ drps(); // drps
252 __ isb(); // isb
253
254 // SystemOp
255 __ dsb(Assembler::SY); // dsb SY
256 __ dmb(Assembler::ISHST); // dmb ISHST
257
258 // OneRegOp
259 __ br(r2); // br x2
260 __ blr(r5); // blr x5
261
262 // LoadStoreExclusiveOp
263 __ stxr(r20, r21, r2); // stxr w20, x21, [x2]
264 __ stlxr(r7, r29, r7); // stlxr w7, x29, [x7]
265 __ ldxr(r5, r16); // ldxr x5, [x16]
266 __ ldaxr(r27, r29); // ldaxr x27, [x29]
267 __ stlr(r0, r29); // stlr x0, [x29]
268 __ ldar(r21, r28); // ldar x21, [x28]
269
270 // LoadStoreExclusiveOp
271 __ stxrw(r24, r24, r7); // stxr w24, w24, [x7]
272 __ stlxrw(r21, r26, r28); // stlxr w21, w26, [x28]
273 __ ldxrw(r21, r6); // ldxr w21, [x6]
274 __ ldaxrw(r15, r30); // ldaxr w15, [x30]
275 __ stlrw(r19, r3); // stlr w19, [x3]
276 __ ldarw(r22, r2); // ldar w22, [x2]
277
278 // LoadStoreExclusiveOp
279 __ stxrh(r18, r15, r0); // stxrh w18, w15, [x0]
280 __ stlxrh(r11, r5, r28); // stlxrh w11, w5, [x28]
281 __ ldxrh(r29, r6); // ldxrh w29, [x6]
282 __ ldaxrh(r18, r7); // ldaxrh w18, [x7]
283 __ stlrh(r25, r28); // stlrh w25, [x28]
284 __ ldarh(r2, r19); // ldarh w2, [x19]
285
286 // LoadStoreExclusiveOp
287 __ stxrb(r10, r30, r1); // stxrb w10, w30, [x1]
288 __ stlxrb(r20, r21, r22); // stlxrb w20, w21, [x22]
289 __ ldxrb(r25, r2); // ldxrb w25, [x2]
290 __ ldaxrb(r24, r5); // ldaxrb w24, [x5]
291 __ stlrb(r16, r3); // stlrb w16, [x3]
292 __ ldarb(r22, r29); // ldarb w22, [x29]
293
294 // LoadStoreExclusiveOp
295 __ ldxp(r8, r2, r19); // ldxp x8, x2, [x19]
296 __ ldaxp(r7, r19, r14); // ldaxp x7, x19, [x14]
297 __ stxp(r8, r27, r28, r5); // stxp w8, x27, x28, [x5]
298 __ stlxp(r6, r8, r14, r6); // stlxp w6, x8, x14, [x6]
299
300 // LoadStoreExclusiveOp
301 __ ldxpw(r25, r4, r22); // ldxp w25, w4, [x22]
302 __ ldaxpw(r14, r14, r15); // ldaxp w14, w14, [x15]
303 __ stxpw(r20, r26, r8, r10); // stxp w20, w26, w8, [x10]
304 __ stlxpw(r23, r18, r18, r18); // stlxp w23, w18, w18, [x18]
305
306 // base_plus_unscaled_offset
307 // LoadStoreOp
308 __ str(r30, Address(r11, 99)); // str x30, [x11, 99]
309 __ strw(r23, Address(r25, -77)); // str w23, [x25, -77]
310 __ strb(r2, Address(r14, 3)); // strb w2, [x14, 3]
311 __ strh(r9, Address(r10, 5)); // strh w9, [x10, 5]
312 __ ldr(r20, Address(r15, 57)); // ldr x20, [x15, 57]
313 __ ldrw(r12, Address(r16, -78)); // ldr w12, [x16, -78]
314 __ ldrb(r22, Address(r26, -3)); // ldrb w22, [x26, -3]
315 __ ldrh(r30, Address(r19, -47)); // ldrh w30, [x19, -47]
316 __ ldrsb(r9, Address(r10, -12)); // ldrsb x9, [x10, -12]
317 __ ldrsh(r28, Address(r17, 14)); // ldrsh x28, [x17, 14]
318 __ ldrshw(r3, Address(r5, 10)); // ldrsh w3, [x5, 10]
319 __ ldrsw(r17, Address(r17, -91)); // ldrsw x17, [x17, -91]
320 __ ldrd(v2, Address(r20, -17)); // ldr d2, [x20, -17]
321 __ ldrs(v22, Address(r7, -10)); // ldr s22, [x7, -10]
322 __ strd(v30, Address(r18, -223)); // str d30, [x18, -223]
323 __ strs(v13, Address(r22, 21)); // str s13, [x22, 21]
324
325 // pre
326 // LoadStoreOp
327 __ str(r9, Address(__ pre(r18, -112))); // str x9, [x18, -112]!
328 __ strw(r29, Address(__ pre(r23, 11))); // str w29, [x23, 11]!
329 __ strb(r18, Address(__ pre(r12, -1))); // strb w18, [x12, -1]!
330 __ strh(r16, Address(__ pre(r20, -23))); // strh w16, [x20, -23]!
331 __ ldr(r3, Address(__ pre(r29, 9))); // ldr x3, [x29, 9]!
332 __ ldrw(r25, Address(__ pre(r3, 19))); // ldr w25, [x3, 19]!
333 __ ldrb(r1, Address(__ pre(r29, -1))); // ldrb w1, [x29, -1]!
334 __ ldrh(r8, Address(__ pre(r29, -57))); // ldrh w8, [x29, -57]!
335 __ ldrsb(r5, Address(__ pre(r14, -13))); // ldrsb x5, [x14, -13]!
336 __ ldrsh(r10, Address(__ pre(r27, 1))); // ldrsh x10, [x27, 1]!
337 __ ldrshw(r11, Address(__ pre(r10, 25))); // ldrsh w11, [x10, 25]!
338 __ ldrsw(r4, Address(__ pre(r22, -92))); // ldrsw x4, [x22, -92]!
339 __ ldrd(v11, Address(__ pre(r23, 8))); // ldr d11, [x23, 8]!
340 __ ldrs(v25, Address(__ pre(r19, 54))); // ldr s25, [x19, 54]!
341 __ strd(v1, Address(__ pre(r7, -174))); // str d1, [x7, -174]!
342 __ strs(v8, Address(__ pre(r25, 54))); // str s8, [x25, 54]!
343
344 // post
345 // LoadStoreOp
346 __ str(r5, Address(__ post(r11, 37))); // str x5, [x11], 37
347 __ strw(r24, Address(__ post(r15, 19))); // str w24, [x15], 19
348 __ strb(r15, Address(__ post(r26, -1))); // strb w15, [x26], -1
349 __ strh(r18, Address(__ post(r18, -6))); // strh w18, [x18], -6
350 __ ldr(r7, Address(__ post(r2, -230))); // ldr x7, [x2], -230
351 __ ldrw(r27, Address(__ post(r11, -27))); // ldr w27, [x11], -27
352 __ ldrb(r18, Address(__ post(r3, -25))); // ldrb w18, [x3], -25
353 __ ldrh(r10, Address(__ post(r24, -32))); // ldrh w10, [x24], -32
354 __ ldrsb(r22, Address(__ post(r10, 4))); // ldrsb x22, [x10], 4
355 __ ldrsh(r17, Address(__ post(r12, 25))); // ldrsh x17, [x12], 25
356 __ ldrshw(r8, Address(__ post(r7, -62))); // ldrsh w8, [x7], -62
357 __ ldrsw(r23, Address(__ post(r22, -51))); // ldrsw x23, [x22], -51
358 __ ldrd(v24, Address(__ post(r25, 48))); // ldr d24, [x25], 48
359 __ ldrs(v21, Address(__ post(r12, -10))); // ldr s21, [x12], -10
360 __ strd(v18, Address(__ post(r13, -222))); // str d18, [x13], -222
361 __ strs(v16, Address(__ post(r1, -41))); // str s16, [x1], -41
362
363 // base_plus_reg
364 // LoadStoreOp
365 __ str(r2, Address(r22, r15, Address::sxtw(0))); // str x2, [x22, w15, sxtw #0]
366 __ strw(r2, Address(r16, r29, Address::lsl(0))); // str w2, [x16, x29, lsl #0]
367 __ strb(r20, Address(r18, r14, Address::uxtw(0))); // strb w20, [x18, w14, uxtw #0]
368 __ strh(r6, Address(r19, r20, Address::sxtx(1))); // strh w6, [x19, x20, sxtx #1]
369 __ ldr(r14, Address(r29, r14, Address::sxtw(0))); // ldr x14, [x29, w14, sxtw #0]
370 __ ldrw(r16, Address(r20, r12, Address::sxtw(2))); // ldr w16, [x20, w12, sxtw #2]
371 __ ldrb(r9, Address(r12, r0, Address::sxtw(0))); // ldrb w9, [x12, w0, sxtw #0]
372 __ ldrh(r12, Address(r17, r3, Address::lsl(1))); // ldrh w12, [x17, x3, lsl #1]
373 __ ldrsb(r2, Address(r17, r3, Address::sxtx(0))); // ldrsb x2, [x17, x3, sxtx #0]
374 __ ldrsh(r7, Address(r1, r17, Address::uxtw(1))); // ldrsh x7, [x1, w17, uxtw #1]
375 __ ldrshw(r25, Address(r15, r18, Address::sxtw(1))); // ldrsh w25, [x15, w18, sxtw #1]
376 __ ldrsw(r23, Address(r21, r12, Address::lsl(0))); // ldrsw x23, [x21, x12, lsl #0]
377 __ ldrd(v5, Address(r13, r8, Address::lsl(3))); // ldr d5, [x13, x8, lsl #3]
378 __ ldrs(v3, Address(r10, r22, Address::lsl(2))); // ldr s3, [x10, x22, lsl #2]
379 __ strd(v14, Address(r2, r27, Address::sxtw(0))); // str d14, [x2, w27, sxtw #0]
380 __ strs(v20, Address(r6, r25, Address::lsl(0))); // str s20, [x6, x25, lsl #0]
381
382 // base_plus_scaled_offset
383 // LoadStoreOp
384 __ str(r30, Address(r7, 16256)); // str x30, [x7, 16256]
385 __ strw(r15, Address(r8, 7588)); // str w15, [x8, 7588]
386 __ strb(r11, Address(r0, 1866)); // strb w11, [x0, 1866]
387 __ strh(r3, Address(r17, 3734)); // strh w3, [x17, 3734]
388 __ ldr(r2, Address(r7, 14224)); // ldr x2, [x7, 14224]
389 __ ldrw(r5, Address(r9, 7396)); // ldr w5, [x9, 7396]
390 __ ldrb(r28, Address(r9, 1721)); // ldrb w28, [x9, 1721]
391 __ ldrh(r2, Address(r20, 3656)); // ldrh w2, [x20, 3656]
392 __ ldrsb(r22, Address(r14, 1887)); // ldrsb x22, [x14, 1887]
393 __ ldrsh(r8, Address(r0, 4080)); // ldrsh x8, [x0, 4080]
394 __ ldrshw(r0, Address(r30, 3916)); // ldrsh w0, [x30, 3916]
395 __ ldrsw(r24, Address(r19, 6828)); // ldrsw x24, [x19, 6828]
396 __ ldrd(v24, Address(r12, 13032)); // ldr d24, [x12, 13032]
397 __ ldrs(v8, Address(r8, 7452)); // ldr s8, [x8, 7452]
398 __ strd(v10, Address(r15, 15992)); // str d10, [x15, 15992]
399 __ strs(v26, Address(r19, 6688)); // str s26, [x19, 6688]
400
401 // pcrel
402 // LoadStoreOp
403 __ ldr(r10, forth); // ldr x10, forth
404 __ ldrw(r3, __ pc()); // ldr w3, .
405
406 // LoadStoreOp
407 __ prfm(Address(r23, 9)); // prfm PLDL1KEEP, [x23, 9]
408
409 // LoadStoreOp
410 __ prfm(back); // prfm PLDL1KEEP, back
411
412 // LoadStoreOp
413 __ prfm(Address(r3, r8, Address::uxtw(0))); // prfm PLDL1KEEP, [x3, w8, uxtw #0]
414
415 // LoadStoreOp
416 __ prfm(Address(r11, 15080)); // prfm PLDL1KEEP, [x11, 15080]
417
418 // AddSubCarryOp
419 __ adcw(r13, r9, r28); // adc w13, w9, w28
420 __ adcsw(r27, r19, r28); // adcs w27, w19, w28
421 __ sbcw(r19, r18, r6); // sbc w19, w18, w6
422 __ sbcsw(r14, r20, r3); // sbcs w14, w20, w3
423 __ adc(r16, r14, r8); // adc x16, x14, x8
424 __ adcs(r0, r29, r8); // adcs x0, x29, x8
425 __ sbc(r8, r24, r20); // sbc x8, x24, x20
426 __ sbcs(r12, r28, r0); // sbcs x12, x28, x0
427
428 // AddSubExtendedOp
429 __ addw(r23, r6, r16, ext::uxtb, 4); // add w23, w6, w16, uxtb #4
430 __ addsw(r25, r25, r23, ext::sxth, 2); // adds w25, w25, w23, sxth #2
431 __ sub(r26, r22, r4, ext::uxtx, 1); // sub x26, x22, x4, uxtx #1
432 __ subsw(r17, r29, r19, ext::sxtx, 3); // subs w17, w29, w19, sxtx #3
433 __ add(r11, r30, r21, ext::uxtb, 3); // add x11, x30, x21, uxtb #3
434 __ adds(r16, r19, r0, ext::sxtb, 2); // adds x16, x19, x0, sxtb #2
435 __ sub(r11, r9, r25, ext::sxtx, 1); // sub x11, x9, x25, sxtx #1
436 __ subs(r17, r20, r12, ext::sxtb, 4); // subs x17, x20, x12, sxtb #4
437
438 // ConditionalCompareOp
439 __ ccmnw(r13, r11, 3u, Assembler::LE); // ccmn w13, w11, #3, LE
440 __ ccmpw(r13, r12, 2u, Assembler::HI); // ccmp w13, w12, #2, HI
441 __ ccmn(r3, r2, 12u, Assembler::NE); // ccmn x3, x2, #12, NE
442 __ ccmp(r7, r21, 3u, Assembler::VS); // ccmp x7, x21, #3, VS
443
444 // ConditionalCompareImmedOp
445 __ ccmnw(r2, 14, 4, Assembler::CC); // ccmn w2, #14, #4, CC
446 __ ccmpw(r17, 17, 6, Assembler::PL); // ccmp w17, #17, #6, PL
447 __ ccmn(r10, 12, 0, Assembler::CS); // ccmn x10, #12, #0, CS
448 __ ccmp(r21, 18, 14, Assembler::GE); // ccmp x21, #18, #14, GE
449
450 // ConditionalSelectOp
451 __ cselw(r21, r13, r12, Assembler::GT); // csel w21, w13, w12, GT
452 __ csincw(r10, r27, r15, Assembler::LS); // csinc w10, w27, w15, LS
453 __ csinvw(r0, r13, r9, Assembler::HI); // csinv w0, w13, w9, HI
454 __ csnegw(r18, r4, r26, Assembler::VS); // csneg w18, w4, w26, VS
455 __ csel(r12, r29, r7, Assembler::LS); // csel x12, x29, x7, LS
456 __ csinc(r6, r7, r20, Assembler::VC); // csinc x6, x7, x20, VC
457 __ csinv(r22, r21, r3, Assembler::LE); // csinv x22, x21, x3, LE
458 __ csneg(r19, r12, r27, Assembler::LS); // csneg x19, x12, x27, LS
459
460 // TwoRegOp
461 __ rbitw(r0, r16); // rbit w0, w16
462 __ rev16w(r17, r23); // rev16 w17, w23
463 __ revw(r17, r14); // rev w17, w14
464 __ clzw(r24, r30); // clz w24, w30
465 __ clsw(r24, r22); // cls w24, w22
466 __ rbit(r3, r17); // rbit x3, x17
467 __ rev16(r12, r13); // rev16 x12, x13
468 __ rev32(r9, r22); // rev32 x9, x22
469 __ rev(r0, r0); // rev x0, x0
470 __ clz(r5, r16); // clz x5, x16
471 __ cls(r25, r22); // cls x25, x22
472
473 // ThreeRegOp
474 __ udivw(r29, r4, r0); // udiv w29, w4, w0
475 __ sdivw(r0, r29, r29); // sdiv w0, w29, w29
476 __ lslvw(r5, r17, r21); // lslv w5, w17, w21
477 __ lsrvw(r9, r9, r18); // lsrv w9, w9, w18
478 __ asrvw(r1, r27, r8); // asrv w1, w27, w8
479 __ rorvw(r18, r20, r13); // rorv w18, w20, w13
480 __ udiv(r8, r25, r12); // udiv x8, x25, x12
481 __ sdiv(r7, r5, r28); // sdiv x7, x5, x28
482 __ lslv(r5, r17, r27); // lslv x5, x17, x27
483 __ lsrv(r23, r26, r20); // lsrv x23, x26, x20
484 __ asrv(r28, r8, r28); // asrv x28, x8, x28
485 __ rorv(r3, r29, r4); // rorv x3, x29, x4
486
487 // FourRegMulOp
488 __ maddw(r17, r14, r26, r21); // madd w17, w14, w26, w21
489 __ msubw(r1, r30, r11, r11); // msub w1, w30, w11, w11
490 __ madd(r1, r17, r6, r28); // madd x1, x17, x6, x28
491 __ msub(r30, r6, r30, r8); // msub x30, x6, x30, x8
492 __ smaddl(r21, r6, r14, r8); // smaddl x21, w6, w14, x8
493 __ smsubl(r10, r10, r24, r19); // smsubl x10, w10, w24, x19
494 __ umaddl(r20, r18, r14, r24); // umaddl x20, w18, w14, x24
495 __ umsubl(r18, r2, r5, r5); // umsubl x18, w2, w5, x5
496
497 // ThreeRegFloatOp
498 __ fmuls(v8, v18, v13); // fmul s8, s18, s13
499 __ fdivs(v2, v14, v28); // fdiv s2, s14, s28
500 __ fadds(v15, v12, v28); // fadd s15, s12, s28
501 __ fsubs(v0, v12, v1); // fsub s0, s12, s1
502 __ fmuls(v15, v29, v4); // fmul s15, s29, s4
503 __ fmuld(v12, v1, v23); // fmul d12, d1, d23
504 __ fdivd(v27, v8, v18); // fdiv d27, d8, d18
505 __ faddd(v23, v20, v11); // fadd d23, d20, d11
506 __ fsubd(v8, v12, v18); // fsub d8, d12, d18
507 __ fmuld(v26, v24, v23); // fmul d26, d24, d23
508
509 // FourRegFloatOp
510 __ fmadds(v21, v23, v13, v25); // fmadd s21, s23, s13, s25
511 __ fmsubs(v22, v10, v1, v14); // fmsub s22, s10, s1, s14
512 __ fnmadds(v14, v20, v2, v30); // fnmadd s14, s20, s2, s30
513 __ fnmadds(v7, v29, v22, v22); // fnmadd s7, s29, s22, s22
514 __ fmaddd(v13, v5, v15, v5); // fmadd d13, d5, d15, d5
515 __ fmsubd(v14, v12, v5, v10); // fmsub d14, d12, d5, d10
516 __ fnmaddd(v10, v19, v0, v1); // fnmadd d10, d19, d0, d1
517 __ fnmaddd(v20, v2, v2, v0); // fnmadd d20, d2, d2, d0
518
519 // TwoRegFloatOp
520 __ fmovs(v25, v9); // fmov s25, s9
521 __ fabss(v20, v4); // fabs s20, s4
522 __ fnegs(v3, v27); // fneg s3, s27
523 __ fsqrts(v1, v2); // fsqrt s1, s2
524 __ fcvts(v30, v0); // fcvt d30, s0
525 __ fmovd(v12, v4); // fmov d12, d4
526 __ fabsd(v1, v27); // fabs d1, d27
527 __ fnegd(v8, v22); // fneg d8, d22
528 __ fsqrtd(v11, v11); // fsqrt d11, d11
529 __ fcvtd(v22, v28); // fcvt s22, d28
530
531 // FloatConvertOp
532 __ fcvtzsw(r28, v22); // fcvtzs w28, s22
533 __ fcvtzs(r20, v27); // fcvtzs x20, s27
534 __ fcvtzdw(r14, v0); // fcvtzs w14, d0
535 __ fcvtzd(r26, v11); // fcvtzs x26, d11
536 __ scvtfws(v28, r22); // scvtf s28, w22
537 __ scvtfs(v16, r10); // scvtf s16, x10
538 __ scvtfwd(v8, r21); // scvtf d8, w21
539 __ scvtfd(v21, r28); // scvtf d21, x28
540 __ fmovs(r24, v24); // fmov w24, s24
541 __ fmovd(r8, v19); // fmov x8, d19
542 __ fmovs(v8, r12); // fmov s8, w12
543 __ fmovd(v6, r7); // fmov d6, x7
544
545 // TwoRegFloatOp
546 __ fcmps(v30, v16); // fcmp s30, s16
547 __ fcmpd(v25, v11); // fcmp d25, d11
548 __ fcmps(v11, 0.0); // fcmp s11, #0.0
549 __ fcmpd(v11, 0.0); // fcmp d11, #0.0
550
551 // LoadStorePairOp
552 __ stpw(r29, r12, Address(r17, 128)); // stp w29, w12, [x17, #128]
553 __ ldpw(r22, r18, Address(r14, -96)); // ldp w22, w18, [x14, #-96]
554 __ ldpsw(r11, r16, Address(r1, 64)); // ldpsw x11, x16, [x1, #64]
555 __ stp(r0, r11, Address(r26, 112)); // stp x0, x11, [x26, #112]
556 __ ldp(r7, r1, Address(r26, 16)); // ldp x7, x1, [x26, #16]
557
558 // LoadStorePairOp
559 __ stpw(r10, r7, Address(__ pre(r24, 0))); // stp w10, w7, [x24, #0]!
560 __ ldpw(r7, r28, Address(__ pre(r24, -256))); // ldp w7, w28, [x24, #-256]!
561 __ ldpsw(r25, r28, Address(__ pre(r21, -240))); // ldpsw x25, x28, [x21, #-240]!
562 __ stp(r20, r18, Address(__ pre(r14, -16))); // stp x20, x18, [x14, #-16]!
563 __ ldp(r8, r10, Address(__ pre(r13, 80))); // ldp x8, x10, [x13, #80]!
564
565 // LoadStorePairOp
566 __ stpw(r26, r24, Address(__ post(r2, -128))); // stp w26, w24, [x2], #-128
567 __ ldpw(r2, r25, Address(__ post(r21, -192))); // ldp w2, w25, [x21], #-192
568 __ ldpsw(r17, r2, Address(__ post(r21, -144))); // ldpsw x17, x2, [x21], #-144
569 __ stp(r12, r10, Address(__ post(r11, 96))); // stp x12, x10, [x11], #96
570 __ ldp(r24, r6, Address(__ post(r17, -32))); // ldp x24, x6, [x17], #-32
571
572 // LoadStorePairOp
573 __ stnpw(r3, r30, Address(r14, -224)); // stnp w3, w30, [x14, #-224]
574 __ ldnpw(r15, r20, Address(r26, -144)); // ldnp w15, w20, [x26, #-144]
575 __ stnp(r22, r25, Address(r12, -128)); // stnp x22, x25, [x12, #-128]
576 __ ldnp(r27, r22, Address(r17, -176)); // ldnp x27, x22, [x17, #-176]
577
578 // FloatImmediateOp
579 __ fmovd(v0, 2.0); // fmov d0, #2.0
580 __ fmovd(v0, 2.125); // fmov d0, #2.125
581 __ fmovd(v0, 4.0); // fmov d0, #4.0
582 __ fmovd(v0, 4.25); // fmov d0, #4.25
583 __ fmovd(v0, 8.0); // fmov d0, #8.0
584 __ fmovd(v0, 8.5); // fmov d0, #8.5
585 __ fmovd(v0, 16.0); // fmov d0, #16.0
586 __ fmovd(v0, 17.0); // fmov d0, #17.0
587 __ fmovd(v0, 0.125); // fmov d0, #0.125
588 __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125
589 __ fmovd(v0, 0.25); // fmov d0, #0.25
590 __ fmovd(v0, 0.265625); // fmov d0, #0.265625
591 __ fmovd(v0, 0.5); // fmov d0, #0.5
592 __ fmovd(v0, 0.53125); // fmov d0, #0.53125
593 __ fmovd(v0, 1.0); // fmov d0, #1.0
594 __ fmovd(v0, 1.0625); // fmov d0, #1.0625
595 __ fmovd(v0, -2.0); // fmov d0, #-2.0
596 __ fmovd(v0, -2.125); // fmov d0, #-2.125
597 __ fmovd(v0, -4.0); // fmov d0, #-4.0
598 __ fmovd(v0, -4.25); // fmov d0, #-4.25
599 __ fmovd(v0, -8.0); // fmov d0, #-8.0
600 __ fmovd(v0, -8.5); // fmov d0, #-8.5
601 __ fmovd(v0, -16.0); // fmov d0, #-16.0
602 __ fmovd(v0, -17.0); // fmov d0, #-17.0
603 __ fmovd(v0, -0.125); // fmov d0, #-0.125
604 __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125
605 __ fmovd(v0, -0.25); // fmov d0, #-0.25
606 __ fmovd(v0, -0.265625); // fmov d0, #-0.265625
607 __ fmovd(v0, -0.5); // fmov d0, #-0.5
608 __ fmovd(v0, -0.53125); // fmov d0, #-0.53125
609 __ fmovd(v0, -1.0); // fmov d0, #-1.0
610 __ fmovd(v0, -1.0625); // fmov d0, #-1.0625
611
612 __ bind(forth);
613
614 /*
615 aarch64ops.o: file format elf64-littleaarch64
616
617
618 Disassembly of section .text:
619
620 0000000000000000 <back>:
621 0: 8b0772d3 add x19, x22, x7, lsl #28
622 4: cb4a3570 sub x16, x11, x10, lsr #13
623 8: ab9c09bb adds x27, x13, x28, asr #2
624 c: eb9aa794 subs x20, x28, x26, asr #41
625 10: 0b934e68 add w8, w19, w19, asr #19
626 14: 4b0a3924 sub w4, w9, w10, lsl #14
627 18: 2b1e3568 adds w8, w11, w30, lsl #13
628 1c: 6b132720 subs w0, w25, w19, lsl #9
629 20: 8a154c14 and x20, x0, x21, lsl #19
630 24: aa1445d5 orr x21, x14, x20, lsl #17
631 28: ca01cf99 eor x25, x28, x1, lsl #51
632 2c: ea8b3f6a ands x10, x27, x11, asr #15
633 30: 0a8c5cb9 and w25, w5, w12, asr #23
634 34: 2a4a11d2 orr w18, w14, w10, lsr #4
635 38: 4a855aa4 eor w4, w21, w5, asr #22
636 3c: 6a857415 ands w21, w0, w5, asr #29
637 40: 8aa697da bic x26, x30, x6, asr #37
638 44: aa6d7423 orn x3, x1, x13, lsr #29
639 48: ca29bf80 eon x0, x28, x9, lsl #47
640 4c: ea3cb8bd bics x29, x5, x28, lsl #46
641 50: 0a675249 bic w9, w18, w7, lsr #20
642 54: 2ab961ba orn w26, w13, w25, asr #24
643 58: 4a331899 eon w25, w4, w19, lsl #6
644 5c: 6a646345 bics w5, w26, w4, lsr #24
645 60: 11055267 add w7, w19, #0x154
646 64: 31064408 adds w8, w0, #0x191
647 68: 51028e9d sub w29, w20, #0xa3
648 6c: 710bdee8 subs w8, w23, #0x2f7
649 70: 91082d81 add x1, x12, #0x20b
650 74: b106a962 adds x2, x11, #0x1aa
651 78: d10b33ae sub x14, x29, #0x2cc
652 7c: f10918ab subs x11, x5, #0x246
653 80: 121102d7 and w23, w22, #0x8000
654 84: 3204cd44 orr w4, w10, #0xf0f0f0f0
655 88: 5204cf00 eor w0, w24, #0xf0f0f0f0
656 8c: 72099fb3 ands w19, w29, #0x7f807f80
657 90: 92729545 and x5, x10, #0xfffffffffc000
658 94: b20e37cc orr x12, x30, #0xfffc0000fffc0000
659 98: d27c34be eor x30, x5, #0x3fff0
660 9c: f27e4efa ands x26, x23, #0x3ffffc
661 a0: 14000000 b a0 <back+0xa0>
662 a4: 17ffffd7 b 0 <back>
663 a8: 1400017f b 6a4 <forth>
664 ac: 94000000 bl ac <back+0xac>
665 b0: 97ffffd4 bl 0 <back>
666 b4: 9400017c bl 6a4 <forth>
667 b8: 3400000c cbz w12, b8 <back+0xb8>
668 bc: 34fffa2c cbz w12, 0 <back>
669 c0: 34002f2c cbz w12, 6a4 <forth>
670 c4: 35000014 cbnz w20, c4 <back+0xc4>
671 c8: 35fff9d4 cbnz w20, 0 <back>
672 cc: 35002ed4 cbnz w20, 6a4 <forth>
673 d0: b400000c cbz x12, d0 <back+0xd0>
674 d4: b4fff96c cbz x12, 0 <back>
675 d8: b4002e6c cbz x12, 6a4 <forth>
676 dc: b5000018 cbnz x24, dc <back+0xdc>
677 e0: b5fff918 cbnz x24, 0 <back>
678 e4: b5002e18 cbnz x24, 6a4 <forth>
679 e8: 10000006 adr x6, e8 <back+0xe8>
680 ec: 10fff8a6 adr x6, 0 <back>
681 f0: 10002da6 adr x6, 6a4 <forth>
682 f4: 90000015 adrp x21, 0 <back>
683 f8: 36080001 tbz w1, #1, f8 <back+0xf8>
684 fc: 360ff821 tbz w1, #1, 0 <back>
685 100: 36082d21 tbz w1, #1, 6a4 <forth>
686 104: 37480008 tbnz w8, #9, 104 <back+0x104>
687 108: 374ff7c8 tbnz w8, #9, 0 <back>
688 10c: 37482cc8 tbnz w8, #9, 6a4 <forth>
689 110: 128b50ec movn w12, #0x5a87
690 114: 52a9ff8b movz w11, #0x4ffc, lsl #16
691 118: 7281d095 movk w21, #0xe84
692 11c: 92edfebd movn x29, #0x6ff5, lsl #48
693 120: d28361e3 movz x3, #0x1b0f
694 124: f2a4cc96 movk x22, #0x2664, lsl #16
695 128: 9346590c sbfx x12, x8, #6, #17
696 12c: 33194f33 bfi w19, w25, #7, #20
697 130: 531d3d89 ubfiz w9, w12, #3, #16
698 134: 9350433c sbfx x28, x25, #16, #1
699 138: b34464ac bfxil x12, x5, #4, #22
700 13c: d3462140 ubfx x0, x10, #6, #3
701 140: 139a61a4 extr w4, w13, w26, #24
702 144: 93d87fd7 extr x23, x30, x24, #31
703 148: 54000000 b.eq 148 <back+0x148>
704 14c: 54fff5a0 b.eq 0 <back>
705 150: 54002aa0 b.eq 6a4 <forth>
706 154: 54000001 b.ne 154 <back+0x154>
707 158: 54fff541 b.ne 0 <back>
708 15c: 54002a41 b.ne 6a4 <forth>
709 160: 54000002 b.cs 160 <back+0x160>
710 164: 54fff4e2 b.cs 0 <back>
711 168: 540029e2 b.cs 6a4 <forth>
712 16c: 54000002 b.cs 16c <back+0x16c>
713 170: 54fff482 b.cs 0 <back>
714 174: 54002982 b.cs 6a4 <forth>
715 178: 54000003 b.cc 178 <back+0x178>
716 17c: 54fff423 b.cc 0 <back>
717 180: 54002923 b.cc 6a4 <forth>
718 184: 54000003 b.cc 184 <back+0x184>
719 188: 54fff3c3 b.cc 0 <back>
720 18c: 540028c3 b.cc 6a4 <forth>
721 190: 54000004 b.mi 190 <back+0x190>
722 194: 54fff364 b.mi 0 <back>
723 198: 54002864 b.mi 6a4 <forth>
724 19c: 54000005 b.pl 19c <back+0x19c>
725 1a0: 54fff305 b.pl 0 <back>
726 1a4: 54002805 b.pl 6a4 <forth>
727 1a8: 54000006 b.vs 1a8 <back+0x1a8>
728 1ac: 54fff2a6 b.vs 0 <back>
729 1b0: 540027a6 b.vs 6a4 <forth>
730 1b4: 54000007 b.vc 1b4 <back+0x1b4>
731 1b8: 54fff247 b.vc 0 <back>
732 1bc: 54002747 b.vc 6a4 <forth>
733 1c0: 54000008 b.hi 1c0 <back+0x1c0>
734 1c4: 54fff1e8 b.hi 0 <back>
735 1c8: 540026e8 b.hi 6a4 <forth>
736 1cc: 54000009 b.ls 1cc <back+0x1cc>
737 1d0: 54fff189 b.ls 0 <back>
738 1d4: 54002689 b.ls 6a4 <forth>
739 1d8: 5400000a b.ge 1d8 <back+0x1d8>
740 1dc: 54fff12a b.ge 0 <back>
741 1e0: 5400262a b.ge 6a4 <forth>
742 1e4: 5400000b b.lt 1e4 <back+0x1e4>
743 1e8: 54fff0cb b.lt 0 <back>
744 1ec: 540025cb b.lt 6a4 <forth>
745 1f0: 5400000c b.gt 1f0 <back+0x1f0>
746 1f4: 54fff06c b.gt 0 <back>
747 1f8: 5400256c b.gt 6a4 <forth>
748 1fc: 5400000d b.le 1fc <back+0x1fc>
749 200: 54fff00d b.le 0 <back>
750 204: 5400250d b.le 6a4 <forth>
751 208: 5400000e b.al 208 <back+0x208>
752 20c: 54ffefae b.al 0 <back>
753 210: 540024ae b.al 6a4 <forth>
754 214: 5400000f b.nv 214 <back+0x214>
755 218: 54ffef4f b.nv 0 <back>
756 21c: 5400244f b.nv 6a4 <forth>
757 220: d4063721 svc #0x31b9
758 224: d4035082 hvc #0x1a84
759 228: d400bfe3 smc #0x5ff
760 22c: d4282fc0 brk #0x417e
761 230: d444c320 hlt #0x2619
762 234: d503201f nop
763 238: d69f03e0 eret
764 23c: d6bf03e0 drps
765 240: d5033fdf isb
766 244: d5033f9f dsb sy
767 248: d5033abf dmb ishst
768 24c: d61f0040 br x2
769 250: d63f00a0 blr x5
770 254: c8147c55 stxr w20, x21, [x2]
771 258: c807fcfd stlxr w7, x29, [x7]
772 25c: c85f7e05 ldxr x5, [x16]
773 260: c85fffbb ldaxr x27, [x29]
774 264: c89fffa0 stlr x0, [x29]
775 268: c8dfff95 ldar x21, [x28]
776 26c: 88187cf8 stxr w24, w24, [x7]
777 270: 8815ff9a stlxr w21, w26, [x28]
778 274: 885f7cd5 ldxr w21, [x6]
779 278: 885fffcf ldaxr w15, [x30]
780 27c: 889ffc73 stlr w19, [x3]
781 280: 88dffc56 ldar w22, [x2]
782 284: 48127c0f stxrh w18, w15, [x0]
783 288: 480bff85 stlxrh w11, w5, [x28]
784 28c: 485f7cdd ldxrh w29, [x6]
785 290: 485ffcf2 ldaxrh w18, [x7]
786 294: 489fff99 stlrh w25, [x28]
787 298: 48dffe62 ldarh w2, [x19]
788 29c: 080a7c3e stxrb w10, w30, [x1]
789 2a0: 0814fed5 stlxrb w20, w21, [x22]
790 2a4: 085f7c59 ldxrb w25, [x2]
791 2a8: 085ffcb8 ldaxrb w24, [x5]
792 2ac: 089ffc70 stlrb w16, [x3]
793 2b0: 08dfffb6 ldarb w22, [x29]
794 2b4: c87f0a68 ldxp x8, x2, [x19]
795 2b8: c87fcdc7 ldaxp x7, x19, [x14]
796 2bc: c82870bb stxp w8, x27, x28, [x5]
797 2c0: c826b8c8 stlxp w6, x8, x14, [x6]
798 2c4: 887f12d9 ldxp w25, w4, [x22]
799 2c8: 887fb9ee ldaxp w14, w14, [x15]
800 2cc: 8834215a stxp w20, w26, w8, [x10]
801 2d0: 8837ca52 stlxp w23, w18, w18, [x18]
802 2d4: f806317e str x30, [x11,#99]
803 2d8: b81b3337 str w23, [x25,#-77]
804 2dc: 39000dc2 strb w2, [x14,#3]
805 2e0: 78005149 strh w9, [x10,#5]
806 2e4: f84391f4 ldr x20, [x15,#57]
807 2e8: b85b220c ldr w12, [x16,#-78]
808 2ec: 385fd356 ldrb w22, [x26,#-3]
809 2f0: 785d127e ldrh w30, [x19,#-47]
810 2f4: 389f4149 ldrsb x9, [x10,#-12]
811 2f8: 79801e3c ldrsh x28, [x17,#14]
812 2fc: 79c014a3 ldrsh w3, [x5,#10]
813 300: b89a5231 ldrsw x17, [x17,#-91]
814 304: fc5ef282 ldr d2, [x20,#-17]
815 308: bc5f60f6 ldr s22, [x7,#-10]
816 30c: fc12125e str d30, [x18,#-223]
817 310: bc0152cd str s13, [x22,#21]
818 314: f8190e49 str x9, [x18,#-112]!
819 318: b800befd str w29, [x23,#11]!
820 31c: 381ffd92 strb w18, [x12,#-1]!
821 320: 781e9e90 strh w16, [x20,#-23]!
822 324: f8409fa3 ldr x3, [x29,#9]!
823 328: b8413c79 ldr w25, [x3,#19]!
824 32c: 385fffa1 ldrb w1, [x29,#-1]!
825 330: 785c7fa8 ldrh w8, [x29,#-57]!
826 334: 389f3dc5 ldrsb x5, [x14,#-13]!
827 338: 78801f6a ldrsh x10, [x27,#1]!
828 33c: 78c19d4b ldrsh w11, [x10,#25]!
829 340: b89a4ec4 ldrsw x4, [x22,#-92]!
830 344: fc408eeb ldr d11, [x23,#8]!
831 348: bc436e79 ldr s25, [x19,#54]!
832 34c: fc152ce1 str d1, [x7,#-174]!
833 350: bc036f28 str s8, [x25,#54]!
834 354: f8025565 str x5, [x11],#37
835 358: b80135f8 str w24, [x15],#19
836 35c: 381ff74f strb w15, [x26],#-1
837 360: 781fa652 strh w18, [x18],#-6
838 364: f851a447 ldr x7, [x2],#-230
839 368: b85e557b ldr w27, [x11],#-27
840 36c: 385e7472 ldrb w18, [x3],#-25
841 370: 785e070a ldrh w10, [x24],#-32
842 374: 38804556 ldrsb x22, [x10],#4
843 378: 78819591 ldrsh x17, [x12],#25
844 37c: 78dc24e8 ldrsh w8, [x7],#-62
845 380: b89cd6d7 ldrsw x23, [x22],#-51
846 384: fc430738 ldr d24, [x25],#48
847 388: bc5f6595 ldr s21, [x12],#-10
848 38c: fc1225b2 str d18, [x13],#-222
849 390: bc1d7430 str s16, [x1],#-41
850 394: f82fcac2 str x2, [x22,w15,sxtw]
851 398: b83d6a02 str w2, [x16,x29]
852 39c: 382e5a54 strb w20, [x18,w14,uxtw #0]
853 3a0: 7834fa66 strh w6, [x19,x20,sxtx #1]
854 3a4: f86ecbae ldr x14, [x29,w14,sxtw]
855 3a8: b86cda90 ldr w16, [x20,w12,sxtw #2]
856 3ac: 3860d989 ldrb w9, [x12,w0,sxtw #0]
857 3b0: 78637a2c ldrh w12, [x17,x3,lsl #1]
858 3b4: 38a3fa22 ldrsb x2, [x17,x3,sxtx #0]
859 3b8: 78b15827 ldrsh x7, [x1,w17,uxtw #1]
860 3bc: 78f2d9f9 ldrsh w25, [x15,w18,sxtw #1]
861 3c0: b8ac6ab7 ldrsw x23, [x21,x12]
862 3c4: fc6879a5 ldr d5, [x13,x8,lsl #3]
863 3c8: bc767943 ldr s3, [x10,x22,lsl #2]
864 3cc: fc3bc84e str d14, [x2,w27,sxtw]
865 3d0: bc3968d4 str s20, [x6,x25]
866 3d4: f91fc0fe str x30, [x7,#16256]
867 3d8: b91da50f str w15, [x8,#7588]
868 3dc: 391d280b strb w11, [x0,#1866]
869 3e0: 791d2e23 strh w3, [x17,#3734]
870 3e4: f95bc8e2 ldr x2, [x7,#14224]
871 3e8: b95ce525 ldr w5, [x9,#7396]
872 3ec: 395ae53c ldrb w28, [x9,#1721]
873 3f0: 795c9282 ldrh w2, [x20,#3656]
874 3f4: 399d7dd6 ldrsb x22, [x14,#1887]
875 3f8: 799fe008 ldrsh x8, [x0,#4080]
876 3fc: 79de9bc0 ldrsh w0, [x30,#3916]
877 400: b99aae78 ldrsw x24, [x19,#6828]
878 404: fd597598 ldr d24, [x12,#13032]
879 408: bd5d1d08 ldr s8, [x8,#7452]
880 40c: fd1f3dea str d10, [x15,#15992]
881 410: bd1a227a str s26, [x19,#6688]
882 414: 5800148a ldr x10, 6a4 <forth>
883 418: 18000003 ldr w3, 418 <back+0x418>
884 41c: f88092e0 prfm pldl1keep, [x23,#9]
885 420: d8ffdf00 prfm pldl1keep, 0 <back>
886 424: f8a84860 prfm pldl1keep, [x3,w8,uxtw]
887 428: f99d7560 prfm pldl1keep, [x11,#15080]
888 42c: 1a1c012d adc w13, w9, w28
889 430: 3a1c027b adcs w27, w19, w28
890 434: 5a060253 sbc w19, w18, w6
891 438: 7a03028e sbcs w14, w20, w3
892 43c: 9a0801d0 adc x16, x14, x8
893 440: ba0803a0 adcs x0, x29, x8
894 444: da140308 sbc x8, x24, x20
895 448: fa00038c sbcs x12, x28, x0
896 44c: 0b3010d7 add w23, w6, w16, uxtb #4
897 450: 2b37ab39 adds w25, w25, w23, sxth #2
898 454: cb2466da sub x26, x22, x4, uxtx #1
899 458: 6b33efb1 subs w17, w29, w19, sxtx #3
900 45c: 8b350fcb add x11, x30, w21, uxtb #3
901 460: ab208a70 adds x16, x19, w0, sxtb #2
902 464: cb39e52b sub x11, x9, x25, sxtx #1
903 468: eb2c9291 subs x17, x20, w12, sxtb #4
904 46c: 3a4bd1a3 ccmn w13, w11, #0x3, le
905 470: 7a4c81a2 ccmp w13, w12, #0x2, hi
906 474: ba42106c ccmn x3, x2, #0xc, ne
907 478: fa5560e3 ccmp x7, x21, #0x3, vs
908 47c: 3a4e3844 ccmn w2, #0xe, #0x4, cc
909 480: 7a515a26 ccmp w17, #0x11, #0x6, pl
910 484: ba4c2940 ccmn x10, #0xc, #0x0, cs
911 488: fa52aaae ccmp x21, #0x12, #0xe, ge
912 48c: 1a8cc1b5 csel w21, w13, w12, gt
913 490: 1a8f976a csinc w10, w27, w15, ls
914 494: 5a8981a0 csinv w0, w13, w9, hi
915 498: 5a9a6492 csneg w18, w4, w26, vs
916 49c: 9a8793ac csel x12, x29, x7, ls
917 4a0: 9a9474e6 csinc x6, x7, x20, vc
918 4a4: da83d2b6 csinv x22, x21, x3, le
919 4a8: da9b9593 csneg x19, x12, x27, ls
920 4ac: 5ac00200 rbit w0, w16
921 4b0: 5ac006f1 rev16 w17, w23
922 4b4: 5ac009d1 rev w17, w14
923 4b8: 5ac013d8 clz w24, w30
924 4bc: 5ac016d8 cls w24, w22
925 4c0: dac00223 rbit x3, x17
926 4c4: dac005ac rev16 x12, x13
927 4c8: dac00ac9 rev32 x9, x22
928 4cc: dac00c00 rev x0, x0
929 4d0: dac01205 clz x5, x16
930 4d4: dac016d9 cls x25, x22
931 4d8: 1ac0089d udiv w29, w4, w0
932 4dc: 1add0fa0 sdiv w0, w29, w29
933 4e0: 1ad52225 lsl w5, w17, w21
934 4e4: 1ad22529 lsr w9, w9, w18
935 4e8: 1ac82b61 asr w1, w27, w8
936 4ec: 1acd2e92 ror w18, w20, w13
937 4f0: 9acc0b28 udiv x8, x25, x12
938 4f4: 9adc0ca7 sdiv x7, x5, x28
939 4f8: 9adb2225 lsl x5, x17, x27
940 4fc: 9ad42757 lsr x23, x26, x20
941 500: 9adc291c asr x28, x8, x28
942 504: 9ac42fa3 ror x3, x29, x4
943 508: 1b1a55d1 madd w17, w14, w26, w21
944 50c: 1b0bafc1 msub w1, w30, w11, w11
945 510: 9b067221 madd x1, x17, x6, x28
946 514: 9b1ea0de msub x30, x6, x30, x8
947 518: 9b2e20d5 smaddl x21, w6, w14, x8
948 51c: 9b38cd4a smsubl x10, w10, w24, x19
949 520: 9bae6254 umaddl x20, w18, w14, x24
950 524: 9ba59452 umsubl x18, w2, w5, x5
951 528: 1e2d0a48 fmul s8, s18, s13
952 52c: 1e3c19c2 fdiv s2, s14, s28
953 530: 1e3c298f fadd s15, s12, s28
954 534: 1e213980 fsub s0, s12, s1
955 538: 1e240baf fmul s15, s29, s4
956 53c: 1e77082c fmul d12, d1, d23
957 540: 1e72191b fdiv d27, d8, d18
958 544: 1e6b2a97 fadd d23, d20, d11
959 548: 1e723988 fsub d8, d12, d18
960 54c: 1e770b1a fmul d26, d24, d23
961 550: 1f0d66f5 fmadd s21, s23, s13, s25
962 554: 1f01b956 fmsub s22, s10, s1, s14
963 558: 1f227a8e fnmadd s14, s20, s2, s30
964 55c: 1f365ba7 fnmadd s7, s29, s22, s22
965 560: 1f4f14ad fmadd d13, d5, d15, d5
966 564: 1f45a98e fmsub d14, d12, d5, d10
967 568: 1f60066a fnmadd d10, d19, d0, d1
968 56c: 1f620054 fnmadd d20, d2, d2, d0
969 570: 1e204139 fmov s25, s9
970 574: 1e20c094 fabs s20, s4
971 578: 1e214363 fneg s3, s27
972 57c: 1e21c041 fsqrt s1, s2
973 580: 1e22c01e fcvt d30, s0
974 584: 1e60408c fmov d12, d4
975 588: 1e60c361 fabs d1, d27
976 58c: 1e6142c8 fneg d8, d22
977 590: 1e61c16b fsqrt d11, d11
978 594: 1e624396 fcvt s22, d28
979 598: 1e3802dc fcvtzs w28, s22
980 59c: 9e380374 fcvtzs x20, s27
981 5a0: 1e78000e fcvtzs w14, d0
982 5a4: 9e78017a fcvtzs x26, d11
983 5a8: 1e2202dc scvtf s28, w22
984 5ac: 9e220150 scvtf s16, x10
985 5b0: 1e6202a8 scvtf d8, w21
986 5b4: 9e620395 scvtf d21, x28
987 5b8: 1e260318 fmov w24, s24
988 5bc: 9e660268 fmov x8, d19
989 5c0: 1e270188 fmov s8, w12
990 5c4: 9e6700e6 fmov d6, x7
991 5c8: 1e3023c0 fcmp s30, s16
992 5cc: 1e6b2320 fcmp d25, d11
993 5d0: 1e202168 fcmp s11, #0.0
994 5d4: 1e602168 fcmp d11, #0.0
995 5d8: 2910323d stp w29, w12, [x17,#128]
996 5dc: 297449d6 ldp w22, w18, [x14,#-96]
997 5e0: 6948402b ldpsw x11, x16, [x1,#64]
998 5e4: a9072f40 stp x0, x11, [x26,#112]
999 5e8: a9410747 ldp x7, x1, [x26,#16]
1000 5ec: 29801f0a stp w10, w7, [x24,#0]!
1001 5f0: 29e07307 ldp w7, w28, [x24,#-256]!
1002 5f4: 69e272b9 ldpsw x25, x28, [x21,#-240]!
1003 5f8: a9bf49d4 stp x20, x18, [x14,#-16]!
1004 5fc: a9c529a8 ldp x8, x10, [x13,#80]!
1005 600: 28b0605a stp w26, w24, [x2],#-128
1006 604: 28e866a2 ldp w2, w25, [x21],#-192
1007 608: 68ee0ab1 ldpsw x17, x2, [x21],#-144
1008 60c: a886296c stp x12, x10, [x11],#96
1009 610: a8fe1a38 ldp x24, x6, [x17],#-32
1010 614: 282479c3 stnp w3, w30, [x14,#-224]
1011 618: 286e534f ldnp w15, w20, [x26,#-144]
1012 61c: a8386596 stnp x22, x25, [x12,#-128]
1013 620: a8755a3b ldnp x27, x22, [x17,#-176]
1014 624: 1e601000 fmov d0, #2.000000000000000000e+00
1015 628: 1e603000 fmov d0, #2.125000000000000000e+00
1016 62c: 1e621000 fmov d0, #4.000000000000000000e+00
1017 630: 1e623000 fmov d0, #4.250000000000000000e+00
1018 634: 1e641000 fmov d0, #8.000000000000000000e+00
1019 638: 1e643000 fmov d0, #8.500000000000000000e+00
1020 63c: 1e661000 fmov d0, #1.600000000000000000e+01
1021 640: 1e663000 fmov d0, #1.700000000000000000e+01
1022 644: 1e681000 fmov d0, #1.250000000000000000e-01
1023 648: 1e683000 fmov d0, #1.328125000000000000e-01
1024 64c: 1e6a1000 fmov d0, #2.500000000000000000e-01
1025 650: 1e6a3000 fmov d0, #2.656250000000000000e-01
1026 654: 1e6c1000 fmov d0, #5.000000000000000000e-01
1027 658: 1e6c3000 fmov d0, #5.312500000000000000e-01
1028 65c: 1e6e1000 fmov d0, #1.000000000000000000e+00
1029 660: 1e6e3000 fmov d0, #1.062500000000000000e+00
1030 664: 1e701000 fmov d0, #-2.000000000000000000e+00
1031 668: 1e703000 fmov d0, #-2.125000000000000000e+00
1032 66c: 1e721000 fmov d0, #-4.000000000000000000e+00
1033 670: 1e723000 fmov d0, #-4.250000000000000000e+00
1034 674: 1e741000 fmov d0, #-8.000000000000000000e+00
1035 678: 1e743000 fmov d0, #-8.500000000000000000e+00
1036 67c: 1e761000 fmov d0, #-1.600000000000000000e+01
1037 680: 1e763000 fmov d0, #-1.700000000000000000e+01
1038 684: 1e781000 fmov d0, #-1.250000000000000000e-01
1039 688: 1e783000 fmov d0, #-1.328125000000000000e-01
1040 68c: 1e7a1000 fmov d0, #-2.500000000000000000e-01
1041 690: 1e7a3000 fmov d0, #-2.656250000000000000e-01
1042 694: 1e7c1000 fmov d0, #-5.000000000000000000e-01
1043 698: 1e7c3000 fmov d0, #-5.312500000000000000e-01
1044 69c: 1e7e1000 fmov d0, #-1.000000000000000000e+00
1045 6a0: 1e7e3000 fmov d0, #-1.062500000000000000e+00
1046 */
1047
1048 static const unsigned int insns[] =
1049 {
1050 0x8b0772d3, 0xcb4a3570, 0xab9c09bb, 0xeb9aa794,
1051 0x0b934e68, 0x4b0a3924, 0x2b1e3568, 0x6b132720,
1052 0x8a154c14, 0xaa1445d5, 0xca01cf99, 0xea8b3f6a,
1053 0x0a8c5cb9, 0x2a4a11d2, 0x4a855aa4, 0x6a857415,
1054 0x8aa697da, 0xaa6d7423, 0xca29bf80, 0xea3cb8bd,
1055 0x0a675249, 0x2ab961ba, 0x4a331899, 0x6a646345,
1056 0x11055267, 0x31064408, 0x51028e9d, 0x710bdee8,
1057 0x91082d81, 0xb106a962, 0xd10b33ae, 0xf10918ab,
1058 0x121102d7, 0x3204cd44, 0x5204cf00, 0x72099fb3,
1059 0x92729545, 0xb20e37cc, 0xd27c34be, 0xf27e4efa,
1060 0x14000000, 0x17ffffd7, 0x1400017f, 0x94000000,
1061 0x97ffffd4, 0x9400017c, 0x3400000c, 0x34fffa2c,
1062 0x34002f2c, 0x35000014, 0x35fff9d4, 0x35002ed4,
1063 0xb400000c, 0xb4fff96c, 0xb4002e6c, 0xb5000018,
1064 0xb5fff918, 0xb5002e18, 0x10000006, 0x10fff8a6,
1065 0x10002da6, 0x90000015, 0x36080001, 0x360ff821,
1066 0x36082d21, 0x37480008, 0x374ff7c8, 0x37482cc8,
1067 0x128b50ec, 0x52a9ff8b, 0x7281d095, 0x92edfebd,
1068 0xd28361e3, 0xf2a4cc96, 0x9346590c, 0x33194f33,
1069 0x531d3d89, 0x9350433c, 0xb34464ac, 0xd3462140,
1070 0x139a61a4, 0x93d87fd7, 0x54000000, 0x54fff5a0,
1071 0x54002aa0, 0x54000001, 0x54fff541, 0x54002a41,
1072 0x54000002, 0x54fff4e2, 0x540029e2, 0x54000002,
1073 0x54fff482, 0x54002982, 0x54000003, 0x54fff423,
1074 0x54002923, 0x54000003, 0x54fff3c3, 0x540028c3,
1075 0x54000004, 0x54fff364, 0x54002864, 0x54000005,
1076 0x54fff305, 0x54002805, 0x54000006, 0x54fff2a6,
1077 0x540027a6, 0x54000007, 0x54fff247, 0x54002747,
1078 0x54000008, 0x54fff1e8, 0x540026e8, 0x54000009,
1079 0x54fff189, 0x54002689, 0x5400000a, 0x54fff12a,
1080 0x5400262a, 0x5400000b, 0x54fff0cb, 0x540025cb,
1081 0x5400000c, 0x54fff06c, 0x5400256c, 0x5400000d,
1082 0x54fff00d, 0x5400250d, 0x5400000e, 0x54ffefae,
1083 0x540024ae, 0x5400000f, 0x54ffef4f, 0x5400244f,
1084 0xd4063721, 0xd4035082, 0xd400bfe3, 0xd4282fc0,
1085 0xd444c320, 0xd503201f, 0xd69f03e0, 0xd6bf03e0,
1086 0xd5033fdf, 0xd5033f9f, 0xd5033abf, 0xd61f0040,
1087 0xd63f00a0, 0xc8147c55, 0xc807fcfd, 0xc85f7e05,
1088 0xc85fffbb, 0xc89fffa0, 0xc8dfff95, 0x88187cf8,
1089 0x8815ff9a, 0x885f7cd5, 0x885fffcf, 0x889ffc73,
1090 0x88dffc56, 0x48127c0f, 0x480bff85, 0x485f7cdd,
1091 0x485ffcf2, 0x489fff99, 0x48dffe62, 0x080a7c3e,
1092 0x0814fed5, 0x085f7c59, 0x085ffcb8, 0x089ffc70,
1093 0x08dfffb6, 0xc87f0a68, 0xc87fcdc7, 0xc82870bb,
1094 0xc826b8c8, 0x887f12d9, 0x887fb9ee, 0x8834215a,
1095 0x8837ca52, 0xf806317e, 0xb81b3337, 0x39000dc2,
1096 0x78005149, 0xf84391f4, 0xb85b220c, 0x385fd356,
1097 0x785d127e, 0x389f4149, 0x79801e3c, 0x79c014a3,
1098 0xb89a5231, 0xfc5ef282, 0xbc5f60f6, 0xfc12125e,
1099 0xbc0152cd, 0xf8190e49, 0xb800befd, 0x381ffd92,
1100 0x781e9e90, 0xf8409fa3, 0xb8413c79, 0x385fffa1,
1101 0x785c7fa8, 0x389f3dc5, 0x78801f6a, 0x78c19d4b,
1102 0xb89a4ec4, 0xfc408eeb, 0xbc436e79, 0xfc152ce1,
1103 0xbc036f28, 0xf8025565, 0xb80135f8, 0x381ff74f,
1104 0x781fa652, 0xf851a447, 0xb85e557b, 0x385e7472,
1105 0x785e070a, 0x38804556, 0x78819591, 0x78dc24e8,
1106 0xb89cd6d7, 0xfc430738, 0xbc5f6595, 0xfc1225b2,
1107 0xbc1d7430, 0xf82fcac2, 0xb83d6a02, 0x382e5a54,
1108 0x7834fa66, 0xf86ecbae, 0xb86cda90, 0x3860d989,
1109 0x78637a2c, 0x38a3fa22, 0x78b15827, 0x78f2d9f9,
1110 0xb8ac6ab7, 0xfc6879a5, 0xbc767943, 0xfc3bc84e,
1111 0xbc3968d4, 0xf91fc0fe, 0xb91da50f, 0x391d280b,
1112 0x791d2e23, 0xf95bc8e2, 0xb95ce525, 0x395ae53c,
1113 0x795c9282, 0x399d7dd6, 0x799fe008, 0x79de9bc0,
1114 0xb99aae78, 0xfd597598, 0xbd5d1d08, 0xfd1f3dea,
1115 0xbd1a227a, 0x5800148a, 0x18000003, 0xf88092e0,
1116 0xd8ffdf00, 0xf8a84860, 0xf99d7560, 0x1a1c012d,
1117 0x3a1c027b, 0x5a060253, 0x7a03028e, 0x9a0801d0,
1118 0xba0803a0, 0xda140308, 0xfa00038c, 0x0b3010d7,
1119 0x2b37ab39, 0xcb2466da, 0x6b33efb1, 0x8b350fcb,
1120 0xab208a70, 0xcb39e52b, 0xeb2c9291, 0x3a4bd1a3,
1121 0x7a4c81a2, 0xba42106c, 0xfa5560e3, 0x3a4e3844,
1122 0x7a515a26, 0xba4c2940, 0xfa52aaae, 0x1a8cc1b5,
1123 0x1a8f976a, 0x5a8981a0, 0x5a9a6492, 0x9a8793ac,
1124 0x9a9474e6, 0xda83d2b6, 0xda9b9593, 0x5ac00200,
1125 0x5ac006f1, 0x5ac009d1, 0x5ac013d8, 0x5ac016d8,
1126 0xdac00223, 0xdac005ac, 0xdac00ac9, 0xdac00c00,
1127 0xdac01205, 0xdac016d9, 0x1ac0089d, 0x1add0fa0,
1128 0x1ad52225, 0x1ad22529, 0x1ac82b61, 0x1acd2e92,
1129 0x9acc0b28, 0x9adc0ca7, 0x9adb2225, 0x9ad42757,
1130 0x9adc291c, 0x9ac42fa3, 0x1b1a55d1, 0x1b0bafc1,
1131 0x9b067221, 0x9b1ea0de, 0x9b2e20d5, 0x9b38cd4a,
1132 0x9bae6254, 0x9ba59452, 0x1e2d0a48, 0x1e3c19c2,
1133 0x1e3c298f, 0x1e213980, 0x1e240baf, 0x1e77082c,
1134 0x1e72191b, 0x1e6b2a97, 0x1e723988, 0x1e770b1a,
1135 0x1f0d66f5, 0x1f01b956, 0x1f227a8e, 0x1f365ba7,
1136 0x1f4f14ad, 0x1f45a98e, 0x1f60066a, 0x1f620054,
1137 0x1e204139, 0x1e20c094, 0x1e214363, 0x1e21c041,
1138 0x1e22c01e, 0x1e60408c, 0x1e60c361, 0x1e6142c8,
1139 0x1e61c16b, 0x1e624396, 0x1e3802dc, 0x9e380374,
1140 0x1e78000e, 0x9e78017a, 0x1e2202dc, 0x9e220150,
1141 0x1e6202a8, 0x9e620395, 0x1e260318, 0x9e660268,
1142 0x1e270188, 0x9e6700e6, 0x1e3023c0, 0x1e6b2320,
1143 0x1e202168, 0x1e602168, 0x2910323d, 0x297449d6,
1144 0x6948402b, 0xa9072f40, 0xa9410747, 0x29801f0a,
1145 0x29e07307, 0x69e272b9, 0xa9bf49d4, 0xa9c529a8,
1146 0x28b0605a, 0x28e866a2, 0x68ee0ab1, 0xa886296c,
1147 0xa8fe1a38, 0x282479c3, 0x286e534f, 0xa8386596,
1148 0xa8755a3b, 0x1e601000, 0x1e603000, 0x1e621000,
1149 0x1e623000, 0x1e641000, 0x1e643000, 0x1e661000,
1150 0x1e663000, 0x1e681000, 0x1e683000, 0x1e6a1000,
1151 0x1e6a3000, 0x1e6c1000, 0x1e6c3000, 0x1e6e1000,
1152 0x1e6e3000, 0x1e701000, 0x1e703000, 0x1e721000,
1153 0x1e723000, 0x1e741000, 0x1e743000, 0x1e761000,
1154 0x1e763000, 0x1e781000, 0x1e783000, 0x1e7a1000,
1155 0x1e7a3000, 0x1e7c1000, 0x1e7c3000, 0x1e7e1000,
1156 0x1e7e3000,
1157 };
1158 // END Generated code -- do not edit
1159
1160 {
1161 bool ok = true;
1162 unsigned int *insns1 = (unsigned int *)entry;
1163 for (unsigned int i = 0; i < sizeof insns / sizeof insns[0]; i++) {
1164 if (insns[i] != insns1[i]) {
1165 ok = false;
1166 printf("Ours:\n");
1167 Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]);
1168 printf("Theirs:\n");
1169 Disassembler::decode((address)&insns[i], (address)&insns[i+1]);
1170 printf("\n");
1171 }
1172 }
1173 assert(ok, "Assembler smoke test failed");
1174 }
1175
1176 #ifndef PRODUCT
1177
1178 address PC = __ pc();
1179 __ ld1(v0, __ T16B, Address(r16)); // No offset
1180 __ ld1(v0, __ T16B, __ post(r16, 0)); // Post-index
1181 __ ld1(v0, __ T16B, Address(r16, r17)); //
1182
1183
1184 #endif // PRODUCT
1185 #endif // ASSERT
1186 }
1187
1188 #undef __
1189
1190 void Assembler::emit_data64(jlong data,
1191 relocInfo::relocType rtype,
1192 int format) {
1193 if (rtype == relocInfo::none) {
1194 emit_int64(data);
1195 } else {
1196 emit_data64(data, Relocation::spec_simple(rtype), format);
1197 }
1198 }
1199
1200 void Assembler::emit_data64(jlong data,
1201 RelocationHolder const& rspec,
1202 int format) {
1203
1204 assert(inst_mark() != NULL, "must be inside InstructionMark");
1205 // Do not use AbstractAssembler::relocate, which is not intended for
1206 // embedded words. Instead, relocate to the enclosing instruction.
1207 code_section()->relocate(inst_mark(), rspec, format);
1208 emit_int64(data);
1209 }
1210
1211 extern "C" {
1212 void das(uint64_t start, int len) {
1213 ResourceMark rm;
1214 len <<= 2;
1215 if (len < 0)
1216 Disassembler::decode((address)start + len, (address)start);
1217 else
1218 Disassembler::decode((address)start, (address)start + len);
1219 }
1220
1221 JNIEXPORT void das1(unsigned long insn) {
1222 das(insn, 1);
1223 }
1224 }
1225
1226 #define gas_assert(ARG1) assert(ARG1, #ARG1)
1227
1228 #define __ as->
1229
1230 void Address::lea(MacroAssembler *as, Register r) const {
1231 Relocation* reloc = _rspec.reloc();
1232 relocInfo::relocType rtype = (relocInfo::relocType) reloc->type();
1233
1234 switch(_mode) {
1235 case base_plus_offset: {
1236 if (_offset == 0 && _base == r) // it's a nop
1237 break;
1238 if (_offset > 0)
1239 __ add(r, _base, _offset);
1240 else
1241 __ sub(r, _base, -_offset);
1242 break;
1243 }
1244 case base_plus_offset_reg: {
1245 __ add(r, _base, _index, _ext.op(), MAX(_ext.shift(), 0));
1246 break;
1247 }
1248 case literal: {
1249 if (rtype == relocInfo::none)
1250 __ mov(r, target());
1251 else
1252 __ movptr(r, (uint64_t)target());
1253 break;
1254 }
1255 default:
1256 ShouldNotReachHere();
1257 }
1258 }
1259
1260 void Assembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
1261 ShouldNotReachHere();
1262 }
1263
1264 #undef __
1265
1266 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
1267
1268 void Assembler::adr(Register Rd, address adr) {
1269 long offset = adr - pc();
1270 int offset_lo = offset & 3;
1271 offset >>= 2;
1272 starti;
1273 f(0, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1274 rf(Rd, 0);
1275 }
1276
1277 void Assembler::_adrp(Register Rd, address adr) {
1278 uint64_t pc_page = (uint64_t)pc() >> 12;
1279 uint64_t adr_page = (uint64_t)adr >> 12;
1280 long offset = adr_page - pc_page;
1281 int offset_lo = offset & 3;
1282 offset >>= 2;
1283 starti;
1284 f(1, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1285 rf(Rd, 0);
1286 }
1287
1288 #undef starti
1289
1290 Address::Address(address target, relocInfo::relocType rtype) : _mode(literal){
1291 _is_lval = false;
1292 _target = target;
1293 switch (rtype) {
1294 case relocInfo::oop_type:
1295 case relocInfo::metadata_type:
1296 // Oops are a special case. Normally they would be their own section
1297 // but in cases like icBuffer they are literals in the code stream that
1298 // we don't have a section for. We use none so that we get a literal address
1299 // which is always patchable.
1300 break;
1301 case relocInfo::external_word_type:
1302 _rspec = external_word_Relocation::spec(target);
1303 break;
1304 case relocInfo::internal_word_type:
1305 _rspec = internal_word_Relocation::spec(target);
1306 break;
1307 case relocInfo::opt_virtual_call_type:
1308 _rspec = opt_virtual_call_Relocation::spec();
1309 break;
1310 case relocInfo::static_call_type:
1311 _rspec = static_call_Relocation::spec();
1312 break;
1313 case relocInfo::runtime_call_type:
1314 _rspec = runtime_call_Relocation::spec();
1315 break;
1316 case relocInfo::poll_type:
1317 case relocInfo::poll_return_type:
1318 _rspec = Relocation::spec_simple(rtype);
1319 break;
1320 case relocInfo::none:
1321 _rspec = RelocationHolder::none;
1322 break;
1323 default:
1324 ShouldNotReachHere();
1325 break;
1326 }
1327 }
1328
1329 void Assembler::b(const Address &dest) {
1330 code_section()->relocate(pc(), dest.rspec());
1331 b(dest.target());
1332 }
1333
1334 void Assembler::bl(const Address &dest) {
1335 code_section()->relocate(pc(), dest.rspec());
1336 bl(dest.target());
1337 }
1338
1339 void Assembler::adr(Register r, const Address &dest) {
1340 code_section()->relocate(pc(), dest.rspec());
1341 adr(r, dest.target());
1342 }
1343
1344 void Assembler::br(Condition cc, Label &L) {
1345 if (L.is_bound()) {
1346 br(cc, target(L));
1347 } else {
1348 L.add_patch_at(code(), locator());
1349 br(cc, pc());
1350 }
1351 }
1352
1353 void Assembler::wrap_label(Label &L,
1354 Assembler::uncond_branch_insn insn) {
1355 if (L.is_bound()) {
1356 (this->*insn)(target(L));
1357 } else {
1358 L.add_patch_at(code(), locator());
1359 (this->*insn)(pc());
1360 }
1361 }
1362
1363 void Assembler::wrap_label(Register r, Label &L,
1364 compare_and_branch_insn insn) {
1365 if (L.is_bound()) {
1366 (this->*insn)(r, target(L));
1367 } else {
1368 L.add_patch_at(code(), locator());
1369 (this->*insn)(r, pc());
1370 }
1371 }
1372
1373 void Assembler::wrap_label(Register r, int bitpos, Label &L,
1374 test_and_branch_insn insn) {
1375 if (L.is_bound()) {
1376 (this->*insn)(r, bitpos, target(L));
1377 } else {
1378 L.add_patch_at(code(), locator());
1379 (this->*insn)(r, bitpos, pc());
1380 }
1381 }
1382
1383 void Assembler::wrap_label(Label &L, prfop op, prefetch_insn insn) {
1384 if (L.is_bound()) {
1385 (this->*insn)(target(L), op);
1386 } else {
1387 L.add_patch_at(code(), locator());
1388 (this->*insn)(pc(), op);
1389 }
1390 }
1391
1392 // An "all-purpose" add/subtract immediate, per ARM documentation:
1393 // A "programmer-friendly" assembler may accept a negative immediate
1394 // between -(2^24 -1) and -1 inclusive, causing it to convert a
1395 // requested ADD operation to a SUB, or vice versa, and then encode
1396 // the absolute value of the immediate as for uimm24.
1397 void Assembler::add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
1398 int negated_op) {
1399 bool sets_flags = op & 1; // this op sets flags
1400 union {
1401 unsigned u;
1402 int imm;
1403 };
1404 u = uimm;
1405 bool shift = false;
1406 bool neg = imm < 0;
1407 if (neg) {
1408 imm = -imm;
1409 op = negated_op;
1410 }
1411 assert(Rd != sp || imm % 16 == 0, "misaligned stack");
1412 if (imm >= (1 << 11)
1413 && ((imm >> 12) << 12 == imm)) {
1414 imm >>= 12;
1415 shift = true;
1416 }
1417 f(op, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10);
1418
1419 // add/subtract immediate ops with the S bit set treat r31 as zr;
1420 // with S unset they use sp.
1421 if (sets_flags)
1422 zrf(Rd, 0);
1423 else
1424 srf(Rd, 0);
1425
1426 srf(Rn, 5);
1427 }
1428
1429 bool Assembler::operand_valid_for_add_sub_immediate(long imm) {
1430 bool shift = false;
1431 unsigned long uimm = uabs(imm);
1432 if (uimm < (1 << 12))
1433 return true;
1434 if (uimm < (1 << 24)
1435 && ((uimm >> 12) << 12 == uimm)) {
1436 return true;
1437 }
1438 return false;
1439 }
1440
1441 bool Assembler::operand_valid_for_logical_immediate(bool is32, uint64_t imm) {
1442 return encode_logical_immediate(is32, imm) != 0xffffffff;
1443 }
1444
1445 static uint64_t doubleTo64Bits(jdouble d) {
1446 union {
1447 jdouble double_value;
1448 uint64_t double_bits;
1449 };
1450
1451 double_value = d;
1452 return double_bits;
1453 }
1454
1455 bool Assembler::operand_valid_for_float_immediate(double imm) {
1456 // If imm is all zero bits we can use ZR as the source of a
1457 // floating-point value.
1458 if (doubleTo64Bits(imm) == 0)
1459 return true;
1460
1461 // Otherwise try to encode imm then convert the encoded value back
1462 // and make sure it's the exact same bit pattern.
1463 unsigned result = encoding_for_fp_immediate(imm);
1464 return doubleTo64Bits(imm) == fp_immediate_for_encoding(result, true);
1465 }
1466
1467 int AbstractAssembler::code_fill_byte() {
1468 return 0;
1469 }
1470
1471 // n.b. this is implemented in subclass MacroAssembler
1472 void Assembler::bang_stack_with_offset(int offset) { Unimplemented(); }
1473
1474
1475 // these are the functions provided by the simulator which are used to
1476 // encode and decode logical immediates and floating point immediates
1477 //
1478 // u_int64_t logical_immediate_for_encoding(u_int32_t encoding);
1479 //
1480 // u_int32_t encoding_for_logical_immediate(u_int64_t immediate);
1481 //
1482 // u_int64_t fp_immediate_for_encoding(u_int32_t imm8, int is_dp);
1483 //
1484 // u_int32_t encoding_for_fp_immediate(float immediate);
1485 //
1486 // we currently import these from the simulator librray but the
1487 // definitions will need to be moved to here when we switch to real
1488 // hardware.
1489
1490 // and now the routines called by the assembler which encapsulate the
1491 // above encode and decode functions
1492
1493 uint32_t
1494 asm_util::encode_logical_immediate(bool is32, uint64_t imm)
1495 {
1496 if (is32) {
1497 /* Allow all zeros or all ones in top 32-bits, so that
1498 constant expressions like ~1 are permitted. */
1499 if (imm >> 32 != 0 && imm >> 32 != 0xffffffff)
1500 return 0xffffffff;
1501 /* Replicate the 32 lower bits to the 32 upper bits. */
1502 imm &= 0xffffffff;
1503 imm |= imm << 32;
1504 }
1505
1506 return encoding_for_logical_immediate(imm);
1507 }
1508
1509 unsigned Assembler::pack(double value) {
1510 float val = (float)value;
1511 unsigned result = encoding_for_fp_immediate(val);
1512 guarantee(unpack(result) == value,
1513 "Invalid floating-point immediate operand");
1514 return result;
1515 }
1516
1517 // Packed operands for Floating-point Move (immediate)
1518
1519 static float unpack(unsigned value) {
1520 union {
1521 unsigned ival;
1522 float val;
1523 };
1524 ival = fp_immediate_for_encoding(value, 0);
1525 return val;
1526 }