src/cpu/aarch64/vm/assembler_aarch64.hpp

rev 8692 : 8131483: aarch64: illegal stlxr instructions
Summary: Do not generate stlxX with Ws == Xn
Reviewed-by: aph

@@ -1104,15 +1104,17 @@
     rf(Rs, 16), f(o0, 15), rf(Rt2, 10), rf(Rn, 5), rf(Rt1, 0);
   }
 
 #define INSN4(NAME, sz, op, o0) /* Four registers */                    \
   void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) {     \
+    assert(Rs != Rn, "unpredictable instruction");                  \
     load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0);                 \
   }
 
 #define INSN3(NAME, sz, op, o0) /* Three registers */                   \
   void NAME(Register Rs, Register Rt, Register Rn) {                    \
+    assert(Rs != Rn, "unpredictable instruction");                  \
     load_store_exclusive(Rs, Rt, (Register)0b11111, Rn, sz, op, o0);    \
   }
 
 #define INSN2(NAME, sz, op, o0) /* Two registers */                     \
   void NAME(Register Rt, Register Rn) {                                 \