1 /* 2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP 27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP 28 29 #include "asm/assembler.hpp" 30 31 // MacroAssembler extends Assembler by frequently used macros. 32 // 33 // Instructions for which a 'better' code sequence exists depending 34 // on arguments should also go in here. 35 36 class MacroAssembler: public Assembler { 37 friend class LIR_Assembler; 38 39 public: 40 using Assembler::mov; 41 using Assembler::movi; 42 43 protected: 44 45 // Support for VM calls 46 // 47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 48 // may customize this version by overriding it for its purposes (e.g., to save/restore 49 // additional registers when doing a VM call). 50 #ifdef CC_INTERP 51 // c++ interpreter never wants to use interp_masm version of call_VM 52 #define VIRTUAL 53 #else 54 #define VIRTUAL virtual 55 #endif 56 57 VIRTUAL void call_VM_leaf_base( 58 address entry_point, // the entry point 59 int number_of_arguments, // the number of arguments to pop after the call 60 Label *retaddr = NULL 61 ); 62 63 VIRTUAL void call_VM_leaf_base( 64 address entry_point, // the entry point 65 int number_of_arguments, // the number of arguments to pop after the call 66 Label &retaddr) { 67 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr); 68 } 69 70 // This is the base routine called by the different versions of call_VM. The interpreter 71 // may customize this version by overriding it for its purposes (e.g., to save/restore 72 // additional registers when doing a VM call). 73 // 74 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base 75 // returns the register which contains the thread upon return. If a thread register has been 76 // specified, the return value will correspond to that register. If no last_java_sp is specified 77 // (noreg) than rsp will be used instead. 78 VIRTUAL void call_VM_base( // returns the register containing the thread upon return 79 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 80 Register java_thread, // the thread if computed before ; use noreg otherwise 81 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 82 address entry_point, // the entry point 83 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 84 bool check_exceptions // whether to check for pending exceptions after return 85 ); 86 87 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 88 // The implementation is only non-empty for the InterpreterMacroAssembler, 89 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 90 virtual void check_and_handle_popframe(Register java_thread); 91 virtual void check_and_handle_earlyret(Register java_thread); 92 93 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 94 95 // Maximum size of class area in Metaspace when compressed 96 uint64_t use_XOR_for_compressed_class_base; 97 98 public: 99 MacroAssembler(CodeBuffer* code) : Assembler(code) { 100 use_XOR_for_compressed_class_base 101 = (operand_valid_for_logical_immediate(false /*is32*/, 102 (uint64_t)Universe::narrow_klass_base()) 103 && ((uint64_t)Universe::narrow_klass_base() 104 > (1u << log2_intptr(CompressedClassSpaceSize)))); 105 } 106 107 // Biased locking support 108 // lock_reg and obj_reg must be loaded up with the appropriate values. 109 // swap_reg is killed. 110 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will 111 // be killed; if not supplied, push/pop will be used internally to 112 // allocate a temporary (inefficient, avoid if possible). 113 // Optional slow case is for implementations (interpreter and C1) which branch to 114 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. 115 // Returns offset of first potentially-faulting instruction for null 116 // check info (currently consumed only by C1). If 117 // swap_reg_contains_mark is true then returns -1 as it is assumed 118 // the calling code has already passed any potential faults. 119 int biased_locking_enter(Register lock_reg, Register obj_reg, 120 Register swap_reg, Register tmp_reg, 121 bool swap_reg_contains_mark, 122 Label& done, Label* slow_case = NULL, 123 BiasedLockingCounters* counters = NULL); 124 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); 125 126 127 // Helper functions for statistics gathering. 128 // Unconditional atomic increment. 129 void atomic_incw(Register counter_addr, Register tmp); 130 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2) { 131 lea(tmp1, counter_addr); 132 atomic_incw(tmp1, tmp2); 133 } 134 // Load Effective Address 135 void lea(Register r, const Address &a) { 136 InstructionMark im(this); 137 code_section()->relocate(inst_mark(), a.rspec()); 138 a.lea(this, r); 139 } 140 141 void addmw(Address a, Register incr, Register scratch) { 142 ldrw(scratch, a); 143 addw(scratch, scratch, incr); 144 strw(scratch, a); 145 } 146 147 // Add constant to memory word 148 void addmw(Address a, int imm, Register scratch) { 149 ldrw(scratch, a); 150 if (imm > 0) 151 addw(scratch, scratch, (unsigned)imm); 152 else 153 subw(scratch, scratch, (unsigned)-imm); 154 strw(scratch, a); 155 } 156 157 // Frame creation and destruction shared between JITs. 158 void build_frame(int framesize); 159 void remove_frame(int framesize); 160 161 virtual void _call_Unimplemented(address call_site) { 162 mov(rscratch2, call_site); 163 haltsim(); 164 } 165 166 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__) 167 168 virtual void notify(int type); 169 170 // aliases defined in AARCH64 spec 171 172 template<class T> 173 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); } 174 inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); } 175 176 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); } 177 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); } 178 179 void cset(Register Rd, Assembler::Condition cond) { 180 csinc(Rd, zr, zr, ~cond); 181 } 182 void csetw(Register Rd, Assembler::Condition cond) { 183 csincw(Rd, zr, zr, ~cond); 184 } 185 186 void cneg(Register Rd, Register Rn, Assembler::Condition cond) { 187 csneg(Rd, Rn, Rn, ~cond); 188 } 189 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) { 190 csnegw(Rd, Rn, Rn, ~cond); 191 } 192 193 inline void movw(Register Rd, Register Rn) { 194 if (Rd == sp || Rn == sp) { 195 addw(Rd, Rn, 0U); 196 } else { 197 orrw(Rd, zr, Rn); 198 } 199 } 200 inline void mov(Register Rd, Register Rn) { 201 assert(Rd != r31_sp && Rn != r31_sp, "should be"); 202 if (Rd == Rn) { 203 } else if (Rd == sp || Rn == sp) { 204 add(Rd, Rn, 0U); 205 } else { 206 orr(Rd, zr, Rn); 207 } 208 } 209 210 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); } 211 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); } 212 213 inline void tstw(Register Rd, unsigned imm) { andsw(zr, Rd, imm); } 214 inline void tst(Register Rd, unsigned imm) { ands(zr, Rd, imm); } 215 216 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 217 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 218 } 219 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) { 220 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 221 } 222 223 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 224 bfmw(Rd, Rn, lsb, (lsb + width - 1)); 225 } 226 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) { 227 bfm(Rd, Rn, lsb , (lsb + width - 1)); 228 } 229 230 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 231 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 232 } 233 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 234 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 235 } 236 237 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 238 sbfmw(Rd, Rn, lsb, (lsb + width - 1)); 239 } 240 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 241 sbfm(Rd, Rn, lsb , (lsb + width - 1)); 242 } 243 244 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 245 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 246 } 247 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 248 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 249 } 250 251 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 252 ubfmw(Rd, Rn, lsb, (lsb + width - 1)); 253 } 254 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 255 ubfm(Rd, Rn, lsb , (lsb + width - 1)); 256 } 257 258 inline void asrw(Register Rd, Register Rn, unsigned imm) { 259 sbfmw(Rd, Rn, imm, 31); 260 } 261 262 inline void asr(Register Rd, Register Rn, unsigned imm) { 263 sbfm(Rd, Rn, imm, 63); 264 } 265 266 inline void lslw(Register Rd, Register Rn, unsigned imm) { 267 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm)); 268 } 269 270 inline void lsl(Register Rd, Register Rn, unsigned imm) { 271 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm)); 272 } 273 274 inline void lsrw(Register Rd, Register Rn, unsigned imm) { 275 ubfmw(Rd, Rn, imm, 31); 276 } 277 278 inline void lsr(Register Rd, Register Rn, unsigned imm) { 279 ubfm(Rd, Rn, imm, 63); 280 } 281 282 inline void rorw(Register Rd, Register Rn, unsigned imm) { 283 extrw(Rd, Rn, Rn, imm); 284 } 285 286 inline void ror(Register Rd, Register Rn, unsigned imm) { 287 extr(Rd, Rn, Rn, imm); 288 } 289 290 inline void sxtbw(Register Rd, Register Rn) { 291 sbfmw(Rd, Rn, 0, 7); 292 } 293 inline void sxthw(Register Rd, Register Rn) { 294 sbfmw(Rd, Rn, 0, 15); 295 } 296 inline void sxtb(Register Rd, Register Rn) { 297 sbfm(Rd, Rn, 0, 7); 298 } 299 inline void sxth(Register Rd, Register Rn) { 300 sbfm(Rd, Rn, 0, 15); 301 } 302 inline void sxtw(Register Rd, Register Rn) { 303 sbfm(Rd, Rn, 0, 31); 304 } 305 306 inline void uxtbw(Register Rd, Register Rn) { 307 ubfmw(Rd, Rn, 0, 7); 308 } 309 inline void uxthw(Register Rd, Register Rn) { 310 ubfmw(Rd, Rn, 0, 15); 311 } 312 inline void uxtb(Register Rd, Register Rn) { 313 ubfm(Rd, Rn, 0, 7); 314 } 315 inline void uxth(Register Rd, Register Rn) { 316 ubfm(Rd, Rn, 0, 15); 317 } 318 inline void uxtw(Register Rd, Register Rn) { 319 ubfm(Rd, Rn, 0, 31); 320 } 321 322 inline void cmnw(Register Rn, Register Rm) { 323 addsw(zr, Rn, Rm); 324 } 325 inline void cmn(Register Rn, Register Rm) { 326 adds(zr, Rn, Rm); 327 } 328 329 inline void cmpw(Register Rn, Register Rm) { 330 subsw(zr, Rn, Rm); 331 } 332 inline void cmp(Register Rn, Register Rm) { 333 subs(zr, Rn, Rm); 334 } 335 336 inline void negw(Register Rd, Register Rn) { 337 subw(Rd, zr, Rn); 338 } 339 340 inline void neg(Register Rd, Register Rn) { 341 sub(Rd, zr, Rn); 342 } 343 344 inline void negsw(Register Rd, Register Rn) { 345 subsw(Rd, zr, Rn); 346 } 347 348 inline void negs(Register Rd, Register Rn) { 349 subs(Rd, zr, Rn); 350 } 351 352 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 353 addsw(zr, Rn, Rm, kind, shift); 354 } 355 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 356 adds(zr, Rn, Rm, kind, shift); 357 } 358 359 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 360 subsw(zr, Rn, Rm, kind, shift); 361 } 362 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 363 subs(zr, Rn, Rm, kind, shift); 364 } 365 366 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 367 subw(Rd, zr, Rn, kind, shift); 368 } 369 370 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 371 sub(Rd, zr, Rn, kind, shift); 372 } 373 374 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 375 subsw(Rd, zr, Rn, kind, shift); 376 } 377 378 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 379 subs(Rd, zr, Rn, kind, shift); 380 } 381 382 inline void mnegw(Register Rd, Register Rn, Register Rm) { 383 msubw(Rd, Rn, Rm, zr); 384 } 385 inline void mneg(Register Rd, Register Rn, Register Rm) { 386 msub(Rd, Rn, Rm, zr); 387 } 388 389 inline void mulw(Register Rd, Register Rn, Register Rm) { 390 maddw(Rd, Rn, Rm, zr); 391 } 392 inline void mul(Register Rd, Register Rn, Register Rm) { 393 madd(Rd, Rn, Rm, zr); 394 } 395 396 inline void smnegl(Register Rd, Register Rn, Register Rm) { 397 smsubl(Rd, Rn, Rm, zr); 398 } 399 inline void smull(Register Rd, Register Rn, Register Rm) { 400 smaddl(Rd, Rn, Rm, zr); 401 } 402 403 inline void umnegl(Register Rd, Register Rn, Register Rm) { 404 umsubl(Rd, Rn, Rm, zr); 405 } 406 inline void umull(Register Rd, Register Rn, Register Rm) { 407 umaddl(Rd, Rn, Rm, zr); 408 } 409 410 #define WRAP(INSN) \ 411 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \ 412 if ((VM_Version::cpu_cpuFeatures() & VM_Version::CPU_A53MAC) && Ra != zr) \ 413 nop(); \ 414 Assembler::INSN(Rd, Rn, Rm, Ra); \ 415 } 416 417 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw) 418 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl) 419 #undef WRAP 420 421 422 // macro assembly operations needed for aarch64 423 424 // first two private routines for loading 32 bit or 64 bit constants 425 private: 426 427 void mov_immediate64(Register dst, u_int64_t imm64); 428 void mov_immediate32(Register dst, u_int32_t imm32); 429 430 int push(unsigned int bitset, Register stack); 431 int pop(unsigned int bitset, Register stack); 432 433 void mov(Register dst, Address a); 434 435 public: 436 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); } 437 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); } 438 439 // now mov instructions for loading absolute addresses and 32 or 440 // 64 bit integers 441 442 inline void mov(Register dst, address addr) 443 { 444 mov_immediate64(dst, (u_int64_t)addr); 445 } 446 447 inline void mov(Register dst, u_int64_t imm64) 448 { 449 mov_immediate64(dst, imm64); 450 } 451 452 inline void movw(Register dst, u_int32_t imm32) 453 { 454 mov_immediate32(dst, imm32); 455 } 456 457 inline void mov(Register dst, long l) 458 { 459 mov(dst, (u_int64_t)l); 460 } 461 462 inline void mov(Register dst, int i) 463 { 464 mov(dst, (long)i); 465 } 466 467 void movptr(Register r, uintptr_t imm64); 468 469 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32); 470 471 // macro instructions for accessing and updating floating point 472 // status register 473 // 474 // FPSR : op1 == 011 475 // CRn == 0100 476 // CRm == 0100 477 // op2 == 001 478 479 inline void get_fpsr(Register reg) 480 { 481 mrs(0b11, 0b0100, 0b0100, 0b001, reg); 482 } 483 484 inline void set_fpsr(Register reg) 485 { 486 msr(0b011, 0b0100, 0b0100, 0b001, reg); 487 } 488 489 inline void clear_fpsr() 490 { 491 msr(0b011, 0b0100, 0b0100, 0b001, zr); 492 } 493 494 // idiv variant which deals with MINLONG as dividend and -1 as divisor 495 int corrected_idivl(Register result, Register ra, Register rb, 496 bool want_remainder, Register tmp = rscratch1); 497 int corrected_idivq(Register result, Register ra, Register rb, 498 bool want_remainder, Register tmp = rscratch1); 499 500 // Support for NULL-checks 501 // 502 // Generates code that causes a NULL OS exception if the content of reg is NULL. 503 // If the accessed location is M[reg + offset] and the offset is known, provide the 504 // offset. No explicit code generation is needed if the offset is within a certain 505 // range (0 <= offset <= page_size). 506 507 virtual void null_check(Register reg, int offset = -1); 508 static bool needs_explicit_null_check(intptr_t offset); 509 510 static address target_addr_for_insn(address insn_addr, unsigned insn); 511 static address target_addr_for_insn(address insn_addr) { 512 unsigned insn = *(unsigned*)insn_addr; 513 return target_addr_for_insn(insn_addr, insn); 514 } 515 516 // Required platform-specific helpers for Label::patch_instructions. 517 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 518 static int pd_patch_instruction_size(address branch, address target); 519 static void pd_patch_instruction(address branch, address target) { 520 pd_patch_instruction_size(branch, target); 521 } 522 static address pd_call_destination(address branch) { 523 return target_addr_for_insn(branch); 524 } 525 #ifndef PRODUCT 526 static void pd_print_patched_instruction(address branch); 527 #endif 528 529 static int patch_oop(address insn_addr, address o); 530 531 void emit_trampoline_stub(int insts_call_instruction_offset, address target); 532 533 // The following 4 methods return the offset of the appropriate move instruction 534 535 // Support for fast byte/short loading with zero extension (depending on particular CPU) 536 int load_unsigned_byte(Register dst, Address src); 537 int load_unsigned_short(Register dst, Address src); 538 539 // Support for fast byte/short loading with sign extension (depending on particular CPU) 540 int load_signed_byte(Register dst, Address src); 541 int load_signed_short(Register dst, Address src); 542 543 int load_signed_byte32(Register dst, Address src); 544 int load_signed_short32(Register dst, Address src); 545 546 // Support for sign-extension (hi:lo = extend_sign(lo)) 547 void extend_sign(Register hi, Register lo); 548 549 // Load and store values by size and signed-ness 550 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); 551 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); 552 553 // Support for inc/dec with optimal instruction selection depending on value 554 555 // x86_64 aliases an unqualified register/address increment and 556 // decrement to call incrementq and decrementq but also supports 557 // explicitly sized calls to incrementq/decrementq or 558 // incrementl/decrementl 559 560 // for aarch64 the proper convention would be to use 561 // increment/decrement for 64 bit operatons and 562 // incrementw/decrementw for 32 bit operations. so when porting 563 // x86_64 code we can leave calls to increment/decrement as is, 564 // replace incrementq/decrementq with increment/decrement and 565 // replace incrementl/decrementl with incrementw/decrementw. 566 567 // n.b. increment/decrement calls with an Address destination will 568 // need to use a scratch register to load the value to be 569 // incremented. increment/decrement calls which add or subtract a 570 // constant value greater than 2^12 will need to use a 2nd scratch 571 // register to hold the constant. so, a register increment/decrement 572 // may trash rscratch2 and an address increment/decrement trash 573 // rscratch and rscratch2 574 575 void decrementw(Address dst, int value = 1); 576 void decrementw(Register reg, int value = 1); 577 578 void decrement(Register reg, int value = 1); 579 void decrement(Address dst, int value = 1); 580 581 void incrementw(Address dst, int value = 1); 582 void incrementw(Register reg, int value = 1); 583 584 void increment(Register reg, int value = 1); 585 void increment(Address dst, int value = 1); 586 587 588 // Alignment 589 void align(int modulus); 590 591 // Stack frame creation/removal 592 void enter() 593 { 594 stp(rfp, lr, Address(pre(sp, -2 * wordSize))); 595 mov(rfp, sp); 596 } 597 void leave() 598 { 599 mov(sp, rfp); 600 ldp(rfp, lr, Address(post(sp, 2 * wordSize))); 601 } 602 603 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 604 // The pointer will be loaded into the thread register. 605 void get_thread(Register thread); 606 607 608 // Support for VM calls 609 // 610 // It is imperative that all calls into the VM are handled via the call_VM macros. 611 // They make sure that the stack linkage is setup correctly. call_VM's correspond 612 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 613 614 615 void call_VM(Register oop_result, 616 address entry_point, 617 bool check_exceptions = true); 618 void call_VM(Register oop_result, 619 address entry_point, 620 Register arg_1, 621 bool check_exceptions = true); 622 void call_VM(Register oop_result, 623 address entry_point, 624 Register arg_1, Register arg_2, 625 bool check_exceptions = true); 626 void call_VM(Register oop_result, 627 address entry_point, 628 Register arg_1, Register arg_2, Register arg_3, 629 bool check_exceptions = true); 630 631 // Overloadings with last_Java_sp 632 void call_VM(Register oop_result, 633 Register last_java_sp, 634 address entry_point, 635 int number_of_arguments = 0, 636 bool check_exceptions = true); 637 void call_VM(Register oop_result, 638 Register last_java_sp, 639 address entry_point, 640 Register arg_1, bool 641 check_exceptions = true); 642 void call_VM(Register oop_result, 643 Register last_java_sp, 644 address entry_point, 645 Register arg_1, Register arg_2, 646 bool check_exceptions = true); 647 void call_VM(Register oop_result, 648 Register last_java_sp, 649 address entry_point, 650 Register arg_1, Register arg_2, Register arg_3, 651 bool check_exceptions = true); 652 653 void get_vm_result (Register oop_result, Register thread); 654 void get_vm_result_2(Register metadata_result, Register thread); 655 656 // These always tightly bind to MacroAssembler::call_VM_base 657 // bypassing the virtual implementation 658 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 659 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 660 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 661 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 662 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); 663 664 void call_VM_leaf(address entry_point, 665 int number_of_arguments = 0); 666 void call_VM_leaf(address entry_point, 667 Register arg_1); 668 void call_VM_leaf(address entry_point, 669 Register arg_1, Register arg_2); 670 void call_VM_leaf(address entry_point, 671 Register arg_1, Register arg_2, Register arg_3); 672 673 // These always tightly bind to MacroAssembler::call_VM_leaf_base 674 // bypassing the virtual implementation 675 void super_call_VM_leaf(address entry_point); 676 void super_call_VM_leaf(address entry_point, Register arg_1); 677 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 678 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 679 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); 680 681 // last Java Frame (fills frame anchor) 682 void set_last_Java_frame(Register last_java_sp, 683 Register last_java_fp, 684 address last_java_pc, 685 Register scratch); 686 687 void set_last_Java_frame(Register last_java_sp, 688 Register last_java_fp, 689 Label &last_java_pc, 690 Register scratch); 691 692 void set_last_Java_frame(Register last_java_sp, 693 Register last_java_fp, 694 Register last_java_pc, 695 Register scratch); 696 697 void reset_last_Java_frame(Register thread, bool clearfp, bool clear_pc); 698 699 // thread in the default location (r15_thread on 64bit) 700 void reset_last_Java_frame(bool clear_fp, bool clear_pc); 701 702 // Stores 703 void store_check(Register obj); // store check for obj - register is destroyed afterwards 704 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 705 706 #if INCLUDE_ALL_GCS 707 708 void g1_write_barrier_pre(Register obj, 709 Register pre_val, 710 Register thread, 711 Register tmp, 712 bool tosca_live, 713 bool expand_call); 714 715 void g1_write_barrier_post(Register store_addr, 716 Register new_val, 717 Register thread, 718 Register tmp, 719 Register tmp2); 720 721 #endif // INCLUDE_ALL_GCS 722 723 // oop manipulations 724 void load_klass(Register dst, Register src); 725 void store_klass(Register dst, Register src); 726 void cmp_klass(Register oop, Register trial_klass, Register tmp); 727 728 void load_heap_oop(Register dst, Address src); 729 730 void load_heap_oop_not_null(Register dst, Address src); 731 void store_heap_oop(Address dst, Register src); 732 733 // currently unimplemented 734 // Used for storing NULL. All other oop constants should be 735 // stored using routines that take a jobject. 736 void store_heap_oop_null(Address dst); 737 738 void load_prototype_header(Register dst, Register src); 739 740 void store_klass_gap(Register dst, Register src); 741 742 // This dummy is to prevent a call to store_heap_oop from 743 // converting a zero (like NULL) into a Register by giving 744 // the compiler two choices it can't resolve 745 746 void store_heap_oop(Address dst, void* dummy); 747 748 void encode_heap_oop(Register d, Register s); 749 void encode_heap_oop(Register r) { encode_heap_oop(r, r); } 750 void decode_heap_oop(Register d, Register s); 751 void decode_heap_oop(Register r) { decode_heap_oop(r, r); } 752 void encode_heap_oop_not_null(Register r); 753 void decode_heap_oop_not_null(Register r); 754 void encode_heap_oop_not_null(Register dst, Register src); 755 void decode_heap_oop_not_null(Register dst, Register src); 756 757 void set_narrow_oop(Register dst, jobject obj); 758 759 void encode_klass_not_null(Register r); 760 void decode_klass_not_null(Register r); 761 void encode_klass_not_null(Register dst, Register src); 762 void decode_klass_not_null(Register dst, Register src); 763 764 void set_narrow_klass(Register dst, Klass* k); 765 766 // if heap base register is used - reinit it with the correct value 767 void reinit_heapbase(); 768 769 DEBUG_ONLY(void verify_heapbase(const char* msg);) 770 771 void push_CPU_state(); 772 void pop_CPU_state() ; 773 774 // Round up to a power of two 775 void round_to(Register reg, int modulus); 776 777 // allocation 778 void eden_allocate( 779 Register obj, // result: pointer to object after successful allocation 780 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 781 int con_size_in_bytes, // object size in bytes if known at compile time 782 Register t1, // temp register 783 Label& slow_case // continuation point if fast allocation fails 784 ); 785 void tlab_allocate( 786 Register obj, // result: pointer to object after successful allocation 787 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 788 int con_size_in_bytes, // object size in bytes if known at compile time 789 Register t1, // temp register 790 Register t2, // temp register 791 Label& slow_case // continuation point if fast allocation fails 792 ); 793 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address 794 void verify_tlab(); 795 796 void incr_allocated_bytes(Register thread, 797 Register var_size_in_bytes, int con_size_in_bytes, 798 Register t1 = noreg); 799 800 // interface method calling 801 void lookup_interface_method(Register recv_klass, 802 Register intf_klass, 803 RegisterOrConstant itable_index, 804 Register method_result, 805 Register scan_temp, 806 Label& no_such_interface); 807 808 // virtual method calling 809 // n.b. x86 allows RegisterOrConstant for vtable_index 810 void lookup_virtual_method(Register recv_klass, 811 RegisterOrConstant vtable_index, 812 Register method_result); 813 814 // Test sub_klass against super_klass, with fast and slow paths. 815 816 // The fast path produces a tri-state answer: yes / no / maybe-slow. 817 // One of the three labels can be NULL, meaning take the fall-through. 818 // If super_check_offset is -1, the value is loaded up from super_klass. 819 // No registers are killed, except temp_reg. 820 void check_klass_subtype_fast_path(Register sub_klass, 821 Register super_klass, 822 Register temp_reg, 823 Label* L_success, 824 Label* L_failure, 825 Label* L_slow_path, 826 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 827 828 // The rest of the type check; must be wired to a corresponding fast path. 829 // It does not repeat the fast path logic, so don't use it standalone. 830 // The temp_reg and temp2_reg can be noreg, if no temps are available. 831 // Updates the sub's secondary super cache as necessary. 832 // If set_cond_codes, condition codes will be Z on success, NZ on failure. 833 void check_klass_subtype_slow_path(Register sub_klass, 834 Register super_klass, 835 Register temp_reg, 836 Register temp2_reg, 837 Label* L_success, 838 Label* L_failure, 839 bool set_cond_codes = false); 840 841 // Simplified, combined version, good for typical uses. 842 // Falls through on failure. 843 void check_klass_subtype(Register sub_klass, 844 Register super_klass, 845 Register temp_reg, 846 Label& L_success); 847 848 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); 849 850 851 // Debugging 852 853 // only if +VerifyOops 854 void verify_oop(Register reg, const char* s = "broken oop"); 855 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); 856 857 // TODO: verify method and klass metadata (compare against vptr?) 858 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} 859 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} 860 861 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 862 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 863 864 // only if +VerifyFPU 865 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); 866 867 // prints msg, dumps registers and stops execution 868 void stop(const char* msg); 869 870 // prints msg and continues 871 void warn(const char* msg); 872 873 static void debug64(char* msg, int64_t pc, int64_t regs[]); 874 875 void untested() { stop("untested"); } 876 877 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } 878 879 void should_not_reach_here() { stop("should not reach here"); } 880 881 // Stack overflow checking 882 void bang_stack_with_offset(int offset) { 883 // stack grows down, caller passes positive offset 884 assert(offset > 0, "must bang with negative offset"); 885 mov(rscratch2, -offset); 886 str(zr, Address(sp, rscratch2)); 887 } 888 889 // Writes to stack successive pages until offset reached to check for 890 // stack overflow + shadow pages. Also, clobbers tmp 891 void bang_stack_size(Register size, Register tmp); 892 893 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 894 Register tmp, 895 int offset); 896 897 // Support for serializing memory accesses between threads 898 void serialize_memory(Register thread, Register tmp); 899 900 // Arithmetics 901 902 void addptr(Address dst, int32_t src) { 903 lea(rscratch2, dst); 904 ldr(rscratch1, Address(rscratch2)); 905 add(rscratch1, rscratch1, src); 906 str(rscratch1, Address(rscratch2)); 907 } 908 909 void cmpptr(Register src1, Address src2); 910 911 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, 912 Label &suceed, Label *fail); 913 914 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, 915 Label &suceed, Label *fail); 916 917 void atomic_add(Register prev, RegisterOrConstant incr, Register addr); 918 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr); 919 920 void atomic_xchg(Register prev, Register newv, Register addr); 921 void atomic_xchgw(Register prev, Register newv, Register addr); 922 923 void orptr(Address adr, RegisterOrConstant src) { 924 ldr(rscratch2, adr); 925 if (src.is_register()) 926 orr(rscratch2, rscratch2, src.as_register()); 927 else 928 orr(rscratch2, rscratch2, src.as_constant()); 929 str(rscratch2, adr); 930 } 931 932 // Calls 933 934 void trampoline_call(Address entry, CodeBuffer *cbuf = NULL); 935 936 static bool far_branches() { 937 return ReservedCodeCacheSize > branch_range; 938 } 939 940 // Jumps that can reach anywhere in the code cache. 941 // Trashes tmp. 942 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1); 943 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1); 944 945 static int far_branch_size() { 946 if (far_branches()) { 947 return 3 * 4; // adrp, add, br 948 } else { 949 return 4; 950 } 951 } 952 953 // Emit the CompiledIC call idiom 954 void ic_call(address entry); 955 956 public: 957 958 // Data 959 960 void mov_metadata(Register dst, Metadata* obj); 961 Address allocate_metadata_address(Metadata* obj); 962 Address constant_oop_address(jobject obj); 963 964 void movoop(Register dst, jobject obj, bool immediate = false); 965 966 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic. 967 void kernel_crc32(Register crc, Register buf, Register len, 968 Register table0, Register table1, Register table2, Register table3, 969 Register tmp, Register tmp2, Register tmp3); 970 // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic. 971 void kernel_crc32c(Register crc, Register buf, Register len, 972 Register table0, Register table1, Register table2, Register table3, 973 Register tmp, Register tmp2, Register tmp3); 974 975 #undef VIRTUAL 976 977 // Stack push and pop individual 64 bit registers 978 void push(Register src); 979 void pop(Register dst); 980 981 // push all registers onto the stack 982 void pusha(); 983 void popa(); 984 985 void repne_scan(Register addr, Register value, Register count, 986 Register scratch); 987 void repne_scanw(Register addr, Register value, Register count, 988 Register scratch); 989 990 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm); 991 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift); 992 993 // If a constant does not fit in an immediate field, generate some 994 // number of MOV instructions and then perform the operation 995 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm, 996 add_sub_imm_insn insn1, 997 add_sub_reg_insn insn2); 998 // Seperate vsn which sets the flags 999 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm, 1000 add_sub_imm_insn insn1, 1001 add_sub_reg_insn insn2); 1002 1003 #define WRAP(INSN) \ 1004 void INSN(Register Rd, Register Rn, unsigned imm) { \ 1005 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \ 1006 } \ 1007 \ 1008 void INSN(Register Rd, Register Rn, Register Rm, \ 1009 enum shift_kind kind, unsigned shift = 0) { \ 1010 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 1011 } \ 1012 \ 1013 void INSN(Register Rd, Register Rn, Register Rm) { \ 1014 Assembler::INSN(Rd, Rn, Rm); \ 1015 } \ 1016 \ 1017 void INSN(Register Rd, Register Rn, Register Rm, \ 1018 ext::operation option, int amount = 0) { \ 1019 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1020 } 1021 1022 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw) 1023 1024 #undef WRAP 1025 #define WRAP(INSN) \ 1026 void INSN(Register Rd, Register Rn, unsigned imm) { \ 1027 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \ 1028 } \ 1029 \ 1030 void INSN(Register Rd, Register Rn, Register Rm, \ 1031 enum shift_kind kind, unsigned shift = 0) { \ 1032 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 1033 } \ 1034 \ 1035 void INSN(Register Rd, Register Rn, Register Rm) { \ 1036 Assembler::INSN(Rd, Rn, Rm); \ 1037 } \ 1038 \ 1039 void INSN(Register Rd, Register Rn, Register Rm, \ 1040 ext::operation option, int amount = 0) { \ 1041 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1042 } 1043 1044 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw) 1045 1046 void add(Register Rd, Register Rn, RegisterOrConstant increment); 1047 void addw(Register Rd, Register Rn, RegisterOrConstant increment); 1048 1049 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset); 1050 1051 void tableswitch(Register index, jint lowbound, jint highbound, 1052 Label &jumptable, Label &jumptable_end, int stride = 1) { 1053 adr(rscratch1, jumptable); 1054 subsw(rscratch2, index, lowbound); 1055 subsw(zr, rscratch2, highbound - lowbound); 1056 br(Assembler::HS, jumptable_end); 1057 add(rscratch1, rscratch1, rscratch2, 1058 ext::sxtw, exact_log2(stride * Assembler::instruction_size)); 1059 br(rscratch1); 1060 } 1061 1062 // Form an address from base + offset in Rd. Rd may or may not 1063 // actually be used: you must use the Address that is returned. It 1064 // is up to you to ensure that the shift provided matches the size 1065 // of your data. 1066 Address form_address(Register Rd, Register base, long byte_offset, int shift); 1067 1068 // Prolog generator routines to support switch between x86 code and 1069 // generated ARM code 1070 1071 // routine to generate an x86 prolog for a stub function which 1072 // bootstraps into the generated ARM code which directly follows the 1073 // stub 1074 // 1075 1076 public: 1077 // enum used for aarch64--x86 linkage to define return type of x86 function 1078 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double}; 1079 1080 #ifdef BUILTIN_SIM 1081 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL); 1082 #else 1083 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { } 1084 #endif 1085 1086 // special version of call_VM_leaf_base needed for aarch64 simulator 1087 // where we need to specify both the gp and fp arg counts and the 1088 // return type so that the linkage routine from aarch64 to x86 and 1089 // back knows which aarch64 registers to copy to x86 registers and 1090 // which x86 result register to copy back to an aarch64 register 1091 1092 void call_VM_leaf_base1( 1093 address entry_point, // the entry point 1094 int number_of_gp_arguments, // the number of gp reg arguments to pass 1095 int number_of_fp_arguments, // the number of fp reg arguments to pass 1096 ret_type type, // the return type for the call 1097 Label* retaddr = NULL 1098 ); 1099 1100 void ldr_constant(Register dest, const Address &const_addr) { 1101 if (NearCpool) { 1102 ldr(dest, const_addr); 1103 } else { 1104 unsigned long offset; 1105 adrp(dest, InternalAddress(const_addr.target()), offset); 1106 ldr(dest, Address(dest, offset)); 1107 } 1108 } 1109 1110 address read_polling_page(Register r, address page, relocInfo::relocType rtype); 1111 address read_polling_page(Register r, relocInfo::relocType rtype); 1112 1113 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic. 1114 void update_byte_crc32(Register crc, Register val, Register table); 1115 void update_word_crc32(Register crc, Register v, Register tmp, 1116 Register table0, Register table1, Register table2, Register table3, 1117 bool upper = false); 1118 1119 void string_compare(Register str1, Register str2, 1120 Register cnt1, Register cnt2, Register result, 1121 Register tmp1); 1122 void string_equals(Register str1, Register str2, 1123 Register cnt, Register result, 1124 Register tmp1); 1125 void char_arrays_equals(Register ary1, Register ary2, 1126 Register result, Register tmp1); 1127 void encode_iso_array(Register src, Register dst, 1128 Register len, Register result, 1129 FloatRegister Vtmp1, FloatRegister Vtmp2, 1130 FloatRegister Vtmp3, FloatRegister Vtmp4); 1131 void string_indexof(Register str1, Register str2, 1132 Register cnt1, Register cnt2, 1133 Register tmp1, Register tmp2, 1134 Register tmp3, Register tmp4, 1135 int int_cnt1, Register result); 1136 private: 1137 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, 1138 Register src1, Register src2); 1139 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 1140 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2); 1141 } 1142 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 1143 Register y, Register y_idx, Register z, 1144 Register carry, Register product, 1145 Register idx, Register kdx); 1146 void multiply_128_x_128_loop(Register y, Register z, 1147 Register carry, Register carry2, 1148 Register idx, Register jdx, 1149 Register yz_idx1, Register yz_idx2, 1150 Register tmp, Register tmp3, Register tmp4, 1151 Register tmp7, Register product_hi); 1152 public: 1153 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, 1154 Register zlen, Register tmp1, Register tmp2, Register tmp3, 1155 Register tmp4, Register tmp5, Register tmp6, Register tmp7); 1156 // ISB may be needed because of a safepoint 1157 void maybe_isb() { isb(); } 1158 1159 private: 1160 // Return the effective address r + (r1 << ext) + offset. 1161 // Uses rscratch2. 1162 Address offsetted_address(Register r, Register r1, Address::extend ext, 1163 int offset, int size); 1164 }; 1165 1166 #ifdef ASSERT 1167 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } 1168 #endif 1169 1170 /** 1171 * class SkipIfEqual: 1172 * 1173 * Instantiating this class will result in assembly code being output that will 1174 * jump around any code emitted between the creation of the instance and it's 1175 * automatic destruction at the end of a scope block, depending on the value of 1176 * the flag passed to the constructor, which will be checked at run-time. 1177 */ 1178 class SkipIfEqual { 1179 private: 1180 MacroAssembler* _masm; 1181 Label _label; 1182 1183 public: 1184 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); 1185 ~SkipIfEqual(); 1186 }; 1187 1188 struct tableswitch { 1189 Register _reg; 1190 int _insn_index; jint _first_key; jint _last_key; 1191 Label _after; 1192 Label _branches; 1193 }; 1194 1195 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP