Cdiffs Udiffs Wdiffs Sdiffs Frames Old New ----- Raw src/cpu/aarch64/vm/assembler_aarch64.cpp

rev 8835 : 8133352: aarch64: generates constrained unpredictable instructions
Summary: Fix generation of unpredictable STXR Rs, Rt, [Rn] with Rs == Rt
Reviewed-by: kvn

6 lines changed: 0 ins; 0 del; 6 mod; 1520 unchg

Cdiffs Udiffs Wdiffs Sdiffs Frames Old New ----- Raw src/cpu/aarch64/vm/assembler_aarch64.hpp

rev 8835 : 8133352: aarch64: generates constrained unpredictable instructions
Summary: Fix generation of unpredictable STXR Rs, Rt, [Rn] with Rs == Rt
Reviewed-by: kvn

3 lines changed: 1 ins; 0 del; 2 mod; 2508 unchg

Cdiffs Udiffs Wdiffs Sdiffs Frames Old New ----- Raw src/cpu/aarch64/vm/interp_masm_aarch64.cpp

rev 8835 : 8133352: aarch64: generates constrained unpredictable instructions
Summary: Fix generation of unpredictable STXR Rs, Rt, [Rn] with Rs == Rt
Reviewed-by: kvn

4 lines changed: 1 ins; 0 del; 3 mod; 1681 unchg

Cdiffs Udiffs Wdiffs Sdiffs Frames Old New ----- Raw src/cpu/aarch64/vm/macroAssembler_aarch64.cpp

rev 8835 : 8133352: aarch64: generates constrained unpredictable instructions
Summary: Fix generation of unpredictable STXR Rs, Rt, [Rn] with Rs == Rt
Reviewed-by: kvn

28 lines changed: 9 ins; 4 del; 15 mod; 4576 unchg

Cdiffs Udiffs Wdiffs Sdiffs Frames Old New ----- Raw src/cpu/aarch64/vm/macroAssembler_aarch64.hpp

rev 8835 : 8133352: aarch64: generates constrained unpredictable instructions
Summary: Fix generation of unpredictable STXR Rs, Rt, [Rn] with Rs == Rt
Reviewed-by: kvn

7 lines changed: 1 ins; 2 del; 4 mod; 1241 unchg

Cdiffs Udiffs Wdiffs Sdiffs Frames Old New ----- Raw src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp

rev 8835 : 8133352: aarch64: generates constrained unpredictable instructions
Summary: Fix generation of unpredictable STXR Rs, Rt, [Rn] with Rs == Rt
Reviewed-by: kvn

2 lines changed: 1 ins; 0 del; 1 mod; 3025 unchg

Cdiffs Udiffs Wdiffs Sdiffs Frames Old New ----- Raw src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp

rev 8835 : 8133352: aarch64: generates constrained unpredictable instructions
Summary: Fix generation of unpredictable STXR Rs, Rt, [Rn] with Rs == Rt
Reviewed-by: kvn

5 lines changed: 3 ins; 0 del; 2 mod; 2075 unchg

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