src/cpu/aarch64/vm/aarch64_ad.m4

rev 8842 : 8133842: aarch64: C2 generates illegal instructions with int shifts >=32
Summary: Fix logical operatations combined with shifts >= 32
Reviewed-by: duke

*** 40,50 ****
    ins_encode %{
      __ $3(as_Register($dst$$reg),
                as_Register($src1$$reg),
                as_Register($src2$$reg),
                Assembler::$5,
!               $src3$$constant & 0x3f);
    %}
  
    ins_pipe(ialu_reg_reg_shift);
  %}')dnl
  define(`BASE_INVERTED_INSN',
--- 40,50 ----
    ins_encode %{
      __ $3(as_Register($dst$$reg),
                as_Register($src1$$reg),
                as_Register($src2$$reg),
                Assembler::$5,
!               $src3$$constant & ifelse($1,I,0x1f,0x3f));
    %}
  
    ins_pipe(ialu_reg_reg_shift);
  %}')dnl
  define(`BASE_INVERTED_INSN',
*** 85,95 ****
    ins_encode %{
      __ $3(as_Register($dst$$reg),
                as_Register($src1$$reg),
                as_Register($src2$$reg),
                Assembler::$5,
!               $src3$$constant & 0x3f);
    %}
  
    ins_pipe(ialu_reg_reg_shift);
  %}')dnl
  define(`NOT_INSN',
--- 85,95 ----
    ins_encode %{
      __ $3(as_Register($dst$$reg),
                as_Register($src1$$reg),
                as_Register($src2$$reg),
                Assembler::$5,
!               $src3$$constant & ifelse($1,I,0x1f,0x3f));
    %}
  
    ins_pipe(ialu_reg_reg_shift);
  %}')dnl
  define(`NOT_INSN',