rev 8838 : 8133935: aarch64: fails to build from source
Summary: add inlucde of oops/oop.inline.hpp to fix build
Reviewed-by: duke

   1 /*
   2  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include <sys/types.h>
  27 
  28 #include "precompiled.hpp"
  29 #include "asm/assembler.hpp"
  30 #include "asm/assembler.inline.hpp"
  31 #include "interpreter/interpreter.hpp"
  32 
  33 #include "compiler/disassembler.hpp"
  34 #include "memory/resourceArea.hpp"
  35 #include "nativeInst_aarch64.hpp"
  36 #include "oops/klass.inline.hpp"
  37 #include "opto/compile.hpp"
  38 #include "opto/node.hpp"
  39 #include "runtime/biasedLocking.hpp"
  40 #include "runtime/icache.hpp"
  41 #include "runtime/interfaceSupport.hpp"
  42 #include "runtime/sharedRuntime.hpp"

  43 
  44 #if INCLUDE_ALL_GCS
  45 #include "gc/g1/g1CollectedHeap.inline.hpp"
  46 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
  47 #include "gc/g1/heapRegion.hpp"
  48 #endif
  49 
  50 #ifdef PRODUCT
  51 #define BLOCK_COMMENT(str) /* nothing */
  52 #define STOP(error) stop(error)
  53 #else
  54 #define BLOCK_COMMENT(str) block_comment(str)
  55 #define STOP(error) block_comment(error); stop(error)
  56 #endif
  57 
  58 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  59 
  60 // Patch any kind of instruction; there may be several instructions.
  61 // Return the total length (in bytes) of the instructions.
  62 int MacroAssembler::pd_patch_instruction_size(address branch, address target) {
  63   int instructions = 1;
  64   assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant");
  65   long offset = (target - branch) >> 2;
  66   unsigned insn = *(unsigned*)branch;
  67   if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
  68     // Load register (literal)
  69     Instruction_aarch64::spatch(branch, 23, 5, offset);
  70   } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
  71     // Unconditional branch (immediate)
  72     Instruction_aarch64::spatch(branch, 25, 0, offset);
  73   } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
  74     // Conditional branch (immediate)
  75     Instruction_aarch64::spatch(branch, 23, 5, offset);
  76   } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
  77     // Compare & branch (immediate)
  78     Instruction_aarch64::spatch(branch, 23, 5, offset);
  79   } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
  80     // Test & branch (immediate)
  81     Instruction_aarch64::spatch(branch, 18, 5, offset);
  82   } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
  83     // PC-rel. addressing
  84     offset = target-branch;
  85     int shift = Instruction_aarch64::extract(insn, 31, 31);
  86     if (shift) {
  87       u_int64_t dest = (u_int64_t)target;
  88       uint64_t pc_page = (uint64_t)branch >> 12;
  89       uint64_t adr_page = (uint64_t)target >> 12;
  90       unsigned offset_lo = dest & 0xfff;
  91       offset = adr_page - pc_page;
  92 
  93       // We handle 3 types of PC relative addressing
  94       //   1 - adrp    Rx, target_page
  95       //       ldr/str Ry, [Rx, #offset_in_page]
  96       //   2 - adrp    Rx, target_page
  97       //       add     Ry, Rx, #offset_in_page
  98       //   3 - adrp    Rx, target_page (page aligned reloc, offset == 0)
  99       // In the first 2 cases we must check that Rx is the same in the adrp and the
 100       // subsequent ldr/str or add instruction. Otherwise we could accidentally end
 101       // up treating a type 3 relocation as a type 1 or 2 just because it happened
 102       // to be followed by a random unrelated ldr/str or add instruction.
 103       //
 104       // In the case of a type 3 relocation, we know that these are only generated
 105       // for the safepoint polling page, or for the card type byte map base so we
 106       // assert as much and of course that the offset is 0.
 107       //
 108       unsigned insn2 = ((unsigned*)branch)[1];
 109       if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
 110                 Instruction_aarch64::extract(insn, 4, 0) ==
 111                         Instruction_aarch64::extract(insn2, 9, 5)) {
 112         // Load/store register (unsigned immediate)
 113         unsigned size = Instruction_aarch64::extract(insn2, 31, 30);
 114         Instruction_aarch64::patch(branch + sizeof (unsigned),
 115                                     21, 10, offset_lo >> size);
 116         guarantee(((dest >> size) << size) == dest, "misaligned target");
 117         instructions = 2;
 118       } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
 119                 Instruction_aarch64::extract(insn, 4, 0) ==
 120                         Instruction_aarch64::extract(insn2, 4, 0)) {
 121         // add (immediate)
 122         Instruction_aarch64::patch(branch + sizeof (unsigned),
 123                                    21, 10, offset_lo);
 124         instructions = 2;
 125       } else {
 126         assert((jbyte *)target ==
 127                 ((CardTableModRefBS*)(Universe::heap()->barrier_set()))->byte_map_base ||
 128                target == StubRoutines::crc_table_addr() ||
 129                (address)target == os::get_polling_page(),
 130                "adrp must be polling page or byte map base");
 131         assert(offset_lo == 0, "offset must be 0 for polling page or byte map base");
 132       }
 133     }
 134     int offset_lo = offset & 3;
 135     offset >>= 2;
 136     Instruction_aarch64::spatch(branch, 23, 5, offset);
 137     Instruction_aarch64::patch(branch, 30, 29, offset_lo);
 138   } else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) {
 139     u_int64_t dest = (u_int64_t)target;
 140     // Move wide constant
 141     assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch");
 142     assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch");
 143     Instruction_aarch64::patch(branch, 20, 5, dest & 0xffff);
 144     Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff);
 145     Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff);
 146     assert(target_addr_for_insn(branch) == target, "should be");
 147     instructions = 3;
 148   } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
 149              Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
 150     // nothing to do
 151     assert(target == 0, "did not expect to relocate target for polling page load");
 152   } else {
 153     ShouldNotReachHere();
 154   }
 155   return instructions * NativeInstruction::instruction_size;
 156 }
 157 
 158 int MacroAssembler::patch_oop(address insn_addr, address o) {
 159   int instructions;
 160   unsigned insn = *(unsigned*)insn_addr;
 161   assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
 162 
 163   // OOPs are either narrow (32 bits) or wide (48 bits).  We encode
 164   // narrow OOPs by setting the upper 16 bits in the first
 165   // instruction.
 166   if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
 167     // Move narrow OOP
 168     narrowOop n = oopDesc::encode_heap_oop((oop)o);
 169     Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
 170     Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
 171     instructions = 2;
 172   } else {
 173     // Move wide OOP
 174     assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
 175     uintptr_t dest = (uintptr_t)o;
 176     Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
 177     Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
 178     Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
 179     instructions = 3;
 180   }
 181   return instructions * NativeInstruction::instruction_size;
 182 }
 183 
 184 address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) {
 185   long offset = 0;
 186   if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) {
 187     // Load register (literal)
 188     offset = Instruction_aarch64::sextract(insn, 23, 5);
 189     return address(((uint64_t)insn_addr + (offset << 2)));
 190   } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
 191     // Unconditional branch (immediate)
 192     offset = Instruction_aarch64::sextract(insn, 25, 0);
 193   } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
 194     // Conditional branch (immediate)
 195     offset = Instruction_aarch64::sextract(insn, 23, 5);
 196   } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
 197     // Compare & branch (immediate)
 198     offset = Instruction_aarch64::sextract(insn, 23, 5);
 199    } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
 200     // Test & branch (immediate)
 201     offset = Instruction_aarch64::sextract(insn, 18, 5);
 202   } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
 203     // PC-rel. addressing
 204     offset = Instruction_aarch64::extract(insn, 30, 29);
 205     offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
 206     int shift = Instruction_aarch64::extract(insn, 31, 31) ? 12 : 0;
 207     if (shift) {
 208       offset <<= shift;
 209       uint64_t target_page = ((uint64_t)insn_addr) + offset;
 210       target_page &= ((uint64_t)-1) << shift;
 211       // Return the target address for the following sequences
 212       //   1 - adrp    Rx, target_page
 213       //       ldr/str Ry, [Rx, #offset_in_page]
 214       //   2 - adrp    Rx, target_page         ]
 215       //       add     Ry, Rx, #offset_in_page
 216       //   3 - adrp    Rx, target_page (page aligned reloc, offset == 0)
 217       //
 218       // In the first two cases  we check that the register is the same and
 219       // return the target_page + the offset within the page.
 220       // Otherwise we assume it is a page aligned relocation and return
 221       // the target page only. The only cases this is generated is for
 222       // the safepoint polling page or for the card table byte map base so
 223       // we assert as much.
 224       //
 225       unsigned insn2 = ((unsigned*)insn_addr)[1];
 226       if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
 227                 Instruction_aarch64::extract(insn, 4, 0) ==
 228                         Instruction_aarch64::extract(insn2, 9, 5)) {
 229         // Load/store register (unsigned immediate)
 230         unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
 231         unsigned int size = Instruction_aarch64::extract(insn2, 31, 30);
 232         return address(target_page + (byte_offset << size));
 233       } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
 234                 Instruction_aarch64::extract(insn, 4, 0) ==
 235                         Instruction_aarch64::extract(insn2, 4, 0)) {
 236         // add (immediate)
 237         unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
 238         return address(target_page + byte_offset);
 239       } else {
 240         assert((jbyte *)target_page ==
 241                 ((CardTableModRefBS*)(Universe::heap()->barrier_set()))->byte_map_base ||
 242                (address)target_page == os::get_polling_page(),
 243                "adrp must be polling page or byte map base");
 244         return (address)target_page;
 245       }
 246     } else {
 247       ShouldNotReachHere();
 248     }
 249   } else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) {
 250     u_int32_t *insns = (u_int32_t *)insn_addr;
 251     // Move wide constant: movz, movk, movk.  See movptr().
 252     assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
 253     assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
 254     return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5))
 255                    + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
 256                    + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
 257   } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
 258              Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
 259     return 0;
 260   } else {
 261     ShouldNotReachHere();
 262   }
 263   return address(((uint64_t)insn_addr + (offset << 2)));
 264 }
 265 
 266 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
 267   dsb(Assembler::SY);
 268 }
 269 
 270 
 271 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
 272                                            bool clear_pc) {
 273   // we must set sp to zero to clear frame
 274   str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
 275   // must clear fp, so that compiled frames are not confused; it is
 276   // possible that we need it only for debugging
 277   if (clear_fp) {
 278     str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
 279   }
 280 
 281   if (clear_pc) {
 282     str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
 283   }
 284 }
 285 
 286 // Calls to C land
 287 //
 288 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
 289 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
 290 // has to be reset to 0. This is required to allow proper stack traversal.
 291 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
 292                                          Register last_java_fp,
 293                                          Register last_java_pc,
 294                                          Register scratch) {
 295 
 296   if (last_java_pc->is_valid()) {
 297       str(last_java_pc, Address(rthread,
 298                                 JavaThread::frame_anchor_offset()
 299                                 + JavaFrameAnchor::last_Java_pc_offset()));
 300     }
 301 
 302   // determine last_java_sp register
 303   if (last_java_sp == sp) {
 304     mov(scratch, sp);
 305     last_java_sp = scratch;
 306   } else if (!last_java_sp->is_valid()) {
 307     last_java_sp = esp;
 308   }
 309 
 310   str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
 311 
 312   // last_java_fp is optional
 313   if (last_java_fp->is_valid()) {
 314     str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
 315   }
 316 }
 317 
 318 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
 319                                          Register last_java_fp,
 320                                          address  last_java_pc,
 321                                          Register scratch) {
 322   if (last_java_pc != NULL) {
 323     adr(scratch, last_java_pc);
 324   } else {
 325     // FIXME: This is almost never correct.  We should delete all
 326     // cases of set_last_Java_frame with last_java_pc=NULL and use the
 327     // correct return address instead.
 328     adr(scratch, pc());
 329   }
 330 
 331   str(scratch, Address(rthread,
 332                        JavaThread::frame_anchor_offset()
 333                        + JavaFrameAnchor::last_Java_pc_offset()));
 334 
 335   set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
 336 }
 337 
 338 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
 339                                          Register last_java_fp,
 340                                          Label &L,
 341                                          Register scratch) {
 342   if (L.is_bound()) {
 343     set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
 344   } else {
 345     InstructionMark im(this);
 346     L.add_patch_at(code(), locator());
 347     set_last_Java_frame(last_java_sp, last_java_fp, (address)NULL, scratch);
 348   }
 349 }
 350 
 351 void MacroAssembler::far_call(Address entry, CodeBuffer *cbuf, Register tmp) {
 352   assert(ReservedCodeCacheSize < 4*G, "branch out of range");
 353   assert(CodeCache::find_blob(entry.target()) != NULL,
 354          "destination of far call not found in code cache");
 355   if (far_branches()) {
 356     unsigned long offset;
 357     // We can use ADRP here because we know that the total size of
 358     // the code cache cannot exceed 2Gb.
 359     adrp(tmp, entry, offset);
 360     add(tmp, tmp, offset);
 361     if (cbuf) cbuf->set_insts_mark();
 362     blr(tmp);
 363   } else {
 364     if (cbuf) cbuf->set_insts_mark();
 365     bl(entry);
 366   }
 367 }
 368 
 369 void MacroAssembler::far_jump(Address entry, CodeBuffer *cbuf, Register tmp) {
 370   assert(ReservedCodeCacheSize < 4*G, "branch out of range");
 371   assert(CodeCache::find_blob(entry.target()) != NULL,
 372          "destination of far call not found in code cache");
 373   if (far_branches()) {
 374     unsigned long offset;
 375     // We can use ADRP here because we know that the total size of
 376     // the code cache cannot exceed 2Gb.
 377     adrp(tmp, entry, offset);
 378     add(tmp, tmp, offset);
 379     if (cbuf) cbuf->set_insts_mark();
 380     br(tmp);
 381   } else {
 382     if (cbuf) cbuf->set_insts_mark();
 383     b(entry);
 384   }
 385 }
 386 
 387 int MacroAssembler::biased_locking_enter(Register lock_reg,
 388                                          Register obj_reg,
 389                                          Register swap_reg,
 390                                          Register tmp_reg,
 391                                          bool swap_reg_contains_mark,
 392                                          Label& done,
 393                                          Label* slow_case,
 394                                          BiasedLockingCounters* counters) {
 395   assert(UseBiasedLocking, "why call this otherwise?");
 396   assert_different_registers(lock_reg, obj_reg, swap_reg);
 397 
 398   if (PrintBiasedLockingStatistics && counters == NULL)
 399     counters = BiasedLocking::counters();
 400 
 401   bool need_tmp_reg = false;
 402   if (tmp_reg == noreg) {
 403     tmp_reg = rscratch2;
 404   }
 405   assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1);
 406   assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
 407   Address mark_addr      (obj_reg, oopDesc::mark_offset_in_bytes());
 408   Address klass_addr     (obj_reg, oopDesc::klass_offset_in_bytes());
 409   Address saved_mark_addr(lock_reg, 0);
 410 
 411   // Biased locking
 412   // See whether the lock is currently biased toward our thread and
 413   // whether the epoch is still valid
 414   // Note that the runtime guarantees sufficient alignment of JavaThread
 415   // pointers to allow age to be placed into low bits
 416   // First check to see whether biasing is even enabled for this object
 417   Label cas_label;
 418   int null_check_offset = -1;
 419   if (!swap_reg_contains_mark) {
 420     null_check_offset = offset();
 421     ldr(swap_reg, mark_addr);
 422   }
 423   andr(tmp_reg, swap_reg, markOopDesc::biased_lock_mask_in_place);
 424   cmp(tmp_reg, markOopDesc::biased_lock_pattern);
 425   br(Assembler::NE, cas_label);
 426   // The bias pattern is present in the object's header. Need to check
 427   // whether the bias owner and the epoch are both still current.
 428   load_prototype_header(tmp_reg, obj_reg);
 429   orr(tmp_reg, tmp_reg, rthread);
 430   eor(tmp_reg, swap_reg, tmp_reg);
 431   andr(tmp_reg, tmp_reg, ~((int) markOopDesc::age_mask_in_place));
 432   if (counters != NULL) {
 433     Label around;
 434     cbnz(tmp_reg, around);
 435     atomic_incw(Address((address)counters->biased_lock_entry_count_addr()), tmp_reg, rscratch1);
 436     b(done);
 437     bind(around);
 438   } else {
 439     cbz(tmp_reg, done);
 440   }
 441 
 442   Label try_revoke_bias;
 443   Label try_rebias;
 444 
 445   // At this point we know that the header has the bias pattern and
 446   // that we are not the bias owner in the current epoch. We need to
 447   // figure out more details about the state of the header in order to
 448   // know what operations can be legally performed on the object's
 449   // header.
 450 
 451   // If the low three bits in the xor result aren't clear, that means
 452   // the prototype header is no longer biased and we have to revoke
 453   // the bias on this object.
 454   andr(rscratch1, tmp_reg, markOopDesc::biased_lock_mask_in_place);
 455   cbnz(rscratch1, try_revoke_bias);
 456 
 457   // Biasing is still enabled for this data type. See whether the
 458   // epoch of the current bias is still valid, meaning that the epoch
 459   // bits of the mark word are equal to the epoch bits of the
 460   // prototype header. (Note that the prototype header's epoch bits
 461   // only change at a safepoint.) If not, attempt to rebias the object
 462   // toward the current thread. Note that we must be absolutely sure
 463   // that the current epoch is invalid in order to do this because
 464   // otherwise the manipulations it performs on the mark word are
 465   // illegal.
 466   andr(rscratch1, tmp_reg, markOopDesc::epoch_mask_in_place);
 467   cbnz(rscratch1, try_rebias);
 468 
 469   // The epoch of the current bias is still valid but we know nothing
 470   // about the owner; it might be set or it might be clear. Try to
 471   // acquire the bias of the object using an atomic operation. If this
 472   // fails we will go in to the runtime to revoke the object's bias.
 473   // Note that we first construct the presumed unbiased header so we
 474   // don't accidentally blow away another thread's valid bias.
 475   {
 476     Label here;
 477     mov(rscratch1, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
 478     andr(swap_reg, swap_reg, rscratch1);
 479     orr(tmp_reg, swap_reg, rthread);
 480     cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case);
 481     // If the biasing toward our thread failed, this means that
 482     // another thread succeeded in biasing it toward itself and we
 483     // need to revoke that bias. The revocation will occur in the
 484     // interpreter runtime in the slow case.
 485     bind(here);
 486     if (counters != NULL) {
 487       atomic_incw(Address((address)counters->anonymously_biased_lock_entry_count_addr()),
 488                   tmp_reg, rscratch1);
 489     }
 490   }
 491   b(done);
 492 
 493   bind(try_rebias);
 494   // At this point we know the epoch has expired, meaning that the
 495   // current "bias owner", if any, is actually invalid. Under these
 496   // circumstances _only_, we are allowed to use the current header's
 497   // value as the comparison value when doing the cas to acquire the
 498   // bias in the current epoch. In other words, we allow transfer of
 499   // the bias from one thread to another directly in this situation.
 500   //
 501   // FIXME: due to a lack of registers we currently blow away the age
 502   // bits in this situation. Should attempt to preserve them.
 503   {
 504     Label here;
 505     load_prototype_header(tmp_reg, obj_reg);
 506     orr(tmp_reg, rthread, tmp_reg);
 507     cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case);
 508     // If the biasing toward our thread failed, then another thread
 509     // succeeded in biasing it toward itself and we need to revoke that
 510     // bias. The revocation will occur in the runtime in the slow case.
 511     bind(here);
 512     if (counters != NULL) {
 513       atomic_incw(Address((address)counters->rebiased_lock_entry_count_addr()),
 514                   tmp_reg, rscratch1);
 515     }
 516   }
 517   b(done);
 518 
 519   bind(try_revoke_bias);
 520   // The prototype mark in the klass doesn't have the bias bit set any
 521   // more, indicating that objects of this data type are not supposed
 522   // to be biased any more. We are going to try to reset the mark of
 523   // this object to the prototype value and fall through to the
 524   // CAS-based locking scheme. Note that if our CAS fails, it means
 525   // that another thread raced us for the privilege of revoking the
 526   // bias of this particular object, so it's okay to continue in the
 527   // normal locking code.
 528   //
 529   // FIXME: due to a lack of registers we currently blow away the age
 530   // bits in this situation. Should attempt to preserve them.
 531   {
 532     Label here, nope;
 533     load_prototype_header(tmp_reg, obj_reg);
 534     cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, &nope);
 535     bind(here);
 536 
 537     // Fall through to the normal CAS-based lock, because no matter what
 538     // the result of the above CAS, some thread must have succeeded in
 539     // removing the bias bit from the object's header.
 540     if (counters != NULL) {
 541       atomic_incw(Address((address)counters->revoked_lock_entry_count_addr()), tmp_reg,
 542                   rscratch1);
 543     }
 544     bind(nope);
 545   }
 546 
 547   bind(cas_label);
 548 
 549   return null_check_offset;
 550 }
 551 
 552 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
 553   assert(UseBiasedLocking, "why call this otherwise?");
 554 
 555   // Check for biased locking unlock case, which is a no-op
 556   // Note: we do not have to check the thread ID for two reasons.
 557   // First, the interpreter checks for IllegalMonitorStateException at
 558   // a higher level. Second, if the bias was revoked while we held the
 559   // lock, the object could not be rebiased toward another thread, so
 560   // the bias bit would be clear.
 561   ldr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
 562   andr(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
 563   cmp(temp_reg, markOopDesc::biased_lock_pattern);
 564   br(Assembler::EQ, done);
 565 }
 566 
 567 
 568 // added to make this compile
 569 
 570 REGISTER_DEFINITION(Register, noreg);
 571 
 572 static void pass_arg0(MacroAssembler* masm, Register arg) {
 573   if (c_rarg0 != arg ) {
 574     masm->mov(c_rarg0, arg);
 575   }
 576 }
 577 
 578 static void pass_arg1(MacroAssembler* masm, Register arg) {
 579   if (c_rarg1 != arg ) {
 580     masm->mov(c_rarg1, arg);
 581   }
 582 }
 583 
 584 static void pass_arg2(MacroAssembler* masm, Register arg) {
 585   if (c_rarg2 != arg ) {
 586     masm->mov(c_rarg2, arg);
 587   }
 588 }
 589 
 590 static void pass_arg3(MacroAssembler* masm, Register arg) {
 591   if (c_rarg3 != arg ) {
 592     masm->mov(c_rarg3, arg);
 593   }
 594 }
 595 
 596 void MacroAssembler::call_VM_base(Register oop_result,
 597                                   Register java_thread,
 598                                   Register last_java_sp,
 599                                   address  entry_point,
 600                                   int      number_of_arguments,
 601                                   bool     check_exceptions) {
 602    // determine java_thread register
 603   if (!java_thread->is_valid()) {
 604     java_thread = rthread;
 605   }
 606 
 607   // determine last_java_sp register
 608   if (!last_java_sp->is_valid()) {
 609     last_java_sp = esp;
 610   }
 611 
 612   // debugging support
 613   assert(number_of_arguments >= 0   , "cannot have negative number of arguments");
 614   assert(java_thread == rthread, "unexpected register");
 615 #ifdef ASSERT
 616   // TraceBytecodes does not use r12 but saves it over the call, so don't verify
 617   // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
 618 #endif // ASSERT
 619 
 620   assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
 621   assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
 622 
 623   // push java thread (becomes first argument of C function)
 624 
 625   mov(c_rarg0, java_thread);
 626 
 627   // set last Java frame before call
 628   assert(last_java_sp != rfp, "can't use rfp");
 629 
 630   Label l;
 631   set_last_Java_frame(last_java_sp, rfp, l, rscratch1);
 632 
 633   // do the call, remove parameters
 634   MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
 635 
 636   // reset last Java frame
 637   // Only interpreter should have to clear fp
 638   reset_last_Java_frame(true, true);
 639 
 640    // C++ interp handles this in the interpreter
 641   check_and_handle_popframe(java_thread);
 642   check_and_handle_earlyret(java_thread);
 643 
 644   if (check_exceptions) {
 645     // check for pending exceptions (java_thread is set upon return)
 646     ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
 647     Label ok;
 648     cbz(rscratch1, ok);
 649     lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
 650     br(rscratch1);
 651     bind(ok);
 652   }
 653 
 654   // get oop result if there is one and reset the value in the thread
 655   if (oop_result->is_valid()) {
 656     get_vm_result(oop_result, java_thread);
 657   }
 658 }
 659 
 660 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
 661   call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
 662 }
 663 
 664 // Maybe emit a call via a trampoline.  If the code cache is small
 665 // trampolines won't be emitted.
 666 
 667 address MacroAssembler::trampoline_call(Address entry, CodeBuffer *cbuf) {
 668   assert(entry.rspec().type() == relocInfo::runtime_call_type
 669          || entry.rspec().type() == relocInfo::opt_virtual_call_type
 670          || entry.rspec().type() == relocInfo::static_call_type
 671          || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
 672 
 673   unsigned int start_offset = offset();
 674   if (far_branches() && !Compile::current()->in_scratch_emit_size()) {
 675     address stub = emit_trampoline_stub(start_offset, entry.target());
 676     if (stub == NULL) {
 677       return NULL; // CodeCache is full
 678     }
 679   }
 680 
 681   if (cbuf) cbuf->set_insts_mark();
 682   relocate(entry.rspec());
 683   if (Assembler::reachable_from_branch_at(pc(), entry.target())) {
 684     bl(entry.target());
 685   } else {
 686     bl(pc());
 687   }
 688   // just need to return a non-null address
 689   return pc();
 690 }
 691 
 692 
 693 // Emit a trampoline stub for a call to a target which is too far away.
 694 //
 695 // code sequences:
 696 //
 697 // call-site:
 698 //   branch-and-link to <destination> or <trampoline stub>
 699 //
 700 // Related trampoline stub for this call site in the stub section:
 701 //   load the call target from the constant pool
 702 //   branch (LR still points to the call site above)
 703 
 704 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
 705                                              address dest) {
 706   address stub = start_a_stub(Compile::MAX_stubs_size/2);
 707   if (stub == NULL) {
 708     return NULL;  // CodeBuffer::expand failed
 709   }
 710 
 711   // Create a trampoline stub relocation which relates this trampoline stub
 712   // with the call instruction at insts_call_instruction_offset in the
 713   // instructions code-section.
 714   align(wordSize);
 715   relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
 716                                             + insts_call_instruction_offset));
 717   const int stub_start_offset = offset();
 718 
 719   // Now, create the trampoline stub's code:
 720   // - load the call
 721   // - call
 722   Label target;
 723   ldr(rscratch1, target);
 724   br(rscratch1);
 725   bind(target);
 726   assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
 727          "should be");
 728   emit_int64((int64_t)dest);
 729 
 730   const address stub_start_addr = addr_at(stub_start_offset);
 731 
 732   assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
 733 
 734   end_a_stub();
 735   return stub;
 736 }
 737 
 738 address MacroAssembler::ic_call(address entry) {
 739   RelocationHolder rh = virtual_call_Relocation::spec(pc());
 740   // address const_ptr = long_constant((jlong)Universe::non_oop_word());
 741   // unsigned long offset;
 742   // ldr_constant(rscratch2, const_ptr);
 743   movptr(rscratch2, (uintptr_t)Universe::non_oop_word());
 744   return trampoline_call(Address(entry, rh));
 745 }
 746 
 747 // Implementation of call_VM versions
 748 
 749 void MacroAssembler::call_VM(Register oop_result,
 750                              address entry_point,
 751                              bool check_exceptions) {
 752   call_VM_helper(oop_result, entry_point, 0, check_exceptions);
 753 }
 754 
 755 void MacroAssembler::call_VM(Register oop_result,
 756                              address entry_point,
 757                              Register arg_1,
 758                              bool check_exceptions) {
 759   pass_arg1(this, arg_1);
 760   call_VM_helper(oop_result, entry_point, 1, check_exceptions);
 761 }
 762 
 763 void MacroAssembler::call_VM(Register oop_result,
 764                              address entry_point,
 765                              Register arg_1,
 766                              Register arg_2,
 767                              bool check_exceptions) {
 768   assert(arg_1 != c_rarg2, "smashed arg");
 769   pass_arg2(this, arg_2);
 770   pass_arg1(this, arg_1);
 771   call_VM_helper(oop_result, entry_point, 2, check_exceptions);
 772 }
 773 
 774 void MacroAssembler::call_VM(Register oop_result,
 775                              address entry_point,
 776                              Register arg_1,
 777                              Register arg_2,
 778                              Register arg_3,
 779                              bool check_exceptions) {
 780   assert(arg_1 != c_rarg3, "smashed arg");
 781   assert(arg_2 != c_rarg3, "smashed arg");
 782   pass_arg3(this, arg_3);
 783 
 784   assert(arg_1 != c_rarg2, "smashed arg");
 785   pass_arg2(this, arg_2);
 786 
 787   pass_arg1(this, arg_1);
 788   call_VM_helper(oop_result, entry_point, 3, check_exceptions);
 789 }
 790 
 791 void MacroAssembler::call_VM(Register oop_result,
 792                              Register last_java_sp,
 793                              address entry_point,
 794                              int number_of_arguments,
 795                              bool check_exceptions) {
 796   call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
 797 }
 798 
 799 void MacroAssembler::call_VM(Register oop_result,
 800                              Register last_java_sp,
 801                              address entry_point,
 802                              Register arg_1,
 803                              bool check_exceptions) {
 804   pass_arg1(this, arg_1);
 805   call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
 806 }
 807 
 808 void MacroAssembler::call_VM(Register oop_result,
 809                              Register last_java_sp,
 810                              address entry_point,
 811                              Register arg_1,
 812                              Register arg_2,
 813                              bool check_exceptions) {
 814 
 815   assert(arg_1 != c_rarg2, "smashed arg");
 816   pass_arg2(this, arg_2);
 817   pass_arg1(this, arg_1);
 818   call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
 819 }
 820 
 821 void MacroAssembler::call_VM(Register oop_result,
 822                              Register last_java_sp,
 823                              address entry_point,
 824                              Register arg_1,
 825                              Register arg_2,
 826                              Register arg_3,
 827                              bool check_exceptions) {
 828   assert(arg_1 != c_rarg3, "smashed arg");
 829   assert(arg_2 != c_rarg3, "smashed arg");
 830   pass_arg3(this, arg_3);
 831   assert(arg_1 != c_rarg2, "smashed arg");
 832   pass_arg2(this, arg_2);
 833   pass_arg1(this, arg_1);
 834   call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
 835 }
 836 
 837 
 838 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
 839   ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
 840   str(zr, Address(java_thread, JavaThread::vm_result_offset()));
 841   verify_oop(oop_result, "broken oop in call_VM_base");
 842 }
 843 
 844 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
 845   ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
 846   str(zr, Address(java_thread, JavaThread::vm_result_2_offset()));
 847 }
 848 
 849 void MacroAssembler::align(int modulus) {
 850   while (offset() % modulus != 0) nop();
 851 }
 852 
 853 // these are no-ops overridden by InterpreterMacroAssembler
 854 
 855 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
 856 
 857 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
 858 
 859 
 860 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
 861                                                       Register tmp,
 862                                                       int offset) {
 863   intptr_t value = *delayed_value_addr;
 864   if (value != 0)
 865     return RegisterOrConstant(value + offset);
 866 
 867   // load indirectly to solve generation ordering problem
 868   ldr(tmp, ExternalAddress((address) delayed_value_addr));
 869 
 870   if (offset != 0)
 871     add(tmp, tmp, offset);
 872 
 873   return RegisterOrConstant(tmp);
 874 }
 875 
 876 
 877 void MacroAssembler:: notify(int type) {
 878   if (type == bytecode_start) {
 879     // set_last_Java_frame(esp, rfp, (address)NULL);
 880     Assembler:: notify(type);
 881     // reset_last_Java_frame(true, false);
 882   }
 883   else
 884     Assembler:: notify(type);
 885 }
 886 
 887 // Look up the method for a megamorphic invokeinterface call.
 888 // The target method is determined by <intf_klass, itable_index>.
 889 // The receiver klass is in recv_klass.
 890 // On success, the result will be in method_result, and execution falls through.
 891 // On failure, execution transfers to the given label.
 892 void MacroAssembler::lookup_interface_method(Register recv_klass,
 893                                              Register intf_klass,
 894                                              RegisterOrConstant itable_index,
 895                                              Register method_result,
 896                                              Register scan_temp,
 897                                              Label& L_no_such_interface) {
 898   assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
 899   assert(itable_index.is_constant() || itable_index.as_register() == method_result,
 900          "caller must use same register for non-constant itable index as for method");
 901 
 902   // Compute start of first itableOffsetEntry (which is at the end of the vtable)
 903   int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
 904   int itentry_off = itableMethodEntry::method_offset_in_bytes();
 905   int scan_step   = itableOffsetEntry::size() * wordSize;
 906   int vte_size    = vtableEntry::size() * wordSize;
 907   assert(vte_size == wordSize, "else adjust times_vte_scale");
 908 
 909   ldrw(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
 910 
 911   // %%% Could store the aligned, prescaled offset in the klassoop.
 912   // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
 913   lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
 914   add(scan_temp, scan_temp, vtable_base);
 915   if (HeapWordsPerLong > 1) {
 916     // Round up to align_object_offset boundary
 917     // see code for instanceKlass::start_of_itable!
 918     round_to(scan_temp, BytesPerLong);
 919   }
 920 
 921   // Adjust recv_klass by scaled itable_index, so we can free itable_index.
 922   assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
 923   // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
 924   lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
 925   if (itentry_off)
 926     add(recv_klass, recv_klass, itentry_off);
 927 
 928   // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
 929   //   if (scan->interface() == intf) {
 930   //     result = (klass + scan->offset() + itable_index);
 931   //   }
 932   // }
 933   Label search, found_method;
 934 
 935   for (int peel = 1; peel >= 0; peel--) {
 936     ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
 937     cmp(intf_klass, method_result);
 938 
 939     if (peel) {
 940       br(Assembler::EQ, found_method);
 941     } else {
 942       br(Assembler::NE, search);
 943       // (invert the test to fall through to found_method...)
 944     }
 945 
 946     if (!peel)  break;
 947 
 948     bind(search);
 949 
 950     // Check that the previous entry is non-null.  A null entry means that
 951     // the receiver class doesn't implement the interface, and wasn't the
 952     // same as when the caller was compiled.
 953     cbz(method_result, L_no_such_interface);
 954     add(scan_temp, scan_temp, scan_step);
 955   }
 956 
 957   bind(found_method);
 958 
 959   // Got a hit.
 960   ldr(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
 961   ldr(method_result, Address(recv_klass, scan_temp));
 962 }
 963 
 964 // virtual method calling
 965 void MacroAssembler::lookup_virtual_method(Register recv_klass,
 966                                            RegisterOrConstant vtable_index,
 967                                            Register method_result) {
 968   const int base = InstanceKlass::vtable_start_offset() * wordSize;
 969   assert(vtableEntry::size() * wordSize == 8,
 970          "adjust the scaling in the code below");
 971   int vtable_offset_in_bytes = base + vtableEntry::method_offset_in_bytes();
 972 
 973   if (vtable_index.is_register()) {
 974     lea(method_result, Address(recv_klass,
 975                                vtable_index.as_register(),
 976                                Address::lsl(LogBytesPerWord)));
 977     ldr(method_result, Address(method_result, vtable_offset_in_bytes));
 978   } else {
 979     vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
 980     ldr(method_result, Address(recv_klass, vtable_offset_in_bytes));
 981   }
 982 }
 983 
 984 void MacroAssembler::check_klass_subtype(Register sub_klass,
 985                            Register super_klass,
 986                            Register temp_reg,
 987                            Label& L_success) {
 988   Label L_failure;
 989   check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg,        &L_success, &L_failure, NULL);
 990   check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
 991   bind(L_failure);
 992 }
 993 
 994 
 995 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
 996                                                    Register super_klass,
 997                                                    Register temp_reg,
 998                                                    Label* L_success,
 999                                                    Label* L_failure,
1000                                                    Label* L_slow_path,
1001                                         RegisterOrConstant super_check_offset) {
1002   assert_different_registers(sub_klass, super_klass, temp_reg);
1003   bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
1004   if (super_check_offset.is_register()) {
1005     assert_different_registers(sub_klass, super_klass,
1006                                super_check_offset.as_register());
1007   } else if (must_load_sco) {
1008     assert(temp_reg != noreg, "supply either a temp or a register offset");
1009   }
1010 
1011   Label L_fallthrough;
1012   int label_nulls = 0;
1013   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
1014   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
1015   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
1016   assert(label_nulls <= 1, "at most one NULL in the batch");
1017 
1018   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1019   int sco_offset = in_bytes(Klass::super_check_offset_offset());
1020   Address super_check_offset_addr(super_klass, sco_offset);
1021 
1022   // Hacked jmp, which may only be used just before L_fallthrough.
1023 #define final_jmp(label)                                                \
1024   if (&(label) == &L_fallthrough) { /*do nothing*/ }                    \
1025   else                            b(label)                /*omit semi*/
1026 
1027   // If the pointers are equal, we are done (e.g., String[] elements).
1028   // This self-check enables sharing of secondary supertype arrays among
1029   // non-primary types such as array-of-interface.  Otherwise, each such
1030   // type would need its own customized SSA.
1031   // We move this check to the front of the fast path because many
1032   // type checks are in fact trivially successful in this manner,
1033   // so we get a nicely predicted branch right at the start of the check.
1034   cmp(sub_klass, super_klass);
1035   br(Assembler::EQ, *L_success);
1036 
1037   // Check the supertype display:
1038   if (must_load_sco) {
1039     ldrw(temp_reg, super_check_offset_addr);
1040     super_check_offset = RegisterOrConstant(temp_reg);
1041   }
1042   Address super_check_addr(sub_klass, super_check_offset);
1043   ldr(rscratch1, super_check_addr);
1044   cmp(super_klass, rscratch1); // load displayed supertype
1045 
1046   // This check has worked decisively for primary supers.
1047   // Secondary supers are sought in the super_cache ('super_cache_addr').
1048   // (Secondary supers are interfaces and very deeply nested subtypes.)
1049   // This works in the same check above because of a tricky aliasing
1050   // between the super_cache and the primary super display elements.
1051   // (The 'super_check_addr' can address either, as the case requires.)
1052   // Note that the cache is updated below if it does not help us find
1053   // what we need immediately.
1054   // So if it was a primary super, we can just fail immediately.
1055   // Otherwise, it's the slow path for us (no success at this point).
1056 
1057   if (super_check_offset.is_register()) {
1058     br(Assembler::EQ, *L_success);
1059     cmp(super_check_offset.as_register(), sc_offset);
1060     if (L_failure == &L_fallthrough) {
1061       br(Assembler::EQ, *L_slow_path);
1062     } else {
1063       br(Assembler::NE, *L_failure);
1064       final_jmp(*L_slow_path);
1065     }
1066   } else if (super_check_offset.as_constant() == sc_offset) {
1067     // Need a slow path; fast failure is impossible.
1068     if (L_slow_path == &L_fallthrough) {
1069       br(Assembler::EQ, *L_success);
1070     } else {
1071       br(Assembler::NE, *L_slow_path);
1072       final_jmp(*L_success);
1073     }
1074   } else {
1075     // No slow path; it's a fast decision.
1076     if (L_failure == &L_fallthrough) {
1077       br(Assembler::EQ, *L_success);
1078     } else {
1079       br(Assembler::NE, *L_failure);
1080       final_jmp(*L_success);
1081     }
1082   }
1083 
1084   bind(L_fallthrough);
1085 
1086 #undef final_jmp
1087 }
1088 
1089 // These two are taken from x86, but they look generally useful
1090 
1091 // scans count pointer sized words at [addr] for occurence of value,
1092 // generic
1093 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1094                                 Register scratch) {
1095   Label Lloop, Lexit;
1096   cbz(count, Lexit);
1097   bind(Lloop);
1098   ldr(scratch, post(addr, wordSize));
1099   cmp(value, scratch);
1100   br(EQ, Lexit);
1101   sub(count, count, 1);
1102   cbnz(count, Lloop);
1103   bind(Lexit);
1104 }
1105 
1106 // scans count 4 byte words at [addr] for occurence of value,
1107 // generic
1108 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1109                                 Register scratch) {
1110   Label Lloop, Lexit;
1111   cbz(count, Lexit);
1112   bind(Lloop);
1113   ldrw(scratch, post(addr, wordSize));
1114   cmpw(value, scratch);
1115   br(EQ, Lexit);
1116   sub(count, count, 1);
1117   cbnz(count, Lloop);
1118   bind(Lexit);
1119 }
1120 
1121 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1122                                                    Register super_klass,
1123                                                    Register temp_reg,
1124                                                    Register temp2_reg,
1125                                                    Label* L_success,
1126                                                    Label* L_failure,
1127                                                    bool set_cond_codes) {
1128   assert_different_registers(sub_klass, super_klass, temp_reg);
1129   if (temp2_reg != noreg)
1130     assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1131 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1132 
1133   Label L_fallthrough;
1134   int label_nulls = 0;
1135   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
1136   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
1137   assert(label_nulls <= 1, "at most one NULL in the batch");
1138 
1139   // a couple of useful fields in sub_klass:
1140   int ss_offset = in_bytes(Klass::secondary_supers_offset());
1141   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1142   Address secondary_supers_addr(sub_klass, ss_offset);
1143   Address super_cache_addr(     sub_klass, sc_offset);
1144 
1145   BLOCK_COMMENT("check_klass_subtype_slow_path");
1146 
1147   // Do a linear scan of the secondary super-klass chain.
1148   // This code is rarely used, so simplicity is a virtue here.
1149   // The repne_scan instruction uses fixed registers, which we must spill.
1150   // Don't worry too much about pre-existing connections with the input regs.
1151 
1152   assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1153   assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1154 
1155   // Get super_klass value into r0 (even if it was in r5 or r2).
1156   RegSet pushed_registers;
1157   if (!IS_A_TEMP(r2))    pushed_registers += r2;
1158   if (!IS_A_TEMP(r5))    pushed_registers += r5;
1159 
1160   if (super_klass != r0 || UseCompressedOops) {
1161     if (!IS_A_TEMP(r0))   pushed_registers += r0;
1162   }
1163 
1164   push(pushed_registers, sp);
1165 
1166 #ifndef PRODUCT
1167   mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr);
1168   Address pst_counter_addr(rscratch2);
1169   ldr(rscratch1, pst_counter_addr);
1170   add(rscratch1, rscratch1, 1);
1171   str(rscratch1, pst_counter_addr);
1172 #endif //PRODUCT
1173 
1174   // We will consult the secondary-super array.
1175   ldr(r5, secondary_supers_addr);
1176   // Load the array length.
1177   ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1178   // Skip to start of data.
1179   add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1180 
1181   cmp(sp, zr); // Clear Z flag; SP is never zero
1182   // Scan R2 words at [R5] for an occurrence of R0.
1183   // Set NZ/Z based on last compare.
1184   repne_scan(r5, r0, r2, rscratch1);
1185 
1186   // Unspill the temp. registers:
1187   pop(pushed_registers, sp);
1188 
1189   br(Assembler::NE, *L_failure);
1190 
1191   // Success.  Cache the super we found and proceed in triumph.
1192   str(super_klass, super_cache_addr);
1193 
1194   if (L_success != &L_fallthrough) {
1195     b(*L_success);
1196   }
1197 
1198 #undef IS_A_TEMP
1199 
1200   bind(L_fallthrough);
1201 }
1202 
1203 
1204 void MacroAssembler::verify_oop(Register reg, const char* s) {
1205   if (!VerifyOops) return;
1206 
1207   // Pass register number to verify_oop_subroutine
1208   const char* b = NULL;
1209   {
1210     ResourceMark rm;
1211     stringStream ss;
1212     ss.print("verify_oop: %s: %s", reg->name(), s);
1213     b = code_string(ss.as_string());
1214   }
1215   BLOCK_COMMENT("verify_oop {");
1216 
1217   stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1218   stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1219 
1220   mov(r0, reg);
1221   mov(rscratch1, (address)b);
1222 
1223   // call indirectly to solve generation ordering problem
1224   lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1225   ldr(rscratch2, Address(rscratch2));
1226   blr(rscratch2);
1227 
1228   ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1229   ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1230 
1231   BLOCK_COMMENT("} verify_oop");
1232 }
1233 
1234 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
1235   if (!VerifyOops) return;
1236 
1237   const char* b = NULL;
1238   {
1239     ResourceMark rm;
1240     stringStream ss;
1241     ss.print("verify_oop_addr: %s", s);
1242     b = code_string(ss.as_string());
1243   }
1244   BLOCK_COMMENT("verify_oop_addr {");
1245 
1246   stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1247   stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1248 
1249   // addr may contain sp so we will have to adjust it based on the
1250   // pushes that we just did.
1251   if (addr.uses(sp)) {
1252     lea(r0, addr);
1253     ldr(r0, Address(r0, 4 * wordSize));
1254   } else {
1255     ldr(r0, addr);
1256   }
1257   mov(rscratch1, (address)b);
1258 
1259   // call indirectly to solve generation ordering problem
1260   lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1261   ldr(rscratch2, Address(rscratch2));
1262   blr(rscratch2);
1263 
1264   ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1265   ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1266 
1267   BLOCK_COMMENT("} verify_oop_addr");
1268 }
1269 
1270 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
1271                                          int extra_slot_offset) {
1272   // cf. TemplateTable::prepare_invoke(), if (load_receiver).
1273   int stackElementSize = Interpreter::stackElementSize;
1274   int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
1275 #ifdef ASSERT
1276   int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
1277   assert(offset1 - offset == stackElementSize, "correct arithmetic");
1278 #endif
1279   if (arg_slot.is_constant()) {
1280     return Address(esp, arg_slot.as_constant() * stackElementSize
1281                    + offset);
1282   } else {
1283     add(rscratch1, esp, arg_slot.as_register(),
1284         ext::uxtx, exact_log2(stackElementSize));
1285     return Address(rscratch1, offset);
1286   }
1287 }
1288 
1289 void MacroAssembler::call_VM_leaf_base(address entry_point,
1290                                        int number_of_arguments,
1291                                        Label *retaddr) {
1292   call_VM_leaf_base1(entry_point, number_of_arguments, 0, ret_type_integral, retaddr);
1293 }
1294 
1295 void MacroAssembler::call_VM_leaf_base1(address entry_point,
1296                                         int number_of_gp_arguments,
1297                                         int number_of_fp_arguments,
1298                                         ret_type type,
1299                                         Label *retaddr) {
1300   Label E, L;
1301 
1302   stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
1303 
1304   // We add 1 to number_of_arguments because the thread in arg0 is
1305   // not counted
1306   mov(rscratch1, entry_point);
1307   blrt(rscratch1, number_of_gp_arguments + 1, number_of_fp_arguments, type);
1308   if (retaddr)
1309     bind(*retaddr);
1310 
1311   ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
1312   maybe_isb();
1313 }
1314 
1315 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1316   call_VM_leaf_base(entry_point, number_of_arguments);
1317 }
1318 
1319 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1320   pass_arg0(this, arg_0);
1321   call_VM_leaf_base(entry_point, 1);
1322 }
1323 
1324 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1325   pass_arg0(this, arg_0);
1326   pass_arg1(this, arg_1);
1327   call_VM_leaf_base(entry_point, 2);
1328 }
1329 
1330 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1331                                   Register arg_1, Register arg_2) {
1332   pass_arg0(this, arg_0);
1333   pass_arg1(this, arg_1);
1334   pass_arg2(this, arg_2);
1335   call_VM_leaf_base(entry_point, 3);
1336 }
1337 
1338 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1339   pass_arg0(this, arg_0);
1340   MacroAssembler::call_VM_leaf_base(entry_point, 1);
1341 }
1342 
1343 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1344 
1345   assert(arg_0 != c_rarg1, "smashed arg");
1346   pass_arg1(this, arg_1);
1347   pass_arg0(this, arg_0);
1348   MacroAssembler::call_VM_leaf_base(entry_point, 2);
1349 }
1350 
1351 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1352   assert(arg_0 != c_rarg2, "smashed arg");
1353   assert(arg_1 != c_rarg2, "smashed arg");
1354   pass_arg2(this, arg_2);
1355   assert(arg_0 != c_rarg1, "smashed arg");
1356   pass_arg1(this, arg_1);
1357   pass_arg0(this, arg_0);
1358   MacroAssembler::call_VM_leaf_base(entry_point, 3);
1359 }
1360 
1361 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1362   assert(arg_0 != c_rarg3, "smashed arg");
1363   assert(arg_1 != c_rarg3, "smashed arg");
1364   assert(arg_2 != c_rarg3, "smashed arg");
1365   pass_arg3(this, arg_3);
1366   assert(arg_0 != c_rarg2, "smashed arg");
1367   assert(arg_1 != c_rarg2, "smashed arg");
1368   pass_arg2(this, arg_2);
1369   assert(arg_0 != c_rarg1, "smashed arg");
1370   pass_arg1(this, arg_1);
1371   pass_arg0(this, arg_0);
1372   MacroAssembler::call_VM_leaf_base(entry_point, 4);
1373 }
1374 
1375 void MacroAssembler::null_check(Register reg, int offset) {
1376   if (needs_explicit_null_check(offset)) {
1377     // provoke OS NULL exception if reg = NULL by
1378     // accessing M[reg] w/o changing any registers
1379     // NOTE: this is plenty to provoke a segv
1380     ldr(zr, Address(reg));
1381   } else {
1382     // nothing to do, (later) access of M[reg + offset]
1383     // will provoke OS NULL exception if reg = NULL
1384   }
1385 }
1386 
1387 // MacroAssembler protected routines needed to implement
1388 // public methods
1389 
1390 void MacroAssembler::mov(Register r, Address dest) {
1391   code_section()->relocate(pc(), dest.rspec());
1392   u_int64_t imm64 = (u_int64_t)dest.target();
1393   movptr(r, imm64);
1394 }
1395 
1396 // Move a constant pointer into r.  In AArch64 mode the virtual
1397 // address space is 48 bits in size, so we only need three
1398 // instructions to create a patchable instruction sequence that can
1399 // reach anywhere.
1400 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
1401 #ifndef PRODUCT
1402   {
1403     char buffer[64];
1404     snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
1405     block_comment(buffer);
1406   }
1407 #endif
1408   assert(imm64 < (1ul << 48), "48-bit overflow in address constant");
1409   movz(r, imm64 & 0xffff);
1410   imm64 >>= 16;
1411   movk(r, imm64 & 0xffff, 16);
1412   imm64 >>= 16;
1413   movk(r, imm64 & 0xffff, 32);
1414 }
1415 
1416 // Macro to mov replicated immediate to vector register.
1417 //  Vd will get the following values for different arrangements in T
1418 //   imm32 == hex 000000gh  T8B:  Vd = ghghghghghghghgh
1419 //   imm32 == hex 000000gh  T16B: Vd = ghghghghghghghghghghghghghghghgh
1420 //   imm32 == hex 0000efgh  T4H:  Vd = efghefghefghefgh
1421 //   imm32 == hex 0000efgh  T8H:  Vd = efghefghefghefghefghefghefghefgh
1422 //   imm32 == hex abcdefgh  T2S:  Vd = abcdefghabcdefgh
1423 //   imm32 == hex abcdefgh  T4S:  Vd = abcdefghabcdefghabcdefghabcdefgh
1424 //   T1D/T2D: invalid
1425 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) {
1426   assert(T != T1D && T != T2D, "invalid arrangement");
1427   if (T == T8B || T == T16B) {
1428     assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)");
1429     movi(Vd, T, imm32 & 0xff, 0);
1430     return;
1431   }
1432   u_int32_t nimm32 = ~imm32;
1433   if (T == T4H || T == T8H) {
1434     assert((imm32  & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)");
1435     imm32 &= 0xffff;
1436     nimm32 &= 0xffff;
1437   }
1438   u_int32_t x = imm32;
1439   int movi_cnt = 0;
1440   int movn_cnt = 0;
1441   while (x) { if (x & 0xff) movi_cnt++; x >>= 8; }
1442   x = nimm32;
1443   while (x) { if (x & 0xff) movn_cnt++; x >>= 8; }
1444   if (movn_cnt < movi_cnt) imm32 = nimm32;
1445   unsigned lsl = 0;
1446   while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
1447   if (movn_cnt < movi_cnt)
1448     mvni(Vd, T, imm32 & 0xff, lsl);
1449   else
1450     movi(Vd, T, imm32 & 0xff, lsl);
1451   imm32 >>= 8; lsl += 8;
1452   while (imm32) {
1453     while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
1454     if (movn_cnt < movi_cnt)
1455       bici(Vd, T, imm32 & 0xff, lsl);
1456     else
1457       orri(Vd, T, imm32 & 0xff, lsl);
1458     lsl += 8; imm32 >>= 8;
1459   }
1460 }
1461 
1462 void MacroAssembler::mov_immediate64(Register dst, u_int64_t imm64)
1463 {
1464 #ifndef PRODUCT
1465   {
1466     char buffer[64];
1467     snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
1468     block_comment(buffer);
1469   }
1470 #endif
1471   if (operand_valid_for_logical_immediate(false, imm64)) {
1472     orr(dst, zr, imm64);
1473   } else {
1474     // we can use a combination of MOVZ or MOVN with
1475     // MOVK to build up the constant
1476     u_int64_t imm_h[4];
1477     int zero_count = 0;
1478     int neg_count = 0;
1479     int i;
1480     for (i = 0; i < 4; i++) {
1481       imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
1482       if (imm_h[i] == 0) {
1483         zero_count++;
1484       } else if (imm_h[i] == 0xffffL) {
1485         neg_count++;
1486       }
1487     }
1488     if (zero_count == 4) {
1489       // one MOVZ will do
1490       movz(dst, 0);
1491     } else if (neg_count == 4) {
1492       // one MOVN will do
1493       movn(dst, 0);
1494     } else if (zero_count == 3) {
1495       for (i = 0; i < 4; i++) {
1496         if (imm_h[i] != 0L) {
1497           movz(dst, (u_int32_t)imm_h[i], (i << 4));
1498           break;
1499         }
1500       }
1501     } else if (neg_count == 3) {
1502       // one MOVN will do
1503       for (int i = 0; i < 4; i++) {
1504         if (imm_h[i] != 0xffffL) {
1505           movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1506           break;
1507         }
1508       }
1509     } else if (zero_count == 2) {
1510       // one MOVZ and one MOVK will do
1511       for (i = 0; i < 3; i++) {
1512         if (imm_h[i] != 0L) {
1513           movz(dst, (u_int32_t)imm_h[i], (i << 4));
1514           i++;
1515           break;
1516         }
1517       }
1518       for (;i < 4; i++) {
1519         if (imm_h[i] != 0L) {
1520           movk(dst, (u_int32_t)imm_h[i], (i << 4));
1521         }
1522       }
1523     } else if (neg_count == 2) {
1524       // one MOVN and one MOVK will do
1525       for (i = 0; i < 4; i++) {
1526         if (imm_h[i] != 0xffffL) {
1527           movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1528           i++;
1529           break;
1530         }
1531       }
1532       for (;i < 4; i++) {
1533         if (imm_h[i] != 0xffffL) {
1534           movk(dst, (u_int32_t)imm_h[i], (i << 4));
1535         }
1536       }
1537     } else if (zero_count == 1) {
1538       // one MOVZ and two MOVKs will do
1539       for (i = 0; i < 4; i++) {
1540         if (imm_h[i] != 0L) {
1541           movz(dst, (u_int32_t)imm_h[i], (i << 4));
1542           i++;
1543           break;
1544         }
1545       }
1546       for (;i < 4; i++) {
1547         if (imm_h[i] != 0x0L) {
1548           movk(dst, (u_int32_t)imm_h[i], (i << 4));
1549         }
1550       }
1551     } else if (neg_count == 1) {
1552       // one MOVN and two MOVKs will do
1553       for (i = 0; i < 4; i++) {
1554         if (imm_h[i] != 0xffffL) {
1555           movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1556           i++;
1557           break;
1558         }
1559       }
1560       for (;i < 4; i++) {
1561         if (imm_h[i] != 0xffffL) {
1562           movk(dst, (u_int32_t)imm_h[i], (i << 4));
1563         }
1564       }
1565     } else {
1566       // use a MOVZ and 3 MOVKs (makes it easier to debug)
1567       movz(dst, (u_int32_t)imm_h[0], 0);
1568       for (i = 1; i < 4; i++) {
1569         movk(dst, (u_int32_t)imm_h[i], (i << 4));
1570       }
1571     }
1572   }
1573 }
1574 
1575 void MacroAssembler::mov_immediate32(Register dst, u_int32_t imm32)
1576 {
1577 #ifndef PRODUCT
1578     {
1579       char buffer[64];
1580       snprintf(buffer, sizeof(buffer), "0x%"PRIX32, imm32);
1581       block_comment(buffer);
1582     }
1583 #endif
1584   if (operand_valid_for_logical_immediate(true, imm32)) {
1585     orrw(dst, zr, imm32);
1586   } else {
1587     // we can use MOVZ, MOVN or two calls to MOVK to build up the
1588     // constant
1589     u_int32_t imm_h[2];
1590     imm_h[0] = imm32 & 0xffff;
1591     imm_h[1] = ((imm32 >> 16) & 0xffff);
1592     if (imm_h[0] == 0) {
1593       movzw(dst, imm_h[1], 16);
1594     } else if (imm_h[0] == 0xffff) {
1595       movnw(dst, imm_h[1] ^ 0xffff, 16);
1596     } else if (imm_h[1] == 0) {
1597       movzw(dst, imm_h[0], 0);
1598     } else if (imm_h[1] == 0xffff) {
1599       movnw(dst, imm_h[0] ^ 0xffff, 0);
1600     } else {
1601       // use a MOVZ and MOVK (makes it easier to debug)
1602       movzw(dst, imm_h[0], 0);
1603       movkw(dst, imm_h[1], 16);
1604     }
1605   }
1606 }
1607 
1608 // Form an address from base + offset in Rd.  Rd may or may
1609 // not actually be used: you must use the Address that is returned.
1610 // It is up to you to ensure that the shift provided matches the size
1611 // of your data.
1612 Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) {
1613   if (Address::offset_ok_for_immed(byte_offset, shift))
1614     // It fits; no need for any heroics
1615     return Address(base, byte_offset);
1616 
1617   // Don't do anything clever with negative or misaligned offsets
1618   unsigned mask = (1 << shift) - 1;
1619   if (byte_offset < 0 || byte_offset & mask) {
1620     mov(Rd, byte_offset);
1621     add(Rd, base, Rd);
1622     return Address(Rd);
1623   }
1624 
1625   // See if we can do this with two 12-bit offsets
1626   {
1627     unsigned long word_offset = byte_offset >> shift;
1628     unsigned long masked_offset = word_offset & 0xfff000;
1629     if (Address::offset_ok_for_immed(word_offset - masked_offset)
1630         && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
1631       add(Rd, base, masked_offset << shift);
1632       word_offset -= masked_offset;
1633       return Address(Rd, word_offset << shift);
1634     }
1635   }
1636 
1637   // Do it the hard way
1638   mov(Rd, byte_offset);
1639   add(Rd, base, Rd);
1640   return Address(Rd);
1641 }
1642 
1643 void MacroAssembler::atomic_incw(Register counter_addr, Register tmp) {
1644   Label retry_load;
1645   bind(retry_load);
1646   // flush and load exclusive from the memory location
1647   ldxrw(tmp, counter_addr);
1648   addw(tmp, tmp, 1);
1649   // if we store+flush with no intervening write tmp wil be zero
1650   stxrw(tmp, tmp, counter_addr);
1651   cbnzw(tmp, retry_load);
1652 }
1653 
1654 
1655 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
1656                                     bool want_remainder, Register scratch)
1657 {
1658   // Full implementation of Java idiv and irem.  The function
1659   // returns the (pc) offset of the div instruction - may be needed
1660   // for implicit exceptions.
1661   //
1662   // constraint : ra/rb =/= scratch
1663   //         normal case
1664   //
1665   // input : ra: dividend
1666   //         rb: divisor
1667   //
1668   // result: either
1669   //         quotient  (= ra idiv rb)
1670   //         remainder (= ra irem rb)
1671 
1672   assert(ra != scratch && rb != scratch, "reg cannot be scratch");
1673 
1674   int idivl_offset = offset();
1675   if (! want_remainder) {
1676     sdivw(result, ra, rb);
1677   } else {
1678     sdivw(scratch, ra, rb);
1679     Assembler::msubw(result, scratch, rb, ra);
1680   }
1681 
1682   return idivl_offset;
1683 }
1684 
1685 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
1686                                     bool want_remainder, Register scratch)
1687 {
1688   // Full implementation of Java ldiv and lrem.  The function
1689   // returns the (pc) offset of the div instruction - may be needed
1690   // for implicit exceptions.
1691   //
1692   // constraint : ra/rb =/= scratch
1693   //         normal case
1694   //
1695   // input : ra: dividend
1696   //         rb: divisor
1697   //
1698   // result: either
1699   //         quotient  (= ra idiv rb)
1700   //         remainder (= ra irem rb)
1701 
1702   assert(ra != scratch && rb != scratch, "reg cannot be scratch");
1703 
1704   int idivq_offset = offset();
1705   if (! want_remainder) {
1706     sdiv(result, ra, rb);
1707   } else {
1708     sdiv(scratch, ra, rb);
1709     Assembler::msub(result, scratch, rb, ra);
1710   }
1711 
1712   return idivq_offset;
1713 }
1714 
1715 // MacroAssembler routines found actually to be needed
1716 
1717 void MacroAssembler::push(Register src)
1718 {
1719   str(src, Address(pre(esp, -1 * wordSize)));
1720 }
1721 
1722 void MacroAssembler::pop(Register dst)
1723 {
1724   ldr(dst, Address(post(esp, 1 * wordSize)));
1725 }
1726 
1727 // Note: load_unsigned_short used to be called load_unsigned_word.
1728 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1729   int off = offset();
1730   ldrh(dst, src);
1731   return off;
1732 }
1733 
1734 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1735   int off = offset();
1736   ldrb(dst, src);
1737   return off;
1738 }
1739 
1740 int MacroAssembler::load_signed_short(Register dst, Address src) {
1741   int off = offset();
1742   ldrsh(dst, src);
1743   return off;
1744 }
1745 
1746 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1747   int off = offset();
1748   ldrsb(dst, src);
1749   return off;
1750 }
1751 
1752 int MacroAssembler::load_signed_short32(Register dst, Address src) {
1753   int off = offset();
1754   ldrshw(dst, src);
1755   return off;
1756 }
1757 
1758 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
1759   int off = offset();
1760   ldrsbw(dst, src);
1761   return off;
1762 }
1763 
1764 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1765   switch (size_in_bytes) {
1766   case  8:  ldr(dst, src); break;
1767   case  4:  ldrw(dst, src); break;
1768   case  2:  is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1769   case  1:  is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1770   default:  ShouldNotReachHere();
1771   }
1772 }
1773 
1774 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1775   switch (size_in_bytes) {
1776   case  8:  str(src, dst); break;
1777   case  4:  strw(src, dst); break;
1778   case  2:  strh(src, dst); break;
1779   case  1:  strb(src, dst); break;
1780   default:  ShouldNotReachHere();
1781   }
1782 }
1783 
1784 void MacroAssembler::decrementw(Register reg, int value)
1785 {
1786   if (value < 0)  { incrementw(reg, -value);      return; }
1787   if (value == 0) {                               return; }
1788   if (value < (1 << 12)) { subw(reg, reg, value); return; }
1789   /* else */ {
1790     guarantee(reg != rscratch2, "invalid dst for register decrement");
1791     movw(rscratch2, (unsigned)value);
1792     subw(reg, reg, rscratch2);
1793   }
1794 }
1795 
1796 void MacroAssembler::decrement(Register reg, int value)
1797 {
1798   if (value < 0)  { increment(reg, -value);      return; }
1799   if (value == 0) {                              return; }
1800   if (value < (1 << 12)) { sub(reg, reg, value); return; }
1801   /* else */ {
1802     assert(reg != rscratch2, "invalid dst for register decrement");
1803     mov(rscratch2, (unsigned long)value);
1804     sub(reg, reg, rscratch2);
1805   }
1806 }
1807 
1808 void MacroAssembler::decrementw(Address dst, int value)
1809 {
1810   assert(!dst.uses(rscratch1), "invalid dst for address decrement");
1811   ldrw(rscratch1, dst);
1812   decrementw(rscratch1, value);
1813   strw(rscratch1, dst);
1814 }
1815 
1816 void MacroAssembler::decrement(Address dst, int value)
1817 {
1818   assert(!dst.uses(rscratch1), "invalid address for decrement");
1819   ldr(rscratch1, dst);
1820   decrement(rscratch1, value);
1821   str(rscratch1, dst);
1822 }
1823 
1824 void MacroAssembler::incrementw(Register reg, int value)
1825 {
1826   if (value < 0)  { decrementw(reg, -value);      return; }
1827   if (value == 0) {                               return; }
1828   if (value < (1 << 12)) { addw(reg, reg, value); return; }
1829   /* else */ {
1830     assert(reg != rscratch2, "invalid dst for register increment");
1831     movw(rscratch2, (unsigned)value);
1832     addw(reg, reg, rscratch2);
1833   }
1834 }
1835 
1836 void MacroAssembler::increment(Register reg, int value)
1837 {
1838   if (value < 0)  { decrement(reg, -value);      return; }
1839   if (value == 0) {                              return; }
1840   if (value < (1 << 12)) { add(reg, reg, value); return; }
1841   /* else */ {
1842     assert(reg != rscratch2, "invalid dst for register increment");
1843     movw(rscratch2, (unsigned)value);
1844     add(reg, reg, rscratch2);
1845   }
1846 }
1847 
1848 void MacroAssembler::incrementw(Address dst, int value)
1849 {
1850   assert(!dst.uses(rscratch1), "invalid dst for address increment");
1851   ldrw(rscratch1, dst);
1852   incrementw(rscratch1, value);
1853   strw(rscratch1, dst);
1854 }
1855 
1856 void MacroAssembler::increment(Address dst, int value)
1857 {
1858   assert(!dst.uses(rscratch1), "invalid dst for address increment");
1859   ldr(rscratch1, dst);
1860   increment(rscratch1, value);
1861   str(rscratch1, dst);
1862 }
1863 
1864 
1865 void MacroAssembler::pusha() {
1866   push(0x7fffffff, sp);
1867 }
1868 
1869 void MacroAssembler::popa() {
1870   pop(0x7fffffff, sp);
1871 }
1872 
1873 // Push lots of registers in the bit set supplied.  Don't push sp.
1874 // Return the number of words pushed
1875 int MacroAssembler::push(unsigned int bitset, Register stack) {
1876   int words_pushed = 0;
1877 
1878   // Scan bitset to accumulate register pairs
1879   unsigned char regs[32];
1880   int count = 0;
1881   for (int reg = 0; reg <= 30; reg++) {
1882     if (1 & bitset)
1883       regs[count++] = reg;
1884     bitset >>= 1;
1885   }
1886   regs[count++] = zr->encoding_nocheck();
1887   count &= ~1;  // Only push an even nuber of regs
1888 
1889   if (count) {
1890     stp(as_Register(regs[0]), as_Register(regs[1]),
1891        Address(pre(stack, -count * wordSize)));
1892     words_pushed += 2;
1893   }
1894   for (int i = 2; i < count; i += 2) {
1895     stp(as_Register(regs[i]), as_Register(regs[i+1]),
1896        Address(stack, i * wordSize));
1897     words_pushed += 2;
1898   }
1899 
1900   assert(words_pushed == count, "oops, pushed != count");
1901 
1902   return count;
1903 }
1904 
1905 int MacroAssembler::pop(unsigned int bitset, Register stack) {
1906   int words_pushed = 0;
1907 
1908   // Scan bitset to accumulate register pairs
1909   unsigned char regs[32];
1910   int count = 0;
1911   for (int reg = 0; reg <= 30; reg++) {
1912     if (1 & bitset)
1913       regs[count++] = reg;
1914     bitset >>= 1;
1915   }
1916   regs[count++] = zr->encoding_nocheck();
1917   count &= ~1;
1918 
1919   for (int i = 2; i < count; i += 2) {
1920     ldp(as_Register(regs[i]), as_Register(regs[i+1]),
1921        Address(stack, i * wordSize));
1922     words_pushed += 2;
1923   }
1924   if (count) {
1925     ldp(as_Register(regs[0]), as_Register(regs[1]),
1926        Address(post(stack, count * wordSize)));
1927     words_pushed += 2;
1928   }
1929 
1930   assert(words_pushed == count, "oops, pushed != count");
1931 
1932   return count;
1933 }
1934 #ifdef ASSERT
1935 void MacroAssembler::verify_heapbase(const char* msg) {
1936 #if 0
1937   assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
1938   assert (Universe::heap() != NULL, "java heap should be initialized");
1939   if (CheckCompressedOops) {
1940     Label ok;
1941     push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
1942     cmpptr(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
1943     br(Assembler::EQ, ok);
1944     stop(msg);
1945     bind(ok);
1946     pop(1 << rscratch1->encoding(), sp);
1947   }
1948 #endif
1949 }
1950 #endif
1951 
1952 void MacroAssembler::stop(const char* msg) {
1953   address ip = pc();
1954   pusha();
1955   mov(c_rarg0, (address)msg);
1956   mov(c_rarg1, (address)ip);
1957   mov(c_rarg2, sp);
1958   mov(c_rarg3, CAST_FROM_FN_PTR(address, MacroAssembler::debug64));
1959   // call(c_rarg3);
1960   blrt(c_rarg3, 3, 0, 1);
1961   hlt(0);
1962 }
1963 
1964 // If a constant does not fit in an immediate field, generate some
1965 // number of MOV instructions and then perform the operation.
1966 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1967                                            add_sub_imm_insn insn1,
1968                                            add_sub_reg_insn insn2) {
1969   assert(Rd != zr, "Rd = zr and not setting flags?");
1970   if (operand_valid_for_add_sub_immediate((int)imm)) {
1971     (this->*insn1)(Rd, Rn, imm);
1972   } else {
1973     if (uabs(imm) < (1 << 24)) {
1974        (this->*insn1)(Rd, Rn, imm & -(1 << 12));
1975        (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
1976     } else {
1977        assert_different_registers(Rd, Rn);
1978        mov(Rd, (uint64_t)imm);
1979        (this->*insn2)(Rd, Rn, Rd, LSL, 0);
1980     }
1981   }
1982 }
1983 
1984 // Seperate vsn which sets the flags. Optimisations are more restricted
1985 // because we must set the flags correctly.
1986 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1987                                            add_sub_imm_insn insn1,
1988                                            add_sub_reg_insn insn2) {
1989   if (operand_valid_for_add_sub_immediate((int)imm)) {
1990     (this->*insn1)(Rd, Rn, imm);
1991   } else {
1992     assert_different_registers(Rd, Rn);
1993     assert(Rd != zr, "overflow in immediate operand");
1994     mov(Rd, (uint64_t)imm);
1995     (this->*insn2)(Rd, Rn, Rd, LSL, 0);
1996   }
1997 }
1998 
1999 
2000 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
2001   if (increment.is_register()) {
2002     add(Rd, Rn, increment.as_register());
2003   } else {
2004     add(Rd, Rn, increment.as_constant());
2005   }
2006 }
2007 
2008 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
2009   if (increment.is_register()) {
2010     addw(Rd, Rn, increment.as_register());
2011   } else {
2012     addw(Rd, Rn, increment.as_constant());
2013   }
2014 }
2015 
2016 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
2017   if (decrement.is_register()) {
2018     sub(Rd, Rn, decrement.as_register());
2019   } else {
2020     sub(Rd, Rn, decrement.as_constant());
2021   }
2022 }
2023 
2024 void MacroAssembler::reinit_heapbase()
2025 {
2026   if (UseCompressedOops) {
2027     if (Universe::is_fully_initialized()) {
2028       mov(rheapbase, Universe::narrow_ptrs_base());
2029     } else {
2030       lea(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
2031       ldr(rheapbase, Address(rheapbase));
2032     }
2033   }
2034 }
2035 
2036 // this simulates the behaviour of the x86 cmpxchg instruction using a
2037 // load linked/store conditional pair. we use the acquire/release
2038 // versions of these instructions so that we flush pending writes as
2039 // per Java semantics.
2040 
2041 // n.b the x86 version assumes the old value to be compared against is
2042 // in rax and updates rax with the value located in memory if the
2043 // cmpxchg fails. we supply a register for the old value explicitly
2044 
2045 // the aarch64 load linked/store conditional instructions do not
2046 // accept an offset. so, unlike x86, we must provide a plain register
2047 // to identify the memory word to be compared/exchanged rather than a
2048 // register+offset Address.
2049 
2050 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
2051                                 Label &succeed, Label *fail) {
2052   // oldv holds comparison value
2053   // newv holds value to write in exchange
2054   // addr identifies memory word to compare against/update
2055   // tmp returns 0/1 for success/failure
2056   Label retry_load, nope;
2057 
2058   bind(retry_load);
2059   // flush and load exclusive from the memory location
2060   // and fail if it is not what we expect
2061   ldaxr(tmp, addr);
2062   cmp(tmp, oldv);
2063   br(Assembler::NE, nope);
2064   // if we store+flush with no intervening write tmp wil be zero
2065   stlxr(tmp, newv, addr);
2066   cbzw(tmp, succeed);
2067   // retry so we only ever return after a load fails to compare
2068   // ensures we don't return a stale value after a failed write.
2069   b(retry_load);
2070   // if the memory word differs we return it in oldv and signal a fail
2071   bind(nope);
2072   membar(AnyAny);
2073   mov(oldv, tmp);
2074   if (fail)
2075     b(*fail);
2076 }
2077 
2078 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
2079                                 Label &succeed, Label *fail) {
2080   // oldv holds comparison value
2081   // newv holds value to write in exchange
2082   // addr identifies memory word to compare against/update
2083   // tmp returns 0/1 for success/failure
2084   Label retry_load, nope;
2085 
2086   bind(retry_load);
2087   // flush and load exclusive from the memory location
2088   // and fail if it is not what we expect
2089   ldaxrw(tmp, addr);
2090   cmp(tmp, oldv);
2091   br(Assembler::NE, nope);
2092   // if we store+flush with no intervening write tmp wil be zero
2093   stlxrw(tmp, newv, addr);
2094   cbzw(tmp, succeed);
2095   // retry so we only ever return after a load fails to compare
2096   // ensures we don't return a stale value after a failed write.
2097   b(retry_load);
2098   // if the memory word differs we return it in oldv and signal a fail
2099   bind(nope);
2100   membar(AnyAny);
2101   mov(oldv, tmp);
2102   if (fail)
2103     b(*fail);
2104 }
2105 
2106 static bool different(Register a, RegisterOrConstant b, Register c) {
2107   if (b.is_constant())
2108     return a != c;
2109   else
2110     return a != b.as_register() && a != c && b.as_register() != c;
2111 }
2112 
2113 #define ATOMIC_OP(LDXR, OP, STXR)                                       \
2114 void MacroAssembler::atomic_##OP(Register prev, RegisterOrConstant incr, Register addr) { \
2115   Register result = rscratch2;                                          \
2116   if (prev->is_valid())                                                 \
2117     result = different(prev, incr, addr) ? prev : rscratch2;            \
2118                                                                         \
2119   Label retry_load;                                                     \
2120   bind(retry_load);                                                     \
2121   LDXR(result, addr);                                                   \
2122   OP(rscratch1, result, incr);                                          \
2123   STXR(rscratch1, rscratch1, addr);                                     \
2124   cbnzw(rscratch1, retry_load);                                         \
2125   if (prev->is_valid() && prev != result)                               \
2126     mov(prev, result);                                                  \
2127 }
2128 
2129 ATOMIC_OP(ldxr, add, stxr)
2130 ATOMIC_OP(ldxrw, addw, stxrw)
2131 
2132 #undef ATOMIC_OP
2133 
2134 #define ATOMIC_XCHG(OP, LDXR, STXR)                                     \
2135 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
2136   Register result = rscratch2;                                          \
2137   if (prev->is_valid())                                                 \
2138     result = different(prev, newv, addr) ? prev : rscratch2;            \
2139                                                                         \
2140   Label retry_load;                                                     \
2141   bind(retry_load);                                                     \
2142   LDXR(result, addr);                                                   \
2143   STXR(rscratch1, newv, addr);                                          \
2144   cbnzw(rscratch1, retry_load);                                         \
2145   if (prev->is_valid() && prev != result)                               \
2146     mov(prev, result);                                                  \
2147 }
2148 
2149 ATOMIC_XCHG(xchg, ldxr, stxr)
2150 ATOMIC_XCHG(xchgw, ldxrw, stxrw)
2151 
2152 #undef ATOMIC_XCHG
2153 
2154 void MacroAssembler::incr_allocated_bytes(Register thread,
2155                                           Register var_size_in_bytes,
2156                                           int con_size_in_bytes,
2157                                           Register t1) {
2158   if (!thread->is_valid()) {
2159     thread = rthread;
2160   }
2161   assert(t1->is_valid(), "need temp reg");
2162 
2163   ldr(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset())));
2164   if (var_size_in_bytes->is_valid()) {
2165     add(t1, t1, var_size_in_bytes);
2166   } else {
2167     add(t1, t1, con_size_in_bytes);
2168   }
2169   str(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset())));
2170 }
2171 
2172 #ifndef PRODUCT
2173 extern "C" void findpc(intptr_t x);
2174 #endif
2175 
2176 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
2177 {
2178   // In order to get locks to work, we need to fake a in_VM state
2179   if (ShowMessageBoxOnError ) {
2180     JavaThread* thread = JavaThread::current();
2181     JavaThreadState saved_state = thread->thread_state();
2182     thread->set_thread_state(_thread_in_vm);
2183 #ifndef PRODUCT
2184     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
2185       ttyLocker ttyl;
2186       BytecodeCounter::print();
2187     }
2188 #endif
2189     if (os::message_box(msg, "Execution stopped, print registers?")) {
2190       ttyLocker ttyl;
2191       tty->print_cr(" pc = 0x%016lx", pc);
2192 #ifndef PRODUCT
2193       tty->cr();
2194       findpc(pc);
2195       tty->cr();
2196 #endif
2197       tty->print_cr(" r0 = 0x%016lx", regs[0]);
2198       tty->print_cr(" r1 = 0x%016lx", regs[1]);
2199       tty->print_cr(" r2 = 0x%016lx", regs[2]);
2200       tty->print_cr(" r3 = 0x%016lx", regs[3]);
2201       tty->print_cr(" r4 = 0x%016lx", regs[4]);
2202       tty->print_cr(" r5 = 0x%016lx", regs[5]);
2203       tty->print_cr(" r6 = 0x%016lx", regs[6]);
2204       tty->print_cr(" r7 = 0x%016lx", regs[7]);
2205       tty->print_cr(" r8 = 0x%016lx", regs[8]);
2206       tty->print_cr(" r9 = 0x%016lx", regs[9]);
2207       tty->print_cr("r10 = 0x%016lx", regs[10]);
2208       tty->print_cr("r11 = 0x%016lx", regs[11]);
2209       tty->print_cr("r12 = 0x%016lx", regs[12]);
2210       tty->print_cr("r13 = 0x%016lx", regs[13]);
2211       tty->print_cr("r14 = 0x%016lx", regs[14]);
2212       tty->print_cr("r15 = 0x%016lx", regs[15]);
2213       tty->print_cr("r16 = 0x%016lx", regs[16]);
2214       tty->print_cr("r17 = 0x%016lx", regs[17]);
2215       tty->print_cr("r18 = 0x%016lx", regs[18]);
2216       tty->print_cr("r19 = 0x%016lx", regs[19]);
2217       tty->print_cr("r20 = 0x%016lx", regs[20]);
2218       tty->print_cr("r21 = 0x%016lx", regs[21]);
2219       tty->print_cr("r22 = 0x%016lx", regs[22]);
2220       tty->print_cr("r23 = 0x%016lx", regs[23]);
2221       tty->print_cr("r24 = 0x%016lx", regs[24]);
2222       tty->print_cr("r25 = 0x%016lx", regs[25]);
2223       tty->print_cr("r26 = 0x%016lx", regs[26]);
2224       tty->print_cr("r27 = 0x%016lx", regs[27]);
2225       tty->print_cr("r28 = 0x%016lx", regs[28]);
2226       tty->print_cr("r30 = 0x%016lx", regs[30]);
2227       tty->print_cr("r31 = 0x%016lx", regs[31]);
2228       BREAKPOINT;
2229     }
2230     ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
2231   } else {
2232     ttyLocker ttyl;
2233     ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
2234                     msg);
2235     assert(false, err_msg("DEBUG MESSAGE: %s", msg));
2236   }
2237 }
2238 
2239 #ifdef BUILTIN_SIM
2240 // routine to generate an x86 prolog for a stub function which
2241 // bootstraps into the generated ARM code which directly follows the
2242 // stub
2243 //
2244 // the argument encodes the number of general and fp registers
2245 // passed by the caller and the callng convention (currently just
2246 // the number of general registers and assumes C argument passing)
2247 
2248 extern "C" {
2249 int aarch64_stub_prolog_size();
2250 void aarch64_stub_prolog();
2251 void aarch64_prolog();
2252 }
2253 
2254 void MacroAssembler::c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type,
2255                                    address *prolog_ptr)
2256 {
2257   int calltype = (((ret_type & 0x3) << 8) |
2258                   ((fp_arg_count & 0xf) << 4) |
2259                   (gp_arg_count & 0xf));
2260 
2261   // the addresses for the x86 to ARM entry code we need to use
2262   address start = pc();
2263   // printf("start = %lx\n", start);
2264   int byteCount =  aarch64_stub_prolog_size();
2265   // printf("byteCount = %x\n", byteCount);
2266   int instructionCount = (byteCount + 3)/ 4;
2267   // printf("instructionCount = %x\n", instructionCount);
2268   for (int i = 0; i < instructionCount; i++) {
2269     nop();
2270   }
2271 
2272   memcpy(start, (void*)aarch64_stub_prolog, byteCount);
2273 
2274   // write the address of the setup routine and the call format at the
2275   // end of into the copied code
2276   u_int64_t *patch_end = (u_int64_t *)(start + byteCount);
2277   if (prolog_ptr)
2278     patch_end[-2] = (u_int64_t)prolog_ptr;
2279   patch_end[-1] = calltype;
2280 }
2281 #endif
2282 
2283 void MacroAssembler::push_CPU_state() {
2284     push(0x3fffffff, sp);         // integer registers except lr & sp
2285 
2286     for (int i = 30; i >= 0; i -= 2)
2287       stpd(as_FloatRegister(i), as_FloatRegister(i+1),
2288            Address(pre(sp, -2 * wordSize)));
2289 }
2290 
2291 void MacroAssembler::pop_CPU_state() {
2292   for (int i = 0; i < 32; i += 2)
2293     ldpd(as_FloatRegister(i), as_FloatRegister(i+1),
2294          Address(post(sp, 2 * wordSize)));
2295 
2296   pop(0x3fffffff, sp);         // integer registers except lr & sp
2297 }
2298 
2299 /**
2300  * Helpers for multiply_to_len().
2301  */
2302 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
2303                                      Register src1, Register src2) {
2304   adds(dest_lo, dest_lo, src1);
2305   adc(dest_hi, dest_hi, zr);
2306   adds(dest_lo, dest_lo, src2);
2307   adc(final_dest_hi, dest_hi, zr);
2308 }
2309 
2310 // Generate an address from (r + r1 extend offset).  "size" is the
2311 // size of the operand.  The result may be in rscratch2.
2312 Address MacroAssembler::offsetted_address(Register r, Register r1,
2313                                           Address::extend ext, int offset, int size) {
2314   if (offset || (ext.shift() % size != 0)) {
2315     lea(rscratch2, Address(r, r1, ext));
2316     return Address(rscratch2, offset);
2317   } else {
2318     return Address(r, r1, ext);
2319   }
2320 }
2321 
2322 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
2323 {
2324   assert(offset >= 0, "spill to negative address?");
2325   // Offset reachable ?
2326   //   Not aligned - 9 bits signed offset
2327   //   Aligned - 12 bits unsigned offset shifted
2328   Register base = sp;
2329   if ((offset & (size-1)) && offset >= (1<<8)) {
2330     add(tmp, base, offset & ((1<<12)-1));
2331     base = tmp;
2332     offset &= -1<<12;
2333   }
2334 
2335   if (offset >= (1<<12) * size) {
2336     add(tmp, base, offset & (((1<<12)-1)<<12));
2337     base = tmp;
2338     offset &= ~(((1<<12)-1)<<12);
2339   }
2340 
2341   return Address(base, offset);
2342 }
2343 
2344 /**
2345  * Multiply 64 bit by 64 bit first loop.
2346  */
2347 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
2348                                            Register y, Register y_idx, Register z,
2349                                            Register carry, Register product,
2350                                            Register idx, Register kdx) {
2351   //
2352   //  jlong carry, x[], y[], z[];
2353   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
2354   //    huge_128 product = y[idx] * x[xstart] + carry;
2355   //    z[kdx] = (jlong)product;
2356   //    carry  = (jlong)(product >>> 64);
2357   //  }
2358   //  z[xstart] = carry;
2359   //
2360 
2361   Label L_first_loop, L_first_loop_exit;
2362   Label L_one_x, L_one_y, L_multiply;
2363 
2364   subsw(xstart, xstart, 1);
2365   br(Assembler::MI, L_one_x);
2366 
2367   lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
2368   ldr(x_xstart, Address(rscratch1));
2369   ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
2370 
2371   bind(L_first_loop);
2372   subsw(idx, idx, 1);
2373   br(Assembler::MI, L_first_loop_exit);
2374   subsw(idx, idx, 1);
2375   br(Assembler::MI, L_one_y);
2376   lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2377   ldr(y_idx, Address(rscratch1));
2378   ror(y_idx, y_idx, 32); // convert big-endian to little-endian
2379   bind(L_multiply);
2380 
2381   // AArch64 has a multiply-accumulate instruction that we can't use
2382   // here because it has no way to process carries, so we have to use
2383   // separate add and adc instructions.  Bah.
2384   umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
2385   mul(product, x_xstart, y_idx);
2386   adds(product, product, carry);
2387   adc(carry, rscratch1, zr);   // x_xstart * y_idx + carry -> carry:product
2388 
2389   subw(kdx, kdx, 2);
2390   ror(product, product, 32); // back to big-endian
2391   str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
2392 
2393   b(L_first_loop);
2394 
2395   bind(L_one_y);
2396   ldrw(y_idx, Address(y,  0));
2397   b(L_multiply);
2398 
2399   bind(L_one_x);
2400   ldrw(x_xstart, Address(x,  0));
2401   b(L_first_loop);
2402 
2403   bind(L_first_loop_exit);
2404 }
2405 
2406 /**
2407  * Multiply 128 bit by 128. Unrolled inner loop.
2408  *
2409  */
2410 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
2411                                              Register carry, Register carry2,
2412                                              Register idx, Register jdx,
2413                                              Register yz_idx1, Register yz_idx2,
2414                                              Register tmp, Register tmp3, Register tmp4,
2415                                              Register tmp6, Register product_hi) {
2416 
2417   //   jlong carry, x[], y[], z[];
2418   //   int kdx = ystart+1;
2419   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
2420   //     huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
2421   //     jlong carry2  = (jlong)(tmp3 >>> 64);
2422   //     huge_128 tmp4 = (y[idx]   * product_hi) + z[kdx+idx] + carry2;
2423   //     carry  = (jlong)(tmp4 >>> 64);
2424   //     z[kdx+idx+1] = (jlong)tmp3;
2425   //     z[kdx+idx] = (jlong)tmp4;
2426   //   }
2427   //   idx += 2;
2428   //   if (idx > 0) {
2429   //     yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
2430   //     z[kdx+idx] = (jlong)yz_idx1;
2431   //     carry  = (jlong)(yz_idx1 >>> 64);
2432   //   }
2433   //
2434 
2435   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
2436 
2437   lsrw(jdx, idx, 2);
2438 
2439   bind(L_third_loop);
2440 
2441   subsw(jdx, jdx, 1);
2442   br(Assembler::MI, L_third_loop_exit);
2443   subw(idx, idx, 4);
2444 
2445   lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2446 
2447   ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
2448 
2449   lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2450 
2451   ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
2452   ror(yz_idx2, yz_idx2, 32);
2453 
2454   ldp(rscratch2, rscratch1, Address(tmp6, 0));
2455 
2456   mul(tmp3, product_hi, yz_idx1);  //  yz_idx1 * product_hi -> tmp4:tmp3
2457   umulh(tmp4, product_hi, yz_idx1);
2458 
2459   ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
2460   ror(rscratch2, rscratch2, 32);
2461 
2462   mul(tmp, product_hi, yz_idx2);   //  yz_idx2 * product_hi -> carry2:tmp
2463   umulh(carry2, product_hi, yz_idx2);
2464 
2465   // propagate sum of both multiplications into carry:tmp4:tmp3
2466   adds(tmp3, tmp3, carry);
2467   adc(tmp4, tmp4, zr);
2468   adds(tmp3, tmp3, rscratch1);
2469   adcs(tmp4, tmp4, tmp);
2470   adc(carry, carry2, zr);
2471   adds(tmp4, tmp4, rscratch2);
2472   adc(carry, carry, zr);
2473 
2474   ror(tmp3, tmp3, 32); // convert little-endian to big-endian
2475   ror(tmp4, tmp4, 32);
2476   stp(tmp4, tmp3, Address(tmp6, 0));
2477 
2478   b(L_third_loop);
2479   bind (L_third_loop_exit);
2480 
2481   andw (idx, idx, 0x3);
2482   cbz(idx, L_post_third_loop_done);
2483 
2484   Label L_check_1;
2485   subsw(idx, idx, 2);
2486   br(Assembler::MI, L_check_1);
2487 
2488   lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2489   ldr(yz_idx1, Address(rscratch1, 0));
2490   ror(yz_idx1, yz_idx1, 32);
2491   mul(tmp3, product_hi, yz_idx1);  //  yz_idx1 * product_hi -> tmp4:tmp3
2492   umulh(tmp4, product_hi, yz_idx1);
2493   lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2494   ldr(yz_idx2, Address(rscratch1, 0));
2495   ror(yz_idx2, yz_idx2, 32);
2496 
2497   add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
2498 
2499   ror(tmp3, tmp3, 32);
2500   str(tmp3, Address(rscratch1, 0));
2501 
2502   bind (L_check_1);
2503 
2504   andw (idx, idx, 0x1);
2505   subsw(idx, idx, 1);
2506   br(Assembler::MI, L_post_third_loop_done);
2507   ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2508   mul(tmp3, tmp4, product_hi);  //  tmp4 * product_hi -> carry2:tmp3
2509   umulh(carry2, tmp4, product_hi);
2510   ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2511 
2512   add2_with_carry(carry2, tmp3, tmp4, carry);
2513 
2514   strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2515   extr(carry, carry2, tmp3, 32);
2516 
2517   bind(L_post_third_loop_done);
2518 }
2519 
2520 /**
2521  * Code for BigInteger::multiplyToLen() instrinsic.
2522  *
2523  * r0: x
2524  * r1: xlen
2525  * r2: y
2526  * r3: ylen
2527  * r4:  z
2528  * r5: zlen
2529  * r10: tmp1
2530  * r11: tmp2
2531  * r12: tmp3
2532  * r13: tmp4
2533  * r14: tmp5
2534  * r15: tmp6
2535  * r16: tmp7
2536  *
2537  */
2538 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
2539                                      Register z, Register zlen,
2540                                      Register tmp1, Register tmp2, Register tmp3, Register tmp4,
2541                                      Register tmp5, Register tmp6, Register product_hi) {
2542 
2543   assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6);
2544 
2545   const Register idx = tmp1;
2546   const Register kdx = tmp2;
2547   const Register xstart = tmp3;
2548 
2549   const Register y_idx = tmp4;
2550   const Register carry = tmp5;
2551   const Register product  = xlen;
2552   const Register x_xstart = zlen;  // reuse register
2553 
2554   // First Loop.
2555   //
2556   //  final static long LONG_MASK = 0xffffffffL;
2557   //  int xstart = xlen - 1;
2558   //  int ystart = ylen - 1;
2559   //  long carry = 0;
2560   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
2561   //    long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
2562   //    z[kdx] = (int)product;
2563   //    carry = product >>> 32;
2564   //  }
2565   //  z[xstart] = (int)carry;
2566   //
2567 
2568   movw(idx, ylen);      // idx = ylen;
2569   movw(kdx, zlen);      // kdx = xlen+ylen;
2570   mov(carry, zr);       // carry = 0;
2571 
2572   Label L_done;
2573 
2574   movw(xstart, xlen);
2575   subsw(xstart, xstart, 1);
2576   br(Assembler::MI, L_done);
2577 
2578   multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
2579 
2580   Label L_second_loop;
2581   cbzw(kdx, L_second_loop);
2582 
2583   Label L_carry;
2584   subw(kdx, kdx, 1);
2585   cbzw(kdx, L_carry);
2586 
2587   strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
2588   lsr(carry, carry, 32);
2589   subw(kdx, kdx, 1);
2590 
2591   bind(L_carry);
2592   strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
2593 
2594   // Second and third (nested) loops.
2595   //
2596   // for (int i = xstart-1; i >= 0; i--) { // Second loop
2597   //   carry = 0;
2598   //   for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
2599   //     long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
2600   //                    (z[k] & LONG_MASK) + carry;
2601   //     z[k] = (int)product;
2602   //     carry = product >>> 32;
2603   //   }
2604   //   z[i] = (int)carry;
2605   // }
2606   //
2607   // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
2608 
2609   const Register jdx = tmp1;
2610 
2611   bind(L_second_loop);
2612   mov(carry, zr);                // carry = 0;
2613   movw(jdx, ylen);               // j = ystart+1
2614 
2615   subsw(xstart, xstart, 1);      // i = xstart-1;
2616   br(Assembler::MI, L_done);
2617 
2618   str(z, Address(pre(sp, -4 * wordSize)));
2619 
2620   Label L_last_x;
2621   lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
2622   subsw(xstart, xstart, 1);       // i = xstart-1;
2623   br(Assembler::MI, L_last_x);
2624 
2625   lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
2626   ldr(product_hi, Address(rscratch1));
2627   ror(product_hi, product_hi, 32);  // convert big-endian to little-endian
2628 
2629   Label L_third_loop_prologue;
2630   bind(L_third_loop_prologue);
2631 
2632   str(ylen, Address(sp, wordSize));
2633   stp(x, xstart, Address(sp, 2 * wordSize));
2634   multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
2635                           tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
2636   ldp(z, ylen, Address(post(sp, 2 * wordSize)));
2637   ldp(x, xlen, Address(post(sp, 2 * wordSize)));   // copy old xstart -> xlen
2638 
2639   addw(tmp3, xlen, 1);
2640   strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
2641   subsw(tmp3, tmp3, 1);
2642   br(Assembler::MI, L_done);
2643 
2644   lsr(carry, carry, 32);
2645   strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
2646   b(L_second_loop);
2647 
2648   // Next infrequent code is moved outside loops.
2649   bind(L_last_x);
2650   ldrw(product_hi, Address(x,  0));
2651   b(L_third_loop_prologue);
2652 
2653   bind(L_done);
2654 }
2655 
2656 /**
2657  * Emits code to update CRC-32 with a byte value according to constants in table
2658  *
2659  * @param [in,out]crc   Register containing the crc.
2660  * @param [in]val       Register containing the byte to fold into the CRC.
2661  * @param [in]table     Register containing the table of crc constants.
2662  *
2663  * uint32_t crc;
2664  * val = crc_table[(val ^ crc) & 0xFF];
2665  * crc = val ^ (crc >> 8);
2666  *
2667  */
2668 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
2669   eor(val, val, crc);
2670   andr(val, val, 0xff);
2671   ldrw(val, Address(table, val, Address::lsl(2)));
2672   eor(crc, val, crc, Assembler::LSR, 8);
2673 }
2674 
2675 /**
2676  * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
2677  *
2678  * @param [in,out]crc   Register containing the crc.
2679  * @param [in]v         Register containing the 32-bit to fold into the CRC.
2680  * @param [in]table0    Register containing table 0 of crc constants.
2681  * @param [in]table1    Register containing table 1 of crc constants.
2682  * @param [in]table2    Register containing table 2 of crc constants.
2683  * @param [in]table3    Register containing table 3 of crc constants.
2684  *
2685  * uint32_t crc;
2686  *   v = crc ^ v
2687  *   crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
2688  *
2689  */
2690 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
2691         Register table0, Register table1, Register table2, Register table3,
2692         bool upper) {
2693   eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
2694   uxtb(tmp, v);
2695   ldrw(crc, Address(table3, tmp, Address::lsl(2)));
2696   ubfx(tmp, v, 8, 8);
2697   ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
2698   eor(crc, crc, tmp);
2699   ubfx(tmp, v, 16, 8);
2700   ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
2701   eor(crc, crc, tmp);
2702   ubfx(tmp, v, 24, 8);
2703   ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
2704   eor(crc, crc, tmp);
2705 }
2706 
2707 /**
2708  * @param crc   register containing existing CRC (32-bit)
2709  * @param buf   register pointing to input byte buffer (byte*)
2710  * @param len   register containing number of bytes
2711  * @param table register that will contain address of CRC table
2712  * @param tmp   scratch register
2713  */
2714 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
2715         Register table0, Register table1, Register table2, Register table3,
2716         Register tmp, Register tmp2, Register tmp3) {
2717   Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
2718   unsigned long offset;
2719 
2720     ornw(crc, zr, crc);
2721 
2722   if (UseCRC32) {
2723     Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop;
2724 
2725       subs(len, len, 64);
2726       br(Assembler::GE, CRC_by64_loop);
2727       adds(len, len, 64-4);
2728       br(Assembler::GE, CRC_by4_loop);
2729       adds(len, len, 4);
2730       br(Assembler::GT, CRC_by1_loop);
2731       b(L_exit);
2732 
2733     BIND(CRC_by4_loop);
2734       ldrw(tmp, Address(post(buf, 4)));
2735       subs(len, len, 4);
2736       crc32w(crc, crc, tmp);
2737       br(Assembler::GE, CRC_by4_loop);
2738       adds(len, len, 4);
2739       br(Assembler::LE, L_exit);
2740     BIND(CRC_by1_loop);
2741       ldrb(tmp, Address(post(buf, 1)));
2742       subs(len, len, 1);
2743       crc32b(crc, crc, tmp);
2744       br(Assembler::GT, CRC_by1_loop);
2745       b(L_exit);
2746 
2747       align(CodeEntryAlignment);
2748     BIND(CRC_by64_loop);
2749       subs(len, len, 64);
2750       ldp(tmp, tmp3, Address(post(buf, 16)));
2751       crc32x(crc, crc, tmp);
2752       crc32x(crc, crc, tmp3);
2753       ldp(tmp, tmp3, Address(post(buf, 16)));
2754       crc32x(crc, crc, tmp);
2755       crc32x(crc, crc, tmp3);
2756       ldp(tmp, tmp3, Address(post(buf, 16)));
2757       crc32x(crc, crc, tmp);
2758       crc32x(crc, crc, tmp3);
2759       ldp(tmp, tmp3, Address(post(buf, 16)));
2760       crc32x(crc, crc, tmp);
2761       crc32x(crc, crc, tmp3);
2762       br(Assembler::GE, CRC_by64_loop);
2763       adds(len, len, 64-4);
2764       br(Assembler::GE, CRC_by4_loop);
2765       adds(len, len, 4);
2766       br(Assembler::GT, CRC_by1_loop);
2767     BIND(L_exit);
2768       ornw(crc, zr, crc);
2769       return;
2770   }
2771 
2772     adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2773     if (offset) add(table0, table0, offset);
2774     add(table1, table0, 1*256*sizeof(juint));
2775     add(table2, table0, 2*256*sizeof(juint));
2776     add(table3, table0, 3*256*sizeof(juint));
2777 
2778   if (UseNeon) {
2779       cmp(len, 64);
2780       br(Assembler::LT, L_by16);
2781       eor(v16, T16B, v16, v16);
2782 
2783     Label L_fold;
2784 
2785       add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
2786 
2787       ld1(v0, v1, T2D, post(buf, 32));
2788       ld1r(v4, T2D, post(tmp, 8));
2789       ld1r(v5, T2D, post(tmp, 8));
2790       ld1r(v6, T2D, post(tmp, 8));
2791       ld1r(v7, T2D, post(tmp, 8));
2792       mov(v16, T4S, 0, crc);
2793 
2794       eor(v0, T16B, v0, v16);
2795       sub(len, len, 64);
2796 
2797     BIND(L_fold);
2798       pmull(v22, T8H, v0, v5, T8B);
2799       pmull(v20, T8H, v0, v7, T8B);
2800       pmull(v23, T8H, v0, v4, T8B);
2801       pmull(v21, T8H, v0, v6, T8B);
2802 
2803       pmull2(v18, T8H, v0, v5, T16B);
2804       pmull2(v16, T8H, v0, v7, T16B);
2805       pmull2(v19, T8H, v0, v4, T16B);
2806       pmull2(v17, T8H, v0, v6, T16B);
2807 
2808       uzp1(v24, v20, v22, T8H);
2809       uzp2(v25, v20, v22, T8H);
2810       eor(v20, T16B, v24, v25);
2811 
2812       uzp1(v26, v16, v18, T8H);
2813       uzp2(v27, v16, v18, T8H);
2814       eor(v16, T16B, v26, v27);
2815 
2816       ushll2(v22, T4S, v20, T8H, 8);
2817       ushll(v20, T4S, v20, T4H, 8);
2818 
2819       ushll2(v18, T4S, v16, T8H, 8);
2820       ushll(v16, T4S, v16, T4H, 8);
2821 
2822       eor(v22, T16B, v23, v22);
2823       eor(v18, T16B, v19, v18);
2824       eor(v20, T16B, v21, v20);
2825       eor(v16, T16B, v17, v16);
2826 
2827       uzp1(v17, v16, v20, T2D);
2828       uzp2(v21, v16, v20, T2D);
2829       eor(v17, T16B, v17, v21);
2830 
2831       ushll2(v20, T2D, v17, T4S, 16);
2832       ushll(v16, T2D, v17, T2S, 16);
2833 
2834       eor(v20, T16B, v20, v22);
2835       eor(v16, T16B, v16, v18);
2836 
2837       uzp1(v17, v20, v16, T2D);
2838       uzp2(v21, v20, v16, T2D);
2839       eor(v28, T16B, v17, v21);
2840 
2841       pmull(v22, T8H, v1, v5, T8B);
2842       pmull(v20, T8H, v1, v7, T8B);
2843       pmull(v23, T8H, v1, v4, T8B);
2844       pmull(v21, T8H, v1, v6, T8B);
2845 
2846       pmull2(v18, T8H, v1, v5, T16B);
2847       pmull2(v16, T8H, v1, v7, T16B);
2848       pmull2(v19, T8H, v1, v4, T16B);
2849       pmull2(v17, T8H, v1, v6, T16B);
2850 
2851       ld1(v0, v1, T2D, post(buf, 32));
2852 
2853       uzp1(v24, v20, v22, T8H);
2854       uzp2(v25, v20, v22, T8H);
2855       eor(v20, T16B, v24, v25);
2856 
2857       uzp1(v26, v16, v18, T8H);
2858       uzp2(v27, v16, v18, T8H);
2859       eor(v16, T16B, v26, v27);
2860 
2861       ushll2(v22, T4S, v20, T8H, 8);
2862       ushll(v20, T4S, v20, T4H, 8);
2863 
2864       ushll2(v18, T4S, v16, T8H, 8);
2865       ushll(v16, T4S, v16, T4H, 8);
2866 
2867       eor(v22, T16B, v23, v22);
2868       eor(v18, T16B, v19, v18);
2869       eor(v20, T16B, v21, v20);
2870       eor(v16, T16B, v17, v16);
2871 
2872       uzp1(v17, v16, v20, T2D);
2873       uzp2(v21, v16, v20, T2D);
2874       eor(v16, T16B, v17, v21);
2875 
2876       ushll2(v20, T2D, v16, T4S, 16);
2877       ushll(v16, T2D, v16, T2S, 16);
2878 
2879       eor(v20, T16B, v22, v20);
2880       eor(v16, T16B, v16, v18);
2881 
2882       uzp1(v17, v20, v16, T2D);
2883       uzp2(v21, v20, v16, T2D);
2884       eor(v20, T16B, v17, v21);
2885 
2886       shl(v16, T2D, v28, 1);
2887       shl(v17, T2D, v20, 1);
2888 
2889       eor(v0, T16B, v0, v16);
2890       eor(v1, T16B, v1, v17);
2891 
2892       subs(len, len, 32);
2893       br(Assembler::GE, L_fold);
2894 
2895       mov(crc, 0);
2896       mov(tmp, v0, T1D, 0);
2897       update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
2898       update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
2899       mov(tmp, v0, T1D, 1);
2900       update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
2901       update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
2902       mov(tmp, v1, T1D, 0);
2903       update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
2904       update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
2905       mov(tmp, v1, T1D, 1);
2906       update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
2907       update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
2908 
2909       add(len, len, 32);
2910   }
2911 
2912   BIND(L_by16);
2913     subs(len, len, 16);
2914     br(Assembler::GE, L_by16_loop);
2915     adds(len, len, 16-4);
2916     br(Assembler::GE, L_by4_loop);
2917     adds(len, len, 4);
2918     br(Assembler::GT, L_by1_loop);
2919     b(L_exit);
2920 
2921   BIND(L_by4_loop);
2922     ldrw(tmp, Address(post(buf, 4)));
2923     update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
2924     subs(len, len, 4);
2925     br(Assembler::GE, L_by4_loop);
2926     adds(len, len, 4);
2927     br(Assembler::LE, L_exit);
2928   BIND(L_by1_loop);
2929     subs(len, len, 1);
2930     ldrb(tmp, Address(post(buf, 1)));
2931     update_byte_crc32(crc, tmp, table0);
2932     br(Assembler::GT, L_by1_loop);
2933     b(L_exit);
2934 
2935     align(CodeEntryAlignment);
2936   BIND(L_by16_loop);
2937     subs(len, len, 16);
2938     ldp(tmp, tmp3, Address(post(buf, 16)));
2939     update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
2940     update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
2941     update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
2942     update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
2943     br(Assembler::GE, L_by16_loop);
2944     adds(len, len, 16-4);
2945     br(Assembler::GE, L_by4_loop);
2946     adds(len, len, 4);
2947     br(Assembler::GT, L_by1_loop);
2948   BIND(L_exit);
2949     ornw(crc, zr, crc);
2950 }
2951 
2952 /**
2953  * @param crc   register containing existing CRC (32-bit)
2954  * @param buf   register pointing to input byte buffer (byte*)
2955  * @param len   register containing number of bytes
2956  * @param table register that will contain address of CRC table
2957  * @param tmp   scratch register
2958  */
2959 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
2960         Register table0, Register table1, Register table2, Register table3,
2961         Register tmp, Register tmp2, Register tmp3) {
2962   Label L_exit;
2963   Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop;
2964 
2965     subs(len, len, 64);
2966     br(Assembler::GE, CRC_by64_loop);
2967     adds(len, len, 64-4);
2968     br(Assembler::GE, CRC_by4_loop);
2969     adds(len, len, 4);
2970     br(Assembler::GT, CRC_by1_loop);
2971     b(L_exit);
2972 
2973   BIND(CRC_by4_loop);
2974     ldrw(tmp, Address(post(buf, 4)));
2975     subs(len, len, 4);
2976     crc32cw(crc, crc, tmp);
2977     br(Assembler::GE, CRC_by4_loop);
2978     adds(len, len, 4);
2979     br(Assembler::LE, L_exit);
2980   BIND(CRC_by1_loop);
2981     ldrb(tmp, Address(post(buf, 1)));
2982     subs(len, len, 1);
2983     crc32cb(crc, crc, tmp);
2984     br(Assembler::GT, CRC_by1_loop);
2985     b(L_exit);
2986 
2987     align(CodeEntryAlignment);
2988   BIND(CRC_by64_loop);
2989     subs(len, len, 64);
2990     ldp(tmp, tmp3, Address(post(buf, 16)));
2991     crc32cx(crc, crc, tmp);
2992     crc32cx(crc, crc, tmp3);
2993     ldp(tmp, tmp3, Address(post(buf, 16)));
2994     crc32cx(crc, crc, tmp);
2995     crc32cx(crc, crc, tmp3);
2996     ldp(tmp, tmp3, Address(post(buf, 16)));
2997     crc32cx(crc, crc, tmp);
2998     crc32cx(crc, crc, tmp3);
2999     ldp(tmp, tmp3, Address(post(buf, 16)));
3000     crc32cx(crc, crc, tmp);
3001     crc32cx(crc, crc, tmp3);
3002     br(Assembler::GE, CRC_by64_loop);
3003     adds(len, len, 64-4);
3004     br(Assembler::GE, CRC_by4_loop);
3005     adds(len, len, 4);
3006     br(Assembler::GT, CRC_by1_loop);
3007   BIND(L_exit);
3008     return;
3009 }
3010 
3011 SkipIfEqual::SkipIfEqual(
3012     MacroAssembler* masm, const bool* flag_addr, bool value) {
3013   _masm = masm;
3014   unsigned long offset;
3015   _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset);
3016   _masm->ldrb(rscratch1, Address(rscratch1, offset));
3017   _masm->cbzw(rscratch1, _label);
3018 }
3019 
3020 SkipIfEqual::~SkipIfEqual() {
3021   _masm->bind(_label);
3022 }
3023 
3024 void MacroAssembler::cmpptr(Register src1, Address src2) {
3025   unsigned long offset;
3026   adrp(rscratch1, src2, offset);
3027   ldr(rscratch1, Address(rscratch1, offset));
3028   cmp(src1, rscratch1);
3029 }
3030 
3031 void MacroAssembler::store_check(Register obj, Address dst) {
3032   store_check(obj);
3033 }
3034 
3035 void MacroAssembler::store_check(Register obj) {
3036   // Does a store check for the oop in register obj. The content of
3037   // register obj is destroyed afterwards.
3038 
3039   BarrierSet* bs = Universe::heap()->barrier_set();
3040   assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
3041 
3042   CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
3043   assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3044 
3045   lsr(obj, obj, CardTableModRefBS::card_shift);
3046 
3047   assert(CardTableModRefBS::dirty_card_val() == 0, "must be");
3048 
3049   {
3050     ExternalAddress cardtable((address) ct->byte_map_base);
3051     unsigned long offset;
3052     adrp(rscratch1, cardtable, offset);
3053     assert(offset == 0, "byte_map_base is misaligned");
3054   }
3055 
3056   if (UseCondCardMark) {
3057     Label L_already_dirty;
3058     ldrb(rscratch2,  Address(obj, rscratch1));
3059     cbz(rscratch2, L_already_dirty);
3060     strb(zr, Address(obj, rscratch1));
3061     bind(L_already_dirty);
3062   } else {
3063     strb(zr, Address(obj, rscratch1));
3064   }
3065 }
3066 
3067 void MacroAssembler::load_klass(Register dst, Register src) {
3068   if (UseCompressedClassPointers) {
3069     ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3070     decode_klass_not_null(dst);
3071   } else {
3072     ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3073   }
3074 }
3075 
3076 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
3077   if (UseCompressedClassPointers) {
3078     ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3079     if (Universe::narrow_klass_base() == NULL) {
3080       cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift());
3081       return;
3082     } else if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3083                && Universe::narrow_klass_shift() == 0) {
3084       // Only the bottom 32 bits matter
3085       cmpw(trial_klass, tmp);
3086       return;
3087     }
3088     decode_klass_not_null(tmp);
3089   } else {
3090     ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3091   }
3092   cmp(trial_klass, tmp);
3093 }
3094 
3095 void MacroAssembler::load_prototype_header(Register dst, Register src) {
3096   load_klass(dst, src);
3097   ldr(dst, Address(dst, Klass::prototype_header_offset()));
3098 }
3099 
3100 void MacroAssembler::store_klass(Register dst, Register src) {
3101   // FIXME: Should this be a store release?  concurrent gcs assumes
3102   // klass length is valid if klass field is not null.
3103   if (UseCompressedClassPointers) {
3104     encode_klass_not_null(src);
3105     strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3106   } else {
3107     str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3108   }
3109 }
3110 
3111 void MacroAssembler::store_klass_gap(Register dst, Register src) {
3112   if (UseCompressedClassPointers) {
3113     // Store to klass gap in destination
3114     strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
3115   }
3116 }
3117 
3118 // Algorithm must match oop.inline.hpp encode_heap_oop.
3119 void MacroAssembler::encode_heap_oop(Register d, Register s) {
3120 #ifdef ASSERT
3121   verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
3122 #endif
3123   verify_oop(s, "broken oop in encode_heap_oop");
3124   if (Universe::narrow_oop_base() == NULL) {
3125     if (Universe::narrow_oop_shift() != 0) {
3126       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3127       lsr(d, s, LogMinObjAlignmentInBytes);
3128     } else {
3129       mov(d, s);
3130     }
3131   } else {
3132     subs(d, s, rheapbase);
3133     csel(d, d, zr, Assembler::HS);
3134     lsr(d, d, LogMinObjAlignmentInBytes);
3135 
3136     /*  Old algorithm: is this any worse?
3137     Label nonnull;
3138     cbnz(r, nonnull);
3139     sub(r, r, rheapbase);
3140     bind(nonnull);
3141     lsr(r, r, LogMinObjAlignmentInBytes);
3142     */
3143   }
3144 }
3145 
3146 void MacroAssembler::encode_heap_oop_not_null(Register r) {
3147 #ifdef ASSERT
3148   verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
3149   if (CheckCompressedOops) {
3150     Label ok;
3151     cbnz(r, ok);
3152     stop("null oop passed to encode_heap_oop_not_null");
3153     bind(ok);
3154   }
3155 #endif
3156   verify_oop(r, "broken oop in encode_heap_oop_not_null");
3157   if (Universe::narrow_oop_base() != NULL) {
3158     sub(r, r, rheapbase);
3159   }
3160   if (Universe::narrow_oop_shift() != 0) {
3161     assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3162     lsr(r, r, LogMinObjAlignmentInBytes);
3163   }
3164 }
3165 
3166 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
3167 #ifdef ASSERT
3168   verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
3169   if (CheckCompressedOops) {
3170     Label ok;
3171     cbnz(src, ok);
3172     stop("null oop passed to encode_heap_oop_not_null2");
3173     bind(ok);
3174   }
3175 #endif
3176   verify_oop(src, "broken oop in encode_heap_oop_not_null2");
3177 
3178   Register data = src;
3179   if (Universe::narrow_oop_base() != NULL) {
3180     sub(dst, src, rheapbase);
3181     data = dst;
3182   }
3183   if (Universe::narrow_oop_shift() != 0) {
3184     assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3185     lsr(dst, data, LogMinObjAlignmentInBytes);
3186     data = dst;
3187   }
3188   if (data == src)
3189     mov(dst, src);
3190 }
3191 
3192 void  MacroAssembler::decode_heap_oop(Register d, Register s) {
3193 #ifdef ASSERT
3194   verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
3195 #endif
3196   if (Universe::narrow_oop_base() == NULL) {
3197     if (Universe::narrow_oop_shift() != 0 || d != s) {
3198       lsl(d, s, Universe::narrow_oop_shift());
3199     }
3200   } else {
3201     Label done;
3202     if (d != s)
3203       mov(d, s);
3204     cbz(s, done);
3205     add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
3206     bind(done);
3207   }
3208   verify_oop(d, "broken oop in decode_heap_oop");
3209 }
3210 
3211 void  MacroAssembler::decode_heap_oop_not_null(Register r) {
3212   assert (UseCompressedOops, "should only be used for compressed headers");
3213   assert (Universe::heap() != NULL, "java heap should be initialized");
3214   // Cannot assert, unverified entry point counts instructions (see .ad file)
3215   // vtableStubs also counts instructions in pd_code_size_limit.
3216   // Also do not verify_oop as this is called by verify_oop.
3217   if (Universe::narrow_oop_shift() != 0) {
3218     assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3219     if (Universe::narrow_oop_base() != NULL) {
3220       add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
3221     } else {
3222       add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
3223     }
3224   } else {
3225     assert (Universe::narrow_oop_base() == NULL, "sanity");
3226   }
3227 }
3228 
3229 void  MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
3230   assert (UseCompressedOops, "should only be used for compressed headers");
3231   assert (Universe::heap() != NULL, "java heap should be initialized");
3232   // Cannot assert, unverified entry point counts instructions (see .ad file)
3233   // vtableStubs also counts instructions in pd_code_size_limit.
3234   // Also do not verify_oop as this is called by verify_oop.
3235   if (Universe::narrow_oop_shift() != 0) {
3236     assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3237     if (Universe::narrow_oop_base() != NULL) {
3238       add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
3239     } else {
3240       add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
3241     }
3242   } else {
3243     assert (Universe::narrow_oop_base() == NULL, "sanity");
3244     if (dst != src) {
3245       mov(dst, src);
3246     }
3247   }
3248 }
3249 
3250 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
3251   if (Universe::narrow_klass_base() == NULL) {
3252     if (Universe::narrow_klass_shift() != 0) {
3253       assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3254       lsr(dst, src, LogKlassAlignmentInBytes);
3255     } else {
3256       if (dst != src) mov(dst, src);
3257     }
3258     return;
3259   }
3260 
3261   if (use_XOR_for_compressed_class_base) {
3262     if (Universe::narrow_klass_shift() != 0) {
3263       eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3264       lsr(dst, dst, LogKlassAlignmentInBytes);
3265     } else {
3266       eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3267     }
3268     return;
3269   }
3270 
3271   if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3272       && Universe::narrow_klass_shift() == 0) {
3273     movw(dst, src);
3274     return;
3275   }
3276 
3277 #ifdef ASSERT
3278   verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?");
3279 #endif
3280 
3281   Register rbase = dst;
3282   if (dst == src) rbase = rheapbase;
3283   mov(rbase, (uint64_t)Universe::narrow_klass_base());
3284   sub(dst, src, rbase);
3285   if (Universe::narrow_klass_shift() != 0) {
3286     assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3287     lsr(dst, dst, LogKlassAlignmentInBytes);
3288   }
3289   if (dst == src) reinit_heapbase();
3290 }
3291 
3292 void MacroAssembler::encode_klass_not_null(Register r) {
3293   encode_klass_not_null(r, r);
3294 }
3295 
3296 void  MacroAssembler::decode_klass_not_null(Register dst, Register src) {
3297   Register rbase = dst;
3298   assert (UseCompressedClassPointers, "should only be used for compressed headers");
3299 
3300   if (Universe::narrow_klass_base() == NULL) {
3301     if (Universe::narrow_klass_shift() != 0) {
3302       assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3303       lsl(dst, src, LogKlassAlignmentInBytes);
3304     } else {
3305       if (dst != src) mov(dst, src);
3306     }
3307     return;
3308   }
3309 
3310   if (use_XOR_for_compressed_class_base) {
3311     if (Universe::narrow_klass_shift() != 0) {
3312       lsl(dst, src, LogKlassAlignmentInBytes);
3313       eor(dst, dst, (uint64_t)Universe::narrow_klass_base());
3314     } else {
3315       eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3316     }
3317     return;
3318   }
3319 
3320   if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3321       && Universe::narrow_klass_shift() == 0) {
3322     if (dst != src)
3323       movw(dst, src);
3324     movk(dst, (uint64_t)Universe::narrow_klass_base() >> 32, 32);
3325     return;
3326   }
3327 
3328   // Cannot assert, unverified entry point counts instructions (see .ad file)
3329   // vtableStubs also counts instructions in pd_code_size_limit.
3330   // Also do not verify_oop as this is called by verify_oop.
3331   if (dst == src) rbase = rheapbase;
3332   mov(rbase, (uint64_t)Universe::narrow_klass_base());
3333   if (Universe::narrow_klass_shift() != 0) {
3334     assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3335     add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes);
3336   } else {
3337     add(dst, rbase, src);
3338   }
3339   if (dst == src) reinit_heapbase();
3340 }
3341 
3342 void  MacroAssembler::decode_klass_not_null(Register r) {
3343   decode_klass_not_null(r, r);
3344 }
3345 
3346 void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
3347   assert (UseCompressedOops, "should only be used for compressed oops");
3348   assert (Universe::heap() != NULL, "java heap should be initialized");
3349   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
3350 
3351   int oop_index = oop_recorder()->find_index(obj);
3352   assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop");
3353 
3354   InstructionMark im(this);
3355   RelocationHolder rspec = oop_Relocation::spec(oop_index);
3356   code_section()->relocate(inst_mark(), rspec);
3357   movz(dst, 0xDEAD, 16);
3358   movk(dst, 0xBEEF);
3359 }
3360 
3361 void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
3362   assert (UseCompressedClassPointers, "should only be used for compressed headers");
3363   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
3364   int index = oop_recorder()->find_index(k);
3365   assert(! Universe::heap()->is_in_reserved(k), "should not be an oop");
3366 
3367   InstructionMark im(this);
3368   RelocationHolder rspec = metadata_Relocation::spec(index);
3369   code_section()->relocate(inst_mark(), rspec);
3370   narrowKlass nk = Klass::encode_klass(k);
3371   movz(dst, (nk >> 16), 16);
3372   movk(dst, nk & 0xffff);
3373 }
3374 
3375 void MacroAssembler::load_heap_oop(Register dst, Address src)
3376 {
3377   if (UseCompressedOops) {
3378     ldrw(dst, src);
3379     decode_heap_oop(dst);
3380   } else {
3381     ldr(dst, src);
3382   }
3383 }
3384 
3385 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src)
3386 {
3387   if (UseCompressedOops) {
3388     ldrw(dst, src);
3389     decode_heap_oop_not_null(dst);
3390   } else {
3391     ldr(dst, src);
3392   }
3393 }
3394 
3395 void MacroAssembler::store_heap_oop(Address dst, Register src) {
3396   if (UseCompressedOops) {
3397     assert(!dst.uses(src), "not enough registers");
3398     encode_heap_oop(src);
3399     strw(src, dst);
3400   } else
3401     str(src, dst);
3402 }
3403 
3404 // Used for storing NULLs.
3405 void MacroAssembler::store_heap_oop_null(Address dst) {
3406   if (UseCompressedOops) {
3407     strw(zr, dst);
3408   } else
3409     str(zr, dst);
3410 }
3411 
3412 #if INCLUDE_ALL_GCS
3413 void MacroAssembler::g1_write_barrier_pre(Register obj,
3414                                           Register pre_val,
3415                                           Register thread,
3416                                           Register tmp,
3417                                           bool tosca_live,
3418                                           bool expand_call) {
3419   // If expand_call is true then we expand the call_VM_leaf macro
3420   // directly to skip generating the check by
3421   // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
3422 
3423   assert(thread == rthread, "must be");
3424 
3425   Label done;
3426   Label runtime;
3427 
3428   assert(pre_val != noreg, "check this code");
3429 
3430   if (obj != noreg)
3431     assert_different_registers(obj, pre_val, tmp);
3432 
3433   Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
3434                                        PtrQueue::byte_offset_of_active()));
3435   Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
3436                                        PtrQueue::byte_offset_of_index()));
3437   Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
3438                                        PtrQueue::byte_offset_of_buf()));
3439 
3440 
3441   // Is marking active?
3442   if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
3443     ldrw(tmp, in_progress);
3444   } else {
3445     assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
3446     ldrb(tmp, in_progress);
3447   }
3448   cbzw(tmp, done);
3449 
3450   // Do we need to load the previous value?
3451   if (obj != noreg) {
3452     load_heap_oop(pre_val, Address(obj, 0));
3453   }
3454 
3455   // Is the previous value null?
3456   cbz(pre_val, done);
3457 
3458   // Can we store original value in the thread's buffer?
3459   // Is index == 0?
3460   // (The index field is typed as size_t.)
3461 
3462   ldr(tmp, index);                      // tmp := *index_adr
3463   cbz(tmp, runtime);                    // tmp == 0?
3464                                         // If yes, goto runtime
3465 
3466   sub(tmp, tmp, wordSize);              // tmp := tmp - wordSize
3467   str(tmp, index);                      // *index_adr := tmp
3468   ldr(rscratch1, buffer);
3469   add(tmp, tmp, rscratch1);             // tmp := tmp + *buffer_adr
3470 
3471   // Record the previous value
3472   str(pre_val, Address(tmp, 0));
3473   b(done);
3474 
3475   bind(runtime);
3476   // save the live input values
3477   push(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp);
3478 
3479   // Calling the runtime using the regular call_VM_leaf mechanism generates
3480   // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
3481   // that checks that the *(rfp+frame::interpreter_frame_last_sp) == NULL.
3482   //
3483   // If we care generating the pre-barrier without a frame (e.g. in the
3484   // intrinsified Reference.get() routine) then ebp might be pointing to
3485   // the caller frame and so this check will most likely fail at runtime.
3486   //
3487   // Expanding the call directly bypasses the generation of the check.
3488   // So when we do not have have a full interpreter frame on the stack
3489   // expand_call should be passed true.
3490 
3491   if (expand_call) {
3492     assert(pre_val != c_rarg1, "smashed arg");
3493     pass_arg1(this, thread);
3494     pass_arg0(this, pre_val);
3495     MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
3496   } else {
3497     call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
3498   }
3499 
3500   pop(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp);
3501 
3502   bind(done);
3503 }
3504 
3505 void MacroAssembler::g1_write_barrier_post(Register store_addr,
3506                                            Register new_val,
3507                                            Register thread,
3508                                            Register tmp,
3509                                            Register tmp2) {
3510   assert(thread == rthread, "must be");
3511 
3512   Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
3513                                        PtrQueue::byte_offset_of_index()));
3514   Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
3515                                        PtrQueue::byte_offset_of_buf()));
3516 
3517   BarrierSet* bs = Universe::heap()->barrier_set();
3518   CardTableModRefBS* ct = (CardTableModRefBS*)bs;
3519   assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3520 
3521   Label done;
3522   Label runtime;
3523 
3524   // Does store cross heap regions?
3525 
3526   eor(tmp, store_addr, new_val);
3527   lsr(tmp, tmp, HeapRegion::LogOfHRGrainBytes);
3528   cbz(tmp, done);
3529 
3530   // crosses regions, storing NULL?
3531 
3532   cbz(new_val, done);
3533 
3534   // storing region crossing non-NULL, is card already dirty?
3535 
3536   ExternalAddress cardtable((address) ct->byte_map_base);
3537   assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3538   const Register card_addr = tmp;
3539 
3540   lsr(card_addr, store_addr, CardTableModRefBS::card_shift);
3541 
3542   unsigned long offset;
3543   adrp(tmp2, cardtable, offset);
3544 
3545   // get the address of the card
3546   add(card_addr, card_addr, tmp2);
3547   ldrb(tmp2, Address(card_addr, offset));
3548   cmpw(tmp2, (int)G1SATBCardTableModRefBS::g1_young_card_val());
3549   br(Assembler::EQ, done);
3550 
3551   assert((int)CardTableModRefBS::dirty_card_val() == 0, "must be 0");
3552 
3553   membar(Assembler::StoreLoad);
3554 
3555   ldrb(tmp2, Address(card_addr, offset));
3556   cbzw(tmp2, done);
3557 
3558   // storing a region crossing, non-NULL oop, card is clean.
3559   // dirty card and log.
3560 
3561   strb(zr, Address(card_addr, offset));
3562 
3563   ldr(rscratch1, queue_index);
3564   cbz(rscratch1, runtime);
3565   sub(rscratch1, rscratch1, wordSize);
3566   str(rscratch1, queue_index);
3567 
3568   ldr(tmp2, buffer);
3569   str(card_addr, Address(tmp2, rscratch1));
3570   b(done);
3571 
3572   bind(runtime);
3573   // save the live input values
3574   push(store_addr->bit(true) | new_val->bit(true), sp);
3575   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
3576   pop(store_addr->bit(true) | new_val->bit(true), sp);
3577 
3578   bind(done);
3579 }
3580 
3581 #endif // INCLUDE_ALL_GCS
3582 
3583 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
3584   assert(oop_recorder() != NULL, "this assembler needs a Recorder");
3585   int index = oop_recorder()->allocate_metadata_index(obj);
3586   RelocationHolder rspec = metadata_Relocation::spec(index);
3587   return Address((address)obj, rspec);
3588 }
3589 
3590 // Move an oop into a register.  immediate is true if we want
3591 // immediate instrcutions, i.e. we are not going to patch this
3592 // instruction while the code is being executed by another thread.  In
3593 // that case we can use move immediates rather than the constant pool.
3594 void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) {
3595   int oop_index;
3596   if (obj == NULL) {
3597     oop_index = oop_recorder()->allocate_oop_index(obj);
3598   } else {
3599     oop_index = oop_recorder()->find_index(obj);
3600     assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop");
3601   }
3602   RelocationHolder rspec = oop_Relocation::spec(oop_index);
3603   if (! immediate) {
3604     address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
3605     ldr_constant(dst, Address(dummy, rspec));
3606   } else
3607     mov(dst, Address((address)obj, rspec));
3608 }
3609 
3610 // Move a metadata address into a register.
3611 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
3612   int oop_index;
3613   if (obj == NULL) {
3614     oop_index = oop_recorder()->allocate_metadata_index(obj);
3615   } else {
3616     oop_index = oop_recorder()->find_index(obj);
3617   }
3618   RelocationHolder rspec = metadata_Relocation::spec(oop_index);
3619   mov(dst, Address((address)obj, rspec));
3620 }
3621 
3622 Address MacroAssembler::constant_oop_address(jobject obj) {
3623   assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
3624   assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop");
3625   int oop_index = oop_recorder()->find_index(obj);
3626   return Address((address)obj, oop_Relocation::spec(oop_index));
3627 }
3628 
3629 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3630 void MacroAssembler::tlab_allocate(Register obj,
3631                                    Register var_size_in_bytes,
3632                                    int con_size_in_bytes,
3633                                    Register t1,
3634                                    Register t2,
3635                                    Label& slow_case) {
3636   assert_different_registers(obj, t2);
3637   assert_different_registers(obj, var_size_in_bytes);
3638   Register end = t2;
3639 
3640   // verify_tlab();
3641 
3642   ldr(obj, Address(rthread, JavaThread::tlab_top_offset()));
3643   if (var_size_in_bytes == noreg) {
3644     lea(end, Address(obj, con_size_in_bytes));
3645   } else {
3646     lea(end, Address(obj, var_size_in_bytes));
3647   }
3648   ldr(rscratch1, Address(rthread, JavaThread::tlab_end_offset()));
3649   cmp(end, rscratch1);
3650   br(Assembler::HI, slow_case);
3651 
3652   // update the tlab top pointer
3653   str(end, Address(rthread, JavaThread::tlab_top_offset()));
3654 
3655   // recover var_size_in_bytes if necessary
3656   if (var_size_in_bytes == end) {
3657     sub(var_size_in_bytes, var_size_in_bytes, obj);
3658   }
3659   // verify_tlab();
3660 }
3661 
3662 // Preserves r19, and r3.
3663 Register MacroAssembler::tlab_refill(Label& retry,
3664                                      Label& try_eden,
3665                                      Label& slow_case) {
3666   Register top = r0;
3667   Register t1  = r2;
3668   Register t2  = r4;
3669   assert_different_registers(top, rthread, t1, t2, /* preserve: */ r19, r3);
3670   Label do_refill, discard_tlab;
3671 
3672   if (!Universe::heap()->supports_inline_contig_alloc()) {
3673     // No allocation in the shared eden.
3674     b(slow_case);
3675   }
3676 
3677   ldr(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3678   ldr(t1,  Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
3679 
3680   // calculate amount of free space
3681   sub(t1, t1, top);
3682   lsr(t1, t1, LogHeapWordSize);
3683 
3684   // Retain tlab and allocate object in shared space if
3685   // the amount free in the tlab is too large to discard.
3686 
3687   ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
3688   cmp(t1, rscratch1);
3689   br(Assembler::LE, discard_tlab);
3690 
3691   // Retain
3692   // ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
3693   mov(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
3694   add(rscratch1, rscratch1, t2);
3695   str(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
3696 
3697   if (TLABStats) {
3698     // increment number of slow_allocations
3699     addmw(Address(rthread, in_bytes(JavaThread::tlab_slow_allocations_offset())),
3700          1, rscratch1);
3701   }
3702   b(try_eden);
3703 
3704   bind(discard_tlab);
3705   if (TLABStats) {
3706     // increment number of refills
3707     addmw(Address(rthread, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1,
3708          rscratch1);
3709     // accumulate wastage -- t1 is amount free in tlab
3710     addmw(Address(rthread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1,
3711          rscratch1);
3712   }
3713 
3714   // if tlab is currently allocated (top or end != null) then
3715   // fill [top, end + alignment_reserve) with array object
3716   cbz(top, do_refill);
3717 
3718   // set up the mark word
3719   mov(rscratch1, (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
3720   str(rscratch1, Address(top, oopDesc::mark_offset_in_bytes()));
3721   // set the length to the remaining space
3722   sub(t1, t1, typeArrayOopDesc::header_size(T_INT));
3723   add(t1, t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
3724   lsl(t1, t1, log2_intptr(HeapWordSize/sizeof(jint)));
3725   strw(t1, Address(top, arrayOopDesc::length_offset_in_bytes()));
3726   // set klass to intArrayKlass
3727   {
3728     unsigned long offset;
3729     // dubious reloc why not an oop reloc?
3730     adrp(rscratch1, ExternalAddress((address)Universe::intArrayKlassObj_addr()),
3731          offset);
3732     ldr(t1, Address(rscratch1, offset));
3733   }
3734   // store klass last.  concurrent gcs assumes klass length is valid if
3735   // klass field is not null.
3736   store_klass(top, t1);
3737 
3738   mov(t1, top);
3739   ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
3740   sub(t1, t1, rscratch1);
3741   incr_allocated_bytes(rthread, t1, 0, rscratch1);
3742 
3743   // refill the tlab with an eden allocation
3744   bind(do_refill);
3745   ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_size_offset())));
3746   lsl(t1, t1, LogHeapWordSize);
3747   // allocate new tlab, address returned in top
3748   eden_allocate(top, t1, 0, t2, slow_case);
3749 
3750   // Check that t1 was preserved in eden_allocate.
3751 #ifdef ASSERT
3752   if (UseTLAB) {
3753     Label ok;
3754     Register tsize = r4;
3755     assert_different_registers(tsize, rthread, t1);
3756     str(tsize, Address(pre(sp, -16)));
3757     ldr(tsize, Address(rthread, in_bytes(JavaThread::tlab_size_offset())));
3758     lsl(tsize, tsize, LogHeapWordSize);
3759     cmp(t1, tsize);
3760     br(Assembler::EQ, ok);
3761     STOP("assert(t1 != tlab size)");
3762     should_not_reach_here();
3763 
3764     bind(ok);
3765     ldr(tsize, Address(post(sp, 16)));
3766   }
3767 #endif
3768   str(top, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
3769   str(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3770   add(top, top, t1);
3771   sub(top, top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
3772   str(top, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
3773   verify_tlab();
3774   b(retry);
3775 
3776   return rthread; // for use by caller
3777 }
3778 
3779 // Defines obj, preserves var_size_in_bytes
3780 void MacroAssembler::eden_allocate(Register obj,
3781                                    Register var_size_in_bytes,
3782                                    int con_size_in_bytes,
3783                                    Register t1,
3784                                    Label& slow_case) {
3785   assert_different_registers(obj, var_size_in_bytes, t1);
3786   if (!Universe::heap()->supports_inline_contig_alloc()) {
3787     b(slow_case);
3788   } else {
3789     Register end = t1;
3790     Register heap_end = rscratch2;
3791     Label retry;
3792     bind(retry);
3793     {
3794       unsigned long offset;
3795       adrp(rscratch1, ExternalAddress((address) Universe::heap()->end_addr()), offset);
3796       ldr(heap_end, Address(rscratch1, offset));
3797     }
3798 
3799     ExternalAddress heap_top((address) Universe::heap()->top_addr());
3800 
3801     // Get the current top of the heap
3802     {
3803       unsigned long offset;
3804       adrp(rscratch1, heap_top, offset);
3805       // Use add() here after ARDP, rather than lea().
3806       // lea() does not generate anything if its offset is zero.
3807       // However, relocs expect to find either an ADD or a load/store
3808       // insn after an ADRP.  add() always generates an ADD insn, even
3809       // for add(Rn, Rn, 0).
3810       add(rscratch1, rscratch1, offset);
3811       ldaxr(obj, rscratch1);
3812     }
3813 
3814     // Adjust it my the size of our new object
3815     if (var_size_in_bytes == noreg) {
3816       lea(end, Address(obj, con_size_in_bytes));
3817     } else {
3818       lea(end, Address(obj, var_size_in_bytes));
3819     }
3820 
3821     // if end < obj then we wrapped around high memory
3822     cmp(end, obj);
3823     br(Assembler::LO, slow_case);
3824 
3825     cmp(end, heap_end);
3826     br(Assembler::HI, slow_case);
3827 
3828     // If heap_top hasn't been changed by some other thread, update it.
3829     stlxr(rscratch2, end, rscratch1);
3830     cbnzw(rscratch2, retry);
3831   }
3832 }
3833 
3834 void MacroAssembler::verify_tlab() {
3835 #ifdef ASSERT
3836   if (UseTLAB && VerifyOops) {
3837     Label next, ok;
3838 
3839     stp(rscratch2, rscratch1, Address(pre(sp, -16)));
3840 
3841     ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3842     ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
3843     cmp(rscratch2, rscratch1);
3844     br(Assembler::HS, next);
3845     STOP("assert(top >= start)");
3846     should_not_reach_here();
3847 
3848     bind(next);
3849     ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
3850     ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3851     cmp(rscratch2, rscratch1);
3852     br(Assembler::HS, ok);
3853     STOP("assert(top <= end)");
3854     should_not_reach_here();
3855 
3856     bind(ok);
3857     ldp(rscratch2, rscratch1, Address(post(sp, 16)));
3858   }
3859 #endif
3860 }
3861 
3862 // Writes to stack successive pages until offset reached to check for
3863 // stack overflow + shadow pages.  This clobbers tmp.
3864 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
3865   assert_different_registers(tmp, size, rscratch1);
3866   mov(tmp, sp);
3867   // Bang stack for total size given plus shadow page size.
3868   // Bang one page at a time because large size can bang beyond yellow and
3869   // red zones.
3870   Label loop;
3871   mov(rscratch1, os::vm_page_size());
3872   bind(loop);
3873   lea(tmp, Address(tmp, -os::vm_page_size()));
3874   subsw(size, size, rscratch1);
3875   str(size, Address(tmp));
3876   br(Assembler::GT, loop);
3877 
3878   // Bang down shadow pages too.
3879   // At this point, (tmp-0) is the last address touched, so don't
3880   // touch it again.  (It was touched as (tmp-pagesize) but then tmp
3881   // was post-decremented.)  Skip this address by starting at i=1, and
3882   // touch a few more pages below.  N.B.  It is important to touch all
3883   // the way down to and including i=StackShadowPages.
3884   for (int i = 0; i< StackShadowPages-1; i++) {
3885     // this could be any sized move but this is can be a debugging crumb
3886     // so the bigger the better.
3887     lea(tmp, Address(tmp, -os::vm_page_size()));
3888     str(size, Address(tmp));
3889   }
3890 }
3891 
3892 
3893 address MacroAssembler::read_polling_page(Register r, address page, relocInfo::relocType rtype) {
3894   unsigned long off;
3895   adrp(r, Address(page, rtype), off);
3896   InstructionMark im(this);
3897   code_section()->relocate(inst_mark(), rtype);
3898   ldrw(zr, Address(r, off));
3899   return inst_mark();
3900 }
3901 
3902 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
3903   InstructionMark im(this);
3904   code_section()->relocate(inst_mark(), rtype);
3905   ldrw(zr, Address(r, 0));
3906   return inst_mark();
3907 }
3908 
3909 void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
3910   relocInfo::relocType rtype = dest.rspec().reloc()->type();
3911   if (uabs(pc() - dest.target()) >= (1LL << 32)) {
3912     guarantee(rtype == relocInfo::none
3913               || rtype == relocInfo::external_word_type
3914               || rtype == relocInfo::poll_type
3915               || rtype == relocInfo::poll_return_type,
3916               "can only use a fixed address with an ADRP");
3917     // Out of range.  This doesn't happen very often, but we have to
3918     // handle it
3919     mov(reg1, dest);
3920     byte_offset = 0;
3921   } else {
3922     InstructionMark im(this);
3923     code_section()->relocate(inst_mark(), dest.rspec());
3924     byte_offset = (uint64_t)dest.target() & 0xfff;
3925     _adrp(reg1, dest.target());
3926   }
3927 }
3928 
3929 void MacroAssembler::build_frame(int framesize) {
3930   assert(framesize > 0, "framesize must be > 0");
3931   if (framesize < ((1 << 9) + 2 * wordSize)) {
3932     sub(sp, sp, framesize);
3933     stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
3934     if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
3935   } else {
3936     stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
3937     if (PreserveFramePointer) mov(rfp, sp);
3938     if (framesize < ((1 << 12) + 2 * wordSize))
3939       sub(sp, sp, framesize - 2 * wordSize);
3940     else {
3941       mov(rscratch1, framesize - 2 * wordSize);
3942       sub(sp, sp, rscratch1);
3943     }
3944   }
3945 }
3946 
3947 void MacroAssembler::remove_frame(int framesize) {
3948   assert(framesize > 0, "framesize must be > 0");
3949   if (framesize < ((1 << 9) + 2 * wordSize)) {
3950     ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
3951     add(sp, sp, framesize);
3952   } else {
3953     if (framesize < ((1 << 12) + 2 * wordSize))
3954       add(sp, sp, framesize - 2 * wordSize);
3955     else {
3956       mov(rscratch1, framesize - 2 * wordSize);
3957       add(sp, sp, rscratch1);
3958     }
3959     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
3960   }
3961 }
3962 
3963 
3964 // Search for str1 in str2 and return index or -1
3965 void MacroAssembler::string_indexof(Register str2, Register str1,
3966                                     Register cnt2, Register cnt1,
3967                                     Register tmp1, Register tmp2,
3968                                     Register tmp3, Register tmp4,
3969                                     int icnt1, Register result) {
3970   Label BM, LINEARSEARCH, DONE, NOMATCH, MATCH;
3971 
3972   Register ch1 = rscratch1;
3973   Register ch2 = rscratch2;
3974   Register cnt1tmp = tmp1;
3975   Register cnt2tmp = tmp2;
3976   Register cnt1_neg = cnt1;
3977   Register cnt2_neg = cnt2;
3978   Register result_tmp = tmp4;
3979 
3980   // Note, inline_string_indexOf() generates checks:
3981   // if (substr.count > string.count) return -1;
3982   // if (substr.count == 0) return 0;
3983 
3984 // We have two strings, a source string in str2, cnt2 and a pattern string
3985 // in str1, cnt1. Find the 1st occurence of pattern in source or return -1.
3986 
3987 // For larger pattern and source we use a simplified Boyer Moore algorithm.
3988 // With a small pattern and source we use linear scan.
3989 
3990   if (icnt1 == -1) {
3991     cmp(cnt1, 256);             // Use Linear Scan if cnt1 < 8 || cnt1 >= 256
3992     ccmp(cnt1, 8, 0b0000, LO);  // Can't handle skip >= 256 because we use
3993     br(LO, LINEARSEARCH);       // a byte array.
3994     cmp(cnt1, cnt2, LSR, 2);    // Source must be 4 * pattern for BM
3995     br(HS, LINEARSEARCH);
3996   }
3997 
3998 // The Boyer Moore alogorithm is based on the description here:-
3999 //
4000 // http://en.wikipedia.org/wiki/Boyer%E2%80%93Moore_string_search_algorithm
4001 //
4002 // This describes and algorithm with 2 shift rules. The 'Bad Character' rule
4003 // and the 'Good Suffix' rule.
4004 //
4005 // These rules are essentially heuristics for how far we can shift the
4006 // pattern along the search string.
4007 //
4008 // The implementation here uses the 'Bad Character' rule only because of the
4009 // complexity of initialisation for the 'Good Suffix' rule.
4010 //
4011 // This is also known as the Boyer-Moore-Horspool algorithm:-
4012 //
4013 // http://en.wikipedia.org/wiki/Boyer-Moore-Horspool_algorithm
4014 //
4015 // #define ASIZE 128
4016 //
4017 //    int bm(unsigned char *x, int m, unsigned char *y, int n) {
4018 //       int i, j;
4019 //       unsigned c;
4020 //       unsigned char bc[ASIZE];
4021 //
4022 //       /* Preprocessing */
4023 //       for (i = 0; i < ASIZE; ++i)
4024 //          bc[i] = 0;
4025 //       for (i = 0; i < m - 1; ) {
4026 //          c = x[i];
4027 //          ++i;
4028 //          if (c < ASIZE) bc[c] = i;
4029 //       }
4030 //
4031 //       /* Searching */
4032 //       j = 0;
4033 //       while (j <= n - m) {
4034 //          c = y[i+j];
4035 //          if (x[m-1] == c)
4036 //            for (i = m - 2; i >= 0 && x[i] == y[i + j]; --i);
4037 //          if (i < 0) return j;
4038 //          if (c < ASIZE)
4039 //            j = j - bc[y[j+m-1]] + m;
4040 //          else
4041 //            j += 1; // Advance by 1 only if char >= ASIZE
4042 //       }
4043 //    }
4044 
4045   if (icnt1 == -1) {
4046     BIND(BM);
4047 
4048     Label ZLOOP, BCLOOP, BCSKIP, BMLOOPSTR2, BMLOOPSTR1, BMSKIP;
4049     Label BMADV, BMMATCH, BMCHECKEND;
4050 
4051     Register cnt1end = tmp2;
4052     Register str2end = cnt2;
4053     Register skipch = tmp2;
4054 
4055     // Restrict ASIZE to 128 to reduce stack space/initialisation.
4056     // The presence of chars >= ASIZE in the target string does not affect
4057     // performance, but we must be careful not to initialise them in the stack
4058     // array.
4059     // The presence of chars >= ASIZE in the source string may adversely affect
4060     // performance since we can only advance by one when we encounter one.
4061 
4062       stp(zr, zr, pre(sp, -128));
4063       for (int i = 1; i < 8; i++)
4064           stp(zr, zr, Address(sp, i*16));
4065 
4066       mov(cnt1tmp, 0);
4067       sub(cnt1end, cnt1, 1);
4068     BIND(BCLOOP);
4069       ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1)));
4070       cmp(ch1, 128);
4071       add(cnt1tmp, cnt1tmp, 1);
4072       br(HS, BCSKIP);
4073       strb(cnt1tmp, Address(sp, ch1));
4074     BIND(BCSKIP);
4075       cmp(cnt1tmp, cnt1end);
4076       br(LT, BCLOOP);
4077 
4078       mov(result_tmp, str2);
4079 
4080       sub(cnt2, cnt2, cnt1);
4081       add(str2end, str2, cnt2, LSL, 1);
4082     BIND(BMLOOPSTR2);
4083       sub(cnt1tmp, cnt1, 1);
4084       ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1)));
4085       ldrh(skipch, Address(str2, cnt1tmp, Address::lsl(1)));
4086       cmp(ch1, skipch);
4087       br(NE, BMSKIP);
4088       subs(cnt1tmp, cnt1tmp, 1);
4089       br(LT, BMMATCH);
4090     BIND(BMLOOPSTR1);
4091       ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1)));
4092       ldrh(ch2, Address(str2, cnt1tmp, Address::lsl(1)));
4093       cmp(ch1, ch2);
4094       br(NE, BMSKIP);
4095       subs(cnt1tmp, cnt1tmp, 1);
4096       br(GE, BMLOOPSTR1);
4097     BIND(BMMATCH);
4098       sub(result_tmp, str2, result_tmp);
4099       lsr(result, result_tmp, 1);
4100       add(sp, sp, 128);
4101       b(DONE);
4102     BIND(BMADV);
4103       add(str2, str2, 2);
4104       b(BMCHECKEND);
4105     BIND(BMSKIP);
4106       cmp(skipch, 128);
4107       br(HS, BMADV);
4108       ldrb(ch2, Address(sp, skipch));
4109       add(str2, str2, cnt1, LSL, 1);
4110       sub(str2, str2, ch2, LSL, 1);
4111     BIND(BMCHECKEND);
4112       cmp(str2, str2end);
4113       br(LE, BMLOOPSTR2);
4114       add(sp, sp, 128);
4115       b(NOMATCH);
4116   }
4117 
4118   BIND(LINEARSEARCH);
4119   {
4120     Label DO1, DO2, DO3;
4121 
4122     Register str2tmp = tmp2;
4123     Register first = tmp3;
4124 
4125     if (icnt1 == -1)
4126     {
4127         Label DOSHORT, FIRST_LOOP, STR2_NEXT, STR1_LOOP, STR1_NEXT, LAST_WORD;
4128 
4129         cmp(cnt1, 4);
4130         br(LT, DOSHORT);
4131 
4132         sub(cnt2, cnt2, cnt1);
4133         sub(cnt1, cnt1, 4);
4134         mov(result_tmp, cnt2);
4135 
4136         lea(str1, Address(str1, cnt1, Address::uxtw(1)));
4137         lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4138         sub(cnt1_neg, zr, cnt1, LSL, 1);
4139         sub(cnt2_neg, zr, cnt2, LSL, 1);
4140         ldr(first, Address(str1, cnt1_neg));
4141 
4142       BIND(FIRST_LOOP);
4143         ldr(ch2, Address(str2, cnt2_neg));
4144         cmp(first, ch2);
4145         br(EQ, STR1_LOOP);
4146       BIND(STR2_NEXT);
4147         adds(cnt2_neg, cnt2_neg, 2);
4148         br(LE, FIRST_LOOP);
4149         b(NOMATCH);
4150 
4151       BIND(STR1_LOOP);
4152         adds(cnt1tmp, cnt1_neg, 8);
4153         add(cnt2tmp, cnt2_neg, 8);
4154         br(GE, LAST_WORD);
4155 
4156       BIND(STR1_NEXT);
4157         ldr(ch1, Address(str1, cnt1tmp));
4158         ldr(ch2, Address(str2, cnt2tmp));
4159         cmp(ch1, ch2);
4160         br(NE, STR2_NEXT);
4161         adds(cnt1tmp, cnt1tmp, 8);
4162         add(cnt2tmp, cnt2tmp, 8);
4163         br(LT, STR1_NEXT);
4164 
4165       BIND(LAST_WORD);
4166         ldr(ch1, Address(str1));
4167         sub(str2tmp, str2, cnt1_neg);         // adjust to corresponding
4168         ldr(ch2, Address(str2tmp, cnt2_neg)); // word in str2
4169         cmp(ch1, ch2);
4170         br(NE, STR2_NEXT);
4171         b(MATCH);
4172 
4173       BIND(DOSHORT);
4174         cmp(cnt1, 2);
4175         br(LT, DO1);
4176         br(GT, DO3);
4177     }
4178 
4179     if (icnt1 == 4) {
4180       Label CH1_LOOP;
4181 
4182         ldr(ch1, str1);
4183         sub(cnt2, cnt2, 4);
4184         mov(result_tmp, cnt2);
4185         lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4186         sub(cnt2_neg, zr, cnt2, LSL, 1);
4187 
4188       BIND(CH1_LOOP);
4189         ldr(ch2, Address(str2, cnt2_neg));
4190         cmp(ch1, ch2);
4191         br(EQ, MATCH);
4192         adds(cnt2_neg, cnt2_neg, 2);
4193         br(LE, CH1_LOOP);
4194         b(NOMATCH);
4195     }
4196 
4197     if (icnt1 == -1 || icnt1 == 2) {
4198       Label CH1_LOOP;
4199 
4200       BIND(DO2);
4201         ldrw(ch1, str1);
4202         sub(cnt2, cnt2, 2);
4203         mov(result_tmp, cnt2);
4204         lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4205         sub(cnt2_neg, zr, cnt2, LSL, 1);
4206 
4207       BIND(CH1_LOOP);
4208         ldrw(ch2, Address(str2, cnt2_neg));
4209         cmp(ch1, ch2);
4210         br(EQ, MATCH);
4211         adds(cnt2_neg, cnt2_neg, 2);
4212         br(LE, CH1_LOOP);
4213         b(NOMATCH);
4214     }
4215 
4216     if (icnt1 == -1 || icnt1 == 3) {
4217       Label FIRST_LOOP, STR2_NEXT, STR1_LOOP;
4218 
4219       BIND(DO3);
4220         ldrw(first, str1);
4221         ldrh(ch1, Address(str1, 4));
4222 
4223         sub(cnt2, cnt2, 3);
4224         mov(result_tmp, cnt2);
4225         lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4226         sub(cnt2_neg, zr, cnt2, LSL, 1);
4227 
4228       BIND(FIRST_LOOP);
4229         ldrw(ch2, Address(str2, cnt2_neg));
4230         cmpw(first, ch2);
4231         br(EQ, STR1_LOOP);
4232       BIND(STR2_NEXT);
4233         adds(cnt2_neg, cnt2_neg, 2);
4234         br(LE, FIRST_LOOP);
4235         b(NOMATCH);
4236 
4237       BIND(STR1_LOOP);
4238         add(cnt2tmp, cnt2_neg, 4);
4239         ldrh(ch2, Address(str2, cnt2tmp));
4240         cmp(ch1, ch2);
4241         br(NE, STR2_NEXT);
4242         b(MATCH);
4243     }
4244 
4245     if (icnt1 == -1 || icnt1 == 1) {
4246       Label CH1_LOOP, HAS_ZERO;
4247       Label DO1_SHORT, DO1_LOOP;
4248 
4249       BIND(DO1);
4250         ldrh(ch1, str1);
4251         cmp(cnt2, 4);
4252         br(LT, DO1_SHORT);
4253 
4254         orr(ch1, ch1, ch1, LSL, 16);
4255         orr(ch1, ch1, ch1, LSL, 32);
4256 
4257         sub(cnt2, cnt2, 4);
4258         mov(result_tmp, cnt2);
4259         lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4260         sub(cnt2_neg, zr, cnt2, LSL, 1);
4261 
4262         mov(tmp3, 0x0001000100010001);
4263       BIND(CH1_LOOP);
4264         ldr(ch2, Address(str2, cnt2_neg));
4265         eor(ch2, ch1, ch2);
4266         sub(tmp1, ch2, tmp3);
4267         orr(tmp2, ch2, 0x7fff7fff7fff7fff);
4268         bics(tmp1, tmp1, tmp2);
4269         br(NE, HAS_ZERO);
4270         adds(cnt2_neg, cnt2_neg, 8);
4271         br(LT, CH1_LOOP);
4272 
4273         cmp(cnt2_neg, 8);
4274         mov(cnt2_neg, 0);
4275         br(LT, CH1_LOOP);
4276         b(NOMATCH);
4277 
4278       BIND(HAS_ZERO);
4279         rev(tmp1, tmp1);
4280         clz(tmp1, tmp1);
4281         add(cnt2_neg, cnt2_neg, tmp1, LSR, 3);
4282         b(MATCH);
4283 
4284       BIND(DO1_SHORT);
4285         mov(result_tmp, cnt2);
4286         lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4287         sub(cnt2_neg, zr, cnt2, LSL, 1);
4288       BIND(DO1_LOOP);
4289         ldrh(ch2, Address(str2, cnt2_neg));
4290         cmpw(ch1, ch2);
4291         br(EQ, MATCH);
4292         adds(cnt2_neg, cnt2_neg, 2);
4293         br(LT, DO1_LOOP);
4294     }
4295   }
4296   BIND(NOMATCH);
4297     mov(result, -1);
4298     b(DONE);
4299   BIND(MATCH);
4300     add(result, result_tmp, cnt2_neg, ASR, 1);
4301   BIND(DONE);
4302 }
4303 
4304 // Compare strings.
4305 void MacroAssembler::string_compare(Register str1, Register str2,
4306                                     Register cnt1, Register cnt2, Register result,
4307                                     Register tmp1) {
4308   Label LENGTH_DIFF, DONE, SHORT_LOOP, SHORT_STRING,
4309     NEXT_WORD, DIFFERENCE;
4310 
4311   BLOCK_COMMENT("string_compare {");
4312 
4313   // Compute the minimum of the string lengths and save the difference.
4314   subsw(tmp1, cnt1, cnt2);
4315   cselw(cnt2, cnt1, cnt2, Assembler::LE); // min
4316 
4317   // A very short string
4318   cmpw(cnt2, 4);
4319   br(Assembler::LT, SHORT_STRING);
4320 
4321   // Check if the strings start at the same location.
4322   cmp(str1, str2);
4323   br(Assembler::EQ, LENGTH_DIFF);
4324 
4325   // Compare longwords
4326   {
4327     subw(cnt2, cnt2, 4); // The last longword is a special case
4328 
4329     // Move both string pointers to the last longword of their
4330     // strings, negate the remaining count, and convert it to bytes.
4331     lea(str1, Address(str1, cnt2, Address::uxtw(1)));
4332     lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4333     sub(cnt2, zr, cnt2, LSL, 1);
4334 
4335     // Loop, loading longwords and comparing them into rscratch2.
4336     bind(NEXT_WORD);
4337     ldr(result, Address(str1, cnt2));
4338     ldr(cnt1, Address(str2, cnt2));
4339     adds(cnt2, cnt2, wordSize);
4340     eor(rscratch2, result, cnt1);
4341     cbnz(rscratch2, DIFFERENCE);
4342     br(Assembler::LT, NEXT_WORD);
4343 
4344     // Last longword.  In the case where length == 4 we compare the
4345     // same longword twice, but that's still faster than another
4346     // conditional branch.
4347 
4348     ldr(result, Address(str1));
4349     ldr(cnt1, Address(str2));
4350     eor(rscratch2, result, cnt1);
4351     cbz(rscratch2, LENGTH_DIFF);
4352 
4353     // Find the first different characters in the longwords and
4354     // compute their difference.
4355     bind(DIFFERENCE);
4356     rev(rscratch2, rscratch2);
4357     clz(rscratch2, rscratch2);
4358     andr(rscratch2, rscratch2, -16);
4359     lsrv(result, result, rscratch2);
4360     uxthw(result, result);
4361     lsrv(cnt1, cnt1, rscratch2);
4362     uxthw(cnt1, cnt1);
4363     subw(result, result, cnt1);
4364     b(DONE);
4365   }
4366 
4367   bind(SHORT_STRING);
4368   // Is the minimum length zero?
4369   cbz(cnt2, LENGTH_DIFF);
4370 
4371   bind(SHORT_LOOP);
4372   load_unsigned_short(result, Address(post(str1, 2)));
4373   load_unsigned_short(cnt1, Address(post(str2, 2)));
4374   subw(result, result, cnt1);
4375   cbnz(result, DONE);
4376   sub(cnt2, cnt2, 1);
4377   cbnz(cnt2, SHORT_LOOP);
4378 
4379   // Strings are equal up to min length.  Return the length difference.
4380   bind(LENGTH_DIFF);
4381   mov(result, tmp1);
4382 
4383   // That's it
4384   bind(DONE);
4385 
4386   BLOCK_COMMENT("} string_compare");
4387 }
4388 
4389 
4390 void MacroAssembler::string_equals(Register str1, Register str2,
4391                                    Register cnt, Register result,
4392                                    Register tmp1) {
4393   Label SAME_CHARS, DONE, SHORT_LOOP, SHORT_STRING,
4394     NEXT_WORD;
4395 
4396   const Register tmp2 = rscratch1;
4397   assert_different_registers(str1, str2, cnt, result, tmp1, tmp2, rscratch2);
4398 
4399   BLOCK_COMMENT("string_equals {");
4400 
4401   // Start by assuming that the strings are not equal.
4402   mov(result, zr);
4403 
4404   // A very short string
4405   cmpw(cnt, 4);
4406   br(Assembler::LT, SHORT_STRING);
4407 
4408   // Check if the strings start at the same location.
4409   cmp(str1, str2);
4410   br(Assembler::EQ, SAME_CHARS);
4411 
4412   // Compare longwords
4413   {
4414     subw(cnt, cnt, 4); // The last longword is a special case
4415 
4416     // Move both string pointers to the last longword of their
4417     // strings, negate the remaining count, and convert it to bytes.
4418     lea(str1, Address(str1, cnt, Address::uxtw(1)));
4419     lea(str2, Address(str2, cnt, Address::uxtw(1)));
4420     sub(cnt, zr, cnt, LSL, 1);
4421 
4422     // Loop, loading longwords and comparing them into rscratch2.
4423     bind(NEXT_WORD);
4424     ldr(tmp1, Address(str1, cnt));
4425     ldr(tmp2, Address(str2, cnt));
4426     adds(cnt, cnt, wordSize);
4427     eor(rscratch2, tmp1, tmp2);
4428     cbnz(rscratch2, DONE);
4429     br(Assembler::LT, NEXT_WORD);
4430 
4431     // Last longword.  In the case where length == 4 we compare the
4432     // same longword twice, but that's still faster than another
4433     // conditional branch.
4434 
4435     ldr(tmp1, Address(str1));
4436     ldr(tmp2, Address(str2));
4437     eor(rscratch2, tmp1, tmp2);
4438     cbz(rscratch2, SAME_CHARS);
4439     b(DONE);
4440   }
4441 
4442   bind(SHORT_STRING);
4443   // Is the length zero?
4444   cbz(cnt, SAME_CHARS);
4445 
4446   bind(SHORT_LOOP);
4447   load_unsigned_short(tmp1, Address(post(str1, 2)));
4448   load_unsigned_short(tmp2, Address(post(str2, 2)));
4449   subw(tmp1, tmp1, tmp2);
4450   cbnz(tmp1, DONE);
4451   sub(cnt, cnt, 1);
4452   cbnz(cnt, SHORT_LOOP);
4453 
4454   // Strings are equal.
4455   bind(SAME_CHARS);
4456   mov(result, true);
4457 
4458   // That's it
4459   bind(DONE);
4460 
4461   BLOCK_COMMENT("} string_equals");
4462 }
4463 
4464 // Compare char[] arrays aligned to 4 bytes
4465 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2,
4466                                         Register result, Register tmp1)
4467 {
4468   Register cnt1 = rscratch1;
4469   Register cnt2 = rscratch2;
4470   Register tmp2 = rscratch2;
4471 
4472   Label SAME, DIFFER, NEXT, TAIL03, TAIL01;
4473 
4474   int length_offset  = arrayOopDesc::length_offset_in_bytes();
4475   int base_offset    = arrayOopDesc::base_offset_in_bytes(T_CHAR);
4476 
4477   BLOCK_COMMENT("char_arrays_equals  {");
4478 
4479     // different until proven equal
4480     mov(result, false);
4481 
4482     // same array?
4483     cmp(ary1, ary2);
4484     br(Assembler::EQ, SAME);
4485 
4486     // ne if either null
4487     cbz(ary1, DIFFER);
4488     cbz(ary2, DIFFER);
4489 
4490     // lengths ne?
4491     ldrw(cnt1, Address(ary1, length_offset));
4492     ldrw(cnt2, Address(ary2, length_offset));
4493     cmp(cnt1, cnt2);
4494     br(Assembler::NE, DIFFER);
4495 
4496     lea(ary1, Address(ary1, base_offset));
4497     lea(ary2, Address(ary2, base_offset));
4498 
4499     subs(cnt1, cnt1, 4);
4500     br(LT, TAIL03);
4501 
4502   BIND(NEXT);
4503     ldr(tmp1, Address(post(ary1, 8)));
4504     ldr(tmp2, Address(post(ary2, 8)));
4505     subs(cnt1, cnt1, 4);
4506     eor(tmp1, tmp1, tmp2);
4507     cbnz(tmp1, DIFFER);
4508     br(GE, NEXT);
4509 
4510   BIND(TAIL03);  // 0-3 chars left, cnt1 = #chars left - 4
4511     tst(cnt1, 0b10);
4512     br(EQ, TAIL01);
4513     ldrw(tmp1, Address(post(ary1, 4)));
4514     ldrw(tmp2, Address(post(ary2, 4)));
4515     cmp(tmp1, tmp2);
4516     br(NE, DIFFER);
4517   BIND(TAIL01);  // 0-1 chars left
4518     tst(cnt1, 0b01);
4519     br(EQ, SAME);
4520     ldrh(tmp1, ary1);
4521     ldrh(tmp2, ary2);
4522     cmp(tmp1, tmp2);
4523     br(NE, DIFFER);
4524 
4525   BIND(SAME);
4526     mov(result, true);
4527   BIND(DIFFER); // result already set
4528 
4529   BLOCK_COMMENT("} char_arrays_equals");
4530 }
4531 
4532 // encode char[] to byte[] in ISO_8859_1
4533 void MacroAssembler::encode_iso_array(Register src, Register dst,
4534                       Register len, Register result,
4535                       FloatRegister Vtmp1, FloatRegister Vtmp2,
4536                       FloatRegister Vtmp3, FloatRegister Vtmp4)
4537 {
4538     Label DONE, NEXT_32, LOOP_8, NEXT_8, LOOP_1, NEXT_1;
4539     Register tmp1 = rscratch1;
4540 
4541       mov(result, len); // Save initial len
4542 
4543 #ifndef BUILTIN_SIM
4544       subs(len, len, 32);
4545       br(LT, LOOP_8);
4546 
4547 // The following code uses the SIMD 'uqxtn' and 'uqxtn2' instructions
4548 // to convert chars to bytes. These set the 'QC' bit in the FPSR if
4549 // any char could not fit in a byte, so clear the FPSR so we can test it.
4550       clear_fpsr();
4551 
4552     BIND(NEXT_32);
4553       ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src);
4554       uqxtn(Vtmp1, T8B, Vtmp1, T8H);  // uqxtn  - write bottom half
4555       uqxtn(Vtmp1, T16B, Vtmp2, T8H); // uqxtn2 - write top half
4556       uqxtn(Vtmp2, T8B, Vtmp3, T8H);
4557       uqxtn(Vtmp2, T16B, Vtmp4, T8H); // uqxtn2
4558       get_fpsr(tmp1);
4559       cbnzw(tmp1, LOOP_8);
4560       st1(Vtmp1, Vtmp2, T16B, post(dst, 32));
4561       subs(len, len, 32);
4562       add(src, src, 64);
4563       br(GE, NEXT_32);
4564 
4565     BIND(LOOP_8);
4566       adds(len, len, 32-8);
4567       br(LT, LOOP_1);
4568       clear_fpsr(); // QC may be set from loop above, clear again
4569     BIND(NEXT_8);
4570       ld1(Vtmp1, T8H, src);
4571       uqxtn(Vtmp1, T8B, Vtmp1, T8H);
4572       get_fpsr(tmp1);
4573       cbnzw(tmp1, LOOP_1);
4574       st1(Vtmp1, T8B, post(dst, 8));
4575       subs(len, len, 8);
4576       add(src, src, 16);
4577       br(GE, NEXT_8);
4578 
4579     BIND(LOOP_1);
4580       adds(len, len, 8);
4581       br(LE, DONE);
4582 #else
4583       cbz(len, DONE);
4584 #endif
4585     BIND(NEXT_1);
4586       ldrh(tmp1, Address(post(src, 2)));
4587       tst(tmp1, 0xff00);
4588       br(NE, DONE);
4589       strb(tmp1, Address(post(dst, 1)));
4590       subs(len, len, 1);
4591       br(GT, NEXT_1);
4592 
4593     BIND(DONE);
4594       sub(result, result, len); // Return index where we stopped
4595 }
--- EOF ---