1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30
31 // MacroAssembler extends Assembler by frequently used macros.
32 //
33 // Instructions for which a 'better' code sequence exists depending
34 // on arguments should also go in here.
35
36 class MacroAssembler: public Assembler {
37 friend class LIR_Assembler;
38
39 public:
40 using Assembler::mov;
41 using Assembler::movi;
42
43 protected:
44
45 // Support for VM calls
46 //
47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
48 // may customize this version by overriding it for its purposes (e.g., to save/restore
49 // additional registers when doing a VM call).
50 #ifdef CC_INTERP
51 // c++ interpreter never wants to use interp_masm version of call_VM
52 #define VIRTUAL
53 #else
54 #define VIRTUAL virtual
55 #endif
56
57 VIRTUAL void call_VM_leaf_base(
58 address entry_point, // the entry point
59 int number_of_arguments, // the number of arguments to pop after the call
60 Label *retaddr = NULL
61 );
62
63 VIRTUAL void call_VM_leaf_base(
64 address entry_point, // the entry point
65 int number_of_arguments, // the number of arguments to pop after the call
66 Label &retaddr) {
67 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
68 }
69
70 // This is the base routine called by the different versions of call_VM. The interpreter
71 // may customize this version by overriding it for its purposes (e.g., to save/restore
72 // additional registers when doing a VM call).
73 //
74 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
75 // returns the register which contains the thread upon return. If a thread register has been
76 // specified, the return value will correspond to that register. If no last_java_sp is specified
77 // (noreg) than rsp will be used instead.
78 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
79 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
80 Register java_thread, // the thread if computed before ; use noreg otherwise
81 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
82 address entry_point, // the entry point
83 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
84 bool check_exceptions // whether to check for pending exceptions after return
85 );
86
87 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
88 // The implementation is only non-empty for the InterpreterMacroAssembler,
89 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
90 virtual void check_and_handle_popframe(Register java_thread);
91 virtual void check_and_handle_earlyret(Register java_thread);
92
93 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
94
95 // Maximum size of class area in Metaspace when compressed
96 uint64_t use_XOR_for_compressed_class_base;
97
98 public:
99 MacroAssembler(CodeBuffer* code) : Assembler(code) {
100 use_XOR_for_compressed_class_base
101 = (operand_valid_for_logical_immediate(false /*is32*/,
102 (uint64_t)Universe::narrow_klass_base())
103 && ((uint64_t)Universe::narrow_klass_base()
104 > (1u << log2_intptr(CompressedClassSpaceSize))));
105 }
106
107 // Biased locking support
108 // lock_reg and obj_reg must be loaded up with the appropriate values.
109 // swap_reg is killed.
110 // tmp_reg must be supplied and must not be rscratch1 or rscratch2
111 // Optional slow case is for implementations (interpreter and C1) which branch to
112 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
113 // Returns offset of first potentially-faulting instruction for null
114 // check info (currently consumed only by C1). If
115 // swap_reg_contains_mark is true then returns -1 as it is assumed
116 // the calling code has already passed any potential faults.
117 int biased_locking_enter(Register lock_reg, Register obj_reg,
118 Register swap_reg, Register tmp_reg,
119 bool swap_reg_contains_mark,
120 Label& done, Label* slow_case = NULL,
121 BiasedLockingCounters* counters = NULL);
122 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
123
124
125 // Helper functions for statistics gathering.
126 // Unconditional atomic increment.
127 void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
128 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
129 lea(tmp1, counter_addr);
130 atomic_incw(tmp1, tmp2, tmp3);
131 }
132 // Load Effective Address
133 void lea(Register r, const Address &a) {
134 InstructionMark im(this);
135 code_section()->relocate(inst_mark(), a.rspec());
136 a.lea(this, r);
137 }
138
139 void addmw(Address a, Register incr, Register scratch) {
140 ldrw(scratch, a);
141 addw(scratch, scratch, incr);
142 strw(scratch, a);
143 }
144
145 // Add constant to memory word
146 void addmw(Address a, int imm, Register scratch) {
147 ldrw(scratch, a);
148 if (imm > 0)
149 addw(scratch, scratch, (unsigned)imm);
150 else
151 subw(scratch, scratch, (unsigned)-imm);
152 strw(scratch, a);
153 }
154
155 // Frame creation and destruction shared between JITs.
156 void build_frame(int framesize);
157 void remove_frame(int framesize);
158
159 virtual void _call_Unimplemented(address call_site) {
160 mov(rscratch2, call_site);
161 haltsim();
162 }
163
164 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
165
166 virtual void notify(int type);
167
168 // aliases defined in AARCH64 spec
169
170 template<class T>
171 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
172 inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); }
173
174 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
175 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
176
177 void cset(Register Rd, Assembler::Condition cond) {
178 csinc(Rd, zr, zr, ~cond);
179 }
180 void csetw(Register Rd, Assembler::Condition cond) {
181 csincw(Rd, zr, zr, ~cond);
182 }
183
184 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
185 csneg(Rd, Rn, Rn, ~cond);
186 }
187 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
188 csnegw(Rd, Rn, Rn, ~cond);
189 }
190
191 inline void movw(Register Rd, Register Rn) {
192 if (Rd == sp || Rn == sp) {
193 addw(Rd, Rn, 0U);
194 } else {
195 orrw(Rd, zr, Rn);
196 }
197 }
198 inline void mov(Register Rd, Register Rn) {
199 assert(Rd != r31_sp && Rn != r31_sp, "should be");
200 if (Rd == Rn) {
201 } else if (Rd == sp || Rn == sp) {
202 add(Rd, Rn, 0U);
203 } else {
204 orr(Rd, zr, Rn);
205 }
206 }
207
208 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
209 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
210
211 inline void tstw(Register Rd, unsigned imm) { andsw(zr, Rd, imm); }
212 inline void tst(Register Rd, unsigned imm) { ands(zr, Rd, imm); }
213
214 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
215 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
216 }
217 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
218 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
219 }
220
221 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
222 bfmw(Rd, Rn, lsb, (lsb + width - 1));
223 }
224 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
225 bfm(Rd, Rn, lsb , (lsb + width - 1));
226 }
227
228 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
229 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
230 }
231 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
232 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
233 }
234
235 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
236 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
237 }
238 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
239 sbfm(Rd, Rn, lsb , (lsb + width - 1));
240 }
241
242 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
243 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
244 }
245 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
246 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
247 }
248
249 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
250 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
251 }
252 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
253 ubfm(Rd, Rn, lsb , (lsb + width - 1));
254 }
255
256 inline void asrw(Register Rd, Register Rn, unsigned imm) {
257 sbfmw(Rd, Rn, imm, 31);
258 }
259
260 inline void asr(Register Rd, Register Rn, unsigned imm) {
261 sbfm(Rd, Rn, imm, 63);
262 }
263
264 inline void lslw(Register Rd, Register Rn, unsigned imm) {
265 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
266 }
267
268 inline void lsl(Register Rd, Register Rn, unsigned imm) {
269 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
270 }
271
272 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
273 ubfmw(Rd, Rn, imm, 31);
274 }
275
276 inline void lsr(Register Rd, Register Rn, unsigned imm) {
277 ubfm(Rd, Rn, imm, 63);
278 }
279
280 inline void rorw(Register Rd, Register Rn, unsigned imm) {
281 extrw(Rd, Rn, Rn, imm);
282 }
283
284 inline void ror(Register Rd, Register Rn, unsigned imm) {
285 extr(Rd, Rn, Rn, imm);
286 }
287
288 inline void sxtbw(Register Rd, Register Rn) {
289 sbfmw(Rd, Rn, 0, 7);
290 }
291 inline void sxthw(Register Rd, Register Rn) {
292 sbfmw(Rd, Rn, 0, 15);
293 }
294 inline void sxtb(Register Rd, Register Rn) {
295 sbfm(Rd, Rn, 0, 7);
296 }
297 inline void sxth(Register Rd, Register Rn) {
298 sbfm(Rd, Rn, 0, 15);
299 }
300 inline void sxtw(Register Rd, Register Rn) {
301 sbfm(Rd, Rn, 0, 31);
302 }
303
304 inline void uxtbw(Register Rd, Register Rn) {
305 ubfmw(Rd, Rn, 0, 7);
306 }
307 inline void uxthw(Register Rd, Register Rn) {
308 ubfmw(Rd, Rn, 0, 15);
309 }
310 inline void uxtb(Register Rd, Register Rn) {
311 ubfm(Rd, Rn, 0, 7);
312 }
313 inline void uxth(Register Rd, Register Rn) {
314 ubfm(Rd, Rn, 0, 15);
315 }
316 inline void uxtw(Register Rd, Register Rn) {
317 ubfm(Rd, Rn, 0, 31);
318 }
319
320 inline void cmnw(Register Rn, Register Rm) {
321 addsw(zr, Rn, Rm);
322 }
323 inline void cmn(Register Rn, Register Rm) {
324 adds(zr, Rn, Rm);
325 }
326
327 inline void cmpw(Register Rn, Register Rm) {
328 subsw(zr, Rn, Rm);
329 }
330 inline void cmp(Register Rn, Register Rm) {
331 subs(zr, Rn, Rm);
332 }
333
334 inline void negw(Register Rd, Register Rn) {
335 subw(Rd, zr, Rn);
336 }
337
338 inline void neg(Register Rd, Register Rn) {
339 sub(Rd, zr, Rn);
340 }
341
342 inline void negsw(Register Rd, Register Rn) {
343 subsw(Rd, zr, Rn);
344 }
345
346 inline void negs(Register Rd, Register Rn) {
347 subs(Rd, zr, Rn);
348 }
349
350 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
351 addsw(zr, Rn, Rm, kind, shift);
352 }
353 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
354 adds(zr, Rn, Rm, kind, shift);
355 }
356
357 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
358 subsw(zr, Rn, Rm, kind, shift);
359 }
360 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
361 subs(zr, Rn, Rm, kind, shift);
362 }
363
364 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
365 subw(Rd, zr, Rn, kind, shift);
366 }
367
368 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
369 sub(Rd, zr, Rn, kind, shift);
370 }
371
372 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
373 subsw(Rd, zr, Rn, kind, shift);
374 }
375
376 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
377 subs(Rd, zr, Rn, kind, shift);
378 }
379
380 inline void mnegw(Register Rd, Register Rn, Register Rm) {
381 msubw(Rd, Rn, Rm, zr);
382 }
383 inline void mneg(Register Rd, Register Rn, Register Rm) {
384 msub(Rd, Rn, Rm, zr);
385 }
386
387 inline void mulw(Register Rd, Register Rn, Register Rm) {
388 maddw(Rd, Rn, Rm, zr);
389 }
390 inline void mul(Register Rd, Register Rn, Register Rm) {
391 madd(Rd, Rn, Rm, zr);
392 }
393
394 inline void smnegl(Register Rd, Register Rn, Register Rm) {
395 smsubl(Rd, Rn, Rm, zr);
396 }
397 inline void smull(Register Rd, Register Rn, Register Rm) {
398 smaddl(Rd, Rn, Rm, zr);
399 }
400
401 inline void umnegl(Register Rd, Register Rn, Register Rm) {
402 umsubl(Rd, Rn, Rm, zr);
403 }
404 inline void umull(Register Rd, Register Rn, Register Rm) {
405 umaddl(Rd, Rn, Rm, zr);
406 }
407
408 #define WRAP(INSN) \
409 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
410 if ((VM_Version::cpu_cpuFeatures() & VM_Version::CPU_A53MAC) && Ra != zr) \
411 nop(); \
412 Assembler::INSN(Rd, Rn, Rm, Ra); \
413 }
414
415 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
416 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
417 #undef WRAP
418
419
420 // macro assembly operations needed for aarch64
421
422 // first two private routines for loading 32 bit or 64 bit constants
423 private:
424
425 void mov_immediate64(Register dst, u_int64_t imm64);
426 void mov_immediate32(Register dst, u_int32_t imm32);
427
428 int push(unsigned int bitset, Register stack);
429 int pop(unsigned int bitset, Register stack);
430
431 void mov(Register dst, Address a);
432
433 public:
434 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
435 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
436
437 // now mov instructions for loading absolute addresses and 32 or
438 // 64 bit integers
439
440 inline void mov(Register dst, address addr)
441 {
442 mov_immediate64(dst, (u_int64_t)addr);
443 }
444
445 inline void mov(Register dst, u_int64_t imm64)
446 {
447 mov_immediate64(dst, imm64);
448 }
449
450 inline void movw(Register dst, u_int32_t imm32)
451 {
452 mov_immediate32(dst, imm32);
453 }
454
455 inline void mov(Register dst, long l)
456 {
457 mov(dst, (u_int64_t)l);
458 }
459
460 inline void mov(Register dst, int i)
461 {
462 mov(dst, (long)i);
463 }
464
465 void mov(Register dst, RegisterOrConstant src) {
466 if (src.is_register())
467 mov(dst, src.as_register());
468 else
469 mov(dst, src.as_constant());
470 }
471
472 void movptr(Register r, uintptr_t imm64);
473
474 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
475
476 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
477 orr(Vd, T, Vn, Vn);
478 }
479
480 // macro instructions for accessing and updating floating point
481 // status register
482 //
483 // FPSR : op1 == 011
484 // CRn == 0100
485 // CRm == 0100
486 // op2 == 001
487
488 inline void get_fpsr(Register reg)
489 {
490 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
491 }
492
493 inline void set_fpsr(Register reg)
494 {
495 msr(0b011, 0b0100, 0b0100, 0b001, reg);
496 }
497
498 inline void clear_fpsr()
499 {
500 msr(0b011, 0b0100, 0b0100, 0b001, zr);
501 }
502
503 // idiv variant which deals with MINLONG as dividend and -1 as divisor
504 int corrected_idivl(Register result, Register ra, Register rb,
505 bool want_remainder, Register tmp = rscratch1);
506 int corrected_idivq(Register result, Register ra, Register rb,
507 bool want_remainder, Register tmp = rscratch1);
508
509 // Support for NULL-checks
510 //
511 // Generates code that causes a NULL OS exception if the content of reg is NULL.
512 // If the accessed location is M[reg + offset] and the offset is known, provide the
513 // offset. No explicit code generation is needed if the offset is within a certain
514 // range (0 <= offset <= page_size).
515
516 virtual void null_check(Register reg, int offset = -1);
517 static bool needs_explicit_null_check(intptr_t offset);
518
519 static address target_addr_for_insn(address insn_addr, unsigned insn);
520 static address target_addr_for_insn(address insn_addr) {
521 unsigned insn = *(unsigned*)insn_addr;
522 return target_addr_for_insn(insn_addr, insn);
523 }
524
525 // Required platform-specific helpers for Label::patch_instructions.
526 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
527 static int pd_patch_instruction_size(address branch, address target);
528 static void pd_patch_instruction(address branch, address target) {
529 pd_patch_instruction_size(branch, target);
530 }
531 static address pd_call_destination(address branch) {
532 return target_addr_for_insn(branch);
533 }
534 #ifndef PRODUCT
535 static void pd_print_patched_instruction(address branch);
536 #endif
537
538 static int patch_oop(address insn_addr, address o);
539
540 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
541
542 // The following 4 methods return the offset of the appropriate move instruction
543
544 // Support for fast byte/short loading with zero extension (depending on particular CPU)
545 int load_unsigned_byte(Register dst, Address src);
546 int load_unsigned_short(Register dst, Address src);
547
548 // Support for fast byte/short loading with sign extension (depending on particular CPU)
549 int load_signed_byte(Register dst, Address src);
550 int load_signed_short(Register dst, Address src);
551
552 int load_signed_byte32(Register dst, Address src);
553 int load_signed_short32(Register dst, Address src);
554
555 // Support for sign-extension (hi:lo = extend_sign(lo))
556 void extend_sign(Register hi, Register lo);
557
558 // Load and store values by size and signed-ness
559 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
560 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
561
562 // Support for inc/dec with optimal instruction selection depending on value
563
564 // x86_64 aliases an unqualified register/address increment and
565 // decrement to call incrementq and decrementq but also supports
566 // explicitly sized calls to incrementq/decrementq or
567 // incrementl/decrementl
568
569 // for aarch64 the proper convention would be to use
570 // increment/decrement for 64 bit operatons and
571 // incrementw/decrementw for 32 bit operations. so when porting
572 // x86_64 code we can leave calls to increment/decrement as is,
573 // replace incrementq/decrementq with increment/decrement and
574 // replace incrementl/decrementl with incrementw/decrementw.
575
576 // n.b. increment/decrement calls with an Address destination will
577 // need to use a scratch register to load the value to be
578 // incremented. increment/decrement calls which add or subtract a
579 // constant value greater than 2^12 will need to use a 2nd scratch
580 // register to hold the constant. so, a register increment/decrement
581 // may trash rscratch2 and an address increment/decrement trash
582 // rscratch and rscratch2
583
584 void decrementw(Address dst, int value = 1);
585 void decrementw(Register reg, int value = 1);
586
587 void decrement(Register reg, int value = 1);
588 void decrement(Address dst, int value = 1);
589
590 void incrementw(Address dst, int value = 1);
591 void incrementw(Register reg, int value = 1);
592
593 void increment(Register reg, int value = 1);
594 void increment(Address dst, int value = 1);
595
596
597 // Alignment
598 void align(int modulus);
599
600 // Stack frame creation/removal
601 void enter()
602 {
603 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
604 mov(rfp, sp);
605 }
606 void leave()
607 {
608 mov(sp, rfp);
609 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
610 }
611
612 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
613 // The pointer will be loaded into the thread register.
614 void get_thread(Register thread);
615
616
617 // Support for VM calls
618 //
619 // It is imperative that all calls into the VM are handled via the call_VM macros.
620 // They make sure that the stack linkage is setup correctly. call_VM's correspond
621 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
622
623
624 void call_VM(Register oop_result,
625 address entry_point,
626 bool check_exceptions = true);
627 void call_VM(Register oop_result,
628 address entry_point,
629 Register arg_1,
630 bool check_exceptions = true);
631 void call_VM(Register oop_result,
632 address entry_point,
633 Register arg_1, Register arg_2,
634 bool check_exceptions = true);
635 void call_VM(Register oop_result,
636 address entry_point,
637 Register arg_1, Register arg_2, Register arg_3,
638 bool check_exceptions = true);
639
640 // Overloadings with last_Java_sp
641 void call_VM(Register oop_result,
642 Register last_java_sp,
643 address entry_point,
644 int number_of_arguments = 0,
645 bool check_exceptions = true);
646 void call_VM(Register oop_result,
647 Register last_java_sp,
648 address entry_point,
649 Register arg_1, bool
650 check_exceptions = true);
651 void call_VM(Register oop_result,
652 Register last_java_sp,
653 address entry_point,
654 Register arg_1, Register arg_2,
655 bool check_exceptions = true);
656 void call_VM(Register oop_result,
657 Register last_java_sp,
658 address entry_point,
659 Register arg_1, Register arg_2, Register arg_3,
660 bool check_exceptions = true);
661
662 void get_vm_result (Register oop_result, Register thread);
663 void get_vm_result_2(Register metadata_result, Register thread);
664
665 // These always tightly bind to MacroAssembler::call_VM_base
666 // bypassing the virtual implementation
667 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
668 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
669 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
670 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
671 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
672
673 void call_VM_leaf(address entry_point,
674 int number_of_arguments = 0);
675 void call_VM_leaf(address entry_point,
676 Register arg_1);
677 void call_VM_leaf(address entry_point,
678 Register arg_1, Register arg_2);
679 void call_VM_leaf(address entry_point,
680 Register arg_1, Register arg_2, Register arg_3);
681
682 // These always tightly bind to MacroAssembler::call_VM_leaf_base
683 // bypassing the virtual implementation
684 void super_call_VM_leaf(address entry_point);
685 void super_call_VM_leaf(address entry_point, Register arg_1);
686 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
687 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
688 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
689
690 // last Java Frame (fills frame anchor)
691 void set_last_Java_frame(Register last_java_sp,
692 Register last_java_fp,
693 address last_java_pc,
694 Register scratch);
695
696 void set_last_Java_frame(Register last_java_sp,
697 Register last_java_fp,
698 Label &last_java_pc,
699 Register scratch);
700
701 void set_last_Java_frame(Register last_java_sp,
702 Register last_java_fp,
703 Register last_java_pc,
704 Register scratch);
705
706 void reset_last_Java_frame(Register thread, bool clearfp, bool clear_pc);
707
708 // thread in the default location (r15_thread on 64bit)
709 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
710
711 // Stores
712 void store_check(Register obj); // store check for obj - register is destroyed afterwards
713 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
714
715 #if INCLUDE_ALL_GCS
716
717 void g1_write_barrier_pre(Register obj,
718 Register pre_val,
719 Register thread,
720 Register tmp,
721 bool tosca_live,
722 bool expand_call);
723
724 void g1_write_barrier_post(Register store_addr,
725 Register new_val,
726 Register thread,
727 Register tmp,
728 Register tmp2);
729
730 #endif // INCLUDE_ALL_GCS
731
732 // oop manipulations
733 void load_klass(Register dst, Register src);
734 void store_klass(Register dst, Register src);
735 void cmp_klass(Register oop, Register trial_klass, Register tmp);
736
737 void load_heap_oop(Register dst, Address src);
738
739 void load_heap_oop_not_null(Register dst, Address src);
740 void store_heap_oop(Address dst, Register src);
741
742 // currently unimplemented
743 // Used for storing NULL. All other oop constants should be
744 // stored using routines that take a jobject.
745 void store_heap_oop_null(Address dst);
746
747 void load_prototype_header(Register dst, Register src);
748
749 void store_klass_gap(Register dst, Register src);
750
751 // This dummy is to prevent a call to store_heap_oop from
752 // converting a zero (like NULL) into a Register by giving
753 // the compiler two choices it can't resolve
754
755 void store_heap_oop(Address dst, void* dummy);
756
757 void encode_heap_oop(Register d, Register s);
758 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
759 void decode_heap_oop(Register d, Register s);
760 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
761 void encode_heap_oop_not_null(Register r);
762 void decode_heap_oop_not_null(Register r);
763 void encode_heap_oop_not_null(Register dst, Register src);
764 void decode_heap_oop_not_null(Register dst, Register src);
765
766 void set_narrow_oop(Register dst, jobject obj);
767
768 void encode_klass_not_null(Register r);
769 void decode_klass_not_null(Register r);
770 void encode_klass_not_null(Register dst, Register src);
771 void decode_klass_not_null(Register dst, Register src);
772
773 void set_narrow_klass(Register dst, Klass* k);
774
775 // if heap base register is used - reinit it with the correct value
776 void reinit_heapbase();
777
778 DEBUG_ONLY(void verify_heapbase(const char* msg);)
779
780 void push_CPU_state();
781 void pop_CPU_state() ;
782
783 // Round up to a power of two
784 void round_to(Register reg, int modulus);
785
786 // allocation
787 void eden_allocate(
788 Register obj, // result: pointer to object after successful allocation
789 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
790 int con_size_in_bytes, // object size in bytes if known at compile time
791 Register t1, // temp register
792 Label& slow_case // continuation point if fast allocation fails
793 );
794 void tlab_allocate(
795 Register obj, // result: pointer to object after successful allocation
796 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
797 int con_size_in_bytes, // object size in bytes if known at compile time
798 Register t1, // temp register
799 Register t2, // temp register
800 Label& slow_case // continuation point if fast allocation fails
801 );
802 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
803 void verify_tlab();
804
805 void incr_allocated_bytes(Register thread,
806 Register var_size_in_bytes, int con_size_in_bytes,
807 Register t1 = noreg);
808
809 // interface method calling
810 void lookup_interface_method(Register recv_klass,
811 Register intf_klass,
812 RegisterOrConstant itable_index,
813 Register method_result,
814 Register scan_temp,
815 Label& no_such_interface);
816
817 // virtual method calling
818 // n.b. x86 allows RegisterOrConstant for vtable_index
819 void lookup_virtual_method(Register recv_klass,
820 RegisterOrConstant vtable_index,
821 Register method_result);
822
823 // Test sub_klass against super_klass, with fast and slow paths.
824
825 // The fast path produces a tri-state answer: yes / no / maybe-slow.
826 // One of the three labels can be NULL, meaning take the fall-through.
827 // If super_check_offset is -1, the value is loaded up from super_klass.
828 // No registers are killed, except temp_reg.
829 void check_klass_subtype_fast_path(Register sub_klass,
830 Register super_klass,
831 Register temp_reg,
832 Label* L_success,
833 Label* L_failure,
834 Label* L_slow_path,
835 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
836
837 // The rest of the type check; must be wired to a corresponding fast path.
838 // It does not repeat the fast path logic, so don't use it standalone.
839 // The temp_reg and temp2_reg can be noreg, if no temps are available.
840 // Updates the sub's secondary super cache as necessary.
841 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
842 void check_klass_subtype_slow_path(Register sub_klass,
843 Register super_klass,
844 Register temp_reg,
845 Register temp2_reg,
846 Label* L_success,
847 Label* L_failure,
848 bool set_cond_codes = false);
849
850 // Simplified, combined version, good for typical uses.
851 // Falls through on failure.
852 void check_klass_subtype(Register sub_klass,
853 Register super_klass,
854 Register temp_reg,
855 Label& L_success);
856
857 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
858
859
860 // Debugging
861
862 // only if +VerifyOops
863 void verify_oop(Register reg, const char* s = "broken oop");
864 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
865
866 // TODO: verify method and klass metadata (compare against vptr?)
867 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
868 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
869
870 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
871 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
872
873 // only if +VerifyFPU
874 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
875
876 // prints msg, dumps registers and stops execution
877 void stop(const char* msg);
878
879 // prints msg and continues
880 void warn(const char* msg);
881
882 static void debug64(char* msg, int64_t pc, int64_t regs[]);
883
884 void untested() { stop("untested"); }
885
886 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
887
888 void should_not_reach_here() { stop("should not reach here"); }
889
890 // Stack overflow checking
891 void bang_stack_with_offset(int offset) {
892 // stack grows down, caller passes positive offset
893 assert(offset > 0, "must bang with negative offset");
894 mov(rscratch2, -offset);
895 str(zr, Address(sp, rscratch2));
896 }
897
898 // Writes to stack successive pages until offset reached to check for
899 // stack overflow + shadow pages. Also, clobbers tmp
900 void bang_stack_size(Register size, Register tmp);
901
902 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
903 Register tmp,
904 int offset);
905
906 // Support for serializing memory accesses between threads
907 void serialize_memory(Register thread, Register tmp);
908
909 // Arithmetics
910
911 void addptr(Address dst, int32_t src) {
912 lea(rscratch2, dst);
913 ldr(rscratch1, Address(rscratch2));
914 add(rscratch1, rscratch1, src);
915 str(rscratch1, Address(rscratch2));
916 }
917
918 void cmpptr(Register src1, Address src2);
919
920 // Various forms of CAS
921
922 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
923 Label &suceed, Label *fail);
924
925 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
926 Label &suceed, Label *fail);
927
928 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
929 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
930
931 void atomic_xchg(Register prev, Register newv, Register addr);
932 void atomic_xchgw(Register prev, Register newv, Register addr);
933
934 void orptr(Address adr, RegisterOrConstant src) {
935 ldr(rscratch2, adr);
936 if (src.is_register())
937 orr(rscratch2, rscratch2, src.as_register());
938 else
939 orr(rscratch2, rscratch2, src.as_constant());
940 str(rscratch2, adr);
941 }
942
943 // A generic CAS; success or failure is in the EQ flag.
944 template <typename T1, typename T2>
945 void cmpxchg(Register addr, Register expected, Register new_val,
946 T1 load_insn,
947 void (MacroAssembler::*cmp_insn)(Register, Register),
948 T2 store_insn,
949 Register tmp = rscratch1) {
950 Label retry_load, done;
951 bind(retry_load);
952 (this->*load_insn)(tmp, addr);
953 (this->*cmp_insn)(tmp, expected);
954 br(Assembler::NE, done);
955 (this->*store_insn)(tmp, new_val, addr);
956 cbnzw(tmp, retry_load);
957 bind(done);
958 }
959
960 // Calls
961
962 address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
963
964 static bool far_branches() {
965 return ReservedCodeCacheSize > branch_range;
966 }
967
968 // Jumps that can reach anywhere in the code cache.
969 // Trashes tmp.
970 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
971 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
972
973 static int far_branch_size() {
974 if (far_branches()) {
975 return 3 * 4; // adrp, add, br
976 } else {
977 return 4;
978 }
979 }
980
981 // Emit the CompiledIC call idiom
982 address ic_call(address entry);
983
984 public:
985
986 // Data
987
988 void mov_metadata(Register dst, Metadata* obj);
989 Address allocate_metadata_address(Metadata* obj);
990 Address constant_oop_address(jobject obj);
991
992 void movoop(Register dst, jobject obj, bool immediate = false);
993
994 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
995 void kernel_crc32(Register crc, Register buf, Register len,
996 Register table0, Register table1, Register table2, Register table3,
997 Register tmp, Register tmp2, Register tmp3);
998 // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
999 void kernel_crc32c(Register crc, Register buf, Register len,
1000 Register table0, Register table1, Register table2, Register table3,
1001 Register tmp, Register tmp2, Register tmp3);
1002
1003 #undef VIRTUAL
1004
1005 // Stack push and pop individual 64 bit registers
1006 void push(Register src);
1007 void pop(Register dst);
1008
1009 // push all registers onto the stack
1010 void pusha();
1011 void popa();
1012
1013 void repne_scan(Register addr, Register value, Register count,
1014 Register scratch);
1015 void repne_scanw(Register addr, Register value, Register count,
1016 Register scratch);
1017
1018 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1019 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1020
1021 // If a constant does not fit in an immediate field, generate some
1022 // number of MOV instructions and then perform the operation
1023 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1024 add_sub_imm_insn insn1,
1025 add_sub_reg_insn insn2);
1026 // Seperate vsn which sets the flags
1027 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1028 add_sub_imm_insn insn1,
1029 add_sub_reg_insn insn2);
1030
1031 #define WRAP(INSN) \
1032 void INSN(Register Rd, Register Rn, unsigned imm) { \
1033 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1034 } \
1035 \
1036 void INSN(Register Rd, Register Rn, Register Rm, \
1037 enum shift_kind kind, unsigned shift = 0) { \
1038 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1039 } \
1040 \
1041 void INSN(Register Rd, Register Rn, Register Rm) { \
1042 Assembler::INSN(Rd, Rn, Rm); \
1043 } \
1044 \
1045 void INSN(Register Rd, Register Rn, Register Rm, \
1046 ext::operation option, int amount = 0) { \
1047 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1048 }
1049
1050 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1051
1052 #undef WRAP
1053 #define WRAP(INSN) \
1054 void INSN(Register Rd, Register Rn, unsigned imm) { \
1055 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1056 } \
1057 \
1058 void INSN(Register Rd, Register Rn, Register Rm, \
1059 enum shift_kind kind, unsigned shift = 0) { \
1060 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1061 } \
1062 \
1063 void INSN(Register Rd, Register Rn, Register Rm) { \
1064 Assembler::INSN(Rd, Rn, Rm); \
1065 } \
1066 \
1067 void INSN(Register Rd, Register Rn, Register Rm, \
1068 ext::operation option, int amount = 0) { \
1069 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1070 }
1071
1072 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1073
1074 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1075 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1076 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1077 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1078
1079 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1080
1081 void tableswitch(Register index, jint lowbound, jint highbound,
1082 Label &jumptable, Label &jumptable_end, int stride = 1) {
1083 adr(rscratch1, jumptable);
1084 subsw(rscratch2, index, lowbound);
1085 subsw(zr, rscratch2, highbound - lowbound);
1086 br(Assembler::HS, jumptable_end);
1087 add(rscratch1, rscratch1, rscratch2,
1088 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1089 br(rscratch1);
1090 }
1091
1092 // Form an address from base + offset in Rd. Rd may or may not
1093 // actually be used: you must use the Address that is returned. It
1094 // is up to you to ensure that the shift provided matches the size
1095 // of your data.
1096 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1097
1098 // Prolog generator routines to support switch between x86 code and
1099 // generated ARM code
1100
1101 // routine to generate an x86 prolog for a stub function which
1102 // bootstraps into the generated ARM code which directly follows the
1103 // stub
1104 //
1105
1106 public:
1107 // enum used for aarch64--x86 linkage to define return type of x86 function
1108 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1109
1110 #ifdef BUILTIN_SIM
1111 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1112 #else
1113 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1114 #endif
1115
1116 // special version of call_VM_leaf_base needed for aarch64 simulator
1117 // where we need to specify both the gp and fp arg counts and the
1118 // return type so that the linkage routine from aarch64 to x86 and
1119 // back knows which aarch64 registers to copy to x86 registers and
1120 // which x86 result register to copy back to an aarch64 register
1121
1122 void call_VM_leaf_base1(
1123 address entry_point, // the entry point
1124 int number_of_gp_arguments, // the number of gp reg arguments to pass
1125 int number_of_fp_arguments, // the number of fp reg arguments to pass
1126 ret_type type, // the return type for the call
1127 Label* retaddr = NULL
1128 );
1129
1130 void ldr_constant(Register dest, const Address &const_addr) {
1131 if (NearCpool) {
1132 ldr(dest, const_addr);
1133 } else {
1134 unsigned long offset;
1135 adrp(dest, InternalAddress(const_addr.target()), offset);
1136 ldr(dest, Address(dest, offset));
1137 }
1138 }
1139
1140 address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1141 address read_polling_page(Register r, relocInfo::relocType rtype);
1142
1143 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1144 void update_byte_crc32(Register crc, Register val, Register table);
1145 void update_word_crc32(Register crc, Register v, Register tmp,
1146 Register table0, Register table1, Register table2, Register table3,
1147 bool upper = false);
1148
1149 void string_compare(Register str1, Register str2,
1150 Register cnt1, Register cnt2, Register result,
1151 Register tmp1);
1152 void string_equals(Register str1, Register str2,
1153 Register cnt, Register result,
1154 Register tmp1);
1155 void char_arrays_equals(Register ary1, Register ary2,
1156 Register result, Register tmp1);
1157 void encode_iso_array(Register src, Register dst,
1158 Register len, Register result,
1159 FloatRegister Vtmp1, FloatRegister Vtmp2,
1160 FloatRegister Vtmp3, FloatRegister Vtmp4);
1161 void string_indexof(Register str1, Register str2,
1162 Register cnt1, Register cnt2,
1163 Register tmp1, Register tmp2,
1164 Register tmp3, Register tmp4,
1165 int int_cnt1, Register result);
1166 private:
1167 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1168 Register src1, Register src2);
1169 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1170 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1171 }
1172 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1173 Register y, Register y_idx, Register z,
1174 Register carry, Register product,
1175 Register idx, Register kdx);
1176 void multiply_128_x_128_loop(Register y, Register z,
1177 Register carry, Register carry2,
1178 Register idx, Register jdx,
1179 Register yz_idx1, Register yz_idx2,
1180 Register tmp, Register tmp3, Register tmp4,
1181 Register tmp7, Register product_hi);
1182 public:
1183 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1184 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1185 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1186 // ISB may be needed because of a safepoint
1187 void maybe_isb() { isb(); }
1188
1189 private:
1190 // Return the effective address r + (r1 << ext) + offset.
1191 // Uses rscratch2.
1192 Address offsetted_address(Register r, Register r1, Address::extend ext,
1193 int offset, int size);
1194
1195 private:
1196 // Returns an address on the stack which is reachable with a ldr/str of size
1197 // Uses rscratch2 if the address is not directly reachable
1198 Address spill_address(int size, int offset, Register tmp=rscratch2);
1199
1200 public:
1201 void spill(Register Rx, bool is64, int offset) {
1202 if (is64) {
1203 str(Rx, spill_address(8, offset));
1204 } else {
1205 strw(Rx, spill_address(4, offset));
1206 }
1207 }
1208 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1209 str(Vx, T, spill_address(1 << (int)T, offset));
1210 }
1211 void unspill(Register Rx, bool is64, int offset) {
1212 if (is64) {
1213 ldr(Rx, spill_address(8, offset));
1214 } else {
1215 ldrw(Rx, spill_address(4, offset));
1216 }
1217 }
1218 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1219 ldr(Vx, T, spill_address(1 << (int)T, offset));
1220 }
1221 void spill_copy128(int src_offset, int dst_offset,
1222 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1223 if (src_offset < 512 && (src_offset & 7) == 0 &&
1224 dst_offset < 512 && (dst_offset & 7) == 0) {
1225 ldp(tmp1, tmp2, Address(sp, src_offset));
1226 stp(tmp1, tmp2, Address(sp, dst_offset));
1227 } else {
1228 unspill(tmp1, true, src_offset);
1229 spill(tmp1, true, dst_offset);
1230 unspill(tmp1, true, src_offset+8);
1231 spill(tmp1, true, dst_offset+8);
1232 }
1233 }
1234 };
1235
1236 #ifdef ASSERT
1237 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1238 #endif
1239
1240 /**
1241 * class SkipIfEqual:
1242 *
1243 * Instantiating this class will result in assembly code being output that will
1244 * jump around any code emitted between the creation of the instance and it's
1245 * automatic destruction at the end of a scope block, depending on the value of
1246 * the flag passed to the constructor, which will be checked at run-time.
1247 */
1248 class SkipIfEqual {
1249 private:
1250 MacroAssembler* _masm;
1251 Label _label;
1252
1253 public:
1254 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1255 ~SkipIfEqual();
1256 };
1257
1258 struct tableswitch {
1259 Register _reg;
1260 int _insn_index; jint _first_key; jint _last_key;
1261 Label _after;
1262 Label _branches;
1263 };
1264
1265 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP