src/cpu/aarch64/vm/assembler_aarch64.hpp

rev 9026 : 8138583: aarch64: add support for vectorizing fabs/fneg
Reviewed-by: aph

*** 2311,2320 ****
--- 2311,2322 ----
  
  #define MSG "invalid arrangement"
  
  #define ASSERTION (T == T2S || T == T4S || T == T2D)
    INSN(fsqrt, 1, 0b11111);
+   INSN(fabs,  0, 0b01111);
+   INSN(fneg,  1, 0b01111);
  #undef ASSERTION
  
  #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
    INSN(rev64, 0, 0b00000);
  #undef ASSERTION