1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
28
29 #include "asm/register.hpp"
30
31 // definitions of various symbolic names for machine registers
32
33 // First intercalls between C and Java which use 8 general registers
34 // and 8 floating registers
35
36 // we also have to copy between x86 and ARM registers but that's a
37 // secondary complication -- not all code employing C call convention
38 // executes as x86 code though -- we generate some of it
39
40 class Argument VALUE_OBJ_CLASS_SPEC {
41 public:
42 enum {
43 n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
44 n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... )
45
46 n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
47 n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ...
48 };
49 };
50
51 REGISTER_DECLARATION(Register, c_rarg0, r0);
52 REGISTER_DECLARATION(Register, c_rarg1, r1);
53 REGISTER_DECLARATION(Register, c_rarg2, r2);
54 REGISTER_DECLARATION(Register, c_rarg3, r3);
55 REGISTER_DECLARATION(Register, c_rarg4, r4);
56 REGISTER_DECLARATION(Register, c_rarg5, r5);
57 REGISTER_DECLARATION(Register, c_rarg6, r6);
58 REGISTER_DECLARATION(Register, c_rarg7, r7);
59
60 REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
61 REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
62 REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
63 REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
64 REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
65 REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
66 REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
67 REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
68
69 // Symbolically name the register arguments used by the Java calling convention.
70 // We have control over the convention for java so we can do what we please.
71 // What pleases us is to offset the java calling convention so that when
72 // we call a suitable jni method the arguments are lined up and we don't
73 // have to do much shuffling. A suitable jni method is non-static and a
74 // small number of arguments
75 //
76 // |--------------------------------------------------------------------|
77 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 |
78 // |--------------------------------------------------------------------|
79 // | r0 r1 r2 r3 r4 r5 r6 r7 |
80 // |--------------------------------------------------------------------|
81 // | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 |
82 // |--------------------------------------------------------------------|
83
84
85 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
86 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
87 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
88 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
89 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
90 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
91 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
92 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
93
94 // Java floating args are passed as per C
95
96 REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
97 REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
98 REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
99 REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
100 REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
101 REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
102 REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
103 REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
104
105 // registers used to hold VM data either temporarily within a method
106 // or across method calls
107
108 // volatile (caller-save) registers
109
110 // r8 is used for indirect result location return
111 // we use it and r9 as scratch registers
112 REGISTER_DECLARATION(Register, rscratch1, r8);
113 REGISTER_DECLARATION(Register, rscratch2, r9);
114
115 // current method -- must be in a call-clobbered register
116 REGISTER_DECLARATION(Register, rmethod, r12);
117
118 // non-volatile (callee-save) registers are r16-29
119 // of which the following are dedicated global state
120
121 // link register
122 REGISTER_DECLARATION(Register, lr, r30);
123 // frame pointer
124 REGISTER_DECLARATION(Register, rfp, r29);
125 // current thread
126 REGISTER_DECLARATION(Register, rthread, r28);
127 // base of heap
128 REGISTER_DECLARATION(Register, rheapbase, r27);
129 // constant pool cache
130 REGISTER_DECLARATION(Register, rcpool, r26);
131 // monitors allocated on stack
132 REGISTER_DECLARATION(Register, rmonitors, r25);
133 // locals on stack
134 REGISTER_DECLARATION(Register, rlocals, r24);
135 // bytecode pointer
136 REGISTER_DECLARATION(Register, rbcp, r22);
137 // Dispatch table base
138 REGISTER_DECLARATION(Register, rdispatch, r21);
139 // Java stack pointer
140 REGISTER_DECLARATION(Register, esp, r20);
141
142 // TODO : x86 uses rbp to save SP in method handle code
143 // we may need to do the same with fp
144 // JSR 292 fixed register usages:
145 //REGISTER_DECLARATION(Register, r_mh_SP_save, r29);
146
147 #define assert_cond(ARG1) assert(ARG1, #ARG1)
148
149 namespace asm_util {
150 uint32_t encode_logical_immediate(bool is32, uint64_t imm);
151 };
152
153 using namespace asm_util;
154
155
156 class Assembler;
157
158 class Instruction_aarch64 {
159 unsigned insn;
160 #ifdef ASSERT
161 unsigned bits;
162 #endif
163 Assembler *assem;
164
165 public:
166
167 Instruction_aarch64(class Assembler *as) {
168 #ifdef ASSERT
169 bits = 0;
170 #endif
171 insn = 0;
172 assem = as;
173 }
174
175 inline ~Instruction_aarch64();
176
177 unsigned &get_insn() { return insn; }
178 #ifdef ASSERT
179 unsigned &get_bits() { return bits; }
180 #endif
181
182 static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
183 union {
184 unsigned u;
185 int n;
186 };
187
188 u = val << (31 - hi);
189 n = n >> (31 - hi + lo);
190 return n;
191 }
192
193 static inline uint32_t extract(uint32_t val, int msb, int lsb) {
194 int nbits = msb - lsb + 1;
195 assert_cond(msb >= lsb);
196 uint32_t mask = (1U << nbits) - 1;
197 uint32_t result = val >> lsb;
198 result &= mask;
199 return result;
200 }
201
202 static inline int32_t sextract(uint32_t val, int msb, int lsb) {
203 uint32_t uval = extract(val, msb, lsb);
204 return extend(uval, msb - lsb);
205 }
206
207 static void patch(address a, int msb, int lsb, unsigned long val) {
208 int nbits = msb - lsb + 1;
209 guarantee(val < (1U << nbits), "Field too big for insn");
210 assert_cond(msb >= lsb);
211 unsigned mask = (1U << nbits) - 1;
212 val <<= lsb;
213 mask <<= lsb;
214 unsigned target = *(unsigned *)a;
215 target &= ~mask;
216 target |= val;
217 *(unsigned *)a = target;
218 }
219
220 static void spatch(address a, int msb, int lsb, long val) {
221 int nbits = msb - lsb + 1;
222 long chk = val >> (nbits - 1);
223 guarantee (chk == -1 || chk == 0, "Field too big for insn");
224 unsigned uval = val;
225 unsigned mask = (1U << nbits) - 1;
226 uval &= mask;
227 uval <<= lsb;
228 mask <<= lsb;
229 unsigned target = *(unsigned *)a;
230 target &= ~mask;
231 target |= uval;
232 *(unsigned *)a = target;
233 }
234
235 void f(unsigned val, int msb, int lsb) {
236 int nbits = msb - lsb + 1;
237 guarantee(val < (1U << nbits), "Field too big for insn");
238 assert_cond(msb >= lsb);
239 unsigned mask = (1U << nbits) - 1;
240 val <<= lsb;
241 mask <<= lsb;
242 insn |= val;
243 assert_cond((bits & mask) == 0);
244 #ifdef ASSERT
245 bits |= mask;
246 #endif
247 }
248
249 void f(unsigned val, int bit) {
250 f(val, bit, bit);
251 }
252
253 void sf(long val, int msb, int lsb) {
254 int nbits = msb - lsb + 1;
255 long chk = val >> (nbits - 1);
256 guarantee (chk == -1 || chk == 0, "Field too big for insn");
257 unsigned uval = val;
258 unsigned mask = (1U << nbits) - 1;
259 uval &= mask;
260 f(uval, lsb + nbits - 1, lsb);
261 }
262
263 void rf(Register r, int lsb) {
264 f(r->encoding_nocheck(), lsb + 4, lsb);
265 }
266
267 // reg|ZR
268 void zrf(Register r, int lsb) {
269 f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
270 }
271
272 // reg|SP
273 void srf(Register r, int lsb) {
274 f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
275 }
276
277 void rf(FloatRegister r, int lsb) {
278 f(r->encoding_nocheck(), lsb + 4, lsb);
279 }
280
281 unsigned get(int msb = 31, int lsb = 0) {
282 int nbits = msb - lsb + 1;
283 unsigned mask = ((1U << nbits) - 1) << lsb;
284 assert_cond(bits & mask == mask);
285 return (insn & mask) >> lsb;
286 }
287
288 void fixed(unsigned value, unsigned mask) {
289 assert_cond ((mask & bits) == 0);
290 #ifdef ASSERT
291 bits |= mask;
292 #endif
293 insn |= value;
294 }
295 };
296
297 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
298
299 class PrePost {
300 int _offset;
301 Register _r;
302 public:
303 PrePost(Register reg, int o) : _r(reg), _offset(o) { }
304 int offset() { return _offset; }
305 Register reg() { return _r; }
306 };
307
308 class Pre : public PrePost {
309 public:
310 Pre(Register reg, int o) : PrePost(reg, o) { }
311 };
312 class Post : public PrePost {
313 public:
314 Post(Register reg, int o) : PrePost(reg, o) { }
315 };
316
317 namespace ext
318 {
319 enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
320 };
321
322 // abs methods which cannot overflow and so are well-defined across
323 // the entire domain of integer types.
324 static inline unsigned int uabs(unsigned int n) {
325 union {
326 unsigned int result;
327 int value;
328 };
329 result = n;
330 if (value < 0) result = -result;
331 return result;
332 }
333 static inline unsigned long uabs(unsigned long n) {
334 union {
335 unsigned long result;
336 long value;
337 };
338 result = n;
339 if (value < 0) result = -result;
340 return result;
341 }
342 static inline unsigned long uabs(long n) { return uabs((unsigned long)n); }
343 static inline unsigned long uabs(int n) { return uabs((unsigned int)n); }
344
345 // Addressing modes
346 class Address VALUE_OBJ_CLASS_SPEC {
347 public:
348
349 enum mode { no_mode, base_plus_offset, pre, post, pcrel,
350 base_plus_offset_reg, literal };
351
352 // Shift and extend for base reg + reg offset addressing
353 class extend {
354 int _option, _shift;
355 ext::operation _op;
356 public:
357 extend() { }
358 extend(int s, int o, ext::operation op) : _shift(s), _option(o), _op(op) { }
359 int option() const{ return _option; }
360 int shift() const { return _shift; }
361 ext::operation op() const { return _op; }
362 };
363 class uxtw : public extend {
364 public:
365 uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
366 };
367 class lsl : public extend {
368 public:
369 lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
370 };
371 class sxtw : public extend {
372 public:
373 sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
374 };
375 class sxtx : public extend {
376 public:
377 sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
378 };
379
380 private:
381 Register _base;
382 Register _index;
383 long _offset;
384 enum mode _mode;
385 extend _ext;
386
387 RelocationHolder _rspec;
388
389 // Typically we use AddressLiterals we want to use their rval
390 // However in some situations we want the lval (effect address) of
391 // the item. We provide a special factory for making those lvals.
392 bool _is_lval;
393
394 // If the target is far we'll need to load the ea of this to a
395 // register to reach it. Otherwise if near we can do PC-relative
396 // addressing.
397 address _target;
398
399 public:
400 Address()
401 : _mode(no_mode) { }
402 Address(Register r)
403 : _mode(base_plus_offset), _base(r), _offset(0), _index(noreg), _target(0) { }
404 Address(Register r, int o)
405 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
406 Address(Register r, long o)
407 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
408 Address(Register r, unsigned long o)
409 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
410 #ifdef ASSERT
411 Address(Register r, ByteSize disp)
412 : _mode(base_plus_offset), _base(r), _offset(in_bytes(disp)),
413 _index(noreg), _target(0) { }
414 #endif
415 Address(Register r, Register r1, extend ext = lsl())
416 : _mode(base_plus_offset_reg), _base(r), _index(r1),
417 _ext(ext), _offset(0), _target(0) { }
418 Address(Pre p)
419 : _mode(pre), _base(p.reg()), _offset(p.offset()) { }
420 Address(Post p)
421 : _mode(post), _base(p.reg()), _offset(p.offset()), _target(0) { }
422 Address(address target, RelocationHolder const& rspec)
423 : _mode(literal),
424 _rspec(rspec),
425 _is_lval(false),
426 _target(target) { }
427 Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
428 Address(Register base, RegisterOrConstant index, extend ext = lsl())
429 : _base (base),
430 _ext(ext), _offset(0), _target(0) {
431 if (index.is_register()) {
432 _mode = base_plus_offset_reg;
433 _index = index.as_register();
434 } else {
435 guarantee(ext.option() == ext::uxtx, "should be");
436 assert(index.is_constant(), "should be");
437 _mode = base_plus_offset;
438 _offset = index.as_constant() << ext.shift();
439 }
440 }
441
442 Register base() const {
443 guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
444 | _mode == post),
445 "wrong mode");
446 return _base;
447 }
448 long offset() const {
449 return _offset;
450 }
451 Register index() const {
452 return _index;
453 }
454 mode getMode() const {
455 return _mode;
456 }
457 bool uses(Register reg) const { return _base == reg || _index == reg; }
458 address target() const { return _target; }
459 const RelocationHolder& rspec() const { return _rspec; }
460
461 void encode(Instruction_aarch64 *i) const {
462 i->f(0b111, 29, 27);
463 i->srf(_base, 5);
464
465 switch(_mode) {
466 case base_plus_offset:
467 {
468 unsigned size = i->get(31, 30);
469 if (i->get(26, 26) && i->get(23, 23)) {
470 // SIMD Q Type - Size = 128 bits
471 assert(size == 0, "bad size");
472 size = 0b100;
473 }
474 unsigned mask = (1 << size) - 1;
475 if (_offset < 0 || _offset & mask)
476 {
477 i->f(0b00, 25, 24);
478 i->f(0, 21), i->f(0b00, 11, 10);
479 i->sf(_offset, 20, 12);
480 } else {
481 i->f(0b01, 25, 24);
482 i->f(_offset >> size, 21, 10);
483 }
484 }
485 break;
486
487 case base_plus_offset_reg:
488 {
489 i->f(0b00, 25, 24);
490 i->f(1, 21);
491 i->rf(_index, 16);
492 i->f(_ext.option(), 15, 13);
493 unsigned size = i->get(31, 30);
494 if (i->get(26, 26) && i->get(23, 23)) {
495 // SIMD Q Type - Size = 128 bits
496 assert(size == 0, "bad size");
497 size = 0b100;
498 }
499 if (size == 0) // It's a byte
500 i->f(_ext.shift() >= 0, 12);
501 else {
502 if (_ext.shift() > 0)
503 assert(_ext.shift() == (int)size, "bad shift");
504 i->f(_ext.shift() > 0, 12);
505 }
506 i->f(0b10, 11, 10);
507 }
508 break;
509
510 case pre:
511 i->f(0b00, 25, 24);
512 i->f(0, 21), i->f(0b11, 11, 10);
513 i->sf(_offset, 20, 12);
514 break;
515
516 case post:
517 i->f(0b00, 25, 24);
518 i->f(0, 21), i->f(0b01, 11, 10);
519 i->sf(_offset, 20, 12);
520 break;
521
522 default:
523 ShouldNotReachHere();
524 }
525 }
526
527 void encode_pair(Instruction_aarch64 *i) const {
528 switch(_mode) {
529 case base_plus_offset:
530 i->f(0b010, 25, 23);
531 break;
532 case pre:
533 i->f(0b011, 25, 23);
534 break;
535 case post:
536 i->f(0b001, 25, 23);
537 break;
538 default:
539 ShouldNotReachHere();
540 }
541
542 unsigned size; // Operand shift in 32-bit words
543
544 if (i->get(26, 26)) { // float
545 switch(i->get(31, 30)) {
546 case 0b10:
547 size = 2; break;
548 case 0b01:
549 size = 1; break;
550 case 0b00:
551 size = 0; break;
552 default:
553 ShouldNotReachHere();
554 }
555 } else {
556 size = i->get(31, 31);
557 }
558
559 size = 4 << size;
560 guarantee(_offset % size == 0, "bad offset");
561 i->sf(_offset / size, 21, 15);
562 i->srf(_base, 5);
563 }
564
565 void encode_nontemporal_pair(Instruction_aarch64 *i) const {
566 // Only base + offset is allowed
567 i->f(0b000, 25, 23);
568 unsigned size = i->get(31, 31);
569 size = 4 << size;
570 guarantee(_offset % size == 0, "bad offset");
571 i->sf(_offset / size, 21, 15);
572 i->srf(_base, 5);
573 guarantee(_mode == Address::base_plus_offset,
574 "Bad addressing mode for non-temporal op");
575 }
576
577 void lea(MacroAssembler *, Register) const;
578
579 static bool offset_ok_for_immed(long offset, int shift = 0) {
580 unsigned mask = (1 << shift) - 1;
581 if (offset < 0 || offset & mask) {
582 return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset
583 } else {
584 return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset
585 }
586 }
587 };
588
589 // Convience classes
590 class RuntimeAddress: public Address {
591
592 public:
593
594 RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
595
596 };
597
598 class OopAddress: public Address {
599
600 public:
601
602 OopAddress(address target) : Address(target, relocInfo::oop_type){}
603
604 };
605
606 class ExternalAddress: public Address {
607 private:
608 static relocInfo::relocType reloc_for_target(address target) {
609 // Sometimes ExternalAddress is used for values which aren't
610 // exactly addresses, like the card table base.
611 // external_word_type can't be used for values in the first page
612 // so just skip the reloc in that case.
613 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
614 }
615
616 public:
617
618 ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
619
620 };
621
622 class InternalAddress: public Address {
623
624 public:
625
626 InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
627 };
628
629 const int FPUStateSizeInWords = 32 * 2;
630 typedef enum {
631 PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
632 PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
633 PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
634 } prfop;
635
636 class Assembler : public AbstractAssembler {
637
638 #ifndef PRODUCT
639 static const unsigned long asm_bp;
640
641 void emit_long(jint x) {
642 if ((unsigned long)pc() == asm_bp)
643 asm volatile ("nop");
644 AbstractAssembler::emit_int32(x);
645 }
646 #else
647 void emit_long(jint x) {
648 AbstractAssembler::emit_int32(x);
649 }
650 #endif
651
652 public:
653
654 enum { instruction_size = 4 };
655
656 Address adjust(Register base, int offset, bool preIncrement) {
657 if (preIncrement)
658 return Address(Pre(base, offset));
659 else
660 return Address(Post(base, offset));
661 }
662
663 Address pre(Register base, int offset) {
664 return adjust(base, offset, true);
665 }
666
667 Address post (Register base, int offset) {
668 return adjust(base, offset, false);
669 }
670
671 Instruction_aarch64* current;
672
673 void set_current(Instruction_aarch64* i) { current = i; }
674
675 void f(unsigned val, int msb, int lsb) {
676 current->f(val, msb, lsb);
677 }
678 void f(unsigned val, int msb) {
679 current->f(val, msb, msb);
680 }
681 void sf(long val, int msb, int lsb) {
682 current->sf(val, msb, lsb);
683 }
684 void rf(Register reg, int lsb) {
685 current->rf(reg, lsb);
686 }
687 void srf(Register reg, int lsb) {
688 current->srf(reg, lsb);
689 }
690 void zrf(Register reg, int lsb) {
691 current->zrf(reg, lsb);
692 }
693 void rf(FloatRegister reg, int lsb) {
694 current->rf(reg, lsb);
695 }
696 void fixed(unsigned value, unsigned mask) {
697 current->fixed(value, mask);
698 }
699
700 void emit() {
701 emit_long(current->get_insn());
702 assert_cond(current->get_bits() == 0xffffffff);
703 current = NULL;
704 }
705
706 typedef void (Assembler::* uncond_branch_insn)(address dest);
707 typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
708 typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
709 typedef void (Assembler::* prefetch_insn)(address target, prfop);
710
711 void wrap_label(Label &L, uncond_branch_insn insn);
712 void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
713 void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
714 void wrap_label(Label &L, prfop, prefetch_insn insn);
715
716 // PC-rel. addressing
717
718 void adr(Register Rd, address dest);
719 void _adrp(Register Rd, address dest);
720
721 void adr(Register Rd, const Address &dest);
722 void _adrp(Register Rd, const Address &dest);
723
724 void adr(Register Rd, Label &L) {
725 wrap_label(Rd, L, &Assembler::Assembler::adr);
726 }
727 void _adrp(Register Rd, Label &L) {
728 wrap_label(Rd, L, &Assembler::_adrp);
729 }
730
731 void adrp(Register Rd, const Address &dest, unsigned long &offset);
732
733 #undef INSN
734
735 void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
736 int negated_op);
737
738 // Add/subtract (immediate)
739 #define INSN(NAME, decode, negated) \
740 void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \
741 starti; \
742 f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
743 zrf(Rd, 0), srf(Rn, 5); \
744 } \
745 \
746 void NAME(Register Rd, Register Rn, unsigned imm) { \
747 starti; \
748 add_sub_immediate(Rd, Rn, imm, decode, negated); \
749 }
750
751 INSN(addsw, 0b001, 0b011);
752 INSN(subsw, 0b011, 0b001);
753 INSN(adds, 0b101, 0b111);
754 INSN(subs, 0b111, 0b101);
755
756 #undef INSN
757
758 #define INSN(NAME, decode, negated) \
759 void NAME(Register Rd, Register Rn, unsigned imm) { \
760 starti; \
761 add_sub_immediate(Rd, Rn, imm, decode, negated); \
762 }
763
764 INSN(addw, 0b000, 0b010);
765 INSN(subw, 0b010, 0b000);
766 INSN(add, 0b100, 0b110);
767 INSN(sub, 0b110, 0b100);
768
769 #undef INSN
770
771 // Logical (immediate)
772 #define INSN(NAME, decode, is32) \
773 void NAME(Register Rd, Register Rn, uint64_t imm) { \
774 starti; \
775 uint32_t val = encode_logical_immediate(is32, imm); \
776 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
777 srf(Rd, 0), zrf(Rn, 5); \
778 }
779
780 INSN(andw, 0b000, true);
781 INSN(orrw, 0b001, true);
782 INSN(eorw, 0b010, true);
783 INSN(andr, 0b100, false);
784 INSN(orr, 0b101, false);
785 INSN(eor, 0b110, false);
786
787 #undef INSN
788
789 #define INSN(NAME, decode, is32) \
790 void NAME(Register Rd, Register Rn, uint64_t imm) { \
791 starti; \
792 uint32_t val = encode_logical_immediate(is32, imm); \
793 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
794 zrf(Rd, 0), zrf(Rn, 5); \
795 }
796
797 INSN(ands, 0b111, false);
798 INSN(andsw, 0b011, true);
799
800 #undef INSN
801
802 // Move wide (immediate)
803 #define INSN(NAME, opcode) \
804 void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \
805 assert_cond((shift/16)*16 == shift); \
806 starti; \
807 f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \
808 f(imm, 20, 5); \
809 rf(Rd, 0); \
810 }
811
812 INSN(movnw, 0b000);
813 INSN(movzw, 0b010);
814 INSN(movkw, 0b011);
815 INSN(movn, 0b100);
816 INSN(movz, 0b110);
817 INSN(movk, 0b111);
818
819 #undef INSN
820
821 // Bitfield
822 #define INSN(NAME, opcode) \
823 void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \
824 starti; \
825 f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \
826 rf(Rn, 5), rf(Rd, 0); \
827 }
828
829 INSN(sbfmw, 0b0001001100);
830 INSN(bfmw, 0b0011001100);
831 INSN(ubfmw, 0b0101001100);
832 INSN(sbfm, 0b1001001101);
833 INSN(bfm, 0b1011001101);
834 INSN(ubfm, 0b1101001101);
835
836 #undef INSN
837
838 // Extract
839 #define INSN(NAME, opcode) \
840 void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \
841 starti; \
842 f(opcode, 31, 21), f(imms, 15, 10); \
843 rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
844 }
845
846 INSN(extrw, 0b00010011100);
847 INSN(extr, 0b10010011110);
848
849 #undef INSN
850
851 // The maximum range of a branch is fixed for the AArch64
852 // architecture. In debug mode we shrink it in order to test
853 // trampolines, but not so small that branches in the interpreter
854 // are out of range.
855 static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
856
857 static bool reachable_from_branch_at(address branch, address target) {
858 return uabs(target - branch) < branch_range;
859 }
860
861 // Unconditional branch (immediate)
862 #define INSN(NAME, opcode) \
863 void NAME(address dest) { \
864 starti; \
865 long offset = (dest - pc()) >> 2; \
866 DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
867 f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \
868 } \
869 void NAME(Label &L) { \
870 wrap_label(L, &Assembler::NAME); \
871 } \
872 void NAME(const Address &dest);
873
874 INSN(b, 0);
875 INSN(bl, 1);
876
877 #undef INSN
878
879 // Compare & branch (immediate)
880 #define INSN(NAME, opcode) \
881 void NAME(Register Rt, address dest) { \
882 long offset = (dest - pc()) >> 2; \
883 starti; \
884 f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \
885 } \
886 void NAME(Register Rt, Label &L) { \
887 wrap_label(Rt, L, &Assembler::NAME); \
888 }
889
890 INSN(cbzw, 0b00110100);
891 INSN(cbnzw, 0b00110101);
892 INSN(cbz, 0b10110100);
893 INSN(cbnz, 0b10110101);
894
895 #undef INSN
896
897 // Test & branch (immediate)
898 #define INSN(NAME, opcode) \
899 void NAME(Register Rt, int bitpos, address dest) { \
900 long offset = (dest - pc()) >> 2; \
901 int b5 = bitpos >> 5; \
902 bitpos &= 0x1f; \
903 starti; \
904 f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
905 rf(Rt, 0); \
906 } \
907 void NAME(Register Rt, int bitpos, Label &L) { \
908 wrap_label(Rt, bitpos, L, &Assembler::NAME); \
909 }
910
911 INSN(tbz, 0b0110110);
912 INSN(tbnz, 0b0110111);
913
914 #undef INSN
915
916 // Conditional branch (immediate)
917 enum Condition
918 {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
919
920 void br(Condition cond, address dest) {
921 long offset = (dest - pc()) >> 2;
922 starti;
923 f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
924 }
925
926 #define INSN(NAME, cond) \
927 void NAME(address dest) { \
928 br(cond, dest); \
929 }
930
931 INSN(beq, EQ);
932 INSN(bne, NE);
933 INSN(bhs, HS);
934 INSN(bcs, CS);
935 INSN(blo, LO);
936 INSN(bcc, CC);
937 INSN(bmi, MI);
938 INSN(bpl, PL);
939 INSN(bvs, VS);
940 INSN(bvc, VC);
941 INSN(bhi, HI);
942 INSN(bls, LS);
943 INSN(bge, GE);
944 INSN(blt, LT);
945 INSN(bgt, GT);
946 INSN(ble, LE);
947 INSN(bal, AL);
948 INSN(bnv, NV);
949
950 void br(Condition cc, Label &L);
951
952 #undef INSN
953
954 // Exception generation
955 void generate_exception(int opc, int op2, int LL, unsigned imm) {
956 starti;
957 f(0b11010100, 31, 24);
958 f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
959 }
960
961 #define INSN(NAME, opc, op2, LL) \
962 void NAME(unsigned imm) { \
963 generate_exception(opc, op2, LL, imm); \
964 }
965
966 INSN(svc, 0b000, 0, 0b01);
967 INSN(hvc, 0b000, 0, 0b10);
968 INSN(smc, 0b000, 0, 0b11);
969 INSN(brk, 0b001, 0, 0b00);
970 INSN(hlt, 0b010, 0, 0b00);
971 INSN(dpcs1, 0b101, 0, 0b01);
972 INSN(dpcs2, 0b101, 0, 0b10);
973 INSN(dpcs3, 0b101, 0, 0b11);
974
975 #undef INSN
976
977 // System
978 void system(int op0, int op1, int CRn, int CRm, int op2,
979 Register rt = (Register)0b11111)
980 {
981 starti;
982 f(0b11010101000, 31, 21);
983 f(op0, 20, 19);
984 f(op1, 18, 16);
985 f(CRn, 15, 12);
986 f(CRm, 11, 8);
987 f(op2, 7, 5);
988 rf(rt, 0);
989 }
990
991 void hint(int imm) {
992 system(0b00, 0b011, 0b0010, imm, 0b000);
993 }
994
995 void nop() {
996 hint(0);
997 }
998 // we only provide mrs and msr for the special purpose system
999 // registers where op1 (instr[20:19]) == 11 and, (currently) only
1000 // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1001
1002 void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1003 starti;
1004 f(0b1101010100011, 31, 19);
1005 f(op1, 18, 16);
1006 f(CRn, 15, 12);
1007 f(CRm, 11, 8);
1008 f(op2, 7, 5);
1009 // writing zr is ok
1010 zrf(rt, 0);
1011 }
1012
1013 void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1014 starti;
1015 f(0b1101010100111, 31, 19);
1016 f(op1, 18, 16);
1017 f(CRn, 15, 12);
1018 f(CRm, 11, 8);
1019 f(op2, 7, 5);
1020 // reading to zr is a mistake
1021 rf(rt, 0);
1022 }
1023
1024 enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1025 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1026
1027 void dsb(barrier imm) {
1028 system(0b00, 0b011, 0b00011, imm, 0b100);
1029 }
1030
1031 void dmb(barrier imm) {
1032 system(0b00, 0b011, 0b00011, imm, 0b101);
1033 }
1034
1035 void isb() {
1036 system(0b00, 0b011, 0b00011, SY, 0b110);
1037 }
1038
1039 void dc(Register Rt) {
1040 system(0b01, 0b011, 0b0111, 0b1011, 0b001, Rt);
1041 }
1042
1043 void ic(Register Rt) {
1044 system(0b01, 0b011, 0b0111, 0b0101, 0b001, Rt);
1045 }
1046
1047 // A more convenient access to dmb for our purposes
1048 enum Membar_mask_bits {
1049 // We can use ISH for a barrier because the ARM ARM says "This
1050 // architecture assumes that all Processing Elements that use the
1051 // same operating system or hypervisor are in the same Inner
1052 // Shareable shareability domain."
1053 StoreStore = ISHST,
1054 LoadStore = ISHLD,
1055 LoadLoad = ISHLD,
1056 StoreLoad = ISH,
1057 AnyAny = ISH
1058 };
1059
1060 void membar(Membar_mask_bits order_constraint) {
1061 dmb(Assembler::barrier(order_constraint));
1062 }
1063
1064 // Unconditional branch (register)
1065 void branch_reg(Register R, int opc) {
1066 starti;
1067 f(0b1101011, 31, 25);
1068 f(opc, 24, 21);
1069 f(0b11111000000, 20, 10);
1070 rf(R, 5);
1071 f(0b00000, 4, 0);
1072 }
1073
1074 #define INSN(NAME, opc) \
1075 void NAME(Register R) { \
1076 branch_reg(R, opc); \
1077 }
1078
1079 INSN(br, 0b0000);
1080 INSN(blr, 0b0001);
1081 INSN(ret, 0b0010);
1082
1083 void ret(void *p); // This forces a compile-time error for ret(0)
1084
1085 #undef INSN
1086
1087 #define INSN(NAME, opc) \
1088 void NAME() { \
1089 branch_reg((Register)0b11111, opc); \
1090 }
1091
1092 INSN(eret, 0b0100);
1093 INSN(drps, 0b0101);
1094
1095 #undef INSN
1096
1097 // Load/store exclusive
1098 enum operand_size { byte, halfword, word, xword };
1099
1100 void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1101 Register Rn, enum operand_size sz, int op, int o0) {
1102 starti;
1103 f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1104 rf(Rs, 16), f(o0, 15), rf(Rt2, 10), rf(Rn, 5), rf(Rt1, 0);
1105 }
1106
1107 #define INSN4(NAME, sz, op, o0) /* Four registers */ \
1108 void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \
1109 guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \
1110 load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \
1111 }
1112
1113 #define INSN3(NAME, sz, op, o0) /* Three registers */ \
1114 void NAME(Register Rs, Register Rt, Register Rn) { \
1115 guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1116 load_store_exclusive(Rs, Rt, (Register)0b11111, Rn, sz, op, o0); \
1117 }
1118
1119 #define INSN2(NAME, sz, op, o0) /* Two registers */ \
1120 void NAME(Register Rt, Register Rn) { \
1121 load_store_exclusive((Register)0b11111, Rt, (Register)0b11111, \
1122 Rn, sz, op, o0); \
1123 }
1124
1125 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
1126 void NAME(Register Rt1, Register Rt2, Register Rn) { \
1127 guarantee(Rt1 != Rt2, "unpredictable instruction"); \
1128 load_store_exclusive((Register)0b11111, Rt1, Rt2, Rn, sz, op, o0); \
1129 }
1130
1131 // bytes
1132 INSN3(stxrb, byte, 0b000, 0);
1133 INSN3(stlxrb, byte, 0b000, 1);
1134 INSN2(ldxrb, byte, 0b010, 0);
1135 INSN2(ldaxrb, byte, 0b010, 1);
1136 INSN2(stlrb, byte, 0b100, 1);
1137 INSN2(ldarb, byte, 0b110, 1);
1138
1139 // halfwords
1140 INSN3(stxrh, halfword, 0b000, 0);
1141 INSN3(stlxrh, halfword, 0b000, 1);
1142 INSN2(ldxrh, halfword, 0b010, 0);
1143 INSN2(ldaxrh, halfword, 0b010, 1);
1144 INSN2(stlrh, halfword, 0b100, 1);
1145 INSN2(ldarh, halfword, 0b110, 1);
1146
1147 // words
1148 INSN3(stxrw, word, 0b000, 0);
1149 INSN3(stlxrw, word, 0b000, 1);
1150 INSN4(stxpw, word, 0b001, 0);
1151 INSN4(stlxpw, word, 0b001, 1);
1152 INSN2(ldxrw, word, 0b010, 0);
1153 INSN2(ldaxrw, word, 0b010, 1);
1154 INSN_FOO(ldxpw, word, 0b011, 0);
1155 INSN_FOO(ldaxpw, word, 0b011, 1);
1156 INSN2(stlrw, word, 0b100, 1);
1157 INSN2(ldarw, word, 0b110, 1);
1158
1159 // xwords
1160 INSN3(stxr, xword, 0b000, 0);
1161 INSN3(stlxr, xword, 0b000, 1);
1162 INSN4(stxp, xword, 0b001, 0);
1163 INSN4(stlxp, xword, 0b001, 1);
1164 INSN2(ldxr, xword, 0b010, 0);
1165 INSN2(ldaxr, xword, 0b010, 1);
1166 INSN_FOO(ldxp, xword, 0b011, 0);
1167 INSN_FOO(ldaxp, xword, 0b011, 1);
1168 INSN2(stlr, xword, 0b100, 1);
1169 INSN2(ldar, xword, 0b110, 1);
1170
1171 #undef INSN2
1172 #undef INSN3
1173 #undef INSN4
1174 #undef INSN_FOO
1175
1176 // Load register (literal)
1177 #define INSN(NAME, opc, V) \
1178 void NAME(Register Rt, address dest) { \
1179 long offset = (dest - pc()) >> 2; \
1180 starti; \
1181 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1182 sf(offset, 23, 5); \
1183 rf(Rt, 0); \
1184 } \
1185 void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \
1186 InstructionMark im(this); \
1187 guarantee(rtype == relocInfo::internal_word_type, \
1188 "only internal_word_type relocs make sense here"); \
1189 code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
1190 NAME(Rt, dest); \
1191 } \
1192 void NAME(Register Rt, Label &L) { \
1193 wrap_label(Rt, L, &Assembler::NAME); \
1194 }
1195
1196 INSN(ldrw, 0b00, 0);
1197 INSN(ldr, 0b01, 0);
1198 INSN(ldrsw, 0b10, 0);
1199
1200 #undef INSN
1201
1202 #define INSN(NAME, opc, V) \
1203 void NAME(FloatRegister Rt, address dest) { \
1204 long offset = (dest - pc()) >> 2; \
1205 starti; \
1206 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1207 sf(offset, 23, 5); \
1208 rf((Register)Rt, 0); \
1209 }
1210
1211 INSN(ldrs, 0b00, 1);
1212 INSN(ldrd, 0b01, 1);
1213 INSN(ldrq, 0b10, 1);
1214
1215 #undef INSN
1216
1217 #define INSN(NAME, opc, V) \
1218 void NAME(address dest, prfop op = PLDL1KEEP) { \
1219 long offset = (dest - pc()) >> 2; \
1220 starti; \
1221 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1222 sf(offset, 23, 5); \
1223 f(op, 4, 0); \
1224 } \
1225 void NAME(Label &L, prfop op = PLDL1KEEP) { \
1226 wrap_label(L, op, &Assembler::NAME); \
1227 }
1228
1229 INSN(prfm, 0b11, 0);
1230
1231 #undef INSN
1232
1233 // Load/store
1234 void ld_st1(int opc, int p1, int V, int L,
1235 Register Rt1, Register Rt2, Address adr, bool no_allocate) {
1236 starti;
1237 f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
1238 zrf(Rt2, 10), zrf(Rt1, 0);
1239 if (no_allocate) {
1240 adr.encode_nontemporal_pair(current);
1241 } else {
1242 adr.encode_pair(current);
1243 }
1244 }
1245
1246 // Load/store register pair (offset)
1247 #define INSN(NAME, size, p1, V, L, no_allocate) \
1248 void NAME(Register Rt1, Register Rt2, Address adr) { \
1249 ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
1250 }
1251
1252 INSN(stpw, 0b00, 0b101, 0, 0, false);
1253 INSN(ldpw, 0b00, 0b101, 0, 1, false);
1254 INSN(ldpsw, 0b01, 0b101, 0, 1, false);
1255 INSN(stp, 0b10, 0b101, 0, 0, false);
1256 INSN(ldp, 0b10, 0b101, 0, 1, false);
1257
1258 // Load/store no-allocate pair (offset)
1259 INSN(stnpw, 0b00, 0b101, 0, 0, true);
1260 INSN(ldnpw, 0b00, 0b101, 0, 1, true);
1261 INSN(stnp, 0b10, 0b101, 0, 0, true);
1262 INSN(ldnp, 0b10, 0b101, 0, 1, true);
1263
1264 #undef INSN
1265
1266 #define INSN(NAME, size, p1, V, L, no_allocate) \
1267 void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \
1268 ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
1269 }
1270
1271 INSN(stps, 0b00, 0b101, 1, 0, false);
1272 INSN(ldps, 0b00, 0b101, 1, 1, false);
1273 INSN(stpd, 0b01, 0b101, 1, 0, false);
1274 INSN(ldpd, 0b01, 0b101, 1, 1, false);
1275 INSN(stpq, 0b10, 0b101, 1, 0, false);
1276 INSN(ldpq, 0b10, 0b101, 1, 1, false);
1277
1278 #undef INSN
1279
1280 // Load/store register (all modes)
1281 void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
1282 starti;
1283
1284 f(V, 26); // general reg?
1285 zrf(Rt, 0);
1286
1287 // Encoding for literal loads is done here (rather than pushed
1288 // down into Address::encode) because the encoding of this
1289 // instruction is too different from all of the other forms to
1290 // make it worth sharing.
1291 if (adr.getMode() == Address::literal) {
1292 assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
1293 assert(op == 0b01, "literal form can only be used with loads");
1294 f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
1295 long offset = (adr.target() - pc()) >> 2;
1296 sf(offset, 23, 5);
1297 code_section()->relocate(pc(), adr.rspec());
1298 return;
1299 }
1300
1301 f(size, 31, 30);
1302 f(op, 23, 22); // str
1303 adr.encode(current);
1304 }
1305
1306 #define INSN(NAME, size, op) \
1307 void NAME(Register Rt, const Address &adr) { \
1308 ld_st2(Rt, adr, size, op); \
1309 } \
1310
1311 INSN(str, 0b11, 0b00);
1312 INSN(strw, 0b10, 0b00);
1313 INSN(strb, 0b00, 0b00);
1314 INSN(strh, 0b01, 0b00);
1315
1316 INSN(ldr, 0b11, 0b01);
1317 INSN(ldrw, 0b10, 0b01);
1318 INSN(ldrb, 0b00, 0b01);
1319 INSN(ldrh, 0b01, 0b01);
1320
1321 INSN(ldrsb, 0b00, 0b10);
1322 INSN(ldrsbw, 0b00, 0b11);
1323 INSN(ldrsh, 0b01, 0b10);
1324 INSN(ldrshw, 0b01, 0b11);
1325 INSN(ldrsw, 0b10, 0b10);
1326
1327 #undef INSN
1328
1329 #define INSN(NAME, size, op) \
1330 void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \
1331 ld_st2((Register)pfop, adr, size, op); \
1332 }
1333
1334 INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
1335 // writeback modes, but the assembler
1336 // doesn't enfore that.
1337
1338 #undef INSN
1339
1340 #define INSN(NAME, size, op) \
1341 void NAME(FloatRegister Rt, const Address &adr) { \
1342 ld_st2((Register)Rt, adr, size, op, 1); \
1343 }
1344
1345 INSN(strd, 0b11, 0b00);
1346 INSN(strs, 0b10, 0b00);
1347 INSN(ldrd, 0b11, 0b01);
1348 INSN(ldrs, 0b10, 0b01);
1349 INSN(strq, 0b00, 0b10);
1350 INSN(ldrq, 0x00, 0b11);
1351
1352 #undef INSN
1353
1354 enum shift_kind { LSL, LSR, ASR, ROR };
1355
1356 void op_shifted_reg(unsigned decode,
1357 enum shift_kind kind, unsigned shift,
1358 unsigned size, unsigned op) {
1359 f(size, 31);
1360 f(op, 30, 29);
1361 f(decode, 28, 24);
1362 f(shift, 15, 10);
1363 f(kind, 23, 22);
1364 }
1365
1366 // Logical (shifted register)
1367 #define INSN(NAME, size, op, N) \
1368 void NAME(Register Rd, Register Rn, Register Rm, \
1369 enum shift_kind kind = LSL, unsigned shift = 0) { \
1370 starti; \
1371 f(N, 21); \
1372 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1373 op_shifted_reg(0b01010, kind, shift, size, op); \
1374 }
1375
1376 INSN(andr, 1, 0b00, 0);
1377 INSN(orr, 1, 0b01, 0);
1378 INSN(eor, 1, 0b10, 0);
1379 INSN(ands, 1, 0b11, 0);
1380 INSN(andw, 0, 0b00, 0);
1381 INSN(orrw, 0, 0b01, 0);
1382 INSN(eorw, 0, 0b10, 0);
1383 INSN(andsw, 0, 0b11, 0);
1384
1385 INSN(bic, 1, 0b00, 1);
1386 INSN(orn, 1, 0b01, 1);
1387 INSN(eon, 1, 0b10, 1);
1388 INSN(bics, 1, 0b11, 1);
1389 INSN(bicw, 0, 0b00, 1);
1390 INSN(ornw, 0, 0b01, 1);
1391 INSN(eonw, 0, 0b10, 1);
1392 INSN(bicsw, 0, 0b11, 1);
1393
1394 #undef INSN
1395
1396 // Add/subtract (shifted register)
1397 #define INSN(NAME, size, op) \
1398 void NAME(Register Rd, Register Rn, Register Rm, \
1399 enum shift_kind kind, unsigned shift = 0) { \
1400 starti; \
1401 f(0, 21); \
1402 assert_cond(kind != ROR); \
1403 zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \
1404 op_shifted_reg(0b01011, kind, shift, size, op); \
1405 }
1406
1407 INSN(add, 1, 0b000);
1408 INSN(sub, 1, 0b10);
1409 INSN(addw, 0, 0b000);
1410 INSN(subw, 0, 0b10);
1411
1412 INSN(adds, 1, 0b001);
1413 INSN(subs, 1, 0b11);
1414 INSN(addsw, 0, 0b001);
1415 INSN(subsw, 0, 0b11);
1416
1417 #undef INSN
1418
1419 // Add/subtract (extended register)
1420 #define INSN(NAME, op) \
1421 void NAME(Register Rd, Register Rn, Register Rm, \
1422 ext::operation option, int amount = 0) { \
1423 starti; \
1424 zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \
1425 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1426 }
1427
1428 void add_sub_extended_reg(unsigned op, unsigned decode,
1429 Register Rd, Register Rn, Register Rm,
1430 unsigned opt, ext::operation option, unsigned imm) {
1431 guarantee(imm <= 4, "shift amount must be < 4");
1432 f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
1433 f(option, 15, 13), f(imm, 12, 10);
1434 }
1435
1436 INSN(addw, 0b000);
1437 INSN(subw, 0b010);
1438 INSN(add, 0b100);
1439 INSN(sub, 0b110);
1440
1441 #undef INSN
1442
1443 #define INSN(NAME, op) \
1444 void NAME(Register Rd, Register Rn, Register Rm, \
1445 ext::operation option, int amount = 0) { \
1446 starti; \
1447 zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \
1448 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1449 }
1450
1451 INSN(addsw, 0b001);
1452 INSN(subsw, 0b011);
1453 INSN(adds, 0b101);
1454 INSN(subs, 0b111);
1455
1456 #undef INSN
1457
1458 // Aliases for short forms of add and sub
1459 #define INSN(NAME) \
1460 void NAME(Register Rd, Register Rn, Register Rm) { \
1461 if (Rd == sp || Rn == sp) \
1462 NAME(Rd, Rn, Rm, ext::uxtx); \
1463 else \
1464 NAME(Rd, Rn, Rm, LSL); \
1465 }
1466
1467 INSN(addw);
1468 INSN(subw);
1469 INSN(add);
1470 INSN(sub);
1471
1472 INSN(addsw);
1473 INSN(subsw);
1474 INSN(adds);
1475 INSN(subs);
1476
1477 #undef INSN
1478
1479 // Add/subtract (with carry)
1480 void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
1481 starti;
1482 f(op, 31, 29);
1483 f(0b11010000, 28, 21);
1484 f(0b000000, 15, 10);
1485 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
1486 }
1487
1488 #define INSN(NAME, op) \
1489 void NAME(Register Rd, Register Rn, Register Rm) { \
1490 add_sub_carry(op, Rd, Rn, Rm); \
1491 }
1492
1493 INSN(adcw, 0b000);
1494 INSN(adcsw, 0b001);
1495 INSN(sbcw, 0b010);
1496 INSN(sbcsw, 0b011);
1497 INSN(adc, 0b100);
1498 INSN(adcs, 0b101);
1499 INSN(sbc,0b110);
1500 INSN(sbcs, 0b111);
1501
1502 #undef INSN
1503
1504 // Conditional compare (both kinds)
1505 void conditional_compare(unsigned op, int o2, int o3,
1506 Register Rn, unsigned imm5, unsigned nzcv,
1507 unsigned cond) {
1508 f(op, 31, 29);
1509 f(0b11010010, 28, 21);
1510 f(cond, 15, 12);
1511 f(o2, 10);
1512 f(o3, 4);
1513 f(nzcv, 3, 0);
1514 f(imm5, 20, 16), rf(Rn, 5);
1515 }
1516
1517 #define INSN(NAME, op) \
1518 void NAME(Register Rn, Register Rm, int imm, Condition cond) { \
1519 starti; \
1520 f(0, 11); \
1521 conditional_compare(op, 0, 0, Rn, (uintptr_t)Rm, imm, cond); \
1522 } \
1523 \
1524 void NAME(Register Rn, int imm5, int imm, Condition cond) { \
1525 starti; \
1526 f(1, 11); \
1527 conditional_compare(op, 0, 0, Rn, imm5, imm, cond); \
1528 }
1529
1530 INSN(ccmnw, 0b001);
1531 INSN(ccmpw, 0b011);
1532 INSN(ccmn, 0b101);
1533 INSN(ccmp, 0b111);
1534
1535 #undef INSN
1536
1537 // Conditional select
1538 void conditional_select(unsigned op, unsigned op2,
1539 Register Rd, Register Rn, Register Rm,
1540 unsigned cond) {
1541 starti;
1542 f(op, 31, 29);
1543 f(0b11010100, 28, 21);
1544 f(cond, 15, 12);
1545 f(op2, 11, 10);
1546 zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
1547 }
1548
1549 #define INSN(NAME, op, op2) \
1550 void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
1551 conditional_select(op, op2, Rd, Rn, Rm, cond); \
1552 }
1553
1554 INSN(cselw, 0b000, 0b00);
1555 INSN(csincw, 0b000, 0b01);
1556 INSN(csinvw, 0b010, 0b00);
1557 INSN(csnegw, 0b010, 0b01);
1558 INSN(csel, 0b100, 0b00);
1559 INSN(csinc, 0b100, 0b01);
1560 INSN(csinv, 0b110, 0b00);
1561 INSN(csneg, 0b110, 0b01);
1562
1563 #undef INSN
1564
1565 // Data processing
1566 void data_processing(unsigned op29, unsigned opcode,
1567 Register Rd, Register Rn) {
1568 f(op29, 31, 29), f(0b11010110, 28, 21);
1569 f(opcode, 15, 10);
1570 rf(Rn, 5), rf(Rd, 0);
1571 }
1572
1573 // (1 source)
1574 #define INSN(NAME, op29, opcode2, opcode) \
1575 void NAME(Register Rd, Register Rn) { \
1576 starti; \
1577 f(opcode2, 20, 16); \
1578 data_processing(op29, opcode, Rd, Rn); \
1579 }
1580
1581 INSN(rbitw, 0b010, 0b00000, 0b00000);
1582 INSN(rev16w, 0b010, 0b00000, 0b00001);
1583 INSN(revw, 0b010, 0b00000, 0b00010);
1584 INSN(clzw, 0b010, 0b00000, 0b00100);
1585 INSN(clsw, 0b010, 0b00000, 0b00101);
1586
1587 INSN(rbit, 0b110, 0b00000, 0b00000);
1588 INSN(rev16, 0b110, 0b00000, 0b00001);
1589 INSN(rev32, 0b110, 0b00000, 0b00010);
1590 INSN(rev, 0b110, 0b00000, 0b00011);
1591 INSN(clz, 0b110, 0b00000, 0b00100);
1592 INSN(cls, 0b110, 0b00000, 0b00101);
1593
1594 #undef INSN
1595
1596 // (2 sources)
1597 #define INSN(NAME, op29, opcode) \
1598 void NAME(Register Rd, Register Rn, Register Rm) { \
1599 starti; \
1600 rf(Rm, 16); \
1601 data_processing(op29, opcode, Rd, Rn); \
1602 }
1603
1604 INSN(udivw, 0b000, 0b000010);
1605 INSN(sdivw, 0b000, 0b000011);
1606 INSN(lslvw, 0b000, 0b001000);
1607 INSN(lsrvw, 0b000, 0b001001);
1608 INSN(asrvw, 0b000, 0b001010);
1609 INSN(rorvw, 0b000, 0b001011);
1610
1611 INSN(udiv, 0b100, 0b000010);
1612 INSN(sdiv, 0b100, 0b000011);
1613 INSN(lslv, 0b100, 0b001000);
1614 INSN(lsrv, 0b100, 0b001001);
1615 INSN(asrv, 0b100, 0b001010);
1616 INSN(rorv, 0b100, 0b001011);
1617
1618 #undef INSN
1619
1620 // (3 sources)
1621 void data_processing(unsigned op54, unsigned op31, unsigned o0,
1622 Register Rd, Register Rn, Register Rm,
1623 Register Ra) {
1624 starti;
1625 f(op54, 31, 29), f(0b11011, 28, 24);
1626 f(op31, 23, 21), f(o0, 15);
1627 zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
1628 }
1629
1630 #define INSN(NAME, op54, op31, o0) \
1631 void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \
1632 data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \
1633 }
1634
1635 INSN(maddw, 0b000, 0b000, 0);
1636 INSN(msubw, 0b000, 0b000, 1);
1637 INSN(madd, 0b100, 0b000, 0);
1638 INSN(msub, 0b100, 0b000, 1);
1639 INSN(smaddl, 0b100, 0b001, 0);
1640 INSN(smsubl, 0b100, 0b001, 1);
1641 INSN(umaddl, 0b100, 0b101, 0);
1642 INSN(umsubl, 0b100, 0b101, 1);
1643
1644 #undef INSN
1645
1646 #define INSN(NAME, op54, op31, o0) \
1647 void NAME(Register Rd, Register Rn, Register Rm) { \
1648 data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \
1649 }
1650
1651 INSN(smulh, 0b100, 0b010, 0);
1652 INSN(umulh, 0b100, 0b110, 0);
1653
1654 #undef INSN
1655
1656 // Floating-point data-processing (1 source)
1657 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1658 FloatRegister Vd, FloatRegister Vn) {
1659 starti;
1660 f(op31, 31, 29);
1661 f(0b11110, 28, 24);
1662 f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
1663 rf(Vn, 5), rf(Vd, 0);
1664 }
1665
1666 #define INSN(NAME, op31, type, opcode) \
1667 void NAME(FloatRegister Vd, FloatRegister Vn) { \
1668 data_processing(op31, type, opcode, Vd, Vn); \
1669 }
1670
1671 private:
1672 INSN(i_fmovs, 0b000, 0b00, 0b000000);
1673 public:
1674 INSN(fabss, 0b000, 0b00, 0b000001);
1675 INSN(fnegs, 0b000, 0b00, 0b000010);
1676 INSN(fsqrts, 0b000, 0b00, 0b000011);
1677 INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision
1678
1679 private:
1680 INSN(i_fmovd, 0b000, 0b01, 0b000000);
1681 public:
1682 INSN(fabsd, 0b000, 0b01, 0b000001);
1683 INSN(fnegd, 0b000, 0b01, 0b000010);
1684 INSN(fsqrtd, 0b000, 0b01, 0b000011);
1685 INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision
1686
1687 void fmovd(FloatRegister Vd, FloatRegister Vn) {
1688 assert(Vd != Vn, "should be");
1689 i_fmovd(Vd, Vn);
1690 }
1691
1692 void fmovs(FloatRegister Vd, FloatRegister Vn) {
1693 assert(Vd != Vn, "should be");
1694 i_fmovs(Vd, Vn);
1695 }
1696
1697 #undef INSN
1698
1699 // Floating-point data-processing (2 source)
1700 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1701 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1702 starti;
1703 f(op31, 31, 29);
1704 f(0b11110, 28, 24);
1705 f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1706 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1707 }
1708
1709 #define INSN(NAME, op31, type, opcode) \
1710 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \
1711 data_processing(op31, type, opcode, Vd, Vn, Vm); \
1712 }
1713
1714 INSN(fmuls, 0b000, 0b00, 0b0000);
1715 INSN(fdivs, 0b000, 0b00, 0b0001);
1716 INSN(fadds, 0b000, 0b00, 0b0010);
1717 INSN(fsubs, 0b000, 0b00, 0b0011);
1718 INSN(fnmuls, 0b000, 0b00, 0b1000);
1719
1720 INSN(fmuld, 0b000, 0b01, 0b0000);
1721 INSN(fdivd, 0b000, 0b01, 0b0001);
1722 INSN(faddd, 0b000, 0b01, 0b0010);
1723 INSN(fsubd, 0b000, 0b01, 0b0011);
1724 INSN(fnmuld, 0b000, 0b01, 0b1000);
1725
1726 #undef INSN
1727
1728 // Floating-point data-processing (3 source)
1729 void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1730 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1731 FloatRegister Va) {
1732 starti;
1733 f(op31, 31, 29);
1734 f(0b11111, 28, 24);
1735 f(type, 23, 22), f(o1, 21), f(o0, 15);
1736 rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1737 }
1738
1739 #define INSN(NAME, op31, type, o1, o0) \
1740 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \
1741 FloatRegister Va) { \
1742 data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \
1743 }
1744
1745 INSN(fmadds, 0b000, 0b00, 0, 0);
1746 INSN(fmsubs, 0b000, 0b00, 0, 1);
1747 INSN(fnmadds, 0b000, 0b00, 1, 0);
1748 INSN(fnmsubs, 0b000, 0b00, 1, 1);
1749
1750 INSN(fmaddd, 0b000, 0b01, 0, 0);
1751 INSN(fmsubd, 0b000, 0b01, 0, 1);
1752 INSN(fnmaddd, 0b000, 0b01, 1, 0);
1753 INSN(fnmsub, 0b000, 0b01, 1, 1);
1754
1755 #undef INSN
1756
1757 // Floating-point conditional select
1758 void fp_conditional_select(unsigned op31, unsigned type,
1759 unsigned op1, unsigned op2,
1760 Condition cond, FloatRegister Vd,
1761 FloatRegister Vn, FloatRegister Vm) {
1762 starti;
1763 f(op31, 31, 29);
1764 f(0b11110, 28, 24);
1765 f(type, 23, 22);
1766 f(op1, 21, 21);
1767 f(op2, 11, 10);
1768 f(cond, 15, 12);
1769 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1770 }
1771
1772 #define INSN(NAME, op31, type, op1, op2) \
1773 void NAME(FloatRegister Vd, FloatRegister Vn, \
1774 FloatRegister Vm, Condition cond) { \
1775 fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \
1776 }
1777
1778 INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
1779 INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
1780
1781 #undef INSN
1782
1783 // Floating-point<->integer conversions
1784 void float_int_convert(unsigned op31, unsigned type,
1785 unsigned rmode, unsigned opcode,
1786 Register Rd, Register Rn) {
1787 starti;
1788 f(op31, 31, 29);
1789 f(0b11110, 28, 24);
1790 f(type, 23, 22), f(1, 21), f(rmode, 20, 19);
1791 f(opcode, 18, 16), f(0b000000, 15, 10);
1792 zrf(Rn, 5), zrf(Rd, 0);
1793 }
1794
1795 #define INSN(NAME, op31, type, rmode, opcode) \
1796 void NAME(Register Rd, FloatRegister Vn) { \
1797 float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \
1798 }
1799
1800 INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
1801 INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000);
1802 INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000);
1803 INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000);
1804
1805 INSN(fmovs, 0b000, 0b00, 0b00, 0b110);
1806 INSN(fmovd, 0b100, 0b01, 0b00, 0b110);
1807
1808 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110);
1809
1810 #undef INSN
1811
1812 #define INSN(NAME, op31, type, rmode, opcode) \
1813 void NAME(FloatRegister Vd, Register Rn) { \
1814 float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \
1815 }
1816
1817 INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
1818 INSN(fmovd, 0b100, 0b01, 0b00, 0b111);
1819
1820 INSN(scvtfws, 0b000, 0b00, 0b00, 0b010);
1821 INSN(scvtfs, 0b100, 0b00, 0b00, 0b010);
1822 INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010);
1823 INSN(scvtfd, 0b100, 0b01, 0b00, 0b010);
1824
1825 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
1826
1827 #undef INSN
1828
1829 // Floating-point compare
1830 void float_compare(unsigned op31, unsigned type,
1831 unsigned op, unsigned op2,
1832 FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
1833 starti;
1834 f(op31, 31, 29);
1835 f(0b11110, 28, 24);
1836 f(type, 23, 22), f(1, 21);
1837 f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
1838 rf(Vn, 5), rf(Vm, 16);
1839 }
1840
1841
1842 #define INSN(NAME, op31, type, op, op2) \
1843 void NAME(FloatRegister Vn, FloatRegister Vm) { \
1844 float_compare(op31, type, op, op2, Vn, Vm); \
1845 }
1846
1847 #define INSN1(NAME, op31, type, op, op2) \
1848 void NAME(FloatRegister Vn, double d) { \
1849 assert_cond(d == 0.0); \
1850 float_compare(op31, type, op, op2, Vn); \
1851 }
1852
1853 INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
1854 INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
1855 // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
1856 // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
1857
1858 INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000);
1859 INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000);
1860 // INSN(fcmped, 0b000, 0b01, 0b00, 0b10000);
1861 // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
1862
1863 #undef INSN
1864 #undef INSN1
1865
1866 // Floating-point Move (immediate)
1867 private:
1868 unsigned pack(double value);
1869
1870 void fmov_imm(FloatRegister Vn, double value, unsigned size) {
1871 starti;
1872 f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
1873 f(pack(value), 20, 13), f(0b10000000, 12, 5);
1874 rf(Vn, 0);
1875 }
1876
1877 public:
1878
1879 void fmovs(FloatRegister Vn, double value) {
1880 if (value)
1881 fmov_imm(Vn, value, 0b00);
1882 else
1883 fmovs(Vn, zr);
1884 }
1885 void fmovd(FloatRegister Vn, double value) {
1886 if (value)
1887 fmov_imm(Vn, value, 0b01);
1888 else
1889 fmovd(Vn, zr);
1890 }
1891
1892 /* SIMD extensions
1893 *
1894 * We just use FloatRegister in the following. They are exactly the same
1895 * as SIMD registers.
1896 */
1897 public:
1898
1899 enum SIMD_Arrangement {
1900 T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
1901 };
1902
1903 enum SIMD_RegVariant {
1904 B, H, S, D, Q
1905 };
1906
1907 #define INSN(NAME, op) \
1908 void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \
1909 ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
1910 } \
1911
1912 INSN(ldr, 1);
1913 INSN(str, 0);
1914
1915 #undef INSN
1916
1917 private:
1918
1919 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
1920 starti;
1921 f(0,31), f((int)T & 1, 30);
1922 f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
1923 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
1924 }
1925 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
1926 int imm, int op1, int op2) {
1927 starti;
1928 f(0,31), f((int)T & 1, 30);
1929 f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
1930 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
1931 }
1932 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
1933 Register Xm, int op1, int op2) {
1934 starti;
1935 f(0,31), f((int)T & 1, 30);
1936 f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
1937 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
1938 }
1939
1940 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2) {
1941 switch (a.getMode()) {
1942 case Address::base_plus_offset:
1943 guarantee(a.offset() == 0, "no offset allowed here");
1944 ld_st(Vt, T, a.base(), op1, op2);
1945 break;
1946 case Address::post:
1947 ld_st(Vt, T, a.base(), a.offset(), op1, op2);
1948 break;
1949 case Address::base_plus_offset_reg:
1950 ld_st(Vt, T, a.base(), a.index(), op1, op2);
1951 break;
1952 default:
1953 ShouldNotReachHere();
1954 }
1955 }
1956
1957 public:
1958
1959 #define INSN1(NAME, op1, op2) \
1960 void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \
1961 ld_st(Vt, T, a, op1, op2); \
1962 }
1963
1964 #define INSN2(NAME, op1, op2) \
1965 void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
1966 assert(Vt->successor() == Vt2, "Registers must be ordered"); \
1967 ld_st(Vt, T, a, op1, op2); \
1968 }
1969
1970 #define INSN3(NAME, op1, op2) \
1971 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
1972 SIMD_Arrangement T, const Address &a) { \
1973 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \
1974 "Registers must be ordered"); \
1975 ld_st(Vt, T, a, op1, op2); \
1976 }
1977
1978 #define INSN4(NAME, op1, op2) \
1979 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
1980 FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \
1981 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \
1982 Vt3->successor() == Vt4, "Registers must be ordered"); \
1983 ld_st(Vt, T, a, op1, op2); \
1984 }
1985
1986 INSN1(ld1, 0b001100010, 0b0111);
1987 INSN2(ld1, 0b001100010, 0b1010);
1988 INSN3(ld1, 0b001100010, 0b0110);
1989 INSN4(ld1, 0b001100010, 0b0010);
1990
1991 INSN2(ld2, 0b001100010, 0b1000);
1992 INSN3(ld3, 0b001100010, 0b0100);
1993 INSN4(ld4, 0b001100010, 0b0000);
1994
1995 INSN1(st1, 0b001100000, 0b0111);
1996 INSN2(st1, 0b001100000, 0b1010);
1997 INSN3(st1, 0b001100000, 0b0110);
1998 INSN4(st1, 0b001100000, 0b0010);
1999
2000 INSN2(st2, 0b001100000, 0b1000);
2001 INSN3(st3, 0b001100000, 0b0100);
2002 INSN4(st4, 0b001100000, 0b0000);
2003
2004 INSN1(ld1r, 0b001101010, 0b1100);
2005 INSN2(ld2r, 0b001101011, 0b1100);
2006 INSN3(ld3r, 0b001101010, 0b1110);
2007 INSN4(ld4r, 0b001101011, 0b1110);
2008
2009 #undef INSN1
2010 #undef INSN2
2011 #undef INSN3
2012 #undef INSN4
2013
2014 #define INSN(NAME, opc) \
2015 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2016 starti; \
2017 assert(T == T8B || T == T16B, "must be T8B or T16B"); \
2018 f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \
2019 rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2020 }
2021
2022 INSN(eor, 0b101110001);
2023 INSN(orr, 0b001110101);
2024 INSN(andr, 0b001110001);
2025 INSN(bic, 0b001110011);
2026 INSN(bif, 0b101110111);
2027 INSN(bit, 0b101110101);
2028 INSN(bsl, 0b101110011);
2029 INSN(orn, 0b001110111);
2030
2031 #undef INSN
2032
2033 #define INSN(NAME, opc, opc2) \
2034 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2035 starti; \
2036 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2037 f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \
2038 rf(Vn, 5), rf(Vd, 0); \
2039 }
2040
2041 INSN(addv, 0, 0b100001);
2042 INSN(subv, 1, 0b100001);
2043 INSN(mulv, 0, 0b100111);
2044 INSN(sshl, 0, 0b010001);
2045 INSN(ushl, 1, 0b010001);
2046
2047 #undef INSN
2048
2049 #define INSN(NAME, opc, opc2) \
2050 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2051 starti; \
2052 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2053 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
2054 rf(Vn, 5), rf(Vd, 0); \
2055 }
2056
2057 INSN(absr, 0, 0b100000101110);
2058 INSN(negr, 1, 0b100000101110);
2059 INSN(notr, 1, 0b100000010110);
2060 INSN(addv, 0, 0b110001101110);
2061 INSN(cls, 0, 0b100000010010);
2062 INSN(clz, 1, 0b100000010010);
2063 INSN(cnt, 0, 0b100000010110);
2064
2065 #undef INSN
2066
2067 #define INSN(NAME, op0, cmode0) \
2068 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \
2069 unsigned cmode = cmode0; \
2070 unsigned op = op0; \
2071 starti; \
2072 assert(lsl == 0 || \
2073 ((T == T4H || T == T8H) && lsl == 8) || \
2074 ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \
2075 cmode |= lsl >> 2; \
2076 if (T == T4H || T == T8H) cmode |= 0b1000; \
2077 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
2078 assert(op == 0 && cmode0 == 0, "must be MOVI"); \
2079 cmode = 0b1110; \
2080 if (T == T1D || T == T2D) op = 1; \
2081 } \
2082 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \
2083 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
2084 rf(Vd, 0); \
2085 }
2086
2087 INSN(movi, 0, 0);
2088 INSN(orri, 0, 1);
2089 INSN(mvni, 1, 0);
2090 INSN(bici, 1, 1);
2091
2092 #undef INSN
2093
2094 #define INSN(NAME, op1, op2, op3) \
2095 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2096 starti; \
2097 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2098 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \
2099 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2100 }
2101
2102 INSN(fadd, 0, 0, 0b110101);
2103 INSN(fdiv, 1, 0, 0b111111);
2104 INSN(fmul, 1, 0, 0b110111);
2105 INSN(fsub, 0, 1, 0b110101);
2106
2107 #undef INSN
2108
2109 #define INSN(NAME, opc) \
2110 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2111 starti; \
2112 assert(T == T4S, "arrangement must be T4S"); \
2113 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2114 }
2115
2116 INSN(sha1c, 0b000000);
2117 INSN(sha1m, 0b001000);
2118 INSN(sha1p, 0b000100);
2119 INSN(sha1su0, 0b001100);
2120 INSN(sha256h2, 0b010100);
2121 INSN(sha256h, 0b010000);
2122 INSN(sha256su1, 0b011000);
2123
2124 #undef INSN
2125
2126 #define INSN(NAME, opc) \
2127 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2128 starti; \
2129 assert(T == T4S, "arrangement must be T4S"); \
2130 f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2131 }
2132
2133 INSN(sha1h, 0b000010);
2134 INSN(sha1su1, 0b000110);
2135 INSN(sha256su0, 0b001010);
2136
2137 #undef INSN
2138
2139 #define INSN(NAME, opc) \
2140 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2141 starti; \
2142 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2143 }
2144
2145 INSN(aese, 0b0100111000101000010010);
2146 INSN(aesd, 0b0100111000101000010110);
2147 INSN(aesmc, 0b0100111000101000011010);
2148 INSN(aesimc, 0b0100111000101000011110);
2149
2150 #undef INSN
2151
2152 void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
2153 starti;
2154 assert(T != Q, "invalid register variant");
2155 f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
2156 f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2157 }
2158
2159 void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
2160 starti;
2161 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
2162 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10);
2163 rf(Vn, 5), rf(Rd, 0);
2164 }
2165
2166 #define INSN(NAME, opc, opc2) \
2167 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \
2168 starti; \
2169 /* The encodings for the immh:immb fields (bits 22:16) are \
2170 * 0001 xxx 8B/16B, shift = xxx \
2171 * 001x xxx 4H/8H, shift = xxxx \
2172 * 01xx xxx 2S/4S, shift = xxxxx \
2173 * 1xxx xxx 1D/2D, shift = xxxxxx (1D is RESERVED) \
2174 */ \
2175 assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \
2176 f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \
2177 f((1 << ((T>>1)+3))|shift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2178 }
2179
2180 INSN(shl, 0, 0b010101);
2181 INSN(sshr, 0, 0b000001);
2182 INSN(ushr, 1, 0b000001);
2183
2184 #undef INSN
2185
2186 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2187 starti;
2188 /* The encodings for the immh:immb fields (bits 22:16) are
2189 * 0001 xxx 8H, 8B/16b shift = xxx
2190 * 001x xxx 4S, 4H/8H shift = xxxx
2191 * 01xx xxx 2D, 2S/4S shift = xxxxx
2192 * 1xxx xxx RESERVED
2193 */
2194 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2195 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2196 f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
2197 f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2198 }
2199 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2200 ushll(Vd, Ta, Vn, Tb, shift);
2201 }
2202
2203 void uzp1(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T, int op = 0){
2204 starti;
2205 f(0, 31), f((T & 0x1), 30), f(0b001110, 29, 24), f((T >> 1), 23, 22), f(0, 21);
2206 rf(Vm, 16), f(0, 15), f(op, 14), f(0b0110, 13, 10), rf(Vn, 5), rf(Vd, 0);
2207 }
2208 void uzp2(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T){
2209 uzp1(Vd, Vn, Vm, T, 1);
2210 }
2211
2212 // Move from general purpose register
2213 // mov Vd.T[index], Rn
2214 void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
2215 starti;
2216 f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2217 f(0b000111, 15, 10), rf(Xn, 5), rf(Vd, 0);
2218 }
2219
2220 // Move to general purpose register
2221 // mov Rd, Vn.T[index]
2222 void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
2223 starti;
2224 f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
2225 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2226 f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
2227 }
2228
2229 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2230 starti;
2231 assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
2232 (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
2233 int size = (Ta == T1Q) ? 0b11 : 0b00;
2234 f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
2235 f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
2236 }
2237 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2238 assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
2239 pmull(Vd, Ta, Vn, Vm, Tb);
2240 }
2241
2242 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2243 starti;
2244 int size_b = (int)Tb >> 1;
2245 int size_a = (int)Ta >> 1;
2246 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
2247 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
2248 f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
2249 }
2250
2251 void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
2252 {
2253 starti;
2254 assert(T != T1D, "reserved encoding");
2255 f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2256 f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), rf(Xs, 5), rf(Vd, 0);
2257 }
2258
2259 void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
2260 {
2261 starti;
2262 assert(T != T1D, "reserved encoding");
2263 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2264 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2265 f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2266 }
2267
2268 // CRC32 instructions
2269 #define INSN(NAME, c, sf, sz) \
2270 void NAME(Register Rd, Register Rn, Register Rm) { \
2271 starti; \
2272 f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12); \
2273 f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
2274 }
2275
2276 INSN(crc32b, 0, 0, 0b00);
2277 INSN(crc32h, 0, 0, 0b01);
2278 INSN(crc32w, 0, 0, 0b10);
2279 INSN(crc32x, 0, 1, 0b11);
2280 INSN(crc32cb, 1, 0, 0b00);
2281 INSN(crc32ch, 1, 0, 0b01);
2282 INSN(crc32cw, 1, 0, 0b10);
2283 INSN(crc32cx, 1, 1, 0b11);
2284
2285 #undef INSN
2286
2287 // Table vector lookup
2288 #define INSN(NAME, op) \
2289 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \
2290 starti; \
2291 assert(T == T8B || T == T16B, "invalid arrangement"); \
2292 assert(0 < registers && registers <= 4, "invalid number of registers"); \
2293 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \
2294 f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2295 }
2296
2297 INSN(tbl, 0);
2298 INSN(tbx, 1);
2299
2300 #undef INSN
2301
2302 // AdvSIMD two-reg misc
2303 #define INSN(NAME, U, opcode) \
2304 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2305 starti; \
2306 assert((ASSERTION), MSG); \
2307 f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24); \
2308 f((int)(T >> 1), 23, 22), f(0b10000, 21, 17), f(opcode, 16, 12); \
2309 f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2310 }
2311
2312 #define MSG "invalid arrangement"
2313
2314 #define ASSERTION (T == T2S || T == T4S || T == T2D)
2315 INSN(fsqrt, 1, 0b11111);
2316 INSN(fabs, 0, 0b01111);
2317 INSN(fneg, 1, 0b01111);
2318 #undef ASSERTION
2319
2320 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
2321 INSN(rev64, 0, 0b00000);
2322 #undef ASSERTION
2323
2324 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
2325 INSN(rev32, 1, 0b00000);
2326 private:
2327 INSN(_rbit, 1, 0b00101);
2328 public:
2329
2330 #undef ASSERTION
2331
2332 #define ASSERTION (T == T8B || T == T16B)
2333 INSN(rev16, 0, 0b00001);
2334 // RBIT only allows T8B and T16B but encodes them oddly. Argh...
2335 void rbit(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
2336 assert((ASSERTION), MSG);
2337 _rbit(Vd, SIMD_Arrangement(T & 1 | 0b010), Vn);
2338 }
2339 #undef ASSERTION
2340
2341 #undef MSG
2342
2343 #undef INSN
2344
2345 void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
2346 {
2347 starti;
2348 assert(T == T8B || T == T16B, "invalid arrangement");
2349 assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
2350 f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
2351 rf(Vm, 16), f(0, 15), f(index, 14, 11);
2352 f(0, 10), rf(Vn, 5), rf(Vd, 0);
2353 }
2354
2355 /* Simulator extensions to the ISA
2356
2357 haltsim
2358
2359 takes no arguments, causes the sim to enter a debug break and then
2360 return from the simulator run() call with STATUS_HALT? The linking
2361 code will call fatal() when it sees STATUS_HALT.
2362
2363 blrt Xn, Wm
2364 blrt Xn, #gpargs, #fpargs, #type
2365 Xn holds the 64 bit x86 branch_address
2366 call format is encoded either as immediate data in the call
2367 or in register Wm. In the latter case
2368 Wm[13..6] = #gpargs,
2369 Wm[5..2] = #fpargs,
2370 Wm[1,0] = #type
2371
2372 calls the x86 code address 'branch_address' supplied in Xn passing
2373 arguments taken from the general and floating point registers according
2374 to the supplied counts 'gpargs' and 'fpargs'. may return a result in r0
2375 or v0 according to the the return type #type' where
2376
2377 address branch_address;
2378 uimm4 gpargs;
2379 uimm4 fpargs;
2380 enum ReturnType type;
2381
2382 enum ReturnType
2383 {
2384 void_ret = 0,
2385 int_ret = 1,
2386 long_ret = 1,
2387 obj_ret = 1, // i.e. same as long
2388 float_ret = 2,
2389 double_ret = 3
2390 }
2391
2392 notify
2393
2394 notifies the simulator of a transfer of control. instr[14:0]
2395 identifies the type of change of control.
2396
2397 0 ==> initial entry to a method.
2398
2399 1 ==> return into a method from a submethod call.
2400
2401 2 ==> exit out of Java method code.
2402
2403 3 ==> start execution for a new bytecode.
2404
2405 in cases 1 and 2 the simulator is expected to use a JVM callback to
2406 identify the name of the specific method being executed. in case 4
2407 the simulator is expected to use a JVM callback to identify the
2408 bytecode index.
2409
2410 Instruction encodings
2411 ---------------------
2412
2413 These are encoded in the space with instr[28:25] = 00 which is
2414 unallocated. Encodings are
2415
2416 10987654321098765432109876543210
2417 PSEUDO_HALT = 0x11100000000000000000000000000000
2418 PSEUDO_BLRT = 0x11000000000000000_______________
2419 PSEUDO_BLRTR = 0x1100000000000000100000__________
2420 PSEUDO_NOTIFY = 0x10100000000000000_______________
2421
2422 instr[31,29] = op1 : 111 ==> HALT, 110 ==> BLRT/BLRTR, 101 ==> NOTIFY
2423
2424 for BLRT
2425 instr[14,11] = #gpargs, instr[10,7] = #fpargs
2426 instr[6,5] = #type, instr[4,0] = Rn
2427 for BLRTR
2428 instr[9,5] = Rm, instr[4,0] = Rn
2429 for NOTIFY
2430 instr[14:0] = type : 0 ==> entry, 1 ==> reentry, 2 ==> exit, 3 ==> bcstart
2431 */
2432
2433 enum NotifyType { method_entry, method_reentry, method_exit, bytecode_start };
2434
2435 virtual void notify(int type) {
2436 if (UseBuiltinSim) {
2437 starti;
2438 // 109
2439 f(0b101, 31, 29);
2440 // 87654321098765
2441 f(0b00000000000000, 28, 15);
2442 f(type, 14, 0);
2443 }
2444 }
2445
2446 void blrt(Register Rn, int gpargs, int fpargs, int type) {
2447 if (UseBuiltinSim) {
2448 starti;
2449 f(0b110, 31 ,29);
2450 f(0b00, 28, 25);
2451 // 4321098765
2452 f(0b0000000000, 24, 15);
2453 f(gpargs, 14, 11);
2454 f(fpargs, 10, 7);
2455 f(type, 6, 5);
2456 rf(Rn, 0);
2457 } else {
2458 blr(Rn);
2459 }
2460 }
2461
2462 void blrt(Register Rn, Register Rm) {
2463 if (UseBuiltinSim) {
2464 starti;
2465 f(0b110, 31 ,29);
2466 f(0b00, 28, 25);
2467 // 4321098765
2468 f(0b0000000001, 24, 15);
2469 // 43210
2470 f(0b00000, 14, 10);
2471 rf(Rm, 5);
2472 rf(Rn, 0);
2473 } else {
2474 blr(Rn);
2475 }
2476 }
2477
2478 void haltsim() {
2479 starti;
2480 f(0b111, 31 ,29);
2481 f(0b00, 28, 27);
2482 // 654321098765432109876543210
2483 f(0b000000000000000000000000000, 26, 0);
2484 }
2485
2486 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2487 }
2488
2489 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2490 Register tmp,
2491 int offset) {
2492 ShouldNotCallThis();
2493 return RegisterOrConstant();
2494 }
2495
2496 // Stack overflow checking
2497 virtual void bang_stack_with_offset(int offset);
2498
2499 static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
2500 static bool operand_valid_for_add_sub_immediate(long imm);
2501 static bool operand_valid_for_float_immediate(double imm);
2502
2503 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
2504 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
2505 };
2506
2507 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
2508 Assembler::Membar_mask_bits b) {
2509 return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
2510 }
2511
2512 Instruction_aarch64::~Instruction_aarch64() {
2513 assem->emit();
2514 }
2515
2516 #undef starti
2517
2518 // Invert a condition
2519 inline const Assembler::Condition operator~(const Assembler::Condition cond) {
2520 return Assembler::Condition(int(cond) ^ 1);
2521 }
2522
2523 class BiasedLockingCounters;
2524
2525 extern "C" void das(uint64_t start, int len);
2526
2527 #endif // CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP