1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
28
29 #include "asm/register.hpp"
30
31 // definitions of various symbolic names for machine registers
32
33 // First intercalls between C and Java which use 8 general registers
34 // and 8 floating registers
35
36 // we also have to copy between x86 and ARM registers but that's a
37 // secondary complication -- not all code employing C call convention
38 // executes as x86 code though -- we generate some of it
39
40 class Argument VALUE_OBJ_CLASS_SPEC {
41 public:
42 enum {
43 n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
44 n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... )
45
46 n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
47 n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ...
48 };
49 };
50
51 REGISTER_DECLARATION(Register, c_rarg0, r0);
52 REGISTER_DECLARATION(Register, c_rarg1, r1);
53 REGISTER_DECLARATION(Register, c_rarg2, r2);
54 REGISTER_DECLARATION(Register, c_rarg3, r3);
55 REGISTER_DECLARATION(Register, c_rarg4, r4);
56 REGISTER_DECLARATION(Register, c_rarg5, r5);
57 REGISTER_DECLARATION(Register, c_rarg6, r6);
58 REGISTER_DECLARATION(Register, c_rarg7, r7);
59
60 REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
61 REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
62 REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
63 REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
64 REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
65 REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
66 REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
67 REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
68
69 // Symbolically name the register arguments used by the Java calling convention.
70 // We have control over the convention for java so we can do what we please.
71 // What pleases us is to offset the java calling convention so that when
72 // we call a suitable jni method the arguments are lined up and we don't
73 // have to do much shuffling. A suitable jni method is non-static and a
74 // small number of arguments
75 //
76 // |--------------------------------------------------------------------|
77 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 |
78 // |--------------------------------------------------------------------|
79 // | r0 r1 r2 r3 r4 r5 r6 r7 |
80 // |--------------------------------------------------------------------|
81 // | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 |
82 // |--------------------------------------------------------------------|
83
84
85 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
86 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
87 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
88 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
89 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
90 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
91 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
92 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
93
94 // Java floating args are passed as per C
95
96 REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
97 REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
98 REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
99 REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
100 REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
101 REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
102 REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
103 REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
104
105 // registers used to hold VM data either temporarily within a method
106 // or across method calls
107
108 // volatile (caller-save) registers
109
110 // r8 is used for indirect result location return
111 // we use it and r9 as scratch registers
112 REGISTER_DECLARATION(Register, rscratch1, r8);
113 REGISTER_DECLARATION(Register, rscratch2, r9);
114
115 // current method -- must be in a call-clobbered register
116 REGISTER_DECLARATION(Register, rmethod, r12);
117
118 // non-volatile (callee-save) registers are r16-29
119 // of which the following are dedicated global state
120
121 // link register
122 REGISTER_DECLARATION(Register, lr, r30);
123 // frame pointer
124 REGISTER_DECLARATION(Register, rfp, r29);
125 // current thread
126 REGISTER_DECLARATION(Register, rthread, r28);
127 // base of heap
128 REGISTER_DECLARATION(Register, rheapbase, r27);
129 // constant pool cache
130 REGISTER_DECLARATION(Register, rcpool, r26);
131 // monitors allocated on stack
132 REGISTER_DECLARATION(Register, rmonitors, r25);
133 // locals on stack
134 REGISTER_DECLARATION(Register, rlocals, r24);
135 // bytecode pointer
136 REGISTER_DECLARATION(Register, rbcp, r22);
137 // Dispatch table base
138 REGISTER_DECLARATION(Register, rdispatch, r21);
139 // Java stack pointer
140 REGISTER_DECLARATION(Register, esp, r20);
141
142 // TODO : x86 uses rbp to save SP in method handle code
143 // we may need to do the same with fp
144 // JSR 292 fixed register usages:
145 //REGISTER_DECLARATION(Register, r_mh_SP_save, r29);
146
147 #define assert_cond(ARG1) assert(ARG1, #ARG1)
148
149 namespace asm_util {
150 uint32_t encode_logical_immediate(bool is32, uint64_t imm);
151 };
152
153 using namespace asm_util;
154
155
156 class Assembler;
157
158 class Instruction_aarch64 {
159 unsigned insn;
160 #ifdef ASSERT
161 unsigned bits;
162 #endif
163 Assembler *assem;
164
165 public:
166
167 Instruction_aarch64(class Assembler *as) {
168 #ifdef ASSERT
169 bits = 0;
170 #endif
171 insn = 0;
172 assem = as;
173 }
174
175 inline ~Instruction_aarch64();
176
177 unsigned &get_insn() { return insn; }
178 #ifdef ASSERT
179 unsigned &get_bits() { return bits; }
180 #endif
181
182 static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
183 union {
184 unsigned u;
185 int n;
186 };
187
188 u = val << (31 - hi);
189 n = n >> (31 - hi + lo);
190 return n;
191 }
192
193 static inline uint32_t extract(uint32_t val, int msb, int lsb) {
194 int nbits = msb - lsb + 1;
195 assert_cond(msb >= lsb);
196 uint32_t mask = (1U << nbits) - 1;
197 uint32_t result = val >> lsb;
198 result &= mask;
199 return result;
200 }
201
202 static inline int32_t sextract(uint32_t val, int msb, int lsb) {
203 uint32_t uval = extract(val, msb, lsb);
204 return extend(uval, msb - lsb);
205 }
206
207 static void patch(address a, int msb, int lsb, unsigned long val) {
208 int nbits = msb - lsb + 1;
209 guarantee(val < (1U << nbits), "Field too big for insn");
210 assert_cond(msb >= lsb);
211 unsigned mask = (1U << nbits) - 1;
212 val <<= lsb;
213 mask <<= lsb;
214 unsigned target = *(unsigned *)a;
215 target &= ~mask;
216 target |= val;
217 *(unsigned *)a = target;
218 }
219
220 static void spatch(address a, int msb, int lsb, long val) {
221 int nbits = msb - lsb + 1;
222 long chk = val >> (nbits - 1);
223 guarantee (chk == -1 || chk == 0, "Field too big for insn");
224 unsigned uval = val;
225 unsigned mask = (1U << nbits) - 1;
226 uval &= mask;
227 uval <<= lsb;
228 mask <<= lsb;
229 unsigned target = *(unsigned *)a;
230 target &= ~mask;
231 target |= uval;
232 *(unsigned *)a = target;
233 }
234
235 #define aarch64_NOP 0xd503201f
236 static void patch_movk(address a, int pos, int msb, int lsb,
237 unsigned long val, unsigned shift) {
238 address real_a = a + pos;
239
240 // Revert NOP to MOVK
241 if (*(uint32_t*)real_a == aarch64_NOP) {
242 uint32_t patch_val = (0b111100101<<23);
243
244 // Patch shift number.
245 patch_val |= ((shift/16)<<21);
246 // Patch dest register.
247 patch_val |= extract(*(uint32_t *)a, 4, 0);
248
249 *(uint32_t*)real_a = patch_val;
250 }
251
252 patch(real_a, msb, lsb, (val>>shift) & 0xffff);
253 }
254
255 void f(unsigned val, int msb, int lsb) {
256 int nbits = msb - lsb + 1;
257 guarantee(val < (1U << nbits), "Field too big for insn");
258 assert_cond(msb >= lsb);
259 unsigned mask = (1U << nbits) - 1;
260 val <<= lsb;
261 mask <<= lsb;
262 insn |= val;
263 assert_cond((bits & mask) == 0);
264 #ifdef ASSERT
265 bits |= mask;
266 #endif
267 }
268
269 void f(unsigned val, int bit) {
270 f(val, bit, bit);
271 }
272
273 void sf(long val, int msb, int lsb) {
274 int nbits = msb - lsb + 1;
275 long chk = val >> (nbits - 1);
276 guarantee (chk == -1 || chk == 0, "Field too big for insn");
277 unsigned uval = val;
278 unsigned mask = (1U << nbits) - 1;
279 uval &= mask;
280 f(uval, lsb + nbits - 1, lsb);
281 }
282
283 void rf(Register r, int lsb) {
284 f(r->encoding_nocheck(), lsb + 4, lsb);
285 }
286
287 // reg|ZR
288 void zrf(Register r, int lsb) {
289 f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
290 }
291
292 // reg|SP
293 void srf(Register r, int lsb) {
294 f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
295 }
296
297 void rf(FloatRegister r, int lsb) {
298 f(r->encoding_nocheck(), lsb + 4, lsb);
299 }
300
301 unsigned get(int msb = 31, int lsb = 0) {
302 int nbits = msb - lsb + 1;
303 unsigned mask = ((1U << nbits) - 1) << lsb;
304 assert_cond(bits & mask == mask);
305 return (insn & mask) >> lsb;
306 }
307
308 void fixed(unsigned value, unsigned mask) {
309 assert_cond ((mask & bits) == 0);
310 #ifdef ASSERT
311 bits |= mask;
312 #endif
313 insn |= value;
314 }
315 };
316
317 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
318
319 class PrePost {
320 int _offset;
321 Register _r;
322 public:
323 PrePost(Register reg, int o) : _r(reg), _offset(o) { }
324 int offset() { return _offset; }
325 Register reg() { return _r; }
326 };
327
328 class Pre : public PrePost {
329 public:
330 Pre(Register reg, int o) : PrePost(reg, o) { }
331 };
332 class Post : public PrePost {
333 public:
334 Post(Register reg, int o) : PrePost(reg, o) { }
335 };
336
337 namespace ext
338 {
339 enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
340 };
341
342 // abs methods which cannot overflow and so are well-defined across
343 // the entire domain of integer types.
344 static inline unsigned int uabs(unsigned int n) {
345 union {
346 unsigned int result;
347 int value;
348 };
349 result = n;
350 if (value < 0) result = -result;
351 return result;
352 }
353 static inline unsigned long uabs(unsigned long n) {
354 union {
355 unsigned long result;
356 long value;
357 };
358 result = n;
359 if (value < 0) result = -result;
360 return result;
361 }
362 static inline unsigned long uabs(long n) { return uabs((unsigned long)n); }
363 static inline unsigned long uabs(int n) { return uabs((unsigned int)n); }
364
365 // Addressing modes
366 class Address VALUE_OBJ_CLASS_SPEC {
367 public:
368
369 enum mode { no_mode, base_plus_offset, pre, post, pcrel,
370 base_plus_offset_reg, literal };
371
372 // Shift and extend for base reg + reg offset addressing
373 class extend {
374 int _option, _shift;
375 ext::operation _op;
376 public:
377 extend() { }
378 extend(int s, int o, ext::operation op) : _shift(s), _option(o), _op(op) { }
379 int option() const{ return _option; }
380 int shift() const { return _shift; }
381 ext::operation op() const { return _op; }
382 };
383 class uxtw : public extend {
384 public:
385 uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
386 };
387 class lsl : public extend {
388 public:
389 lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
390 };
391 class sxtw : public extend {
392 public:
393 sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
394 };
395 class sxtx : public extend {
396 public:
397 sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
398 };
399
400 private:
401 Register _base;
402 Register _index;
403 long _offset;
404 enum mode _mode;
405 extend _ext;
406
407 RelocationHolder _rspec;
408
409 // Typically we use AddressLiterals we want to use their rval
410 // However in some situations we want the lval (effect address) of
411 // the item. We provide a special factory for making those lvals.
412 bool _is_lval;
413
414 // If the target is far we'll need to load the ea of this to a
415 // register to reach it. Otherwise if near we can do PC-relative
416 // addressing.
417 address _target;
418
419 public:
420 Address()
421 : _mode(no_mode) { }
422 Address(Register r)
423 : _mode(base_plus_offset), _base(r), _offset(0), _index(noreg), _target(0) { }
424 Address(Register r, int o)
425 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
426 Address(Register r, long o)
427 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
428 Address(Register r, unsigned long o)
429 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
430 #ifdef ASSERT
431 Address(Register r, ByteSize disp)
432 : _mode(base_plus_offset), _base(r), _offset(in_bytes(disp)),
433 _index(noreg), _target(0) { }
434 #endif
435 Address(Register r, Register r1, extend ext = lsl())
436 : _mode(base_plus_offset_reg), _base(r), _index(r1),
437 _ext(ext), _offset(0), _target(0) { }
438 Address(Pre p)
439 : _mode(pre), _base(p.reg()), _offset(p.offset()) { }
440 Address(Post p)
441 : _mode(post), _base(p.reg()), _offset(p.offset()), _target(0) { }
442 Address(address target, RelocationHolder const& rspec)
443 : _mode(literal),
444 _rspec(rspec),
445 _is_lval(false),
446 _target(target) { }
447 Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
448 Address(Register base, RegisterOrConstant index, extend ext = lsl())
449 : _base (base),
450 _ext(ext), _offset(0), _target(0) {
451 if (index.is_register()) {
452 _mode = base_plus_offset_reg;
453 _index = index.as_register();
454 } else {
455 guarantee(ext.option() == ext::uxtx, "should be");
456 assert(index.is_constant(), "should be");
457 _mode = base_plus_offset;
458 _offset = index.as_constant() << ext.shift();
459 }
460 }
461
462 Register base() const {
463 guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
464 | _mode == post),
465 "wrong mode");
466 return _base;
467 }
468 long offset() const {
469 return _offset;
470 }
471 Register index() const {
472 return _index;
473 }
474 mode getMode() const {
475 return _mode;
476 }
477 bool uses(Register reg) const { return _base == reg || _index == reg; }
478 address target() const { return _target; }
479 const RelocationHolder& rspec() const { return _rspec; }
480
481 void encode(Instruction_aarch64 *i) const {
482 i->f(0b111, 29, 27);
483 i->srf(_base, 5);
484
485 switch(_mode) {
486 case base_plus_offset:
487 {
488 unsigned size = i->get(31, 30);
489 if (i->get(26, 26) && i->get(23, 23)) {
490 // SIMD Q Type - Size = 128 bits
491 assert(size == 0, "bad size");
492 size = 0b100;
493 }
494 unsigned mask = (1 << size) - 1;
495 if (_offset < 0 || _offset & mask)
496 {
497 i->f(0b00, 25, 24);
498 i->f(0, 21), i->f(0b00, 11, 10);
499 i->sf(_offset, 20, 12);
500 } else {
501 i->f(0b01, 25, 24);
502 i->f(_offset >> size, 21, 10);
503 }
504 }
505 break;
506
507 case base_plus_offset_reg:
508 {
509 i->f(0b00, 25, 24);
510 i->f(1, 21);
511 i->rf(_index, 16);
512 i->f(_ext.option(), 15, 13);
513 unsigned size = i->get(31, 30);
514 if (i->get(26, 26) && i->get(23, 23)) {
515 // SIMD Q Type - Size = 128 bits
516 assert(size == 0, "bad size");
517 size = 0b100;
518 }
519 if (size == 0) // It's a byte
520 i->f(_ext.shift() >= 0, 12);
521 else {
522 if (_ext.shift() > 0)
523 assert(_ext.shift() == (int)size, "bad shift");
524 i->f(_ext.shift() > 0, 12);
525 }
526 i->f(0b10, 11, 10);
527 }
528 break;
529
530 case pre:
531 i->f(0b00, 25, 24);
532 i->f(0, 21), i->f(0b11, 11, 10);
533 i->sf(_offset, 20, 12);
534 break;
535
536 case post:
537 i->f(0b00, 25, 24);
538 i->f(0, 21), i->f(0b01, 11, 10);
539 i->sf(_offset, 20, 12);
540 break;
541
542 default:
543 ShouldNotReachHere();
544 }
545 }
546
547 void encode_pair(Instruction_aarch64 *i) const {
548 switch(_mode) {
549 case base_plus_offset:
550 i->f(0b010, 25, 23);
551 break;
552 case pre:
553 i->f(0b011, 25, 23);
554 break;
555 case post:
556 i->f(0b001, 25, 23);
557 break;
558 default:
559 ShouldNotReachHere();
560 }
561
562 unsigned size; // Operand shift in 32-bit words
563
564 if (i->get(26, 26)) { // float
565 switch(i->get(31, 30)) {
566 case 0b10:
567 size = 2; break;
568 case 0b01:
569 size = 1; break;
570 case 0b00:
571 size = 0; break;
572 default:
573 ShouldNotReachHere();
574 }
575 } else {
576 size = i->get(31, 31);
577 }
578
579 size = 4 << size;
580 guarantee(_offset % size == 0, "bad offset");
581 i->sf(_offset / size, 21, 15);
582 i->srf(_base, 5);
583 }
584
585 void encode_nontemporal_pair(Instruction_aarch64 *i) const {
586 // Only base + offset is allowed
587 i->f(0b000, 25, 23);
588 unsigned size = i->get(31, 31);
589 size = 4 << size;
590 guarantee(_offset % size == 0, "bad offset");
591 i->sf(_offset / size, 21, 15);
592 i->srf(_base, 5);
593 guarantee(_mode == Address::base_plus_offset,
594 "Bad addressing mode for non-temporal op");
595 }
596
597 void lea(MacroAssembler *, Register) const;
598
599 static bool offset_ok_for_immed(long offset, int shift = 0) {
600 unsigned mask = (1 << shift) - 1;
601 if (offset < 0 || offset & mask) {
602 return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset
603 } else {
604 return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset
605 }
606 }
607 };
608
609 // Convience classes
610 class RuntimeAddress: public Address {
611
612 public:
613
614 RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
615
616 };
617
618 class OopAddress: public Address {
619
620 public:
621
622 OopAddress(address target) : Address(target, relocInfo::oop_type){}
623
624 };
625
626 class ExternalAddress: public Address {
627 private:
628 static relocInfo::relocType reloc_for_target(address target) {
629 // Sometimes ExternalAddress is used for values which aren't
630 // exactly addresses, like the card table base.
631 // external_word_type can't be used for values in the first page
632 // so just skip the reloc in that case.
633 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
634 }
635
636 public:
637
638 ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
639
640 };
641
642 class InternalAddress: public Address {
643
644 public:
645
646 InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
647 };
648
649 const int FPUStateSizeInWords = 32 * 2;
650 typedef enum {
651 PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
652 PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
653 PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
654 } prfop;
655
656 class Assembler : public AbstractAssembler {
657
658 #ifndef PRODUCT
659 static const unsigned long asm_bp;
660
661 void emit_long(jint x) {
662 if ((unsigned long)pc() == asm_bp)
663 asm volatile ("nop");
664 AbstractAssembler::emit_int32(x);
665 }
666 #else
667 void emit_long(jint x) {
668 AbstractAssembler::emit_int32(x);
669 }
670 #endif
671
672 public:
673
674 enum { instruction_size = 4 };
675
676 Address adjust(Register base, int offset, bool preIncrement) {
677 if (preIncrement)
678 return Address(Pre(base, offset));
679 else
680 return Address(Post(base, offset));
681 }
682
683 Address pre(Register base, int offset) {
684 return adjust(base, offset, true);
685 }
686
687 Address post (Register base, int offset) {
688 return adjust(base, offset, false);
689 }
690
691 Instruction_aarch64* current;
692
693 void set_current(Instruction_aarch64* i) { current = i; }
694
695 void f(unsigned val, int msb, int lsb) {
696 current->f(val, msb, lsb);
697 }
698 void f(unsigned val, int msb) {
699 current->f(val, msb, msb);
700 }
701 void sf(long val, int msb, int lsb) {
702 current->sf(val, msb, lsb);
703 }
704 void rf(Register reg, int lsb) {
705 current->rf(reg, lsb);
706 }
707 void srf(Register reg, int lsb) {
708 current->srf(reg, lsb);
709 }
710 void zrf(Register reg, int lsb) {
711 current->zrf(reg, lsb);
712 }
713 void rf(FloatRegister reg, int lsb) {
714 current->rf(reg, lsb);
715 }
716 void fixed(unsigned value, unsigned mask) {
717 current->fixed(value, mask);
718 }
719
720 void emit() {
721 emit_long(current->get_insn());
722 assert_cond(current->get_bits() == 0xffffffff);
723 current = NULL;
724 }
725
726 typedef void (Assembler::* uncond_branch_insn)(address dest);
727 typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
728 typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
729 typedef void (Assembler::* prefetch_insn)(address target, prfop);
730
731 void wrap_label(Label &L, uncond_branch_insn insn);
732 void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
733 void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
734 void wrap_label(Label &L, prfop, prefetch_insn insn);
735
736 // PC-rel. addressing
737
738 void adr(Register Rd, address dest);
739 void _adrp(Register Rd, address dest);
740
741 void adr(Register Rd, const Address &dest);
742 void _adrp(Register Rd, const Address &dest);
743
744 void adr(Register Rd, Label &L) {
745 wrap_label(Rd, L, &Assembler::Assembler::adr);
746 }
747 void _adrp(Register Rd, Label &L) {
748 wrap_label(Rd, L, &Assembler::_adrp);
749 }
750
751 void adrp(Register Rd, const Address &dest, unsigned long &offset);
752
753 #undef INSN
754
755 void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
756 int negated_op);
757
758 // Add/subtract (immediate)
759 #define INSN(NAME, decode, negated) \
760 void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \
761 starti; \
762 f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
763 zrf(Rd, 0), srf(Rn, 5); \
764 } \
765 \
766 void NAME(Register Rd, Register Rn, unsigned imm) { \
767 starti; \
768 add_sub_immediate(Rd, Rn, imm, decode, negated); \
769 }
770
771 INSN(addsw, 0b001, 0b011);
772 INSN(subsw, 0b011, 0b001);
773 INSN(adds, 0b101, 0b111);
774 INSN(subs, 0b111, 0b101);
775
776 #undef INSN
777
778 #define INSN(NAME, decode, negated) \
779 void NAME(Register Rd, Register Rn, unsigned imm) { \
780 starti; \
781 add_sub_immediate(Rd, Rn, imm, decode, negated); \
782 }
783
784 INSN(addw, 0b000, 0b010);
785 INSN(subw, 0b010, 0b000);
786 INSN(add, 0b100, 0b110);
787 INSN(sub, 0b110, 0b100);
788
789 #undef INSN
790
791 // Logical (immediate)
792 #define INSN(NAME, decode, is32) \
793 void NAME(Register Rd, Register Rn, uint64_t imm) { \
794 starti; \
795 uint32_t val = encode_logical_immediate(is32, imm); \
796 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
797 srf(Rd, 0), zrf(Rn, 5); \
798 }
799
800 INSN(andw, 0b000, true);
801 INSN(orrw, 0b001, true);
802 INSN(eorw, 0b010, true);
803 INSN(andr, 0b100, false);
804 INSN(orr, 0b101, false);
805 INSN(eor, 0b110, false);
806
807 #undef INSN
808
809 #define INSN(NAME, decode, is32) \
810 void NAME(Register Rd, Register Rn, uint64_t imm) { \
811 starti; \
812 uint32_t val = encode_logical_immediate(is32, imm); \
813 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
814 zrf(Rd, 0), zrf(Rn, 5); \
815 }
816
817 INSN(ands, 0b111, false);
818 INSN(andsw, 0b011, true);
819
820 #undef INSN
821
822 // Move wide (immediate)
823 #define INSN(NAME, opcode) \
824 void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \
825 assert_cond((shift/16)*16 == shift); \
826 starti; \
827 f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \
828 f(imm, 20, 5); \
829 rf(Rd, 0); \
830 }
831
832 INSN(movnw, 0b000);
833 INSN(movzw, 0b010);
834 INSN(movkw, 0b011);
835 INSN(movn, 0b100);
836 INSN(movz, 0b110);
837 INSN(movk, 0b111);
838
839 #undef INSN
840
841 // Bitfield
842 #define INSN(NAME, opcode) \
843 void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \
844 starti; \
845 f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \
846 rf(Rn, 5), rf(Rd, 0); \
847 }
848
849 INSN(sbfmw, 0b0001001100);
850 INSN(bfmw, 0b0011001100);
851 INSN(ubfmw, 0b0101001100);
852 INSN(sbfm, 0b1001001101);
853 INSN(bfm, 0b1011001101);
854 INSN(ubfm, 0b1101001101);
855
856 #undef INSN
857
858 // Extract
859 #define INSN(NAME, opcode) \
860 void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \
861 starti; \
862 f(opcode, 31, 21), f(imms, 15, 10); \
863 rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
864 }
865
866 INSN(extrw, 0b00010011100);
867 INSN(extr, 0b10010011110);
868
869 #undef INSN
870
871 // The maximum range of a branch is fixed for the AArch64
872 // architecture. In debug mode we shrink it in order to test
873 // trampolines, but not so small that branches in the interpreter
874 // are out of range.
875 static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
876
877 static bool reachable_from_branch_at(address branch, address target) {
878 return uabs(target - branch) < branch_range;
879 }
880
881 // Unconditional branch (immediate)
882 #define INSN(NAME, opcode) \
883 void NAME(address dest) { \
884 starti; \
885 long offset = (dest - pc()) >> 2; \
886 DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
887 f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \
888 } \
889 void NAME(Label &L) { \
890 wrap_label(L, &Assembler::NAME); \
891 } \
892 void NAME(const Address &dest);
893
894 INSN(b, 0);
895 INSN(bl, 1);
896
897 #undef INSN
898
899 // Compare & branch (immediate)
900 #define INSN(NAME, opcode) \
901 void NAME(Register Rt, address dest) { \
902 long offset = (dest - pc()) >> 2; \
903 starti; \
904 f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \
905 } \
906 void NAME(Register Rt, Label &L) { \
907 wrap_label(Rt, L, &Assembler::NAME); \
908 }
909
910 INSN(cbzw, 0b00110100);
911 INSN(cbnzw, 0b00110101);
912 INSN(cbz, 0b10110100);
913 INSN(cbnz, 0b10110101);
914
915 #undef INSN
916
917 // Test & branch (immediate)
918 #define INSN(NAME, opcode) \
919 void NAME(Register Rt, int bitpos, address dest) { \
920 long offset = (dest - pc()) >> 2; \
921 int b5 = bitpos >> 5; \
922 bitpos &= 0x1f; \
923 starti; \
924 f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
925 rf(Rt, 0); \
926 } \
927 void NAME(Register Rt, int bitpos, Label &L) { \
928 wrap_label(Rt, bitpos, L, &Assembler::NAME); \
929 }
930
931 INSN(tbz, 0b0110110);
932 INSN(tbnz, 0b0110111);
933
934 #undef INSN
935
936 // Conditional branch (immediate)
937 enum Condition
938 {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
939
940 void br(Condition cond, address dest) {
941 long offset = (dest - pc()) >> 2;
942 starti;
943 f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
944 }
945
946 #define INSN(NAME, cond) \
947 void NAME(address dest) { \
948 br(cond, dest); \
949 }
950
951 INSN(beq, EQ);
952 INSN(bne, NE);
953 INSN(bhs, HS);
954 INSN(bcs, CS);
955 INSN(blo, LO);
956 INSN(bcc, CC);
957 INSN(bmi, MI);
958 INSN(bpl, PL);
959 INSN(bvs, VS);
960 INSN(bvc, VC);
961 INSN(bhi, HI);
962 INSN(bls, LS);
963 INSN(bge, GE);
964 INSN(blt, LT);
965 INSN(bgt, GT);
966 INSN(ble, LE);
967 INSN(bal, AL);
968 INSN(bnv, NV);
969
970 void br(Condition cc, Label &L);
971
972 #undef INSN
973
974 // Exception generation
975 void generate_exception(int opc, int op2, int LL, unsigned imm) {
976 starti;
977 f(0b11010100, 31, 24);
978 f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
979 }
980
981 #define INSN(NAME, opc, op2, LL) \
982 void NAME(unsigned imm) { \
983 generate_exception(opc, op2, LL, imm); \
984 }
985
986 INSN(svc, 0b000, 0, 0b01);
987 INSN(hvc, 0b000, 0, 0b10);
988 INSN(smc, 0b000, 0, 0b11);
989 INSN(brk, 0b001, 0, 0b00);
990 INSN(hlt, 0b010, 0, 0b00);
991 INSN(dpcs1, 0b101, 0, 0b01);
992 INSN(dpcs2, 0b101, 0, 0b10);
993 INSN(dpcs3, 0b101, 0, 0b11);
994
995 #undef INSN
996
997 // System
998 void system(int op0, int op1, int CRn, int CRm, int op2,
999 Register rt = (Register)0b11111)
1000 {
1001 starti;
1002 f(0b11010101000, 31, 21);
1003 f(op0, 20, 19);
1004 f(op1, 18, 16);
1005 f(CRn, 15, 12);
1006 f(CRm, 11, 8);
1007 f(op2, 7, 5);
1008 rf(rt, 0);
1009 }
1010
1011 void hint(int imm) {
1012 system(0b00, 0b011, 0b0010, imm, 0b000);
1013 }
1014
1015 void nop() {
1016 hint(0);
1017 }
1018 // we only provide mrs and msr for the special purpose system
1019 // registers where op1 (instr[20:19]) == 11 and, (currently) only
1020 // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1021
1022 void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1023 starti;
1024 f(0b1101010100011, 31, 19);
1025 f(op1, 18, 16);
1026 f(CRn, 15, 12);
1027 f(CRm, 11, 8);
1028 f(op2, 7, 5);
1029 // writing zr is ok
1030 zrf(rt, 0);
1031 }
1032
1033 void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1034 starti;
1035 f(0b1101010100111, 31, 19);
1036 f(op1, 18, 16);
1037 f(CRn, 15, 12);
1038 f(CRm, 11, 8);
1039 f(op2, 7, 5);
1040 // reading to zr is a mistake
1041 rf(rt, 0);
1042 }
1043
1044 enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1045 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1046
1047 void dsb(barrier imm) {
1048 system(0b00, 0b011, 0b00011, imm, 0b100);
1049 }
1050
1051 void dmb(barrier imm) {
1052 system(0b00, 0b011, 0b00011, imm, 0b101);
1053 }
1054
1055 void isb() {
1056 system(0b00, 0b011, 0b00011, SY, 0b110);
1057 }
1058
1059 void dc(Register Rt) {
1060 system(0b01, 0b011, 0b0111, 0b1011, 0b001, Rt);
1061 }
1062
1063 void ic(Register Rt) {
1064 system(0b01, 0b011, 0b0111, 0b0101, 0b001, Rt);
1065 }
1066
1067 // A more convenient access to dmb for our purposes
1068 enum Membar_mask_bits {
1069 // We can use ISH for a barrier because the ARM ARM says "This
1070 // architecture assumes that all Processing Elements that use the
1071 // same operating system or hypervisor are in the same Inner
1072 // Shareable shareability domain."
1073 StoreStore = ISHST,
1074 LoadStore = ISHLD,
1075 LoadLoad = ISHLD,
1076 StoreLoad = ISH,
1077 AnyAny = ISH
1078 };
1079
1080 void membar(Membar_mask_bits order_constraint) {
1081 dmb(Assembler::barrier(order_constraint));
1082 }
1083
1084 // Unconditional branch (register)
1085 void branch_reg(Register R, int opc) {
1086 starti;
1087 f(0b1101011, 31, 25);
1088 f(opc, 24, 21);
1089 f(0b11111000000, 20, 10);
1090 rf(R, 5);
1091 f(0b00000, 4, 0);
1092 }
1093
1094 #define INSN(NAME, opc) \
1095 void NAME(Register R) { \
1096 branch_reg(R, opc); \
1097 }
1098
1099 INSN(br, 0b0000);
1100 INSN(blr, 0b0001);
1101 INSN(ret, 0b0010);
1102
1103 void ret(void *p); // This forces a compile-time error for ret(0)
1104
1105 #undef INSN
1106
1107 #define INSN(NAME, opc) \
1108 void NAME() { \
1109 branch_reg((Register)0b11111, opc); \
1110 }
1111
1112 INSN(eret, 0b0100);
1113 INSN(drps, 0b0101);
1114
1115 #undef INSN
1116
1117 // Load/store exclusive
1118 enum operand_size { byte, halfword, word, xword };
1119
1120 void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1121 Register Rn, enum operand_size sz, int op, int o0) {
1122 starti;
1123 f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1124 rf(Rs, 16), f(o0, 15), rf(Rt2, 10), rf(Rn, 5), rf(Rt1, 0);
1125 }
1126
1127 #define INSN4(NAME, sz, op, o0) /* Four registers */ \
1128 void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \
1129 guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \
1130 load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \
1131 }
1132
1133 #define INSN3(NAME, sz, op, o0) /* Three registers */ \
1134 void NAME(Register Rs, Register Rt, Register Rn) { \
1135 guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1136 load_store_exclusive(Rs, Rt, (Register)0b11111, Rn, sz, op, o0); \
1137 }
1138
1139 #define INSN2(NAME, sz, op, o0) /* Two registers */ \
1140 void NAME(Register Rt, Register Rn) { \
1141 load_store_exclusive((Register)0b11111, Rt, (Register)0b11111, \
1142 Rn, sz, op, o0); \
1143 }
1144
1145 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
1146 void NAME(Register Rt1, Register Rt2, Register Rn) { \
1147 guarantee(Rt1 != Rt2, "unpredictable instruction"); \
1148 load_store_exclusive((Register)0b11111, Rt1, Rt2, Rn, sz, op, o0); \
1149 }
1150
1151 // bytes
1152 INSN3(stxrb, byte, 0b000, 0);
1153 INSN3(stlxrb, byte, 0b000, 1);
1154 INSN2(ldxrb, byte, 0b010, 0);
1155 INSN2(ldaxrb, byte, 0b010, 1);
1156 INSN2(stlrb, byte, 0b100, 1);
1157 INSN2(ldarb, byte, 0b110, 1);
1158
1159 // halfwords
1160 INSN3(stxrh, halfword, 0b000, 0);
1161 INSN3(stlxrh, halfword, 0b000, 1);
1162 INSN2(ldxrh, halfword, 0b010, 0);
1163 INSN2(ldaxrh, halfword, 0b010, 1);
1164 INSN2(stlrh, halfword, 0b100, 1);
1165 INSN2(ldarh, halfword, 0b110, 1);
1166
1167 // words
1168 INSN3(stxrw, word, 0b000, 0);
1169 INSN3(stlxrw, word, 0b000, 1);
1170 INSN4(stxpw, word, 0b001, 0);
1171 INSN4(stlxpw, word, 0b001, 1);
1172 INSN2(ldxrw, word, 0b010, 0);
1173 INSN2(ldaxrw, word, 0b010, 1);
1174 INSN_FOO(ldxpw, word, 0b011, 0);
1175 INSN_FOO(ldaxpw, word, 0b011, 1);
1176 INSN2(stlrw, word, 0b100, 1);
1177 INSN2(ldarw, word, 0b110, 1);
1178
1179 // xwords
1180 INSN3(stxr, xword, 0b000, 0);
1181 INSN3(stlxr, xword, 0b000, 1);
1182 INSN4(stxp, xword, 0b001, 0);
1183 INSN4(stlxp, xword, 0b001, 1);
1184 INSN2(ldxr, xword, 0b010, 0);
1185 INSN2(ldaxr, xword, 0b010, 1);
1186 INSN_FOO(ldxp, xword, 0b011, 0);
1187 INSN_FOO(ldaxp, xword, 0b011, 1);
1188 INSN2(stlr, xword, 0b100, 1);
1189 INSN2(ldar, xword, 0b110, 1);
1190
1191 #undef INSN2
1192 #undef INSN3
1193 #undef INSN4
1194 #undef INSN_FOO
1195
1196 // Load register (literal)
1197 #define INSN(NAME, opc, V) \
1198 void NAME(Register Rt, address dest) { \
1199 long offset = (dest - pc()) >> 2; \
1200 starti; \
1201 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1202 sf(offset, 23, 5); \
1203 rf(Rt, 0); \
1204 } \
1205 void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \
1206 InstructionMark im(this); \
1207 guarantee(rtype == relocInfo::internal_word_type, \
1208 "only internal_word_type relocs make sense here"); \
1209 code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
1210 NAME(Rt, dest); \
1211 } \
1212 void NAME(Register Rt, Label &L) { \
1213 wrap_label(Rt, L, &Assembler::NAME); \
1214 }
1215
1216 INSN(ldrw, 0b00, 0);
1217 INSN(ldr, 0b01, 0);
1218 INSN(ldrsw, 0b10, 0);
1219
1220 #undef INSN
1221
1222 #define INSN(NAME, opc, V) \
1223 void NAME(FloatRegister Rt, address dest) { \
1224 long offset = (dest - pc()) >> 2; \
1225 starti; \
1226 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1227 sf(offset, 23, 5); \
1228 rf((Register)Rt, 0); \
1229 }
1230
1231 INSN(ldrs, 0b00, 1);
1232 INSN(ldrd, 0b01, 1);
1233 INSN(ldrq, 0b10, 1);
1234
1235 #undef INSN
1236
1237 #define INSN(NAME, opc, V) \
1238 void NAME(address dest, prfop op = PLDL1KEEP) { \
1239 long offset = (dest - pc()) >> 2; \
1240 starti; \
1241 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1242 sf(offset, 23, 5); \
1243 f(op, 4, 0); \
1244 } \
1245 void NAME(Label &L, prfop op = PLDL1KEEP) { \
1246 wrap_label(L, op, &Assembler::NAME); \
1247 }
1248
1249 INSN(prfm, 0b11, 0);
1250
1251 #undef INSN
1252
1253 // Load/store
1254 void ld_st1(int opc, int p1, int V, int L,
1255 Register Rt1, Register Rt2, Address adr, bool no_allocate) {
1256 starti;
1257 f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
1258 zrf(Rt2, 10), zrf(Rt1, 0);
1259 if (no_allocate) {
1260 adr.encode_nontemporal_pair(current);
1261 } else {
1262 adr.encode_pair(current);
1263 }
1264 }
1265
1266 // Load/store register pair (offset)
1267 #define INSN(NAME, size, p1, V, L, no_allocate) \
1268 void NAME(Register Rt1, Register Rt2, Address adr) { \
1269 ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
1270 }
1271
1272 INSN(stpw, 0b00, 0b101, 0, 0, false);
1273 INSN(ldpw, 0b00, 0b101, 0, 1, false);
1274 INSN(ldpsw, 0b01, 0b101, 0, 1, false);
1275 INSN(stp, 0b10, 0b101, 0, 0, false);
1276 INSN(ldp, 0b10, 0b101, 0, 1, false);
1277
1278 // Load/store no-allocate pair (offset)
1279 INSN(stnpw, 0b00, 0b101, 0, 0, true);
1280 INSN(ldnpw, 0b00, 0b101, 0, 1, true);
1281 INSN(stnp, 0b10, 0b101, 0, 0, true);
1282 INSN(ldnp, 0b10, 0b101, 0, 1, true);
1283
1284 #undef INSN
1285
1286 #define INSN(NAME, size, p1, V, L, no_allocate) \
1287 void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \
1288 ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
1289 }
1290
1291 INSN(stps, 0b00, 0b101, 1, 0, false);
1292 INSN(ldps, 0b00, 0b101, 1, 1, false);
1293 INSN(stpd, 0b01, 0b101, 1, 0, false);
1294 INSN(ldpd, 0b01, 0b101, 1, 1, false);
1295 INSN(stpq, 0b10, 0b101, 1, 0, false);
1296 INSN(ldpq, 0b10, 0b101, 1, 1, false);
1297
1298 #undef INSN
1299
1300 // Load/store register (all modes)
1301 void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
1302 starti;
1303
1304 f(V, 26); // general reg?
1305 zrf(Rt, 0);
1306
1307 // Encoding for literal loads is done here (rather than pushed
1308 // down into Address::encode) because the encoding of this
1309 // instruction is too different from all of the other forms to
1310 // make it worth sharing.
1311 if (adr.getMode() == Address::literal) {
1312 assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
1313 assert(op == 0b01, "literal form can only be used with loads");
1314 f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
1315 long offset = (adr.target() - pc()) >> 2;
1316 sf(offset, 23, 5);
1317 code_section()->relocate(pc(), adr.rspec());
1318 return;
1319 }
1320
1321 f(size, 31, 30);
1322 f(op, 23, 22); // str
1323 adr.encode(current);
1324 }
1325
1326 #define INSN(NAME, size, op) \
1327 void NAME(Register Rt, const Address &adr) { \
1328 ld_st2(Rt, adr, size, op); \
1329 } \
1330
1331 INSN(str, 0b11, 0b00);
1332 INSN(strw, 0b10, 0b00);
1333 INSN(strb, 0b00, 0b00);
1334 INSN(strh, 0b01, 0b00);
1335
1336 INSN(ldr, 0b11, 0b01);
1337 INSN(ldrw, 0b10, 0b01);
1338 INSN(ldrb, 0b00, 0b01);
1339 INSN(ldrh, 0b01, 0b01);
1340
1341 INSN(ldrsb, 0b00, 0b10);
1342 INSN(ldrsbw, 0b00, 0b11);
1343 INSN(ldrsh, 0b01, 0b10);
1344 INSN(ldrshw, 0b01, 0b11);
1345 INSN(ldrsw, 0b10, 0b10);
1346
1347 #undef INSN
1348
1349 #define INSN(NAME, size, op) \
1350 void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \
1351 ld_st2((Register)pfop, adr, size, op); \
1352 }
1353
1354 INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
1355 // writeback modes, but the assembler
1356 // doesn't enfore that.
1357
1358 #undef INSN
1359
1360 #define INSN(NAME, size, op) \
1361 void NAME(FloatRegister Rt, const Address &adr) { \
1362 ld_st2((Register)Rt, adr, size, op, 1); \
1363 }
1364
1365 INSN(strd, 0b11, 0b00);
1366 INSN(strs, 0b10, 0b00);
1367 INSN(ldrd, 0b11, 0b01);
1368 INSN(ldrs, 0b10, 0b01);
1369 INSN(strq, 0b00, 0b10);
1370 INSN(ldrq, 0x00, 0b11);
1371
1372 #undef INSN
1373
1374 enum shift_kind { LSL, LSR, ASR, ROR };
1375
1376 void op_shifted_reg(unsigned decode,
1377 enum shift_kind kind, unsigned shift,
1378 unsigned size, unsigned op) {
1379 f(size, 31);
1380 f(op, 30, 29);
1381 f(decode, 28, 24);
1382 f(shift, 15, 10);
1383 f(kind, 23, 22);
1384 }
1385
1386 // Logical (shifted register)
1387 #define INSN(NAME, size, op, N) \
1388 void NAME(Register Rd, Register Rn, Register Rm, \
1389 enum shift_kind kind = LSL, unsigned shift = 0) { \
1390 starti; \
1391 f(N, 21); \
1392 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1393 op_shifted_reg(0b01010, kind, shift, size, op); \
1394 }
1395
1396 INSN(andr, 1, 0b00, 0);
1397 INSN(orr, 1, 0b01, 0);
1398 INSN(eor, 1, 0b10, 0);
1399 INSN(ands, 1, 0b11, 0);
1400 INSN(andw, 0, 0b00, 0);
1401 INSN(orrw, 0, 0b01, 0);
1402 INSN(eorw, 0, 0b10, 0);
1403 INSN(andsw, 0, 0b11, 0);
1404
1405 INSN(bic, 1, 0b00, 1);
1406 INSN(orn, 1, 0b01, 1);
1407 INSN(eon, 1, 0b10, 1);
1408 INSN(bics, 1, 0b11, 1);
1409 INSN(bicw, 0, 0b00, 1);
1410 INSN(ornw, 0, 0b01, 1);
1411 INSN(eonw, 0, 0b10, 1);
1412 INSN(bicsw, 0, 0b11, 1);
1413
1414 #undef INSN
1415
1416 // Add/subtract (shifted register)
1417 #define INSN(NAME, size, op) \
1418 void NAME(Register Rd, Register Rn, Register Rm, \
1419 enum shift_kind kind, unsigned shift = 0) { \
1420 starti; \
1421 f(0, 21); \
1422 assert_cond(kind != ROR); \
1423 zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \
1424 op_shifted_reg(0b01011, kind, shift, size, op); \
1425 }
1426
1427 INSN(add, 1, 0b000);
1428 INSN(sub, 1, 0b10);
1429 INSN(addw, 0, 0b000);
1430 INSN(subw, 0, 0b10);
1431
1432 INSN(adds, 1, 0b001);
1433 INSN(subs, 1, 0b11);
1434 INSN(addsw, 0, 0b001);
1435 INSN(subsw, 0, 0b11);
1436
1437 #undef INSN
1438
1439 // Add/subtract (extended register)
1440 #define INSN(NAME, op) \
1441 void NAME(Register Rd, Register Rn, Register Rm, \
1442 ext::operation option, int amount = 0) { \
1443 starti; \
1444 zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \
1445 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1446 }
1447
1448 void add_sub_extended_reg(unsigned op, unsigned decode,
1449 Register Rd, Register Rn, Register Rm,
1450 unsigned opt, ext::operation option, unsigned imm) {
1451 guarantee(imm <= 4, "shift amount must be < 4");
1452 f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
1453 f(option, 15, 13), f(imm, 12, 10);
1454 }
1455
1456 INSN(addw, 0b000);
1457 INSN(subw, 0b010);
1458 INSN(add, 0b100);
1459 INSN(sub, 0b110);
1460
1461 #undef INSN
1462
1463 #define INSN(NAME, op) \
1464 void NAME(Register Rd, Register Rn, Register Rm, \
1465 ext::operation option, int amount = 0) { \
1466 starti; \
1467 zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \
1468 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1469 }
1470
1471 INSN(addsw, 0b001);
1472 INSN(subsw, 0b011);
1473 INSN(adds, 0b101);
1474 INSN(subs, 0b111);
1475
1476 #undef INSN
1477
1478 // Aliases for short forms of add and sub
1479 #define INSN(NAME) \
1480 void NAME(Register Rd, Register Rn, Register Rm) { \
1481 if (Rd == sp || Rn == sp) \
1482 NAME(Rd, Rn, Rm, ext::uxtx); \
1483 else \
1484 NAME(Rd, Rn, Rm, LSL); \
1485 }
1486
1487 INSN(addw);
1488 INSN(subw);
1489 INSN(add);
1490 INSN(sub);
1491
1492 INSN(addsw);
1493 INSN(subsw);
1494 INSN(adds);
1495 INSN(subs);
1496
1497 #undef INSN
1498
1499 // Add/subtract (with carry)
1500 void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
1501 starti;
1502 f(op, 31, 29);
1503 f(0b11010000, 28, 21);
1504 f(0b000000, 15, 10);
1505 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
1506 }
1507
1508 #define INSN(NAME, op) \
1509 void NAME(Register Rd, Register Rn, Register Rm) { \
1510 add_sub_carry(op, Rd, Rn, Rm); \
1511 }
1512
1513 INSN(adcw, 0b000);
1514 INSN(adcsw, 0b001);
1515 INSN(sbcw, 0b010);
1516 INSN(sbcsw, 0b011);
1517 INSN(adc, 0b100);
1518 INSN(adcs, 0b101);
1519 INSN(sbc,0b110);
1520 INSN(sbcs, 0b111);
1521
1522 #undef INSN
1523
1524 // Conditional compare (both kinds)
1525 void conditional_compare(unsigned op, int o2, int o3,
1526 Register Rn, unsigned imm5, unsigned nzcv,
1527 unsigned cond) {
1528 f(op, 31, 29);
1529 f(0b11010010, 28, 21);
1530 f(cond, 15, 12);
1531 f(o2, 10);
1532 f(o3, 4);
1533 f(nzcv, 3, 0);
1534 f(imm5, 20, 16), rf(Rn, 5);
1535 }
1536
1537 #define INSN(NAME, op) \
1538 void NAME(Register Rn, Register Rm, int imm, Condition cond) { \
1539 starti; \
1540 f(0, 11); \
1541 conditional_compare(op, 0, 0, Rn, (uintptr_t)Rm, imm, cond); \
1542 } \
1543 \
1544 void NAME(Register Rn, int imm5, int imm, Condition cond) { \
1545 starti; \
1546 f(1, 11); \
1547 conditional_compare(op, 0, 0, Rn, imm5, imm, cond); \
1548 }
1549
1550 INSN(ccmnw, 0b001);
1551 INSN(ccmpw, 0b011);
1552 INSN(ccmn, 0b101);
1553 INSN(ccmp, 0b111);
1554
1555 #undef INSN
1556
1557 // Conditional select
1558 void conditional_select(unsigned op, unsigned op2,
1559 Register Rd, Register Rn, Register Rm,
1560 unsigned cond) {
1561 starti;
1562 f(op, 31, 29);
1563 f(0b11010100, 28, 21);
1564 f(cond, 15, 12);
1565 f(op2, 11, 10);
1566 zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
1567 }
1568
1569 #define INSN(NAME, op, op2) \
1570 void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
1571 conditional_select(op, op2, Rd, Rn, Rm, cond); \
1572 }
1573
1574 INSN(cselw, 0b000, 0b00);
1575 INSN(csincw, 0b000, 0b01);
1576 INSN(csinvw, 0b010, 0b00);
1577 INSN(csnegw, 0b010, 0b01);
1578 INSN(csel, 0b100, 0b00);
1579 INSN(csinc, 0b100, 0b01);
1580 INSN(csinv, 0b110, 0b00);
1581 INSN(csneg, 0b110, 0b01);
1582
1583 #undef INSN
1584
1585 // Data processing
1586 void data_processing(unsigned op29, unsigned opcode,
1587 Register Rd, Register Rn) {
1588 f(op29, 31, 29), f(0b11010110, 28, 21);
1589 f(opcode, 15, 10);
1590 rf(Rn, 5), rf(Rd, 0);
1591 }
1592
1593 // (1 source)
1594 #define INSN(NAME, op29, opcode2, opcode) \
1595 void NAME(Register Rd, Register Rn) { \
1596 starti; \
1597 f(opcode2, 20, 16); \
1598 data_processing(op29, opcode, Rd, Rn); \
1599 }
1600
1601 INSN(rbitw, 0b010, 0b00000, 0b00000);
1602 INSN(rev16w, 0b010, 0b00000, 0b00001);
1603 INSN(revw, 0b010, 0b00000, 0b00010);
1604 INSN(clzw, 0b010, 0b00000, 0b00100);
1605 INSN(clsw, 0b010, 0b00000, 0b00101);
1606
1607 INSN(rbit, 0b110, 0b00000, 0b00000);
1608 INSN(rev16, 0b110, 0b00000, 0b00001);
1609 INSN(rev32, 0b110, 0b00000, 0b00010);
1610 INSN(rev, 0b110, 0b00000, 0b00011);
1611 INSN(clz, 0b110, 0b00000, 0b00100);
1612 INSN(cls, 0b110, 0b00000, 0b00101);
1613
1614 #undef INSN
1615
1616 // (2 sources)
1617 #define INSN(NAME, op29, opcode) \
1618 void NAME(Register Rd, Register Rn, Register Rm) { \
1619 starti; \
1620 rf(Rm, 16); \
1621 data_processing(op29, opcode, Rd, Rn); \
1622 }
1623
1624 INSN(udivw, 0b000, 0b000010);
1625 INSN(sdivw, 0b000, 0b000011);
1626 INSN(lslvw, 0b000, 0b001000);
1627 INSN(lsrvw, 0b000, 0b001001);
1628 INSN(asrvw, 0b000, 0b001010);
1629 INSN(rorvw, 0b000, 0b001011);
1630
1631 INSN(udiv, 0b100, 0b000010);
1632 INSN(sdiv, 0b100, 0b000011);
1633 INSN(lslv, 0b100, 0b001000);
1634 INSN(lsrv, 0b100, 0b001001);
1635 INSN(asrv, 0b100, 0b001010);
1636 INSN(rorv, 0b100, 0b001011);
1637
1638 #undef INSN
1639
1640 // (3 sources)
1641 void data_processing(unsigned op54, unsigned op31, unsigned o0,
1642 Register Rd, Register Rn, Register Rm,
1643 Register Ra) {
1644 starti;
1645 f(op54, 31, 29), f(0b11011, 28, 24);
1646 f(op31, 23, 21), f(o0, 15);
1647 zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
1648 }
1649
1650 #define INSN(NAME, op54, op31, o0) \
1651 void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \
1652 data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \
1653 }
1654
1655 INSN(maddw, 0b000, 0b000, 0);
1656 INSN(msubw, 0b000, 0b000, 1);
1657 INSN(madd, 0b100, 0b000, 0);
1658 INSN(msub, 0b100, 0b000, 1);
1659 INSN(smaddl, 0b100, 0b001, 0);
1660 INSN(smsubl, 0b100, 0b001, 1);
1661 INSN(umaddl, 0b100, 0b101, 0);
1662 INSN(umsubl, 0b100, 0b101, 1);
1663
1664 #undef INSN
1665
1666 #define INSN(NAME, op54, op31, o0) \
1667 void NAME(Register Rd, Register Rn, Register Rm) { \
1668 data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \
1669 }
1670
1671 INSN(smulh, 0b100, 0b010, 0);
1672 INSN(umulh, 0b100, 0b110, 0);
1673
1674 #undef INSN
1675
1676 // Floating-point data-processing (1 source)
1677 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1678 FloatRegister Vd, FloatRegister Vn) {
1679 starti;
1680 f(op31, 31, 29);
1681 f(0b11110, 28, 24);
1682 f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
1683 rf(Vn, 5), rf(Vd, 0);
1684 }
1685
1686 #define INSN(NAME, op31, type, opcode) \
1687 void NAME(FloatRegister Vd, FloatRegister Vn) { \
1688 data_processing(op31, type, opcode, Vd, Vn); \
1689 }
1690
1691 private:
1692 INSN(i_fmovs, 0b000, 0b00, 0b000000);
1693 public:
1694 INSN(fabss, 0b000, 0b00, 0b000001);
1695 INSN(fnegs, 0b000, 0b00, 0b000010);
1696 INSN(fsqrts, 0b000, 0b00, 0b000011);
1697 INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision
1698
1699 private:
1700 INSN(i_fmovd, 0b000, 0b01, 0b000000);
1701 public:
1702 INSN(fabsd, 0b000, 0b01, 0b000001);
1703 INSN(fnegd, 0b000, 0b01, 0b000010);
1704 INSN(fsqrtd, 0b000, 0b01, 0b000011);
1705 INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision
1706
1707 void fmovd(FloatRegister Vd, FloatRegister Vn) {
1708 assert(Vd != Vn, "should be");
1709 i_fmovd(Vd, Vn);
1710 }
1711
1712 void fmovs(FloatRegister Vd, FloatRegister Vn) {
1713 assert(Vd != Vn, "should be");
1714 i_fmovs(Vd, Vn);
1715 }
1716
1717 #undef INSN
1718
1719 // Floating-point data-processing (2 source)
1720 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1721 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1722 starti;
1723 f(op31, 31, 29);
1724 f(0b11110, 28, 24);
1725 f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1726 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1727 }
1728
1729 #define INSN(NAME, op31, type, opcode) \
1730 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \
1731 data_processing(op31, type, opcode, Vd, Vn, Vm); \
1732 }
1733
1734 INSN(fmuls, 0b000, 0b00, 0b0000);
1735 INSN(fdivs, 0b000, 0b00, 0b0001);
1736 INSN(fadds, 0b000, 0b00, 0b0010);
1737 INSN(fsubs, 0b000, 0b00, 0b0011);
1738 INSN(fnmuls, 0b000, 0b00, 0b1000);
1739
1740 INSN(fmuld, 0b000, 0b01, 0b0000);
1741 INSN(fdivd, 0b000, 0b01, 0b0001);
1742 INSN(faddd, 0b000, 0b01, 0b0010);
1743 INSN(fsubd, 0b000, 0b01, 0b0011);
1744 INSN(fnmuld, 0b000, 0b01, 0b1000);
1745
1746 #undef INSN
1747
1748 // Floating-point data-processing (3 source)
1749 void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1750 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1751 FloatRegister Va) {
1752 starti;
1753 f(op31, 31, 29);
1754 f(0b11111, 28, 24);
1755 f(type, 23, 22), f(o1, 21), f(o0, 15);
1756 rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1757 }
1758
1759 #define INSN(NAME, op31, type, o1, o0) \
1760 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \
1761 FloatRegister Va) { \
1762 data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \
1763 }
1764
1765 INSN(fmadds, 0b000, 0b00, 0, 0);
1766 INSN(fmsubs, 0b000, 0b00, 0, 1);
1767 INSN(fnmadds, 0b000, 0b00, 1, 0);
1768 INSN(fnmsubs, 0b000, 0b00, 1, 1);
1769
1770 INSN(fmaddd, 0b000, 0b01, 0, 0);
1771 INSN(fmsubd, 0b000, 0b01, 0, 1);
1772 INSN(fnmaddd, 0b000, 0b01, 1, 0);
1773 INSN(fnmsub, 0b000, 0b01, 1, 1);
1774
1775 #undef INSN
1776
1777 // Floating-point conditional select
1778 void fp_conditional_select(unsigned op31, unsigned type,
1779 unsigned op1, unsigned op2,
1780 Condition cond, FloatRegister Vd,
1781 FloatRegister Vn, FloatRegister Vm) {
1782 starti;
1783 f(op31, 31, 29);
1784 f(0b11110, 28, 24);
1785 f(type, 23, 22);
1786 f(op1, 21, 21);
1787 f(op2, 11, 10);
1788 f(cond, 15, 12);
1789 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1790 }
1791
1792 #define INSN(NAME, op31, type, op1, op2) \
1793 void NAME(FloatRegister Vd, FloatRegister Vn, \
1794 FloatRegister Vm, Condition cond) { \
1795 fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \
1796 }
1797
1798 INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
1799 INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
1800
1801 #undef INSN
1802
1803 // Floating-point<->integer conversions
1804 void float_int_convert(unsigned op31, unsigned type,
1805 unsigned rmode, unsigned opcode,
1806 Register Rd, Register Rn) {
1807 starti;
1808 f(op31, 31, 29);
1809 f(0b11110, 28, 24);
1810 f(type, 23, 22), f(1, 21), f(rmode, 20, 19);
1811 f(opcode, 18, 16), f(0b000000, 15, 10);
1812 zrf(Rn, 5), zrf(Rd, 0);
1813 }
1814
1815 #define INSN(NAME, op31, type, rmode, opcode) \
1816 void NAME(Register Rd, FloatRegister Vn) { \
1817 float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \
1818 }
1819
1820 INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
1821 INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000);
1822 INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000);
1823 INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000);
1824
1825 INSN(fmovs, 0b000, 0b00, 0b00, 0b110);
1826 INSN(fmovd, 0b100, 0b01, 0b00, 0b110);
1827
1828 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110);
1829
1830 #undef INSN
1831
1832 #define INSN(NAME, op31, type, rmode, opcode) \
1833 void NAME(FloatRegister Vd, Register Rn) { \
1834 float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \
1835 }
1836
1837 INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
1838 INSN(fmovd, 0b100, 0b01, 0b00, 0b111);
1839
1840 INSN(scvtfws, 0b000, 0b00, 0b00, 0b010);
1841 INSN(scvtfs, 0b100, 0b00, 0b00, 0b010);
1842 INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010);
1843 INSN(scvtfd, 0b100, 0b01, 0b00, 0b010);
1844
1845 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
1846
1847 #undef INSN
1848
1849 // Floating-point compare
1850 void float_compare(unsigned op31, unsigned type,
1851 unsigned op, unsigned op2,
1852 FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
1853 starti;
1854 f(op31, 31, 29);
1855 f(0b11110, 28, 24);
1856 f(type, 23, 22), f(1, 21);
1857 f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
1858 rf(Vn, 5), rf(Vm, 16);
1859 }
1860
1861
1862 #define INSN(NAME, op31, type, op, op2) \
1863 void NAME(FloatRegister Vn, FloatRegister Vm) { \
1864 float_compare(op31, type, op, op2, Vn, Vm); \
1865 }
1866
1867 #define INSN1(NAME, op31, type, op, op2) \
1868 void NAME(FloatRegister Vn, double d) { \
1869 assert_cond(d == 0.0); \
1870 float_compare(op31, type, op, op2, Vn); \
1871 }
1872
1873 INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
1874 INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
1875 // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
1876 // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
1877
1878 INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000);
1879 INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000);
1880 // INSN(fcmped, 0b000, 0b01, 0b00, 0b10000);
1881 // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
1882
1883 #undef INSN
1884 #undef INSN1
1885
1886 // Floating-point Move (immediate)
1887 private:
1888 unsigned pack(double value);
1889
1890 void fmov_imm(FloatRegister Vn, double value, unsigned size) {
1891 starti;
1892 f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
1893 f(pack(value), 20, 13), f(0b10000000, 12, 5);
1894 rf(Vn, 0);
1895 }
1896
1897 public:
1898
1899 void fmovs(FloatRegister Vn, double value) {
1900 if (value)
1901 fmov_imm(Vn, value, 0b00);
1902 else
1903 fmovs(Vn, zr);
1904 }
1905 void fmovd(FloatRegister Vn, double value) {
1906 if (value)
1907 fmov_imm(Vn, value, 0b01);
1908 else
1909 fmovd(Vn, zr);
1910 }
1911
1912 /* SIMD extensions
1913 *
1914 * We just use FloatRegister in the following. They are exactly the same
1915 * as SIMD registers.
1916 */
1917 public:
1918
1919 enum SIMD_Arrangement {
1920 T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
1921 };
1922
1923 enum SIMD_RegVariant {
1924 B, H, S, D, Q
1925 };
1926
1927 #define INSN(NAME, op) \
1928 void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \
1929 ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
1930 } \
1931
1932 INSN(ldr, 1);
1933 INSN(str, 0);
1934
1935 #undef INSN
1936
1937 private:
1938
1939 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
1940 starti;
1941 f(0,31), f((int)T & 1, 30);
1942 f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
1943 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
1944 }
1945 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
1946 int imm, int op1, int op2) {
1947 starti;
1948 f(0,31), f((int)T & 1, 30);
1949 f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
1950 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
1951 }
1952 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
1953 Register Xm, int op1, int op2) {
1954 starti;
1955 f(0,31), f((int)T & 1, 30);
1956 f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
1957 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
1958 }
1959
1960 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2) {
1961 switch (a.getMode()) {
1962 case Address::base_plus_offset:
1963 guarantee(a.offset() == 0, "no offset allowed here");
1964 ld_st(Vt, T, a.base(), op1, op2);
1965 break;
1966 case Address::post:
1967 ld_st(Vt, T, a.base(), a.offset(), op1, op2);
1968 break;
1969 case Address::base_plus_offset_reg:
1970 ld_st(Vt, T, a.base(), a.index(), op1, op2);
1971 break;
1972 default:
1973 ShouldNotReachHere();
1974 }
1975 }
1976
1977 public:
1978
1979 #define INSN1(NAME, op1, op2) \
1980 void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \
1981 ld_st(Vt, T, a, op1, op2); \
1982 }
1983
1984 #define INSN2(NAME, op1, op2) \
1985 void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
1986 assert(Vt->successor() == Vt2, "Registers must be ordered"); \
1987 ld_st(Vt, T, a, op1, op2); \
1988 }
1989
1990 #define INSN3(NAME, op1, op2) \
1991 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
1992 SIMD_Arrangement T, const Address &a) { \
1993 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \
1994 "Registers must be ordered"); \
1995 ld_st(Vt, T, a, op1, op2); \
1996 }
1997
1998 #define INSN4(NAME, op1, op2) \
1999 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
2000 FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \
2001 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \
2002 Vt3->successor() == Vt4, "Registers must be ordered"); \
2003 ld_st(Vt, T, a, op1, op2); \
2004 }
2005
2006 INSN1(ld1, 0b001100010, 0b0111);
2007 INSN2(ld1, 0b001100010, 0b1010);
2008 INSN3(ld1, 0b001100010, 0b0110);
2009 INSN4(ld1, 0b001100010, 0b0010);
2010
2011 INSN2(ld2, 0b001100010, 0b1000);
2012 INSN3(ld3, 0b001100010, 0b0100);
2013 INSN4(ld4, 0b001100010, 0b0000);
2014
2015 INSN1(st1, 0b001100000, 0b0111);
2016 INSN2(st1, 0b001100000, 0b1010);
2017 INSN3(st1, 0b001100000, 0b0110);
2018 INSN4(st1, 0b001100000, 0b0010);
2019
2020 INSN2(st2, 0b001100000, 0b1000);
2021 INSN3(st3, 0b001100000, 0b0100);
2022 INSN4(st4, 0b001100000, 0b0000);
2023
2024 INSN1(ld1r, 0b001101010, 0b1100);
2025 INSN2(ld2r, 0b001101011, 0b1100);
2026 INSN3(ld3r, 0b001101010, 0b1110);
2027 INSN4(ld4r, 0b001101011, 0b1110);
2028
2029 #undef INSN1
2030 #undef INSN2
2031 #undef INSN3
2032 #undef INSN4
2033
2034 #define INSN(NAME, opc) \
2035 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2036 starti; \
2037 assert(T == T8B || T == T16B, "must be T8B or T16B"); \
2038 f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \
2039 rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2040 }
2041
2042 INSN(eor, 0b101110001);
2043 INSN(orr, 0b001110101);
2044 INSN(andr, 0b001110001);
2045 INSN(bic, 0b001110011);
2046 INSN(bif, 0b101110111);
2047 INSN(bit, 0b101110101);
2048 INSN(bsl, 0b101110011);
2049 INSN(orn, 0b001110111);
2050
2051 #undef INSN
2052
2053 #define INSN(NAME, opc, opc2) \
2054 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2055 starti; \
2056 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2057 f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \
2058 rf(Vn, 5), rf(Vd, 0); \
2059 }
2060
2061 INSN(addv, 0, 0b100001);
2062 INSN(subv, 1, 0b100001);
2063 INSN(mulv, 0, 0b100111);
2064 INSN(sshl, 0, 0b010001);
2065 INSN(ushl, 1, 0b010001);
2066
2067 #undef INSN
2068
2069 #define INSN(NAME, opc, opc2) \
2070 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2071 starti; \
2072 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2073 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
2074 rf(Vn, 5), rf(Vd, 0); \
2075 }
2076
2077 INSN(absr, 0, 0b100000101110);
2078 INSN(negr, 1, 0b100000101110);
2079 INSN(notr, 1, 0b100000010110);
2080 INSN(addv, 0, 0b110001101110);
2081 INSN(cls, 0, 0b100000010010);
2082 INSN(clz, 1, 0b100000010010);
2083 INSN(cnt, 0, 0b100000010110);
2084
2085 #undef INSN
2086
2087 #define INSN(NAME, op0, cmode0) \
2088 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \
2089 unsigned cmode = cmode0; \
2090 unsigned op = op0; \
2091 starti; \
2092 assert(lsl == 0 || \
2093 ((T == T4H || T == T8H) && lsl == 8) || \
2094 ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \
2095 cmode |= lsl >> 2; \
2096 if (T == T4H || T == T8H) cmode |= 0b1000; \
2097 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
2098 assert(op == 0 && cmode0 == 0, "must be MOVI"); \
2099 cmode = 0b1110; \
2100 if (T == T1D || T == T2D) op = 1; \
2101 } \
2102 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \
2103 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
2104 rf(Vd, 0); \
2105 }
2106
2107 INSN(movi, 0, 0);
2108 INSN(orri, 0, 1);
2109 INSN(mvni, 1, 0);
2110 INSN(bici, 1, 1);
2111
2112 #undef INSN
2113
2114 #define INSN(NAME, op1, op2, op3) \
2115 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2116 starti; \
2117 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2118 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \
2119 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2120 }
2121
2122 INSN(fadd, 0, 0, 0b110101);
2123 INSN(fdiv, 1, 0, 0b111111);
2124 INSN(fmul, 1, 0, 0b110111);
2125 INSN(fsub, 0, 1, 0b110101);
2126
2127 #undef INSN
2128
2129 #define INSN(NAME, opc) \
2130 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2131 starti; \
2132 assert(T == T4S, "arrangement must be T4S"); \
2133 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2134 }
2135
2136 INSN(sha1c, 0b000000);
2137 INSN(sha1m, 0b001000);
2138 INSN(sha1p, 0b000100);
2139 INSN(sha1su0, 0b001100);
2140 INSN(sha256h2, 0b010100);
2141 INSN(sha256h, 0b010000);
2142 INSN(sha256su1, 0b011000);
2143
2144 #undef INSN
2145
2146 #define INSN(NAME, opc) \
2147 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2148 starti; \
2149 assert(T == T4S, "arrangement must be T4S"); \
2150 f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2151 }
2152
2153 INSN(sha1h, 0b000010);
2154 INSN(sha1su1, 0b000110);
2155 INSN(sha256su0, 0b001010);
2156
2157 #undef INSN
2158
2159 #define INSN(NAME, opc) \
2160 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2161 starti; \
2162 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2163 }
2164
2165 INSN(aese, 0b0100111000101000010010);
2166 INSN(aesd, 0b0100111000101000010110);
2167 INSN(aesmc, 0b0100111000101000011010);
2168 INSN(aesimc, 0b0100111000101000011110);
2169
2170 #undef INSN
2171
2172 void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
2173 starti;
2174 assert(T != Q, "invalid register variant");
2175 f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
2176 f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2177 }
2178
2179 void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
2180 starti;
2181 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
2182 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10);
2183 rf(Vn, 5), rf(Rd, 0);
2184 }
2185
2186 #define INSN(NAME, opc, opc2) \
2187 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \
2188 starti; \
2189 /* The encodings for the immh:immb fields (bits 22:16) are \
2190 * 0001 xxx 8B/16B, shift = xxx \
2191 * 001x xxx 4H/8H, shift = xxxx \
2192 * 01xx xxx 2S/4S, shift = xxxxx \
2193 * 1xxx xxx 1D/2D, shift = xxxxxx (1D is RESERVED) \
2194 */ \
2195 assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \
2196 f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \
2197 f((1 << ((T>>1)+3))|shift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2198 }
2199
2200 INSN(shl, 0, 0b010101);
2201 INSN(sshr, 0, 0b000001);
2202 INSN(ushr, 1, 0b000001);
2203
2204 #undef INSN
2205
2206 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2207 starti;
2208 /* The encodings for the immh:immb fields (bits 22:16) are
2209 * 0001 xxx 8H, 8B/16b shift = xxx
2210 * 001x xxx 4S, 4H/8H shift = xxxx
2211 * 01xx xxx 2D, 2S/4S shift = xxxxx
2212 * 1xxx xxx RESERVED
2213 */
2214 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2215 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2216 f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
2217 f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2218 }
2219 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2220 ushll(Vd, Ta, Vn, Tb, shift);
2221 }
2222
2223 void uzp1(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T, int op = 0){
2224 starti;
2225 f(0, 31), f((T & 0x1), 30), f(0b001110, 29, 24), f((T >> 1), 23, 22), f(0, 21);
2226 rf(Vm, 16), f(0, 15), f(op, 14), f(0b0110, 13, 10), rf(Vn, 5), rf(Vd, 0);
2227 }
2228 void uzp2(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T){
2229 uzp1(Vd, Vn, Vm, T, 1);
2230 }
2231
2232 // Move from general purpose register
2233 // mov Vd.T[index], Rn
2234 void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
2235 starti;
2236 f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2237 f(0b000111, 15, 10), rf(Xn, 5), rf(Vd, 0);
2238 }
2239
2240 // Move to general purpose register
2241 // mov Rd, Vn.T[index]
2242 void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
2243 starti;
2244 f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
2245 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2246 f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
2247 }
2248
2249 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2250 starti;
2251 assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
2252 (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
2253 int size = (Ta == T1Q) ? 0b11 : 0b00;
2254 f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
2255 f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
2256 }
2257 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2258 assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
2259 pmull(Vd, Ta, Vn, Vm, Tb);
2260 }
2261
2262 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2263 starti;
2264 int size_b = (int)Tb >> 1;
2265 int size_a = (int)Ta >> 1;
2266 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
2267 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
2268 f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
2269 }
2270
2271 void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
2272 {
2273 starti;
2274 assert(T != T1D, "reserved encoding");
2275 f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2276 f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), rf(Xs, 5), rf(Vd, 0);
2277 }
2278
2279 void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
2280 {
2281 starti;
2282 assert(T != T1D, "reserved encoding");
2283 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2284 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2285 f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2286 }
2287
2288 // CRC32 instructions
2289 #define INSN(NAME, c, sf, sz) \
2290 void NAME(Register Rd, Register Rn, Register Rm) { \
2291 starti; \
2292 f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12); \
2293 f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
2294 }
2295
2296 INSN(crc32b, 0, 0, 0b00);
2297 INSN(crc32h, 0, 0, 0b01);
2298 INSN(crc32w, 0, 0, 0b10);
2299 INSN(crc32x, 0, 1, 0b11);
2300 INSN(crc32cb, 1, 0, 0b00);
2301 INSN(crc32ch, 1, 0, 0b01);
2302 INSN(crc32cw, 1, 0, 0b10);
2303 INSN(crc32cx, 1, 1, 0b11);
2304
2305 #undef INSN
2306
2307 // Table vector lookup
2308 #define INSN(NAME, op) \
2309 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \
2310 starti; \
2311 assert(T == T8B || T == T16B, "invalid arrangement"); \
2312 assert(0 < registers && registers <= 4, "invalid number of registers"); \
2313 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \
2314 f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2315 }
2316
2317 INSN(tbl, 0);
2318 INSN(tbx, 1);
2319
2320 #undef INSN
2321
2322 // AdvSIMD two-reg misc
2323 #define INSN(NAME, U, opcode) \
2324 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2325 starti; \
2326 assert((ASSERTION), MSG); \
2327 f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24); \
2328 f((int)(T >> 1), 23, 22), f(0b10000, 21, 17), f(opcode, 16, 12); \
2329 f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2330 }
2331
2332 #define MSG "invalid arrangement"
2333
2334 #define ASSERTION (T == T2S || T == T4S || T == T2D)
2335 INSN(fsqrt, 1, 0b11111);
2336 INSN(fabs, 0, 0b01111);
2337 INSN(fneg, 1, 0b01111);
2338 #undef ASSERTION
2339
2340 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
2341 INSN(rev64, 0, 0b00000);
2342 #undef ASSERTION
2343
2344 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
2345 INSN(rev32, 1, 0b00000);
2346 private:
2347 INSN(_rbit, 1, 0b00101);
2348 public:
2349
2350 #undef ASSERTION
2351
2352 #define ASSERTION (T == T8B || T == T16B)
2353 INSN(rev16, 0, 0b00001);
2354 // RBIT only allows T8B and T16B but encodes them oddly. Argh...
2355 void rbit(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
2356 assert((ASSERTION), MSG);
2357 _rbit(Vd, SIMD_Arrangement(T & 1 | 0b010), Vn);
2358 }
2359 #undef ASSERTION
2360
2361 #undef MSG
2362
2363 #undef INSN
2364
2365 void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
2366 {
2367 starti;
2368 assert(T == T8B || T == T16B, "invalid arrangement");
2369 assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
2370 f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
2371 rf(Vm, 16), f(0, 15), f(index, 14, 11);
2372 f(0, 10), rf(Vn, 5), rf(Vd, 0);
2373 }
2374
2375 /* Simulator extensions to the ISA
2376
2377 haltsim
2378
2379 takes no arguments, causes the sim to enter a debug break and then
2380 return from the simulator run() call with STATUS_HALT? The linking
2381 code will call fatal() when it sees STATUS_HALT.
2382
2383 blrt Xn, Wm
2384 blrt Xn, #gpargs, #fpargs, #type
2385 Xn holds the 64 bit x86 branch_address
2386 call format is encoded either as immediate data in the call
2387 or in register Wm. In the latter case
2388 Wm[13..6] = #gpargs,
2389 Wm[5..2] = #fpargs,
2390 Wm[1,0] = #type
2391
2392 calls the x86 code address 'branch_address' supplied in Xn passing
2393 arguments taken from the general and floating point registers according
2394 to the supplied counts 'gpargs' and 'fpargs'. may return a result in r0
2395 or v0 according to the the return type #type' where
2396
2397 address branch_address;
2398 uimm4 gpargs;
2399 uimm4 fpargs;
2400 enum ReturnType type;
2401
2402 enum ReturnType
2403 {
2404 void_ret = 0,
2405 int_ret = 1,
2406 long_ret = 1,
2407 obj_ret = 1, // i.e. same as long
2408 float_ret = 2,
2409 double_ret = 3
2410 }
2411
2412 notify
2413
2414 notifies the simulator of a transfer of control. instr[14:0]
2415 identifies the type of change of control.
2416
2417 0 ==> initial entry to a method.
2418
2419 1 ==> return into a method from a submethod call.
2420
2421 2 ==> exit out of Java method code.
2422
2423 3 ==> start execution for a new bytecode.
2424
2425 in cases 1 and 2 the simulator is expected to use a JVM callback to
2426 identify the name of the specific method being executed. in case 4
2427 the simulator is expected to use a JVM callback to identify the
2428 bytecode index.
2429
2430 Instruction encodings
2431 ---------------------
2432
2433 These are encoded in the space with instr[28:25] = 00 which is
2434 unallocated. Encodings are
2435
2436 10987654321098765432109876543210
2437 PSEUDO_HALT = 0x11100000000000000000000000000000
2438 PSEUDO_BLRT = 0x11000000000000000_______________
2439 PSEUDO_BLRTR = 0x1100000000000000100000__________
2440 PSEUDO_NOTIFY = 0x10100000000000000_______________
2441
2442 instr[31,29] = op1 : 111 ==> HALT, 110 ==> BLRT/BLRTR, 101 ==> NOTIFY
2443
2444 for BLRT
2445 instr[14,11] = #gpargs, instr[10,7] = #fpargs
2446 instr[6,5] = #type, instr[4,0] = Rn
2447 for BLRTR
2448 instr[9,5] = Rm, instr[4,0] = Rn
2449 for NOTIFY
2450 instr[14:0] = type : 0 ==> entry, 1 ==> reentry, 2 ==> exit, 3 ==> bcstart
2451 */
2452
2453 enum NotifyType { method_entry, method_reentry, method_exit, bytecode_start };
2454
2455 virtual void notify(int type) {
2456 if (UseBuiltinSim) {
2457 starti;
2458 // 109
2459 f(0b101, 31, 29);
2460 // 87654321098765
2461 f(0b00000000000000, 28, 15);
2462 f(type, 14, 0);
2463 }
2464 }
2465
2466 void blrt(Register Rn, int gpargs, int fpargs, int type) {
2467 if (UseBuiltinSim) {
2468 starti;
2469 f(0b110, 31 ,29);
2470 f(0b00, 28, 25);
2471 // 4321098765
2472 f(0b0000000000, 24, 15);
2473 f(gpargs, 14, 11);
2474 f(fpargs, 10, 7);
2475 f(type, 6, 5);
2476 rf(Rn, 0);
2477 } else {
2478 blr(Rn);
2479 }
2480 }
2481
2482 void blrt(Register Rn, Register Rm) {
2483 if (UseBuiltinSim) {
2484 starti;
2485 f(0b110, 31 ,29);
2486 f(0b00, 28, 25);
2487 // 4321098765
2488 f(0b0000000001, 24, 15);
2489 // 43210
2490 f(0b00000, 14, 10);
2491 rf(Rm, 5);
2492 rf(Rn, 0);
2493 } else {
2494 blr(Rn);
2495 }
2496 }
2497
2498 void haltsim() {
2499 starti;
2500 f(0b111, 31 ,29);
2501 f(0b00, 28, 27);
2502 // 654321098765432109876543210
2503 f(0b000000000000000000000000000, 26, 0);
2504 }
2505
2506 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2507 }
2508
2509 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2510 Register tmp,
2511 int offset) {
2512 ShouldNotCallThis();
2513 return RegisterOrConstant();
2514 }
2515
2516 // Stack overflow checking
2517 virtual void bang_stack_with_offset(int offset);
2518
2519 static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
2520 static bool operand_valid_for_add_sub_immediate(long imm);
2521 static bool operand_valid_for_float_immediate(double imm);
2522
2523 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
2524 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
2525 };
2526
2527 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
2528 Assembler::Membar_mask_bits b) {
2529 return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
2530 }
2531
2532 Instruction_aarch64::~Instruction_aarch64() {
2533 assem->emit();
2534 }
2535
2536 #undef starti
2537
2538 // Invert a condition
2539 inline const Assembler::Condition operator~(const Assembler::Condition cond) {
2540 return Assembler::Condition(int(cond) ^ 1);
2541 }
2542
2543 class BiasedLockingCounters;
2544
2545 extern "C" void das(uint64_t start, int len);
2546
2547 #endif // CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP