1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include <sys/types.h>
27
28 #include "precompiled.hpp"
29 #include "asm/assembler.hpp"
30 #include "asm/assembler.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32
33 #include "compiler/disassembler.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "nativeInst_aarch64.hpp"
36 #include "oops/klass.inline.hpp"
37 #include "oops/oop.inline.hpp"
38 #include "opto/compile.hpp"
39 #include "opto/node.hpp"
40 #include "runtime/biasedLocking.hpp"
41 #include "runtime/icache.hpp"
42 #include "runtime/interfaceSupport.hpp"
43 #include "runtime/sharedRuntime.hpp"
44
45 #if INCLUDE_ALL_GCS
46 #include "gc/g1/g1CollectedHeap.inline.hpp"
47 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
48 #include "gc/g1/heapRegion.hpp"
49 #endif
50
51 #ifdef PRODUCT
52 #define BLOCK_COMMENT(str) /* nothing */
53 #define STOP(error) stop(error)
54 #else
55 #define BLOCK_COMMENT(str) block_comment(str)
56 #define STOP(error) block_comment(error); stop(error)
57 #endif
58
59 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
60
61 // Patch any kind of instruction; there may be several instructions.
62 // Return the total length (in bytes) of the instructions.
63 int MacroAssembler::pd_patch_instruction_size(address branch, address target) {
64 int instructions = 1;
65 assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant");
66 long offset = (target - branch) >> 2;
67 unsigned insn = *(unsigned*)branch;
68 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
69 // Load register (literal)
70 Instruction_aarch64::spatch(branch, 23, 5, offset);
71 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
72 // Unconditional branch (immediate)
73 Instruction_aarch64::spatch(branch, 25, 0, offset);
74 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
75 // Conditional branch (immediate)
76 Instruction_aarch64::spatch(branch, 23, 5, offset);
77 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
78 // Compare & branch (immediate)
79 Instruction_aarch64::spatch(branch, 23, 5, offset);
80 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
81 // Test & branch (immediate)
82 Instruction_aarch64::spatch(branch, 18, 5, offset);
83 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
84 // PC-rel. addressing
85 offset = target-branch;
86 int shift = Instruction_aarch64::extract(insn, 31, 31);
87 if (shift) {
88 u_int64_t dest = (u_int64_t)target;
89 uint64_t pc_page = (uint64_t)branch >> 12;
90 uint64_t adr_page = (uint64_t)target >> 12;
91 unsigned offset_lo = dest & 0xfff;
92 offset = adr_page - pc_page;
93
94 // We handle 3 types of PC relative addressing
95 // 1 - adrp Rx, target_page
96 // ldr/str Ry, [Rx, #offset_in_page]
97 // 2 - adrp Rx, target_page
98 // add Ry, Rx, #offset_in_page
99 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0)
100 // nop/movk Rx, #imm12<<32
101 // In all cases we check that Rx is the same in the adrp and the subsequent
102 // ldr/str, add or movk.
103 //
104 unsigned insn2 = ((unsigned*)branch)[1];
105 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
106 Instruction_aarch64::extract(insn, 4, 0) ==
107 Instruction_aarch64::extract(insn2, 9, 5)) {
108 // Load/store register (unsigned immediate)
109 unsigned size = Instruction_aarch64::extract(insn2, 31, 30);
110 Instruction_aarch64::patch(branch + sizeof (unsigned),
111 21, 10, offset_lo >> size);
112 guarantee(((dest >> size) << size) == dest, "misaligned target");
113 instructions = 2;
114 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
115 Instruction_aarch64::extract(insn, 4, 0) ==
116 Instruction_aarch64::extract(insn2, 4, 0)) {
117 // add (immediate)
118 Instruction_aarch64::patch(branch + sizeof (unsigned),
119 21, 10, offset_lo);
120 instructions = 2;
121 } else if (insn2 == aarch64_NOP || // NOP or MOVK Rx, #imm12 << 32
122 (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110) &&
123 Instruction_aarch64::extract(insn, 4, 0) ==
124 Instruction_aarch64::extract(insn2, 4, 0)) {
125 if (offset >= -(1<<20) && offset < (1<<20)) {
126 *(unsigned *)(branch + 4) = aarch64_NOP;
127 } else {
128 Instruction_aarch64::patch_movk(branch, 4, 20, 5, (uint64_t)target, 32);
129 offset &= (1<<20)-1;
130 }
131 } else {
132 ShouldNotReachHere();
133 }
134 }
135 int offset_lo = offset & 3;
136 offset >>= 2;
137 Instruction_aarch64::spatch(branch, 23, 5, offset);
138 Instruction_aarch64::patch(branch, 30, 29, offset_lo);
139 } else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) {
140 u_int64_t dest = (u_int64_t)target;
141 // Move wide constant
142 assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch");
143 assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch");
144 Instruction_aarch64::patch(branch, 20, 5, dest & 0xffff);
145 Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff);
146 Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff);
147 assert(target_addr_for_insn(branch) == target, "should be");
148 instructions = 3;
149 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
150 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
151 // nothing to do
152 assert(target == 0, "did not expect to relocate target for polling page load");
153 } else {
154 ShouldNotReachHere();
155 }
156 return instructions * NativeInstruction::instruction_size;
157 }
158
159 int MacroAssembler::patch_oop(address insn_addr, address o) {
160 int instructions;
161 unsigned insn = *(unsigned*)insn_addr;
162 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
163
164 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
165 // narrow OOPs by setting the upper 16 bits in the first
166 // instruction.
167 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
168 // Move narrow OOP
169 narrowOop n = oopDesc::encode_heap_oop((oop)o);
170 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
171 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
172 instructions = 2;
173 } else {
174 // Move wide OOP
175 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
176 uintptr_t dest = (uintptr_t)o;
177 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
178 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
179 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
180 instructions = 3;
181 }
182 return instructions * NativeInstruction::instruction_size;
183 }
184
185 address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) {
186 long offset = 0;
187 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) {
188 // Load register (literal)
189 offset = Instruction_aarch64::sextract(insn, 23, 5);
190 return address(((uint64_t)insn_addr + (offset << 2)));
191 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
192 // Unconditional branch (immediate)
193 offset = Instruction_aarch64::sextract(insn, 25, 0);
194 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
195 // Conditional branch (immediate)
196 offset = Instruction_aarch64::sextract(insn, 23, 5);
197 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
198 // Compare & branch (immediate)
199 offset = Instruction_aarch64::sextract(insn, 23, 5);
200 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
201 // Test & branch (immediate)
202 offset = Instruction_aarch64::sextract(insn, 18, 5);
203 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
204 // PC-rel. addressing
205 offset = Instruction_aarch64::extract(insn, 30, 29);
206 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
207 int shift = Instruction_aarch64::extract(insn, 31, 31) ? 12 : 0;
208 if (shift) {
209 offset <<= shift;
210 uint64_t target_page = ((uint64_t)insn_addr) + offset;
211 target_page &= ((uint64_t)-1) << shift;
212 // Return the target address for the following sequences
213 // 1 - adrp Rx, target_page
214 // ldr/str Ry, [Rx, #offset_in_page]
215 // 2 - adrp Rx, target_page ]
216 // add Ry, Rx, #offset_in_page
217 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0)
218 // nop/movk Rx, #imm12<<32
219 //
220 // In the first two cases we check that the register is the same and
221 // return the target_page + the offset within the page.
222 //
223 // In the third case we return just the target_page
224 //
225 unsigned insn2 = ((unsigned*)insn_addr)[1];
226 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
227 Instruction_aarch64::extract(insn, 4, 0) ==
228 Instruction_aarch64::extract(insn2, 9, 5)) {
229 // Load/store register (unsigned immediate)
230 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
231 unsigned int size = Instruction_aarch64::extract(insn2, 31, 30);
232 return address(target_page + (byte_offset << size));
233 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
234 Instruction_aarch64::extract(insn, 4, 0) ==
235 Instruction_aarch64::extract(insn2, 4, 0)) {
236 // add (immediate)
237 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
238 return address(target_page + byte_offset);
239 } else if (insn2 == aarch64_NOP || // NOP or MOVK Rx, #imm12 << 32
240 (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110) &&
241 Instruction_aarch64::extract(insn, 4, 0) ==
242 Instruction_aarch64::extract(insn2, 4, 0)) {
243 if (insn2 != aarch64_NOP) {
244 target_page = (target_page & 0xffffffff) |
245 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
246 }
247 return (address)target_page;
248 } else {
249 ShouldNotReachHere();
250 }
251 } else {
252 ShouldNotReachHere();
253 }
254 } else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) {
255 u_int32_t *insns = (u_int32_t *)insn_addr;
256 // Move wide constant: movz, movk, movk. See movptr().
257 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
258 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
259 return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5))
260 + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
261 + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
262 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
263 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
264 return 0;
265 } else {
266 ShouldNotReachHere();
267 }
268 return address(((uint64_t)insn_addr + (offset << 2)));
269 }
270
271 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
272 dsb(Assembler::SY);
273 }
274
275
276 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
277 bool clear_pc) {
278 // we must set sp to zero to clear frame
279 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
280 // must clear fp, so that compiled frames are not confused; it is
281 // possible that we need it only for debugging
282 if (clear_fp) {
283 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
284 }
285
286 if (clear_pc) {
287 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
288 }
289 }
290
291 // Calls to C land
292 //
293 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
294 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
295 // has to be reset to 0. This is required to allow proper stack traversal.
296 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
297 Register last_java_fp,
298 Register last_java_pc,
299 Register scratch) {
300
301 if (last_java_pc->is_valid()) {
302 str(last_java_pc, Address(rthread,
303 JavaThread::frame_anchor_offset()
304 + JavaFrameAnchor::last_Java_pc_offset()));
305 }
306
307 // determine last_java_sp register
308 if (last_java_sp == sp) {
309 mov(scratch, sp);
310 last_java_sp = scratch;
311 } else if (!last_java_sp->is_valid()) {
312 last_java_sp = esp;
313 }
314
315 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
316
317 // last_java_fp is optional
318 if (last_java_fp->is_valid()) {
319 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
320 }
321 }
322
323 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
324 Register last_java_fp,
325 address last_java_pc,
326 Register scratch) {
327 if (last_java_pc != NULL) {
328 adr(scratch, last_java_pc);
329 } else {
330 // FIXME: This is almost never correct. We should delete all
331 // cases of set_last_Java_frame with last_java_pc=NULL and use the
332 // correct return address instead.
333 adr(scratch, pc());
334 }
335
336 str(scratch, Address(rthread,
337 JavaThread::frame_anchor_offset()
338 + JavaFrameAnchor::last_Java_pc_offset()));
339
340 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
341 }
342
343 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
344 Register last_java_fp,
345 Label &L,
346 Register scratch) {
347 if (L.is_bound()) {
348 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
349 } else {
350 InstructionMark im(this);
351 L.add_patch_at(code(), locator());
352 set_last_Java_frame(last_java_sp, last_java_fp, (address)NULL, scratch);
353 }
354 }
355
356 void MacroAssembler::far_call(Address entry, CodeBuffer *cbuf, Register tmp) {
357 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
358 assert(CodeCache::find_blob(entry.target()) != NULL,
359 "destination of far call not found in code cache");
360 if (far_branches()) {
361 unsigned long offset;
362 // We can use ADRP here because we know that the total size of
363 // the code cache cannot exceed 2Gb.
364 adrp(tmp, entry, offset);
365 add(tmp, tmp, offset);
366 if (cbuf) cbuf->set_insts_mark();
367 blr(tmp);
368 } else {
369 if (cbuf) cbuf->set_insts_mark();
370 bl(entry);
371 }
372 }
373
374 void MacroAssembler::far_jump(Address entry, CodeBuffer *cbuf, Register tmp) {
375 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
376 assert(CodeCache::find_blob(entry.target()) != NULL,
377 "destination of far call not found in code cache");
378 if (far_branches()) {
379 unsigned long offset;
380 // We can use ADRP here because we know that the total size of
381 // the code cache cannot exceed 2Gb.
382 adrp(tmp, entry, offset);
383 add(tmp, tmp, offset);
384 if (cbuf) cbuf->set_insts_mark();
385 br(tmp);
386 } else {
387 if (cbuf) cbuf->set_insts_mark();
388 b(entry);
389 }
390 }
391
392 int MacroAssembler::biased_locking_enter(Register lock_reg,
393 Register obj_reg,
394 Register swap_reg,
395 Register tmp_reg,
396 bool swap_reg_contains_mark,
397 Label& done,
398 Label* slow_case,
399 BiasedLockingCounters* counters) {
400 assert(UseBiasedLocking, "why call this otherwise?");
401 assert_different_registers(lock_reg, obj_reg, swap_reg);
402
403 if (PrintBiasedLockingStatistics && counters == NULL)
404 counters = BiasedLocking::counters();
405
406 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1, rscratch2, noreg);
407 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
408 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
409 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
410 Address saved_mark_addr(lock_reg, 0);
411
412 // Biased locking
413 // See whether the lock is currently biased toward our thread and
414 // whether the epoch is still valid
415 // Note that the runtime guarantees sufficient alignment of JavaThread
416 // pointers to allow age to be placed into low bits
417 // First check to see whether biasing is even enabled for this object
418 Label cas_label;
419 int null_check_offset = -1;
420 if (!swap_reg_contains_mark) {
421 null_check_offset = offset();
422 ldr(swap_reg, mark_addr);
423 }
424 andr(tmp_reg, swap_reg, markOopDesc::biased_lock_mask_in_place);
425 cmp(tmp_reg, markOopDesc::biased_lock_pattern);
426 br(Assembler::NE, cas_label);
427 // The bias pattern is present in the object's header. Need to check
428 // whether the bias owner and the epoch are both still current.
429 load_prototype_header(tmp_reg, obj_reg);
430 orr(tmp_reg, tmp_reg, rthread);
431 eor(tmp_reg, swap_reg, tmp_reg);
432 andr(tmp_reg, tmp_reg, ~((int) markOopDesc::age_mask_in_place));
433 if (counters != NULL) {
434 Label around;
435 cbnz(tmp_reg, around);
436 atomic_incw(Address((address)counters->biased_lock_entry_count_addr()), tmp_reg, rscratch1, rscratch2);
437 b(done);
438 bind(around);
439 } else {
440 cbz(tmp_reg, done);
441 }
442
443 Label try_revoke_bias;
444 Label try_rebias;
445
446 // At this point we know that the header has the bias pattern and
447 // that we are not the bias owner in the current epoch. We need to
448 // figure out more details about the state of the header in order to
449 // know what operations can be legally performed on the object's
450 // header.
451
452 // If the low three bits in the xor result aren't clear, that means
453 // the prototype header is no longer biased and we have to revoke
454 // the bias on this object.
455 andr(rscratch1, tmp_reg, markOopDesc::biased_lock_mask_in_place);
456 cbnz(rscratch1, try_revoke_bias);
457
458 // Biasing is still enabled for this data type. See whether the
459 // epoch of the current bias is still valid, meaning that the epoch
460 // bits of the mark word are equal to the epoch bits of the
461 // prototype header. (Note that the prototype header's epoch bits
462 // only change at a safepoint.) If not, attempt to rebias the object
463 // toward the current thread. Note that we must be absolutely sure
464 // that the current epoch is invalid in order to do this because
465 // otherwise the manipulations it performs on the mark word are
466 // illegal.
467 andr(rscratch1, tmp_reg, markOopDesc::epoch_mask_in_place);
468 cbnz(rscratch1, try_rebias);
469
470 // The epoch of the current bias is still valid but we know nothing
471 // about the owner; it might be set or it might be clear. Try to
472 // acquire the bias of the object using an atomic operation. If this
473 // fails we will go in to the runtime to revoke the object's bias.
474 // Note that we first construct the presumed unbiased header so we
475 // don't accidentally blow away another thread's valid bias.
476 {
477 Label here;
478 mov(rscratch1, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
479 andr(swap_reg, swap_reg, rscratch1);
480 orr(tmp_reg, swap_reg, rthread);
481 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case);
482 // If the biasing toward our thread failed, this means that
483 // another thread succeeded in biasing it toward itself and we
484 // need to revoke that bias. The revocation will occur in the
485 // interpreter runtime in the slow case.
486 bind(here);
487 if (counters != NULL) {
488 atomic_incw(Address((address)counters->anonymously_biased_lock_entry_count_addr()),
489 tmp_reg, rscratch1, rscratch2);
490 }
491 }
492 b(done);
493
494 bind(try_rebias);
495 // At this point we know the epoch has expired, meaning that the
496 // current "bias owner", if any, is actually invalid. Under these
497 // circumstances _only_, we are allowed to use the current header's
498 // value as the comparison value when doing the cas to acquire the
499 // bias in the current epoch. In other words, we allow transfer of
500 // the bias from one thread to another directly in this situation.
501 //
502 // FIXME: due to a lack of registers we currently blow away the age
503 // bits in this situation. Should attempt to preserve them.
504 {
505 Label here;
506 load_prototype_header(tmp_reg, obj_reg);
507 orr(tmp_reg, rthread, tmp_reg);
508 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case);
509 // If the biasing toward our thread failed, then another thread
510 // succeeded in biasing it toward itself and we need to revoke that
511 // bias. The revocation will occur in the runtime in the slow case.
512 bind(here);
513 if (counters != NULL) {
514 atomic_incw(Address((address)counters->rebiased_lock_entry_count_addr()),
515 tmp_reg, rscratch1, rscratch2);
516 }
517 }
518 b(done);
519
520 bind(try_revoke_bias);
521 // The prototype mark in the klass doesn't have the bias bit set any
522 // more, indicating that objects of this data type are not supposed
523 // to be biased any more. We are going to try to reset the mark of
524 // this object to the prototype value and fall through to the
525 // CAS-based locking scheme. Note that if our CAS fails, it means
526 // that another thread raced us for the privilege of revoking the
527 // bias of this particular object, so it's okay to continue in the
528 // normal locking code.
529 //
530 // FIXME: due to a lack of registers we currently blow away the age
531 // bits in this situation. Should attempt to preserve them.
532 {
533 Label here, nope;
534 load_prototype_header(tmp_reg, obj_reg);
535 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, &nope);
536 bind(here);
537
538 // Fall through to the normal CAS-based lock, because no matter what
539 // the result of the above CAS, some thread must have succeeded in
540 // removing the bias bit from the object's header.
541 if (counters != NULL) {
542 atomic_incw(Address((address)counters->revoked_lock_entry_count_addr()), tmp_reg,
543 rscratch1, rscratch2);
544 }
545 bind(nope);
546 }
547
548 bind(cas_label);
549
550 return null_check_offset;
551 }
552
553 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
554 assert(UseBiasedLocking, "why call this otherwise?");
555
556 // Check for biased locking unlock case, which is a no-op
557 // Note: we do not have to check the thread ID for two reasons.
558 // First, the interpreter checks for IllegalMonitorStateException at
559 // a higher level. Second, if the bias was revoked while we held the
560 // lock, the object could not be rebiased toward another thread, so
561 // the bias bit would be clear.
562 ldr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
563 andr(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
564 cmp(temp_reg, markOopDesc::biased_lock_pattern);
565 br(Assembler::EQ, done);
566 }
567
568
569 // added to make this compile
570
571 REGISTER_DEFINITION(Register, noreg);
572
573 static void pass_arg0(MacroAssembler* masm, Register arg) {
574 if (c_rarg0 != arg ) {
575 masm->mov(c_rarg0, arg);
576 }
577 }
578
579 static void pass_arg1(MacroAssembler* masm, Register arg) {
580 if (c_rarg1 != arg ) {
581 masm->mov(c_rarg1, arg);
582 }
583 }
584
585 static void pass_arg2(MacroAssembler* masm, Register arg) {
586 if (c_rarg2 != arg ) {
587 masm->mov(c_rarg2, arg);
588 }
589 }
590
591 static void pass_arg3(MacroAssembler* masm, Register arg) {
592 if (c_rarg3 != arg ) {
593 masm->mov(c_rarg3, arg);
594 }
595 }
596
597 void MacroAssembler::call_VM_base(Register oop_result,
598 Register java_thread,
599 Register last_java_sp,
600 address entry_point,
601 int number_of_arguments,
602 bool check_exceptions) {
603 // determine java_thread register
604 if (!java_thread->is_valid()) {
605 java_thread = rthread;
606 }
607
608 // determine last_java_sp register
609 if (!last_java_sp->is_valid()) {
610 last_java_sp = esp;
611 }
612
613 // debugging support
614 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
615 assert(java_thread == rthread, "unexpected register");
616 #ifdef ASSERT
617 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
618 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
619 #endif // ASSERT
620
621 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
622 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
623
624 // push java thread (becomes first argument of C function)
625
626 mov(c_rarg0, java_thread);
627
628 // set last Java frame before call
629 assert(last_java_sp != rfp, "can't use rfp");
630
631 Label l;
632 set_last_Java_frame(last_java_sp, rfp, l, rscratch1);
633
634 // do the call, remove parameters
635 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
636
637 // reset last Java frame
638 // Only interpreter should have to clear fp
639 reset_last_Java_frame(true, true);
640
641 // C++ interp handles this in the interpreter
642 check_and_handle_popframe(java_thread);
643 check_and_handle_earlyret(java_thread);
644
645 if (check_exceptions) {
646 // check for pending exceptions (java_thread is set upon return)
647 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
648 Label ok;
649 cbz(rscratch1, ok);
650 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
651 br(rscratch1);
652 bind(ok);
653 }
654
655 // get oop result if there is one and reset the value in the thread
656 if (oop_result->is_valid()) {
657 get_vm_result(oop_result, java_thread);
658 }
659 }
660
661 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
662 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
663 }
664
665 // Maybe emit a call via a trampoline. If the code cache is small
666 // trampolines won't be emitted.
667
668 address MacroAssembler::trampoline_call(Address entry, CodeBuffer *cbuf) {
669 assert(entry.rspec().type() == relocInfo::runtime_call_type
670 || entry.rspec().type() == relocInfo::opt_virtual_call_type
671 || entry.rspec().type() == relocInfo::static_call_type
672 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
673
674 unsigned int start_offset = offset();
675 if (far_branches() && !Compile::current()->in_scratch_emit_size()) {
676 address stub = emit_trampoline_stub(start_offset, entry.target());
677 if (stub == NULL) {
678 return NULL; // CodeCache is full
679 }
680 }
681
682 if (cbuf) cbuf->set_insts_mark();
683 relocate(entry.rspec());
684 if (Assembler::reachable_from_branch_at(pc(), entry.target())) {
685 bl(entry.target());
686 } else {
687 bl(pc());
688 }
689 // just need to return a non-null address
690 return pc();
691 }
692
693
694 // Emit a trampoline stub for a call to a target which is too far away.
695 //
696 // code sequences:
697 //
698 // call-site:
699 // branch-and-link to <destination> or <trampoline stub>
700 //
701 // Related trampoline stub for this call site in the stub section:
702 // load the call target from the constant pool
703 // branch (LR still points to the call site above)
704
705 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
706 address dest) {
707 address stub = start_a_stub(Compile::MAX_stubs_size/2);
708 if (stub == NULL) {
709 return NULL; // CodeBuffer::expand failed
710 }
711
712 // Create a trampoline stub relocation which relates this trampoline stub
713 // with the call instruction at insts_call_instruction_offset in the
714 // instructions code-section.
715 align(wordSize);
716 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
717 + insts_call_instruction_offset));
718 const int stub_start_offset = offset();
719
720 // Now, create the trampoline stub's code:
721 // - load the call
722 // - call
723 Label target;
724 ldr(rscratch1, target);
725 br(rscratch1);
726 bind(target);
727 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
728 "should be");
729 emit_int64((int64_t)dest);
730
731 const address stub_start_addr = addr_at(stub_start_offset);
732
733 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
734
735 end_a_stub();
736 return stub;
737 }
738
739 address MacroAssembler::ic_call(address entry) {
740 RelocationHolder rh = virtual_call_Relocation::spec(pc());
741 // address const_ptr = long_constant((jlong)Universe::non_oop_word());
742 // unsigned long offset;
743 // ldr_constant(rscratch2, const_ptr);
744 movptr(rscratch2, (uintptr_t)Universe::non_oop_word());
745 return trampoline_call(Address(entry, rh));
746 }
747
748 // Implementation of call_VM versions
749
750 void MacroAssembler::call_VM(Register oop_result,
751 address entry_point,
752 bool check_exceptions) {
753 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
754 }
755
756 void MacroAssembler::call_VM(Register oop_result,
757 address entry_point,
758 Register arg_1,
759 bool check_exceptions) {
760 pass_arg1(this, arg_1);
761 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
762 }
763
764 void MacroAssembler::call_VM(Register oop_result,
765 address entry_point,
766 Register arg_1,
767 Register arg_2,
768 bool check_exceptions) {
769 assert(arg_1 != c_rarg2, "smashed arg");
770 pass_arg2(this, arg_2);
771 pass_arg1(this, arg_1);
772 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
773 }
774
775 void MacroAssembler::call_VM(Register oop_result,
776 address entry_point,
777 Register arg_1,
778 Register arg_2,
779 Register arg_3,
780 bool check_exceptions) {
781 assert(arg_1 != c_rarg3, "smashed arg");
782 assert(arg_2 != c_rarg3, "smashed arg");
783 pass_arg3(this, arg_3);
784
785 assert(arg_1 != c_rarg2, "smashed arg");
786 pass_arg2(this, arg_2);
787
788 pass_arg1(this, arg_1);
789 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
790 }
791
792 void MacroAssembler::call_VM(Register oop_result,
793 Register last_java_sp,
794 address entry_point,
795 int number_of_arguments,
796 bool check_exceptions) {
797 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
798 }
799
800 void MacroAssembler::call_VM(Register oop_result,
801 Register last_java_sp,
802 address entry_point,
803 Register arg_1,
804 bool check_exceptions) {
805 pass_arg1(this, arg_1);
806 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
807 }
808
809 void MacroAssembler::call_VM(Register oop_result,
810 Register last_java_sp,
811 address entry_point,
812 Register arg_1,
813 Register arg_2,
814 bool check_exceptions) {
815
816 assert(arg_1 != c_rarg2, "smashed arg");
817 pass_arg2(this, arg_2);
818 pass_arg1(this, arg_1);
819 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
820 }
821
822 void MacroAssembler::call_VM(Register oop_result,
823 Register last_java_sp,
824 address entry_point,
825 Register arg_1,
826 Register arg_2,
827 Register arg_3,
828 bool check_exceptions) {
829 assert(arg_1 != c_rarg3, "smashed arg");
830 assert(arg_2 != c_rarg3, "smashed arg");
831 pass_arg3(this, arg_3);
832 assert(arg_1 != c_rarg2, "smashed arg");
833 pass_arg2(this, arg_2);
834 pass_arg1(this, arg_1);
835 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
836 }
837
838
839 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
840 ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
841 str(zr, Address(java_thread, JavaThread::vm_result_offset()));
842 verify_oop(oop_result, "broken oop in call_VM_base");
843 }
844
845 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
846 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
847 str(zr, Address(java_thread, JavaThread::vm_result_2_offset()));
848 }
849
850 void MacroAssembler::align(int modulus) {
851 while (offset() % modulus != 0) nop();
852 }
853
854 // these are no-ops overridden by InterpreterMacroAssembler
855
856 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
857
858 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
859
860
861 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
862 Register tmp,
863 int offset) {
864 intptr_t value = *delayed_value_addr;
865 if (value != 0)
866 return RegisterOrConstant(value + offset);
867
868 // load indirectly to solve generation ordering problem
869 ldr(tmp, ExternalAddress((address) delayed_value_addr));
870
871 if (offset != 0)
872 add(tmp, tmp, offset);
873
874 return RegisterOrConstant(tmp);
875 }
876
877
878 void MacroAssembler:: notify(int type) {
879 if (type == bytecode_start) {
880 // set_last_Java_frame(esp, rfp, (address)NULL);
881 Assembler:: notify(type);
882 // reset_last_Java_frame(true, false);
883 }
884 else
885 Assembler:: notify(type);
886 }
887
888 // Look up the method for a megamorphic invokeinterface call.
889 // The target method is determined by <intf_klass, itable_index>.
890 // The receiver klass is in recv_klass.
891 // On success, the result will be in method_result, and execution falls through.
892 // On failure, execution transfers to the given label.
893 void MacroAssembler::lookup_interface_method(Register recv_klass,
894 Register intf_klass,
895 RegisterOrConstant itable_index,
896 Register method_result,
897 Register scan_temp,
898 Label& L_no_such_interface) {
899 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
900 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
901 "caller must use same register for non-constant itable index as for method");
902
903 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
904 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
905 int itentry_off = itableMethodEntry::method_offset_in_bytes();
906 int scan_step = itableOffsetEntry::size() * wordSize;
907 int vte_size = vtableEntry::size() * wordSize;
908 assert(vte_size == wordSize, "else adjust times_vte_scale");
909
910 ldrw(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
911
912 // %%% Could store the aligned, prescaled offset in the klassoop.
913 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
914 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
915 add(scan_temp, scan_temp, vtable_base);
916 if (HeapWordsPerLong > 1) {
917 // Round up to align_object_offset boundary
918 // see code for instanceKlass::start_of_itable!
919 round_to(scan_temp, BytesPerLong);
920 }
921
922 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
923 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
924 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
925 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
926 if (itentry_off)
927 add(recv_klass, recv_klass, itentry_off);
928
929 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
930 // if (scan->interface() == intf) {
931 // result = (klass + scan->offset() + itable_index);
932 // }
933 // }
934 Label search, found_method;
935
936 for (int peel = 1; peel >= 0; peel--) {
937 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
938 cmp(intf_klass, method_result);
939
940 if (peel) {
941 br(Assembler::EQ, found_method);
942 } else {
943 br(Assembler::NE, search);
944 // (invert the test to fall through to found_method...)
945 }
946
947 if (!peel) break;
948
949 bind(search);
950
951 // Check that the previous entry is non-null. A null entry means that
952 // the receiver class doesn't implement the interface, and wasn't the
953 // same as when the caller was compiled.
954 cbz(method_result, L_no_such_interface);
955 add(scan_temp, scan_temp, scan_step);
956 }
957
958 bind(found_method);
959
960 // Got a hit.
961 ldr(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
962 ldr(method_result, Address(recv_klass, scan_temp));
963 }
964
965 // virtual method calling
966 void MacroAssembler::lookup_virtual_method(Register recv_klass,
967 RegisterOrConstant vtable_index,
968 Register method_result) {
969 const int base = InstanceKlass::vtable_start_offset() * wordSize;
970 assert(vtableEntry::size() * wordSize == 8,
971 "adjust the scaling in the code below");
972 int vtable_offset_in_bytes = base + vtableEntry::method_offset_in_bytes();
973
974 if (vtable_index.is_register()) {
975 lea(method_result, Address(recv_klass,
976 vtable_index.as_register(),
977 Address::lsl(LogBytesPerWord)));
978 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
979 } else {
980 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
981 ldr(method_result, Address(recv_klass, vtable_offset_in_bytes));
982 }
983 }
984
985 void MacroAssembler::check_klass_subtype(Register sub_klass,
986 Register super_klass,
987 Register temp_reg,
988 Label& L_success) {
989 Label L_failure;
990 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
991 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
992 bind(L_failure);
993 }
994
995
996 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
997 Register super_klass,
998 Register temp_reg,
999 Label* L_success,
1000 Label* L_failure,
1001 Label* L_slow_path,
1002 RegisterOrConstant super_check_offset) {
1003 assert_different_registers(sub_klass, super_klass, temp_reg);
1004 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
1005 if (super_check_offset.is_register()) {
1006 assert_different_registers(sub_klass, super_klass,
1007 super_check_offset.as_register());
1008 } else if (must_load_sco) {
1009 assert(temp_reg != noreg, "supply either a temp or a register offset");
1010 }
1011
1012 Label L_fallthrough;
1013 int label_nulls = 0;
1014 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
1015 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
1016 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
1017 assert(label_nulls <= 1, "at most one NULL in the batch");
1018
1019 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1020 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1021 Address super_check_offset_addr(super_klass, sco_offset);
1022
1023 // Hacked jmp, which may only be used just before L_fallthrough.
1024 #define final_jmp(label) \
1025 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1026 else b(label) /*omit semi*/
1027
1028 // If the pointers are equal, we are done (e.g., String[] elements).
1029 // This self-check enables sharing of secondary supertype arrays among
1030 // non-primary types such as array-of-interface. Otherwise, each such
1031 // type would need its own customized SSA.
1032 // We move this check to the front of the fast path because many
1033 // type checks are in fact trivially successful in this manner,
1034 // so we get a nicely predicted branch right at the start of the check.
1035 cmp(sub_klass, super_klass);
1036 br(Assembler::EQ, *L_success);
1037
1038 // Check the supertype display:
1039 if (must_load_sco) {
1040 ldrw(temp_reg, super_check_offset_addr);
1041 super_check_offset = RegisterOrConstant(temp_reg);
1042 }
1043 Address super_check_addr(sub_klass, super_check_offset);
1044 ldr(rscratch1, super_check_addr);
1045 cmp(super_klass, rscratch1); // load displayed supertype
1046
1047 // This check has worked decisively for primary supers.
1048 // Secondary supers are sought in the super_cache ('super_cache_addr').
1049 // (Secondary supers are interfaces and very deeply nested subtypes.)
1050 // This works in the same check above because of a tricky aliasing
1051 // between the super_cache and the primary super display elements.
1052 // (The 'super_check_addr' can address either, as the case requires.)
1053 // Note that the cache is updated below if it does not help us find
1054 // what we need immediately.
1055 // So if it was a primary super, we can just fail immediately.
1056 // Otherwise, it's the slow path for us (no success at this point).
1057
1058 if (super_check_offset.is_register()) {
1059 br(Assembler::EQ, *L_success);
1060 cmp(super_check_offset.as_register(), sc_offset);
1061 if (L_failure == &L_fallthrough) {
1062 br(Assembler::EQ, *L_slow_path);
1063 } else {
1064 br(Assembler::NE, *L_failure);
1065 final_jmp(*L_slow_path);
1066 }
1067 } else if (super_check_offset.as_constant() == sc_offset) {
1068 // Need a slow path; fast failure is impossible.
1069 if (L_slow_path == &L_fallthrough) {
1070 br(Assembler::EQ, *L_success);
1071 } else {
1072 br(Assembler::NE, *L_slow_path);
1073 final_jmp(*L_success);
1074 }
1075 } else {
1076 // No slow path; it's a fast decision.
1077 if (L_failure == &L_fallthrough) {
1078 br(Assembler::EQ, *L_success);
1079 } else {
1080 br(Assembler::NE, *L_failure);
1081 final_jmp(*L_success);
1082 }
1083 }
1084
1085 bind(L_fallthrough);
1086
1087 #undef final_jmp
1088 }
1089
1090 // These two are taken from x86, but they look generally useful
1091
1092 // scans count pointer sized words at [addr] for occurence of value,
1093 // generic
1094 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1095 Register scratch) {
1096 Label Lloop, Lexit;
1097 cbz(count, Lexit);
1098 bind(Lloop);
1099 ldr(scratch, post(addr, wordSize));
1100 cmp(value, scratch);
1101 br(EQ, Lexit);
1102 sub(count, count, 1);
1103 cbnz(count, Lloop);
1104 bind(Lexit);
1105 }
1106
1107 // scans count 4 byte words at [addr] for occurence of value,
1108 // generic
1109 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1110 Register scratch) {
1111 Label Lloop, Lexit;
1112 cbz(count, Lexit);
1113 bind(Lloop);
1114 ldrw(scratch, post(addr, wordSize));
1115 cmpw(value, scratch);
1116 br(EQ, Lexit);
1117 sub(count, count, 1);
1118 cbnz(count, Lloop);
1119 bind(Lexit);
1120 }
1121
1122 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1123 Register super_klass,
1124 Register temp_reg,
1125 Register temp2_reg,
1126 Label* L_success,
1127 Label* L_failure,
1128 bool set_cond_codes) {
1129 assert_different_registers(sub_klass, super_klass, temp_reg);
1130 if (temp2_reg != noreg)
1131 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1132 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1133
1134 Label L_fallthrough;
1135 int label_nulls = 0;
1136 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
1137 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
1138 assert(label_nulls <= 1, "at most one NULL in the batch");
1139
1140 // a couple of useful fields in sub_klass:
1141 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1142 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1143 Address secondary_supers_addr(sub_klass, ss_offset);
1144 Address super_cache_addr( sub_klass, sc_offset);
1145
1146 BLOCK_COMMENT("check_klass_subtype_slow_path");
1147
1148 // Do a linear scan of the secondary super-klass chain.
1149 // This code is rarely used, so simplicity is a virtue here.
1150 // The repne_scan instruction uses fixed registers, which we must spill.
1151 // Don't worry too much about pre-existing connections with the input regs.
1152
1153 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1154 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1155
1156 // Get super_klass value into r0 (even if it was in r5 or r2).
1157 RegSet pushed_registers;
1158 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1159 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1160
1161 if (super_klass != r0 || UseCompressedOops) {
1162 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1163 }
1164
1165 push(pushed_registers, sp);
1166
1167 #ifndef PRODUCT
1168 mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr);
1169 Address pst_counter_addr(rscratch2);
1170 ldr(rscratch1, pst_counter_addr);
1171 add(rscratch1, rscratch1, 1);
1172 str(rscratch1, pst_counter_addr);
1173 #endif //PRODUCT
1174
1175 // We will consult the secondary-super array.
1176 ldr(r5, secondary_supers_addr);
1177 // Load the array length.
1178 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1179 // Skip to start of data.
1180 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1181
1182 cmp(sp, zr); // Clear Z flag; SP is never zero
1183 // Scan R2 words at [R5] for an occurrence of R0.
1184 // Set NZ/Z based on last compare.
1185 repne_scan(r5, r0, r2, rscratch1);
1186
1187 // Unspill the temp. registers:
1188 pop(pushed_registers, sp);
1189
1190 br(Assembler::NE, *L_failure);
1191
1192 // Success. Cache the super we found and proceed in triumph.
1193 str(super_klass, super_cache_addr);
1194
1195 if (L_success != &L_fallthrough) {
1196 b(*L_success);
1197 }
1198
1199 #undef IS_A_TEMP
1200
1201 bind(L_fallthrough);
1202 }
1203
1204
1205 void MacroAssembler::verify_oop(Register reg, const char* s) {
1206 if (!VerifyOops) return;
1207
1208 // Pass register number to verify_oop_subroutine
1209 const char* b = NULL;
1210 {
1211 ResourceMark rm;
1212 stringStream ss;
1213 ss.print("verify_oop: %s: %s", reg->name(), s);
1214 b = code_string(ss.as_string());
1215 }
1216 BLOCK_COMMENT("verify_oop {");
1217
1218 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1219 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1220
1221 mov(r0, reg);
1222 mov(rscratch1, (address)b);
1223
1224 // call indirectly to solve generation ordering problem
1225 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1226 ldr(rscratch2, Address(rscratch2));
1227 blr(rscratch2);
1228
1229 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1230 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1231
1232 BLOCK_COMMENT("} verify_oop");
1233 }
1234
1235 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
1236 if (!VerifyOops) return;
1237
1238 const char* b = NULL;
1239 {
1240 ResourceMark rm;
1241 stringStream ss;
1242 ss.print("verify_oop_addr: %s", s);
1243 b = code_string(ss.as_string());
1244 }
1245 BLOCK_COMMENT("verify_oop_addr {");
1246
1247 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1248 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1249
1250 // addr may contain sp so we will have to adjust it based on the
1251 // pushes that we just did.
1252 if (addr.uses(sp)) {
1253 lea(r0, addr);
1254 ldr(r0, Address(r0, 4 * wordSize));
1255 } else {
1256 ldr(r0, addr);
1257 }
1258 mov(rscratch1, (address)b);
1259
1260 // call indirectly to solve generation ordering problem
1261 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1262 ldr(rscratch2, Address(rscratch2));
1263 blr(rscratch2);
1264
1265 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1266 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1267
1268 BLOCK_COMMENT("} verify_oop_addr");
1269 }
1270
1271 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
1272 int extra_slot_offset) {
1273 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
1274 int stackElementSize = Interpreter::stackElementSize;
1275 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
1276 #ifdef ASSERT
1277 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
1278 assert(offset1 - offset == stackElementSize, "correct arithmetic");
1279 #endif
1280 if (arg_slot.is_constant()) {
1281 return Address(esp, arg_slot.as_constant() * stackElementSize
1282 + offset);
1283 } else {
1284 add(rscratch1, esp, arg_slot.as_register(),
1285 ext::uxtx, exact_log2(stackElementSize));
1286 return Address(rscratch1, offset);
1287 }
1288 }
1289
1290 void MacroAssembler::call_VM_leaf_base(address entry_point,
1291 int number_of_arguments,
1292 Label *retaddr) {
1293 call_VM_leaf_base1(entry_point, number_of_arguments, 0, ret_type_integral, retaddr);
1294 }
1295
1296 void MacroAssembler::call_VM_leaf_base1(address entry_point,
1297 int number_of_gp_arguments,
1298 int number_of_fp_arguments,
1299 ret_type type,
1300 Label *retaddr) {
1301 Label E, L;
1302
1303 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
1304
1305 // We add 1 to number_of_arguments because the thread in arg0 is
1306 // not counted
1307 mov(rscratch1, entry_point);
1308 blrt(rscratch1, number_of_gp_arguments + 1, number_of_fp_arguments, type);
1309 if (retaddr)
1310 bind(*retaddr);
1311
1312 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
1313 maybe_isb();
1314 }
1315
1316 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1317 call_VM_leaf_base(entry_point, number_of_arguments);
1318 }
1319
1320 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1321 pass_arg0(this, arg_0);
1322 call_VM_leaf_base(entry_point, 1);
1323 }
1324
1325 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1326 pass_arg0(this, arg_0);
1327 pass_arg1(this, arg_1);
1328 call_VM_leaf_base(entry_point, 2);
1329 }
1330
1331 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1332 Register arg_1, Register arg_2) {
1333 pass_arg0(this, arg_0);
1334 pass_arg1(this, arg_1);
1335 pass_arg2(this, arg_2);
1336 call_VM_leaf_base(entry_point, 3);
1337 }
1338
1339 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1340 pass_arg0(this, arg_0);
1341 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1342 }
1343
1344 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1345
1346 assert(arg_0 != c_rarg1, "smashed arg");
1347 pass_arg1(this, arg_1);
1348 pass_arg0(this, arg_0);
1349 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1350 }
1351
1352 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1353 assert(arg_0 != c_rarg2, "smashed arg");
1354 assert(arg_1 != c_rarg2, "smashed arg");
1355 pass_arg2(this, arg_2);
1356 assert(arg_0 != c_rarg1, "smashed arg");
1357 pass_arg1(this, arg_1);
1358 pass_arg0(this, arg_0);
1359 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1360 }
1361
1362 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1363 assert(arg_0 != c_rarg3, "smashed arg");
1364 assert(arg_1 != c_rarg3, "smashed arg");
1365 assert(arg_2 != c_rarg3, "smashed arg");
1366 pass_arg3(this, arg_3);
1367 assert(arg_0 != c_rarg2, "smashed arg");
1368 assert(arg_1 != c_rarg2, "smashed arg");
1369 pass_arg2(this, arg_2);
1370 assert(arg_0 != c_rarg1, "smashed arg");
1371 pass_arg1(this, arg_1);
1372 pass_arg0(this, arg_0);
1373 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1374 }
1375
1376 void MacroAssembler::null_check(Register reg, int offset) {
1377 if (needs_explicit_null_check(offset)) {
1378 // provoke OS NULL exception if reg = NULL by
1379 // accessing M[reg] w/o changing any registers
1380 // NOTE: this is plenty to provoke a segv
1381 ldr(zr, Address(reg));
1382 } else {
1383 // nothing to do, (later) access of M[reg + offset]
1384 // will provoke OS NULL exception if reg = NULL
1385 }
1386 }
1387
1388 // MacroAssembler protected routines needed to implement
1389 // public methods
1390
1391 void MacroAssembler::mov(Register r, Address dest) {
1392 code_section()->relocate(pc(), dest.rspec());
1393 u_int64_t imm64 = (u_int64_t)dest.target();
1394 movptr(r, imm64);
1395 }
1396
1397 // Move a constant pointer into r. In AArch64 mode the virtual
1398 // address space is 48 bits in size, so we only need three
1399 // instructions to create a patchable instruction sequence that can
1400 // reach anywhere.
1401 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
1402 #ifndef PRODUCT
1403 {
1404 char buffer[64];
1405 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
1406 block_comment(buffer);
1407 }
1408 #endif
1409 assert(imm64 < (1ul << 48), "48-bit overflow in address constant");
1410 movz(r, imm64 & 0xffff);
1411 imm64 >>= 16;
1412 movk(r, imm64 & 0xffff, 16);
1413 imm64 >>= 16;
1414 movk(r, imm64 & 0xffff, 32);
1415 }
1416
1417 // Macro to mov replicated immediate to vector register.
1418 // Vd will get the following values for different arrangements in T
1419 // imm32 == hex 000000gh T8B: Vd = ghghghghghghghgh
1420 // imm32 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
1421 // imm32 == hex 0000efgh T4H: Vd = efghefghefghefgh
1422 // imm32 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
1423 // imm32 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
1424 // imm32 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
1425 // T1D/T2D: invalid
1426 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) {
1427 assert(T != T1D && T != T2D, "invalid arrangement");
1428 if (T == T8B || T == T16B) {
1429 assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)");
1430 movi(Vd, T, imm32 & 0xff, 0);
1431 return;
1432 }
1433 u_int32_t nimm32 = ~imm32;
1434 if (T == T4H || T == T8H) {
1435 assert((imm32 & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)");
1436 imm32 &= 0xffff;
1437 nimm32 &= 0xffff;
1438 }
1439 u_int32_t x = imm32;
1440 int movi_cnt = 0;
1441 int movn_cnt = 0;
1442 while (x) { if (x & 0xff) movi_cnt++; x >>= 8; }
1443 x = nimm32;
1444 while (x) { if (x & 0xff) movn_cnt++; x >>= 8; }
1445 if (movn_cnt < movi_cnt) imm32 = nimm32;
1446 unsigned lsl = 0;
1447 while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
1448 if (movn_cnt < movi_cnt)
1449 mvni(Vd, T, imm32 & 0xff, lsl);
1450 else
1451 movi(Vd, T, imm32 & 0xff, lsl);
1452 imm32 >>= 8; lsl += 8;
1453 while (imm32) {
1454 while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
1455 if (movn_cnt < movi_cnt)
1456 bici(Vd, T, imm32 & 0xff, lsl);
1457 else
1458 orri(Vd, T, imm32 & 0xff, lsl);
1459 lsl += 8; imm32 >>= 8;
1460 }
1461 }
1462
1463 void MacroAssembler::mov_immediate64(Register dst, u_int64_t imm64)
1464 {
1465 #ifndef PRODUCT
1466 {
1467 char buffer[64];
1468 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
1469 block_comment(buffer);
1470 }
1471 #endif
1472 if (operand_valid_for_logical_immediate(false, imm64)) {
1473 orr(dst, zr, imm64);
1474 } else {
1475 // we can use a combination of MOVZ or MOVN with
1476 // MOVK to build up the constant
1477 u_int64_t imm_h[4];
1478 int zero_count = 0;
1479 int neg_count = 0;
1480 int i;
1481 for (i = 0; i < 4; i++) {
1482 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
1483 if (imm_h[i] == 0) {
1484 zero_count++;
1485 } else if (imm_h[i] == 0xffffL) {
1486 neg_count++;
1487 }
1488 }
1489 if (zero_count == 4) {
1490 // one MOVZ will do
1491 movz(dst, 0);
1492 } else if (neg_count == 4) {
1493 // one MOVN will do
1494 movn(dst, 0);
1495 } else if (zero_count == 3) {
1496 for (i = 0; i < 4; i++) {
1497 if (imm_h[i] != 0L) {
1498 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1499 break;
1500 }
1501 }
1502 } else if (neg_count == 3) {
1503 // one MOVN will do
1504 for (int i = 0; i < 4; i++) {
1505 if (imm_h[i] != 0xffffL) {
1506 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1507 break;
1508 }
1509 }
1510 } else if (zero_count == 2) {
1511 // one MOVZ and one MOVK will do
1512 for (i = 0; i < 3; i++) {
1513 if (imm_h[i] != 0L) {
1514 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1515 i++;
1516 break;
1517 }
1518 }
1519 for (;i < 4; i++) {
1520 if (imm_h[i] != 0L) {
1521 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1522 }
1523 }
1524 } else if (neg_count == 2) {
1525 // one MOVN and one MOVK will do
1526 for (i = 0; i < 4; i++) {
1527 if (imm_h[i] != 0xffffL) {
1528 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1529 i++;
1530 break;
1531 }
1532 }
1533 for (;i < 4; i++) {
1534 if (imm_h[i] != 0xffffL) {
1535 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1536 }
1537 }
1538 } else if (zero_count == 1) {
1539 // one MOVZ and two MOVKs will do
1540 for (i = 0; i < 4; i++) {
1541 if (imm_h[i] != 0L) {
1542 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1543 i++;
1544 break;
1545 }
1546 }
1547 for (;i < 4; i++) {
1548 if (imm_h[i] != 0x0L) {
1549 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1550 }
1551 }
1552 } else if (neg_count == 1) {
1553 // one MOVN and two MOVKs will do
1554 for (i = 0; i < 4; i++) {
1555 if (imm_h[i] != 0xffffL) {
1556 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1557 i++;
1558 break;
1559 }
1560 }
1561 for (;i < 4; i++) {
1562 if (imm_h[i] != 0xffffL) {
1563 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1564 }
1565 }
1566 } else {
1567 // use a MOVZ and 3 MOVKs (makes it easier to debug)
1568 movz(dst, (u_int32_t)imm_h[0], 0);
1569 for (i = 1; i < 4; i++) {
1570 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1571 }
1572 }
1573 }
1574 }
1575
1576 void MacroAssembler::mov_immediate32(Register dst, u_int32_t imm32)
1577 {
1578 #ifndef PRODUCT
1579 {
1580 char buffer[64];
1581 snprintf(buffer, sizeof(buffer), "0x%"PRIX32, imm32);
1582 block_comment(buffer);
1583 }
1584 #endif
1585 if (operand_valid_for_logical_immediate(true, imm32)) {
1586 orrw(dst, zr, imm32);
1587 } else {
1588 // we can use MOVZ, MOVN or two calls to MOVK to build up the
1589 // constant
1590 u_int32_t imm_h[2];
1591 imm_h[0] = imm32 & 0xffff;
1592 imm_h[1] = ((imm32 >> 16) & 0xffff);
1593 if (imm_h[0] == 0) {
1594 movzw(dst, imm_h[1], 16);
1595 } else if (imm_h[0] == 0xffff) {
1596 movnw(dst, imm_h[1] ^ 0xffff, 16);
1597 } else if (imm_h[1] == 0) {
1598 movzw(dst, imm_h[0], 0);
1599 } else if (imm_h[1] == 0xffff) {
1600 movnw(dst, imm_h[0] ^ 0xffff, 0);
1601 } else {
1602 // use a MOVZ and MOVK (makes it easier to debug)
1603 movzw(dst, imm_h[0], 0);
1604 movkw(dst, imm_h[1], 16);
1605 }
1606 }
1607 }
1608
1609 // Form an address from base + offset in Rd. Rd may or may
1610 // not actually be used: you must use the Address that is returned.
1611 // It is up to you to ensure that the shift provided matches the size
1612 // of your data.
1613 Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) {
1614 if (Address::offset_ok_for_immed(byte_offset, shift))
1615 // It fits; no need for any heroics
1616 return Address(base, byte_offset);
1617
1618 // Don't do anything clever with negative or misaligned offsets
1619 unsigned mask = (1 << shift) - 1;
1620 if (byte_offset < 0 || byte_offset & mask) {
1621 mov(Rd, byte_offset);
1622 add(Rd, base, Rd);
1623 return Address(Rd);
1624 }
1625
1626 // See if we can do this with two 12-bit offsets
1627 {
1628 unsigned long word_offset = byte_offset >> shift;
1629 unsigned long masked_offset = word_offset & 0xfff000;
1630 if (Address::offset_ok_for_immed(word_offset - masked_offset)
1631 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
1632 add(Rd, base, masked_offset << shift);
1633 word_offset -= masked_offset;
1634 return Address(Rd, word_offset << shift);
1635 }
1636 }
1637
1638 // Do it the hard way
1639 mov(Rd, byte_offset);
1640 add(Rd, base, Rd);
1641 return Address(Rd);
1642 }
1643
1644 void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) {
1645 Label retry_load;
1646 bind(retry_load);
1647 // flush and load exclusive from the memory location
1648 ldxrw(tmp, counter_addr);
1649 addw(tmp, tmp, 1);
1650 // if we store+flush with no intervening write tmp wil be zero
1651 stxrw(tmp2, tmp, counter_addr);
1652 cbnzw(tmp2, retry_load);
1653 }
1654
1655
1656 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
1657 bool want_remainder, Register scratch)
1658 {
1659 // Full implementation of Java idiv and irem. The function
1660 // returns the (pc) offset of the div instruction - may be needed
1661 // for implicit exceptions.
1662 //
1663 // constraint : ra/rb =/= scratch
1664 // normal case
1665 //
1666 // input : ra: dividend
1667 // rb: divisor
1668 //
1669 // result: either
1670 // quotient (= ra idiv rb)
1671 // remainder (= ra irem rb)
1672
1673 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
1674
1675 int idivl_offset = offset();
1676 if (! want_remainder) {
1677 sdivw(result, ra, rb);
1678 } else {
1679 sdivw(scratch, ra, rb);
1680 Assembler::msubw(result, scratch, rb, ra);
1681 }
1682
1683 return idivl_offset;
1684 }
1685
1686 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
1687 bool want_remainder, Register scratch)
1688 {
1689 // Full implementation of Java ldiv and lrem. The function
1690 // returns the (pc) offset of the div instruction - may be needed
1691 // for implicit exceptions.
1692 //
1693 // constraint : ra/rb =/= scratch
1694 // normal case
1695 //
1696 // input : ra: dividend
1697 // rb: divisor
1698 //
1699 // result: either
1700 // quotient (= ra idiv rb)
1701 // remainder (= ra irem rb)
1702
1703 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
1704
1705 int idivq_offset = offset();
1706 if (! want_remainder) {
1707 sdiv(result, ra, rb);
1708 } else {
1709 sdiv(scratch, ra, rb);
1710 Assembler::msub(result, scratch, rb, ra);
1711 }
1712
1713 return idivq_offset;
1714 }
1715
1716 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
1717 address prev = pc() - NativeMembar::instruction_size;
1718 if (prev == code()->last_membar()) {
1719 NativeMembar *bar = NativeMembar_at(prev);
1720 // We are merging two memory barrier instructions. On AArch64 we
1721 // can do this simply by ORing them together.
1722 bar->set_kind(bar->get_kind() | order_constraint);
1723 BLOCK_COMMENT("merged membar");
1724 } else {
1725 code()->set_last_membar(pc());
1726 dmb(Assembler::barrier(order_constraint));
1727 }
1728 }
1729
1730 // MacroAssembler routines found actually to be needed
1731
1732 void MacroAssembler::push(Register src)
1733 {
1734 str(src, Address(pre(esp, -1 * wordSize)));
1735 }
1736
1737 void MacroAssembler::pop(Register dst)
1738 {
1739 ldr(dst, Address(post(esp, 1 * wordSize)));
1740 }
1741
1742 // Note: load_unsigned_short used to be called load_unsigned_word.
1743 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1744 int off = offset();
1745 ldrh(dst, src);
1746 return off;
1747 }
1748
1749 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1750 int off = offset();
1751 ldrb(dst, src);
1752 return off;
1753 }
1754
1755 int MacroAssembler::load_signed_short(Register dst, Address src) {
1756 int off = offset();
1757 ldrsh(dst, src);
1758 return off;
1759 }
1760
1761 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1762 int off = offset();
1763 ldrsb(dst, src);
1764 return off;
1765 }
1766
1767 int MacroAssembler::load_signed_short32(Register dst, Address src) {
1768 int off = offset();
1769 ldrshw(dst, src);
1770 return off;
1771 }
1772
1773 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
1774 int off = offset();
1775 ldrsbw(dst, src);
1776 return off;
1777 }
1778
1779 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1780 switch (size_in_bytes) {
1781 case 8: ldr(dst, src); break;
1782 case 4: ldrw(dst, src); break;
1783 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1784 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1785 default: ShouldNotReachHere();
1786 }
1787 }
1788
1789 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1790 switch (size_in_bytes) {
1791 case 8: str(src, dst); break;
1792 case 4: strw(src, dst); break;
1793 case 2: strh(src, dst); break;
1794 case 1: strb(src, dst); break;
1795 default: ShouldNotReachHere();
1796 }
1797 }
1798
1799 void MacroAssembler::decrementw(Register reg, int value)
1800 {
1801 if (value < 0) { incrementw(reg, -value); return; }
1802 if (value == 0) { return; }
1803 if (value < (1 << 12)) { subw(reg, reg, value); return; }
1804 /* else */ {
1805 guarantee(reg != rscratch2, "invalid dst for register decrement");
1806 movw(rscratch2, (unsigned)value);
1807 subw(reg, reg, rscratch2);
1808 }
1809 }
1810
1811 void MacroAssembler::decrement(Register reg, int value)
1812 {
1813 if (value < 0) { increment(reg, -value); return; }
1814 if (value == 0) { return; }
1815 if (value < (1 << 12)) { sub(reg, reg, value); return; }
1816 /* else */ {
1817 assert(reg != rscratch2, "invalid dst for register decrement");
1818 mov(rscratch2, (unsigned long)value);
1819 sub(reg, reg, rscratch2);
1820 }
1821 }
1822
1823 void MacroAssembler::decrementw(Address dst, int value)
1824 {
1825 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
1826 ldrw(rscratch1, dst);
1827 decrementw(rscratch1, value);
1828 strw(rscratch1, dst);
1829 }
1830
1831 void MacroAssembler::decrement(Address dst, int value)
1832 {
1833 assert(!dst.uses(rscratch1), "invalid address for decrement");
1834 ldr(rscratch1, dst);
1835 decrement(rscratch1, value);
1836 str(rscratch1, dst);
1837 }
1838
1839 void MacroAssembler::incrementw(Register reg, int value)
1840 {
1841 if (value < 0) { decrementw(reg, -value); return; }
1842 if (value == 0) { return; }
1843 if (value < (1 << 12)) { addw(reg, reg, value); return; }
1844 /* else */ {
1845 assert(reg != rscratch2, "invalid dst for register increment");
1846 movw(rscratch2, (unsigned)value);
1847 addw(reg, reg, rscratch2);
1848 }
1849 }
1850
1851 void MacroAssembler::increment(Register reg, int value)
1852 {
1853 if (value < 0) { decrement(reg, -value); return; }
1854 if (value == 0) { return; }
1855 if (value < (1 << 12)) { add(reg, reg, value); return; }
1856 /* else */ {
1857 assert(reg != rscratch2, "invalid dst for register increment");
1858 movw(rscratch2, (unsigned)value);
1859 add(reg, reg, rscratch2);
1860 }
1861 }
1862
1863 void MacroAssembler::incrementw(Address dst, int value)
1864 {
1865 assert(!dst.uses(rscratch1), "invalid dst for address increment");
1866 ldrw(rscratch1, dst);
1867 incrementw(rscratch1, value);
1868 strw(rscratch1, dst);
1869 }
1870
1871 void MacroAssembler::increment(Address dst, int value)
1872 {
1873 assert(!dst.uses(rscratch1), "invalid dst for address increment");
1874 ldr(rscratch1, dst);
1875 increment(rscratch1, value);
1876 str(rscratch1, dst);
1877 }
1878
1879
1880 void MacroAssembler::pusha() {
1881 push(0x7fffffff, sp);
1882 }
1883
1884 void MacroAssembler::popa() {
1885 pop(0x7fffffff, sp);
1886 }
1887
1888 // Push lots of registers in the bit set supplied. Don't push sp.
1889 // Return the number of words pushed
1890 int MacroAssembler::push(unsigned int bitset, Register stack) {
1891 int words_pushed = 0;
1892
1893 // Scan bitset to accumulate register pairs
1894 unsigned char regs[32];
1895 int count = 0;
1896 for (int reg = 0; reg <= 30; reg++) {
1897 if (1 & bitset)
1898 regs[count++] = reg;
1899 bitset >>= 1;
1900 }
1901 regs[count++] = zr->encoding_nocheck();
1902 count &= ~1; // Only push an even nuber of regs
1903
1904 if (count) {
1905 stp(as_Register(regs[0]), as_Register(regs[1]),
1906 Address(pre(stack, -count * wordSize)));
1907 words_pushed += 2;
1908 }
1909 for (int i = 2; i < count; i += 2) {
1910 stp(as_Register(regs[i]), as_Register(regs[i+1]),
1911 Address(stack, i * wordSize));
1912 words_pushed += 2;
1913 }
1914
1915 assert(words_pushed == count, "oops, pushed != count");
1916
1917 return count;
1918 }
1919
1920 int MacroAssembler::pop(unsigned int bitset, Register stack) {
1921 int words_pushed = 0;
1922
1923 // Scan bitset to accumulate register pairs
1924 unsigned char regs[32];
1925 int count = 0;
1926 for (int reg = 0; reg <= 30; reg++) {
1927 if (1 & bitset)
1928 regs[count++] = reg;
1929 bitset >>= 1;
1930 }
1931 regs[count++] = zr->encoding_nocheck();
1932 count &= ~1;
1933
1934 for (int i = 2; i < count; i += 2) {
1935 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
1936 Address(stack, i * wordSize));
1937 words_pushed += 2;
1938 }
1939 if (count) {
1940 ldp(as_Register(regs[0]), as_Register(regs[1]),
1941 Address(post(stack, count * wordSize)));
1942 words_pushed += 2;
1943 }
1944
1945 assert(words_pushed == count, "oops, pushed != count");
1946
1947 return count;
1948 }
1949 #ifdef ASSERT
1950 void MacroAssembler::verify_heapbase(const char* msg) {
1951 #if 0
1952 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
1953 assert (Universe::heap() != NULL, "java heap should be initialized");
1954 if (CheckCompressedOops) {
1955 Label ok;
1956 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
1957 cmpptr(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
1958 br(Assembler::EQ, ok);
1959 stop(msg);
1960 bind(ok);
1961 pop(1 << rscratch1->encoding(), sp);
1962 }
1963 #endif
1964 }
1965 #endif
1966
1967 void MacroAssembler::stop(const char* msg) {
1968 address ip = pc();
1969 pusha();
1970 mov(c_rarg0, (address)msg);
1971 mov(c_rarg1, (address)ip);
1972 mov(c_rarg2, sp);
1973 mov(c_rarg3, CAST_FROM_FN_PTR(address, MacroAssembler::debug64));
1974 // call(c_rarg3);
1975 blrt(c_rarg3, 3, 0, 1);
1976 hlt(0);
1977 }
1978
1979 // If a constant does not fit in an immediate field, generate some
1980 // number of MOV instructions and then perform the operation.
1981 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1982 add_sub_imm_insn insn1,
1983 add_sub_reg_insn insn2) {
1984 assert(Rd != zr, "Rd = zr and not setting flags?");
1985 if (operand_valid_for_add_sub_immediate((int)imm)) {
1986 (this->*insn1)(Rd, Rn, imm);
1987 } else {
1988 if (uabs(imm) < (1 << 24)) {
1989 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
1990 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
1991 } else {
1992 assert_different_registers(Rd, Rn);
1993 mov(Rd, (uint64_t)imm);
1994 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
1995 }
1996 }
1997 }
1998
1999 // Seperate vsn which sets the flags. Optimisations are more restricted
2000 // because we must set the flags correctly.
2001 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
2002 add_sub_imm_insn insn1,
2003 add_sub_reg_insn insn2) {
2004 if (operand_valid_for_add_sub_immediate((int)imm)) {
2005 (this->*insn1)(Rd, Rn, imm);
2006 } else {
2007 assert_different_registers(Rd, Rn);
2008 assert(Rd != zr, "overflow in immediate operand");
2009 mov(Rd, (uint64_t)imm);
2010 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
2011 }
2012 }
2013
2014
2015 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
2016 if (increment.is_register()) {
2017 add(Rd, Rn, increment.as_register());
2018 } else {
2019 add(Rd, Rn, increment.as_constant());
2020 }
2021 }
2022
2023 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
2024 if (increment.is_register()) {
2025 addw(Rd, Rn, increment.as_register());
2026 } else {
2027 addw(Rd, Rn, increment.as_constant());
2028 }
2029 }
2030
2031 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
2032 if (decrement.is_register()) {
2033 sub(Rd, Rn, decrement.as_register());
2034 } else {
2035 sub(Rd, Rn, decrement.as_constant());
2036 }
2037 }
2038
2039 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
2040 if (decrement.is_register()) {
2041 subw(Rd, Rn, decrement.as_register());
2042 } else {
2043 subw(Rd, Rn, decrement.as_constant());
2044 }
2045 }
2046
2047 void MacroAssembler::reinit_heapbase()
2048 {
2049 if (UseCompressedOops) {
2050 if (Universe::is_fully_initialized()) {
2051 mov(rheapbase, Universe::narrow_ptrs_base());
2052 } else {
2053 lea(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
2054 ldr(rheapbase, Address(rheapbase));
2055 }
2056 }
2057 }
2058
2059 // this simulates the behaviour of the x86 cmpxchg instruction using a
2060 // load linked/store conditional pair. we use the acquire/release
2061 // versions of these instructions so that we flush pending writes as
2062 // per Java semantics.
2063
2064 // n.b the x86 version assumes the old value to be compared against is
2065 // in rax and updates rax with the value located in memory if the
2066 // cmpxchg fails. we supply a register for the old value explicitly
2067
2068 // the aarch64 load linked/store conditional instructions do not
2069 // accept an offset. so, unlike x86, we must provide a plain register
2070 // to identify the memory word to be compared/exchanged rather than a
2071 // register+offset Address.
2072
2073 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
2074 Label &succeed, Label *fail) {
2075 // oldv holds comparison value
2076 // newv holds value to write in exchange
2077 // addr identifies memory word to compare against/update
2078 // tmp returns 0/1 for success/failure
2079 Label retry_load, nope;
2080
2081 bind(retry_load);
2082 // flush and load exclusive from the memory location
2083 // and fail if it is not what we expect
2084 ldaxr(tmp, addr);
2085 cmp(tmp, oldv);
2086 br(Assembler::NE, nope);
2087 // if we store+flush with no intervening write tmp wil be zero
2088 stlxr(tmp, newv, addr);
2089 cbzw(tmp, succeed);
2090 // retry so we only ever return after a load fails to compare
2091 // ensures we don't return a stale value after a failed write.
2092 b(retry_load);
2093 // if the memory word differs we return it in oldv and signal a fail
2094 bind(nope);
2095 membar(AnyAny);
2096 mov(oldv, tmp);
2097 if (fail)
2098 b(*fail);
2099 }
2100
2101 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
2102 Label &succeed, Label *fail) {
2103 // oldv holds comparison value
2104 // newv holds value to write in exchange
2105 // addr identifies memory word to compare against/update
2106 // tmp returns 0/1 for success/failure
2107 Label retry_load, nope;
2108
2109 bind(retry_load);
2110 // flush and load exclusive from the memory location
2111 // and fail if it is not what we expect
2112 ldaxrw(tmp, addr);
2113 cmp(tmp, oldv);
2114 br(Assembler::NE, nope);
2115 // if we store+flush with no intervening write tmp wil be zero
2116 stlxrw(tmp, newv, addr);
2117 cbzw(tmp, succeed);
2118 // retry so we only ever return after a load fails to compare
2119 // ensures we don't return a stale value after a failed write.
2120 b(retry_load);
2121 // if the memory word differs we return it in oldv and signal a fail
2122 bind(nope);
2123 membar(AnyAny);
2124 mov(oldv, tmp);
2125 if (fail)
2126 b(*fail);
2127 }
2128
2129 static bool different(Register a, RegisterOrConstant b, Register c) {
2130 if (b.is_constant())
2131 return a != c;
2132 else
2133 return a != b.as_register() && a != c && b.as_register() != c;
2134 }
2135
2136 #define ATOMIC_OP(LDXR, OP, IOP, STXR) \
2137 void MacroAssembler::atomic_##OP(Register prev, RegisterOrConstant incr, Register addr) { \
2138 Register result = rscratch2; \
2139 if (prev->is_valid()) \
2140 result = different(prev, incr, addr) ? prev : rscratch2; \
2141 \
2142 Label retry_load; \
2143 bind(retry_load); \
2144 LDXR(result, addr); \
2145 OP(rscratch1, result, incr); \
2146 STXR(rscratch2, rscratch1, addr); \
2147 cbnzw(rscratch2, retry_load); \
2148 if (prev->is_valid() && prev != result) { \
2149 IOP(prev, rscratch1, incr); \
2150 } \
2151 }
2152
2153 ATOMIC_OP(ldxr, add, sub, stxr)
2154 ATOMIC_OP(ldxrw, addw, subw, stxrw)
2155
2156 #undef ATOMIC_OP
2157
2158 #define ATOMIC_XCHG(OP, LDXR, STXR) \
2159 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
2160 Register result = rscratch2; \
2161 if (prev->is_valid()) \
2162 result = different(prev, newv, addr) ? prev : rscratch2; \
2163 \
2164 Label retry_load; \
2165 bind(retry_load); \
2166 LDXR(result, addr); \
2167 STXR(rscratch1, newv, addr); \
2168 cbnzw(rscratch1, retry_load); \
2169 if (prev->is_valid() && prev != result) \
2170 mov(prev, result); \
2171 }
2172
2173 ATOMIC_XCHG(xchg, ldxr, stxr)
2174 ATOMIC_XCHG(xchgw, ldxrw, stxrw)
2175
2176 #undef ATOMIC_XCHG
2177
2178 void MacroAssembler::incr_allocated_bytes(Register thread,
2179 Register var_size_in_bytes,
2180 int con_size_in_bytes,
2181 Register t1) {
2182 if (!thread->is_valid()) {
2183 thread = rthread;
2184 }
2185 assert(t1->is_valid(), "need temp reg");
2186
2187 ldr(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset())));
2188 if (var_size_in_bytes->is_valid()) {
2189 add(t1, t1, var_size_in_bytes);
2190 } else {
2191 add(t1, t1, con_size_in_bytes);
2192 }
2193 str(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset())));
2194 }
2195
2196 #ifndef PRODUCT
2197 extern "C" void findpc(intptr_t x);
2198 #endif
2199
2200 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
2201 {
2202 // In order to get locks to work, we need to fake a in_VM state
2203 if (ShowMessageBoxOnError ) {
2204 JavaThread* thread = JavaThread::current();
2205 JavaThreadState saved_state = thread->thread_state();
2206 thread->set_thread_state(_thread_in_vm);
2207 #ifndef PRODUCT
2208 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
2209 ttyLocker ttyl;
2210 BytecodeCounter::print();
2211 }
2212 #endif
2213 if (os::message_box(msg, "Execution stopped, print registers?")) {
2214 ttyLocker ttyl;
2215 tty->print_cr(" pc = 0x%016lx", pc);
2216 #ifndef PRODUCT
2217 tty->cr();
2218 findpc(pc);
2219 tty->cr();
2220 #endif
2221 tty->print_cr(" r0 = 0x%016lx", regs[0]);
2222 tty->print_cr(" r1 = 0x%016lx", regs[1]);
2223 tty->print_cr(" r2 = 0x%016lx", regs[2]);
2224 tty->print_cr(" r3 = 0x%016lx", regs[3]);
2225 tty->print_cr(" r4 = 0x%016lx", regs[4]);
2226 tty->print_cr(" r5 = 0x%016lx", regs[5]);
2227 tty->print_cr(" r6 = 0x%016lx", regs[6]);
2228 tty->print_cr(" r7 = 0x%016lx", regs[7]);
2229 tty->print_cr(" r8 = 0x%016lx", regs[8]);
2230 tty->print_cr(" r9 = 0x%016lx", regs[9]);
2231 tty->print_cr("r10 = 0x%016lx", regs[10]);
2232 tty->print_cr("r11 = 0x%016lx", regs[11]);
2233 tty->print_cr("r12 = 0x%016lx", regs[12]);
2234 tty->print_cr("r13 = 0x%016lx", regs[13]);
2235 tty->print_cr("r14 = 0x%016lx", regs[14]);
2236 tty->print_cr("r15 = 0x%016lx", regs[15]);
2237 tty->print_cr("r16 = 0x%016lx", regs[16]);
2238 tty->print_cr("r17 = 0x%016lx", regs[17]);
2239 tty->print_cr("r18 = 0x%016lx", regs[18]);
2240 tty->print_cr("r19 = 0x%016lx", regs[19]);
2241 tty->print_cr("r20 = 0x%016lx", regs[20]);
2242 tty->print_cr("r21 = 0x%016lx", regs[21]);
2243 tty->print_cr("r22 = 0x%016lx", regs[22]);
2244 tty->print_cr("r23 = 0x%016lx", regs[23]);
2245 tty->print_cr("r24 = 0x%016lx", regs[24]);
2246 tty->print_cr("r25 = 0x%016lx", regs[25]);
2247 tty->print_cr("r26 = 0x%016lx", regs[26]);
2248 tty->print_cr("r27 = 0x%016lx", regs[27]);
2249 tty->print_cr("r28 = 0x%016lx", regs[28]);
2250 tty->print_cr("r30 = 0x%016lx", regs[30]);
2251 tty->print_cr("r31 = 0x%016lx", regs[31]);
2252 BREAKPOINT;
2253 }
2254 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
2255 } else {
2256 ttyLocker ttyl;
2257 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
2258 msg);
2259 assert(false, "DEBUG MESSAGE: %s", msg);
2260 }
2261 }
2262
2263 #ifdef BUILTIN_SIM
2264 // routine to generate an x86 prolog for a stub function which
2265 // bootstraps into the generated ARM code which directly follows the
2266 // stub
2267 //
2268 // the argument encodes the number of general and fp registers
2269 // passed by the caller and the callng convention (currently just
2270 // the number of general registers and assumes C argument passing)
2271
2272 extern "C" {
2273 int aarch64_stub_prolog_size();
2274 void aarch64_stub_prolog();
2275 void aarch64_prolog();
2276 }
2277
2278 void MacroAssembler::c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type,
2279 address *prolog_ptr)
2280 {
2281 int calltype = (((ret_type & 0x3) << 8) |
2282 ((fp_arg_count & 0xf) << 4) |
2283 (gp_arg_count & 0xf));
2284
2285 // the addresses for the x86 to ARM entry code we need to use
2286 address start = pc();
2287 // printf("start = %lx\n", start);
2288 int byteCount = aarch64_stub_prolog_size();
2289 // printf("byteCount = %x\n", byteCount);
2290 int instructionCount = (byteCount + 3)/ 4;
2291 // printf("instructionCount = %x\n", instructionCount);
2292 for (int i = 0; i < instructionCount; i++) {
2293 nop();
2294 }
2295
2296 memcpy(start, (void*)aarch64_stub_prolog, byteCount);
2297
2298 // write the address of the setup routine and the call format at the
2299 // end of into the copied code
2300 u_int64_t *patch_end = (u_int64_t *)(start + byteCount);
2301 if (prolog_ptr)
2302 patch_end[-2] = (u_int64_t)prolog_ptr;
2303 patch_end[-1] = calltype;
2304 }
2305 #endif
2306
2307 void MacroAssembler::push_CPU_state(bool save_vectors) {
2308 push(0x3fffffff, sp); // integer registers except lr & sp
2309
2310 if (!save_vectors) {
2311 for (int i = 30; i >= 0; i -= 2)
2312 stpd(as_FloatRegister(i), as_FloatRegister(i+1),
2313 Address(pre(sp, -2 * wordSize)));
2314 } else {
2315 for (int i = 30; i >= 0; i -= 2)
2316 stpq(as_FloatRegister(i), as_FloatRegister(i+1),
2317 Address(pre(sp, -4 * wordSize)));
2318 }
2319 }
2320
2321 void MacroAssembler::pop_CPU_state(bool restore_vectors) {
2322 if (!restore_vectors) {
2323 for (int i = 0; i < 32; i += 2)
2324 ldpd(as_FloatRegister(i), as_FloatRegister(i+1),
2325 Address(post(sp, 2 * wordSize)));
2326 } else {
2327 for (int i = 0; i < 32; i += 2)
2328 ldpq(as_FloatRegister(i), as_FloatRegister(i+1),
2329 Address(post(sp, 4 * wordSize)));
2330 }
2331
2332 pop(0x3fffffff, sp); // integer registers except lr & sp
2333 }
2334
2335 /**
2336 * Helpers for multiply_to_len().
2337 */
2338 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
2339 Register src1, Register src2) {
2340 adds(dest_lo, dest_lo, src1);
2341 adc(dest_hi, dest_hi, zr);
2342 adds(dest_lo, dest_lo, src2);
2343 adc(final_dest_hi, dest_hi, zr);
2344 }
2345
2346 // Generate an address from (r + r1 extend offset). "size" is the
2347 // size of the operand. The result may be in rscratch2.
2348 Address MacroAssembler::offsetted_address(Register r, Register r1,
2349 Address::extend ext, int offset, int size) {
2350 if (offset || (ext.shift() % size != 0)) {
2351 lea(rscratch2, Address(r, r1, ext));
2352 return Address(rscratch2, offset);
2353 } else {
2354 return Address(r, r1, ext);
2355 }
2356 }
2357
2358 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
2359 {
2360 assert(offset >= 0, "spill to negative address?");
2361 // Offset reachable ?
2362 // Not aligned - 9 bits signed offset
2363 // Aligned - 12 bits unsigned offset shifted
2364 Register base = sp;
2365 if ((offset & (size-1)) && offset >= (1<<8)) {
2366 add(tmp, base, offset & ((1<<12)-1));
2367 base = tmp;
2368 offset &= -1<<12;
2369 }
2370
2371 if (offset >= (1<<12) * size) {
2372 add(tmp, base, offset & (((1<<12)-1)<<12));
2373 base = tmp;
2374 offset &= ~(((1<<12)-1)<<12);
2375 }
2376
2377 return Address(base, offset);
2378 }
2379
2380 /**
2381 * Multiply 64 bit by 64 bit first loop.
2382 */
2383 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
2384 Register y, Register y_idx, Register z,
2385 Register carry, Register product,
2386 Register idx, Register kdx) {
2387 //
2388 // jlong carry, x[], y[], z[];
2389 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
2390 // huge_128 product = y[idx] * x[xstart] + carry;
2391 // z[kdx] = (jlong)product;
2392 // carry = (jlong)(product >>> 64);
2393 // }
2394 // z[xstart] = carry;
2395 //
2396
2397 Label L_first_loop, L_first_loop_exit;
2398 Label L_one_x, L_one_y, L_multiply;
2399
2400 subsw(xstart, xstart, 1);
2401 br(Assembler::MI, L_one_x);
2402
2403 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
2404 ldr(x_xstart, Address(rscratch1));
2405 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
2406
2407 bind(L_first_loop);
2408 subsw(idx, idx, 1);
2409 br(Assembler::MI, L_first_loop_exit);
2410 subsw(idx, idx, 1);
2411 br(Assembler::MI, L_one_y);
2412 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2413 ldr(y_idx, Address(rscratch1));
2414 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
2415 bind(L_multiply);
2416
2417 // AArch64 has a multiply-accumulate instruction that we can't use
2418 // here because it has no way to process carries, so we have to use
2419 // separate add and adc instructions. Bah.
2420 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
2421 mul(product, x_xstart, y_idx);
2422 adds(product, product, carry);
2423 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
2424
2425 subw(kdx, kdx, 2);
2426 ror(product, product, 32); // back to big-endian
2427 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
2428
2429 b(L_first_loop);
2430
2431 bind(L_one_y);
2432 ldrw(y_idx, Address(y, 0));
2433 b(L_multiply);
2434
2435 bind(L_one_x);
2436 ldrw(x_xstart, Address(x, 0));
2437 b(L_first_loop);
2438
2439 bind(L_first_loop_exit);
2440 }
2441
2442 /**
2443 * Multiply 128 bit by 128. Unrolled inner loop.
2444 *
2445 */
2446 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
2447 Register carry, Register carry2,
2448 Register idx, Register jdx,
2449 Register yz_idx1, Register yz_idx2,
2450 Register tmp, Register tmp3, Register tmp4,
2451 Register tmp6, Register product_hi) {
2452
2453 // jlong carry, x[], y[], z[];
2454 // int kdx = ystart+1;
2455 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
2456 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
2457 // jlong carry2 = (jlong)(tmp3 >>> 64);
2458 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
2459 // carry = (jlong)(tmp4 >>> 64);
2460 // z[kdx+idx+1] = (jlong)tmp3;
2461 // z[kdx+idx] = (jlong)tmp4;
2462 // }
2463 // idx += 2;
2464 // if (idx > 0) {
2465 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
2466 // z[kdx+idx] = (jlong)yz_idx1;
2467 // carry = (jlong)(yz_idx1 >>> 64);
2468 // }
2469 //
2470
2471 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
2472
2473 lsrw(jdx, idx, 2);
2474
2475 bind(L_third_loop);
2476
2477 subsw(jdx, jdx, 1);
2478 br(Assembler::MI, L_third_loop_exit);
2479 subw(idx, idx, 4);
2480
2481 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2482
2483 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
2484
2485 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2486
2487 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
2488 ror(yz_idx2, yz_idx2, 32);
2489
2490 ldp(rscratch2, rscratch1, Address(tmp6, 0));
2491
2492 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
2493 umulh(tmp4, product_hi, yz_idx1);
2494
2495 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
2496 ror(rscratch2, rscratch2, 32);
2497
2498 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
2499 umulh(carry2, product_hi, yz_idx2);
2500
2501 // propagate sum of both multiplications into carry:tmp4:tmp3
2502 adds(tmp3, tmp3, carry);
2503 adc(tmp4, tmp4, zr);
2504 adds(tmp3, tmp3, rscratch1);
2505 adcs(tmp4, tmp4, tmp);
2506 adc(carry, carry2, zr);
2507 adds(tmp4, tmp4, rscratch2);
2508 adc(carry, carry, zr);
2509
2510 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
2511 ror(tmp4, tmp4, 32);
2512 stp(tmp4, tmp3, Address(tmp6, 0));
2513
2514 b(L_third_loop);
2515 bind (L_third_loop_exit);
2516
2517 andw (idx, idx, 0x3);
2518 cbz(idx, L_post_third_loop_done);
2519
2520 Label L_check_1;
2521 subsw(idx, idx, 2);
2522 br(Assembler::MI, L_check_1);
2523
2524 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2525 ldr(yz_idx1, Address(rscratch1, 0));
2526 ror(yz_idx1, yz_idx1, 32);
2527 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
2528 umulh(tmp4, product_hi, yz_idx1);
2529 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2530 ldr(yz_idx2, Address(rscratch1, 0));
2531 ror(yz_idx2, yz_idx2, 32);
2532
2533 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
2534
2535 ror(tmp3, tmp3, 32);
2536 str(tmp3, Address(rscratch1, 0));
2537
2538 bind (L_check_1);
2539
2540 andw (idx, idx, 0x1);
2541 subsw(idx, idx, 1);
2542 br(Assembler::MI, L_post_third_loop_done);
2543 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2544 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
2545 umulh(carry2, tmp4, product_hi);
2546 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2547
2548 add2_with_carry(carry2, tmp3, tmp4, carry);
2549
2550 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2551 extr(carry, carry2, tmp3, 32);
2552
2553 bind(L_post_third_loop_done);
2554 }
2555
2556 /**
2557 * Code for BigInteger::multiplyToLen() instrinsic.
2558 *
2559 * r0: x
2560 * r1: xlen
2561 * r2: y
2562 * r3: ylen
2563 * r4: z
2564 * r5: zlen
2565 * r10: tmp1
2566 * r11: tmp2
2567 * r12: tmp3
2568 * r13: tmp4
2569 * r14: tmp5
2570 * r15: tmp6
2571 * r16: tmp7
2572 *
2573 */
2574 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
2575 Register z, Register zlen,
2576 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
2577 Register tmp5, Register tmp6, Register product_hi) {
2578
2579 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6);
2580
2581 const Register idx = tmp1;
2582 const Register kdx = tmp2;
2583 const Register xstart = tmp3;
2584
2585 const Register y_idx = tmp4;
2586 const Register carry = tmp5;
2587 const Register product = xlen;
2588 const Register x_xstart = zlen; // reuse register
2589
2590 // First Loop.
2591 //
2592 // final static long LONG_MASK = 0xffffffffL;
2593 // int xstart = xlen - 1;
2594 // int ystart = ylen - 1;
2595 // long carry = 0;
2596 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
2597 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
2598 // z[kdx] = (int)product;
2599 // carry = product >>> 32;
2600 // }
2601 // z[xstart] = (int)carry;
2602 //
2603
2604 movw(idx, ylen); // idx = ylen;
2605 movw(kdx, zlen); // kdx = xlen+ylen;
2606 mov(carry, zr); // carry = 0;
2607
2608 Label L_done;
2609
2610 movw(xstart, xlen);
2611 subsw(xstart, xstart, 1);
2612 br(Assembler::MI, L_done);
2613
2614 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
2615
2616 Label L_second_loop;
2617 cbzw(kdx, L_second_loop);
2618
2619 Label L_carry;
2620 subw(kdx, kdx, 1);
2621 cbzw(kdx, L_carry);
2622
2623 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
2624 lsr(carry, carry, 32);
2625 subw(kdx, kdx, 1);
2626
2627 bind(L_carry);
2628 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
2629
2630 // Second and third (nested) loops.
2631 //
2632 // for (int i = xstart-1; i >= 0; i--) { // Second loop
2633 // carry = 0;
2634 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
2635 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
2636 // (z[k] & LONG_MASK) + carry;
2637 // z[k] = (int)product;
2638 // carry = product >>> 32;
2639 // }
2640 // z[i] = (int)carry;
2641 // }
2642 //
2643 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
2644
2645 const Register jdx = tmp1;
2646
2647 bind(L_second_loop);
2648 mov(carry, zr); // carry = 0;
2649 movw(jdx, ylen); // j = ystart+1
2650
2651 subsw(xstart, xstart, 1); // i = xstart-1;
2652 br(Assembler::MI, L_done);
2653
2654 str(z, Address(pre(sp, -4 * wordSize)));
2655
2656 Label L_last_x;
2657 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
2658 subsw(xstart, xstart, 1); // i = xstart-1;
2659 br(Assembler::MI, L_last_x);
2660
2661 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
2662 ldr(product_hi, Address(rscratch1));
2663 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
2664
2665 Label L_third_loop_prologue;
2666 bind(L_third_loop_prologue);
2667
2668 str(ylen, Address(sp, wordSize));
2669 stp(x, xstart, Address(sp, 2 * wordSize));
2670 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
2671 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
2672 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
2673 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
2674
2675 addw(tmp3, xlen, 1);
2676 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
2677 subsw(tmp3, tmp3, 1);
2678 br(Assembler::MI, L_done);
2679
2680 lsr(carry, carry, 32);
2681 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
2682 b(L_second_loop);
2683
2684 // Next infrequent code is moved outside loops.
2685 bind(L_last_x);
2686 ldrw(product_hi, Address(x, 0));
2687 b(L_third_loop_prologue);
2688
2689 bind(L_done);
2690 }
2691
2692 /**
2693 * Emits code to update CRC-32 with a byte value according to constants in table
2694 *
2695 * @param [in,out]crc Register containing the crc.
2696 * @param [in]val Register containing the byte to fold into the CRC.
2697 * @param [in]table Register containing the table of crc constants.
2698 *
2699 * uint32_t crc;
2700 * val = crc_table[(val ^ crc) & 0xFF];
2701 * crc = val ^ (crc >> 8);
2702 *
2703 */
2704 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
2705 eor(val, val, crc);
2706 andr(val, val, 0xff);
2707 ldrw(val, Address(table, val, Address::lsl(2)));
2708 eor(crc, val, crc, Assembler::LSR, 8);
2709 }
2710
2711 /**
2712 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
2713 *
2714 * @param [in,out]crc Register containing the crc.
2715 * @param [in]v Register containing the 32-bit to fold into the CRC.
2716 * @param [in]table0 Register containing table 0 of crc constants.
2717 * @param [in]table1 Register containing table 1 of crc constants.
2718 * @param [in]table2 Register containing table 2 of crc constants.
2719 * @param [in]table3 Register containing table 3 of crc constants.
2720 *
2721 * uint32_t crc;
2722 * v = crc ^ v
2723 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
2724 *
2725 */
2726 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
2727 Register table0, Register table1, Register table2, Register table3,
2728 bool upper) {
2729 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
2730 uxtb(tmp, v);
2731 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
2732 ubfx(tmp, v, 8, 8);
2733 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
2734 eor(crc, crc, tmp);
2735 ubfx(tmp, v, 16, 8);
2736 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
2737 eor(crc, crc, tmp);
2738 ubfx(tmp, v, 24, 8);
2739 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
2740 eor(crc, crc, tmp);
2741 }
2742
2743 /**
2744 * @param crc register containing existing CRC (32-bit)
2745 * @param buf register pointing to input byte buffer (byte*)
2746 * @param len register containing number of bytes
2747 * @param table register that will contain address of CRC table
2748 * @param tmp scratch register
2749 */
2750 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
2751 Register table0, Register table1, Register table2, Register table3,
2752 Register tmp, Register tmp2, Register tmp3) {
2753 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
2754 unsigned long offset;
2755
2756 ornw(crc, zr, crc);
2757
2758 if (UseCRC32) {
2759 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop;
2760
2761 subs(len, len, 64);
2762 br(Assembler::GE, CRC_by64_loop);
2763 adds(len, len, 64-4);
2764 br(Assembler::GE, CRC_by4_loop);
2765 adds(len, len, 4);
2766 br(Assembler::GT, CRC_by1_loop);
2767 b(L_exit);
2768
2769 BIND(CRC_by4_loop);
2770 ldrw(tmp, Address(post(buf, 4)));
2771 subs(len, len, 4);
2772 crc32w(crc, crc, tmp);
2773 br(Assembler::GE, CRC_by4_loop);
2774 adds(len, len, 4);
2775 br(Assembler::LE, L_exit);
2776 BIND(CRC_by1_loop);
2777 ldrb(tmp, Address(post(buf, 1)));
2778 subs(len, len, 1);
2779 crc32b(crc, crc, tmp);
2780 br(Assembler::GT, CRC_by1_loop);
2781 b(L_exit);
2782
2783 align(CodeEntryAlignment);
2784 BIND(CRC_by64_loop);
2785 subs(len, len, 64);
2786 ldp(tmp, tmp3, Address(post(buf, 16)));
2787 crc32x(crc, crc, tmp);
2788 crc32x(crc, crc, tmp3);
2789 ldp(tmp, tmp3, Address(post(buf, 16)));
2790 crc32x(crc, crc, tmp);
2791 crc32x(crc, crc, tmp3);
2792 ldp(tmp, tmp3, Address(post(buf, 16)));
2793 crc32x(crc, crc, tmp);
2794 crc32x(crc, crc, tmp3);
2795 ldp(tmp, tmp3, Address(post(buf, 16)));
2796 crc32x(crc, crc, tmp);
2797 crc32x(crc, crc, tmp3);
2798 br(Assembler::GE, CRC_by64_loop);
2799 adds(len, len, 64-4);
2800 br(Assembler::GE, CRC_by4_loop);
2801 adds(len, len, 4);
2802 br(Assembler::GT, CRC_by1_loop);
2803 BIND(L_exit);
2804 ornw(crc, zr, crc);
2805 return;
2806 }
2807
2808 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2809 if (offset) add(table0, table0, offset);
2810 add(table1, table0, 1*256*sizeof(juint));
2811 add(table2, table0, 2*256*sizeof(juint));
2812 add(table3, table0, 3*256*sizeof(juint));
2813
2814 if (UseNeon) {
2815 cmp(len, 64);
2816 br(Assembler::LT, L_by16);
2817 eor(v16, T16B, v16, v16);
2818
2819 Label L_fold;
2820
2821 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
2822
2823 ld1(v0, v1, T2D, post(buf, 32));
2824 ld1r(v4, T2D, post(tmp, 8));
2825 ld1r(v5, T2D, post(tmp, 8));
2826 ld1r(v6, T2D, post(tmp, 8));
2827 ld1r(v7, T2D, post(tmp, 8));
2828 mov(v16, T4S, 0, crc);
2829
2830 eor(v0, T16B, v0, v16);
2831 sub(len, len, 64);
2832
2833 BIND(L_fold);
2834 pmull(v22, T8H, v0, v5, T8B);
2835 pmull(v20, T8H, v0, v7, T8B);
2836 pmull(v23, T8H, v0, v4, T8B);
2837 pmull(v21, T8H, v0, v6, T8B);
2838
2839 pmull2(v18, T8H, v0, v5, T16B);
2840 pmull2(v16, T8H, v0, v7, T16B);
2841 pmull2(v19, T8H, v0, v4, T16B);
2842 pmull2(v17, T8H, v0, v6, T16B);
2843
2844 uzp1(v24, v20, v22, T8H);
2845 uzp2(v25, v20, v22, T8H);
2846 eor(v20, T16B, v24, v25);
2847
2848 uzp1(v26, v16, v18, T8H);
2849 uzp2(v27, v16, v18, T8H);
2850 eor(v16, T16B, v26, v27);
2851
2852 ushll2(v22, T4S, v20, T8H, 8);
2853 ushll(v20, T4S, v20, T4H, 8);
2854
2855 ushll2(v18, T4S, v16, T8H, 8);
2856 ushll(v16, T4S, v16, T4H, 8);
2857
2858 eor(v22, T16B, v23, v22);
2859 eor(v18, T16B, v19, v18);
2860 eor(v20, T16B, v21, v20);
2861 eor(v16, T16B, v17, v16);
2862
2863 uzp1(v17, v16, v20, T2D);
2864 uzp2(v21, v16, v20, T2D);
2865 eor(v17, T16B, v17, v21);
2866
2867 ushll2(v20, T2D, v17, T4S, 16);
2868 ushll(v16, T2D, v17, T2S, 16);
2869
2870 eor(v20, T16B, v20, v22);
2871 eor(v16, T16B, v16, v18);
2872
2873 uzp1(v17, v20, v16, T2D);
2874 uzp2(v21, v20, v16, T2D);
2875 eor(v28, T16B, v17, v21);
2876
2877 pmull(v22, T8H, v1, v5, T8B);
2878 pmull(v20, T8H, v1, v7, T8B);
2879 pmull(v23, T8H, v1, v4, T8B);
2880 pmull(v21, T8H, v1, v6, T8B);
2881
2882 pmull2(v18, T8H, v1, v5, T16B);
2883 pmull2(v16, T8H, v1, v7, T16B);
2884 pmull2(v19, T8H, v1, v4, T16B);
2885 pmull2(v17, T8H, v1, v6, T16B);
2886
2887 ld1(v0, v1, T2D, post(buf, 32));
2888
2889 uzp1(v24, v20, v22, T8H);
2890 uzp2(v25, v20, v22, T8H);
2891 eor(v20, T16B, v24, v25);
2892
2893 uzp1(v26, v16, v18, T8H);
2894 uzp2(v27, v16, v18, T8H);
2895 eor(v16, T16B, v26, v27);
2896
2897 ushll2(v22, T4S, v20, T8H, 8);
2898 ushll(v20, T4S, v20, T4H, 8);
2899
2900 ushll2(v18, T4S, v16, T8H, 8);
2901 ushll(v16, T4S, v16, T4H, 8);
2902
2903 eor(v22, T16B, v23, v22);
2904 eor(v18, T16B, v19, v18);
2905 eor(v20, T16B, v21, v20);
2906 eor(v16, T16B, v17, v16);
2907
2908 uzp1(v17, v16, v20, T2D);
2909 uzp2(v21, v16, v20, T2D);
2910 eor(v16, T16B, v17, v21);
2911
2912 ushll2(v20, T2D, v16, T4S, 16);
2913 ushll(v16, T2D, v16, T2S, 16);
2914
2915 eor(v20, T16B, v22, v20);
2916 eor(v16, T16B, v16, v18);
2917
2918 uzp1(v17, v20, v16, T2D);
2919 uzp2(v21, v20, v16, T2D);
2920 eor(v20, T16B, v17, v21);
2921
2922 shl(v16, T2D, v28, 1);
2923 shl(v17, T2D, v20, 1);
2924
2925 eor(v0, T16B, v0, v16);
2926 eor(v1, T16B, v1, v17);
2927
2928 subs(len, len, 32);
2929 br(Assembler::GE, L_fold);
2930
2931 mov(crc, 0);
2932 mov(tmp, v0, T1D, 0);
2933 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
2934 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
2935 mov(tmp, v0, T1D, 1);
2936 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
2937 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
2938 mov(tmp, v1, T1D, 0);
2939 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
2940 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
2941 mov(tmp, v1, T1D, 1);
2942 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
2943 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
2944
2945 add(len, len, 32);
2946 }
2947
2948 BIND(L_by16);
2949 subs(len, len, 16);
2950 br(Assembler::GE, L_by16_loop);
2951 adds(len, len, 16-4);
2952 br(Assembler::GE, L_by4_loop);
2953 adds(len, len, 4);
2954 br(Assembler::GT, L_by1_loop);
2955 b(L_exit);
2956
2957 BIND(L_by4_loop);
2958 ldrw(tmp, Address(post(buf, 4)));
2959 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
2960 subs(len, len, 4);
2961 br(Assembler::GE, L_by4_loop);
2962 adds(len, len, 4);
2963 br(Assembler::LE, L_exit);
2964 BIND(L_by1_loop);
2965 subs(len, len, 1);
2966 ldrb(tmp, Address(post(buf, 1)));
2967 update_byte_crc32(crc, tmp, table0);
2968 br(Assembler::GT, L_by1_loop);
2969 b(L_exit);
2970
2971 align(CodeEntryAlignment);
2972 BIND(L_by16_loop);
2973 subs(len, len, 16);
2974 ldp(tmp, tmp3, Address(post(buf, 16)));
2975 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
2976 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
2977 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
2978 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
2979 br(Assembler::GE, L_by16_loop);
2980 adds(len, len, 16-4);
2981 br(Assembler::GE, L_by4_loop);
2982 adds(len, len, 4);
2983 br(Assembler::GT, L_by1_loop);
2984 BIND(L_exit);
2985 ornw(crc, zr, crc);
2986 }
2987
2988 /**
2989 * @param crc register containing existing CRC (32-bit)
2990 * @param buf register pointing to input byte buffer (byte*)
2991 * @param len register containing number of bytes
2992 * @param table register that will contain address of CRC table
2993 * @param tmp scratch register
2994 */
2995 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
2996 Register table0, Register table1, Register table2, Register table3,
2997 Register tmp, Register tmp2, Register tmp3) {
2998 Label L_exit;
2999 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop;
3000
3001 subs(len, len, 64);
3002 br(Assembler::GE, CRC_by64_loop);
3003 adds(len, len, 64-4);
3004 br(Assembler::GE, CRC_by4_loop);
3005 adds(len, len, 4);
3006 br(Assembler::GT, CRC_by1_loop);
3007 b(L_exit);
3008
3009 BIND(CRC_by4_loop);
3010 ldrw(tmp, Address(post(buf, 4)));
3011 subs(len, len, 4);
3012 crc32cw(crc, crc, tmp);
3013 br(Assembler::GE, CRC_by4_loop);
3014 adds(len, len, 4);
3015 br(Assembler::LE, L_exit);
3016 BIND(CRC_by1_loop);
3017 ldrb(tmp, Address(post(buf, 1)));
3018 subs(len, len, 1);
3019 crc32cb(crc, crc, tmp);
3020 br(Assembler::GT, CRC_by1_loop);
3021 b(L_exit);
3022
3023 align(CodeEntryAlignment);
3024 BIND(CRC_by64_loop);
3025 subs(len, len, 64);
3026 ldp(tmp, tmp3, Address(post(buf, 16)));
3027 crc32cx(crc, crc, tmp);
3028 crc32cx(crc, crc, tmp3);
3029 ldp(tmp, tmp3, Address(post(buf, 16)));
3030 crc32cx(crc, crc, tmp);
3031 crc32cx(crc, crc, tmp3);
3032 ldp(tmp, tmp3, Address(post(buf, 16)));
3033 crc32cx(crc, crc, tmp);
3034 crc32cx(crc, crc, tmp3);
3035 ldp(tmp, tmp3, Address(post(buf, 16)));
3036 crc32cx(crc, crc, tmp);
3037 crc32cx(crc, crc, tmp3);
3038 br(Assembler::GE, CRC_by64_loop);
3039 adds(len, len, 64-4);
3040 br(Assembler::GE, CRC_by4_loop);
3041 adds(len, len, 4);
3042 br(Assembler::GT, CRC_by1_loop);
3043 BIND(L_exit);
3044 return;
3045 }
3046
3047 SkipIfEqual::SkipIfEqual(
3048 MacroAssembler* masm, const bool* flag_addr, bool value) {
3049 _masm = masm;
3050 unsigned long offset;
3051 _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset);
3052 _masm->ldrb(rscratch1, Address(rscratch1, offset));
3053 _masm->cbzw(rscratch1, _label);
3054 }
3055
3056 SkipIfEqual::~SkipIfEqual() {
3057 _masm->bind(_label);
3058 }
3059
3060 void MacroAssembler::addptr(const Address &dst, int32_t src) {
3061 Address adr;
3062 switch(dst.getMode()) {
3063 case Address::base_plus_offset:
3064 // This is the expected mode, although we allow all the other
3065 // forms below.
3066 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
3067 break;
3068 default:
3069 lea(rscratch2, dst);
3070 adr = Address(rscratch2);
3071 break;
3072 }
3073 ldr(rscratch1, adr);
3074 add(rscratch1, rscratch1, src);
3075 str(rscratch1, adr);
3076 }
3077
3078 void MacroAssembler::cmpptr(Register src1, Address src2) {
3079 unsigned long offset;
3080 far_adrp(rscratch1, src2, offset);
3081 ldr(rscratch1, Address(rscratch1, offset));
3082 cmp(src1, rscratch1);
3083 }
3084
3085 void MacroAssembler::store_check(Register obj, Address dst) {
3086 store_check(obj);
3087 }
3088
3089 void MacroAssembler::store_check(Register obj) {
3090 // Does a store check for the oop in register obj. The content of
3091 // register obj is destroyed afterwards.
3092
3093 BarrierSet* bs = Universe::heap()->barrier_set();
3094 assert(bs->kind() == BarrierSet::CardTableForRS ||
3095 bs->kind() == BarrierSet::CardTableExtension,
3096 "Wrong barrier set kind");
3097
3098 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
3099 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3100
3101 lsr(obj, obj, CardTableModRefBS::card_shift);
3102
3103 assert(CardTableModRefBS::dirty_card_val() == 0, "must be");
3104
3105 {
3106 ExternalAddress cardtable((address) ct->byte_map_base);
3107 unsigned long offset;
3108 far_adrp(rscratch1, cardtable, offset);
3109 assert(offset == 0, "byte_map_base is misaligned");
3110 }
3111
3112 if (UseCondCardMark) {
3113 Label L_already_dirty;
3114 membar(StoreLoad);
3115 ldrb(rscratch2, Address(obj, rscratch1));
3116 cbz(rscratch2, L_already_dirty);
3117 strb(zr, Address(obj, rscratch1));
3118 bind(L_already_dirty);
3119 } else {
3120 if (UseConcMarkSweepGC && CMSPrecleaningEnabled) {
3121 membar(StoreStore);
3122 }
3123 strb(zr, Address(obj, rscratch1));
3124 }
3125 }
3126
3127 void MacroAssembler::load_klass(Register dst, Register src) {
3128 if (UseCompressedClassPointers) {
3129 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3130 decode_klass_not_null(dst);
3131 } else {
3132 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3133 }
3134 }
3135
3136 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
3137 if (UseCompressedClassPointers) {
3138 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3139 if (Universe::narrow_klass_base() == NULL) {
3140 cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift());
3141 return;
3142 } else if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3143 && Universe::narrow_klass_shift() == 0) {
3144 // Only the bottom 32 bits matter
3145 cmpw(trial_klass, tmp);
3146 return;
3147 }
3148 decode_klass_not_null(tmp);
3149 } else {
3150 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3151 }
3152 cmp(trial_klass, tmp);
3153 }
3154
3155 void MacroAssembler::load_prototype_header(Register dst, Register src) {
3156 load_klass(dst, src);
3157 ldr(dst, Address(dst, Klass::prototype_header_offset()));
3158 }
3159
3160 void MacroAssembler::store_klass(Register dst, Register src) {
3161 // FIXME: Should this be a store release? concurrent gcs assumes
3162 // klass length is valid if klass field is not null.
3163 if (UseCompressedClassPointers) {
3164 encode_klass_not_null(src);
3165 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3166 } else {
3167 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3168 }
3169 }
3170
3171 void MacroAssembler::store_klass_gap(Register dst, Register src) {
3172 if (UseCompressedClassPointers) {
3173 // Store to klass gap in destination
3174 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
3175 }
3176 }
3177
3178 // Algorithm must match oop.inline.hpp encode_heap_oop.
3179 void MacroAssembler::encode_heap_oop(Register d, Register s) {
3180 #ifdef ASSERT
3181 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
3182 #endif
3183 verify_oop(s, "broken oop in encode_heap_oop");
3184 if (Universe::narrow_oop_base() == NULL) {
3185 if (Universe::narrow_oop_shift() != 0) {
3186 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3187 lsr(d, s, LogMinObjAlignmentInBytes);
3188 } else {
3189 mov(d, s);
3190 }
3191 } else {
3192 subs(d, s, rheapbase);
3193 csel(d, d, zr, Assembler::HS);
3194 lsr(d, d, LogMinObjAlignmentInBytes);
3195
3196 /* Old algorithm: is this any worse?
3197 Label nonnull;
3198 cbnz(r, nonnull);
3199 sub(r, r, rheapbase);
3200 bind(nonnull);
3201 lsr(r, r, LogMinObjAlignmentInBytes);
3202 */
3203 }
3204 }
3205
3206 void MacroAssembler::encode_heap_oop_not_null(Register r) {
3207 #ifdef ASSERT
3208 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
3209 if (CheckCompressedOops) {
3210 Label ok;
3211 cbnz(r, ok);
3212 stop("null oop passed to encode_heap_oop_not_null");
3213 bind(ok);
3214 }
3215 #endif
3216 verify_oop(r, "broken oop in encode_heap_oop_not_null");
3217 if (Universe::narrow_oop_base() != NULL) {
3218 sub(r, r, rheapbase);
3219 }
3220 if (Universe::narrow_oop_shift() != 0) {
3221 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3222 lsr(r, r, LogMinObjAlignmentInBytes);
3223 }
3224 }
3225
3226 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
3227 #ifdef ASSERT
3228 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
3229 if (CheckCompressedOops) {
3230 Label ok;
3231 cbnz(src, ok);
3232 stop("null oop passed to encode_heap_oop_not_null2");
3233 bind(ok);
3234 }
3235 #endif
3236 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
3237
3238 Register data = src;
3239 if (Universe::narrow_oop_base() != NULL) {
3240 sub(dst, src, rheapbase);
3241 data = dst;
3242 }
3243 if (Universe::narrow_oop_shift() != 0) {
3244 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3245 lsr(dst, data, LogMinObjAlignmentInBytes);
3246 data = dst;
3247 }
3248 if (data == src)
3249 mov(dst, src);
3250 }
3251
3252 void MacroAssembler::decode_heap_oop(Register d, Register s) {
3253 #ifdef ASSERT
3254 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
3255 #endif
3256 if (Universe::narrow_oop_base() == NULL) {
3257 if (Universe::narrow_oop_shift() != 0 || d != s) {
3258 lsl(d, s, Universe::narrow_oop_shift());
3259 }
3260 } else {
3261 Label done;
3262 if (d != s)
3263 mov(d, s);
3264 cbz(s, done);
3265 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
3266 bind(done);
3267 }
3268 verify_oop(d, "broken oop in decode_heap_oop");
3269 }
3270
3271 void MacroAssembler::decode_heap_oop_not_null(Register r) {
3272 assert (UseCompressedOops, "should only be used for compressed headers");
3273 assert (Universe::heap() != NULL, "java heap should be initialized");
3274 // Cannot assert, unverified entry point counts instructions (see .ad file)
3275 // vtableStubs also counts instructions in pd_code_size_limit.
3276 // Also do not verify_oop as this is called by verify_oop.
3277 if (Universe::narrow_oop_shift() != 0) {
3278 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3279 if (Universe::narrow_oop_base() != NULL) {
3280 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
3281 } else {
3282 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
3283 }
3284 } else {
3285 assert (Universe::narrow_oop_base() == NULL, "sanity");
3286 }
3287 }
3288
3289 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
3290 assert (UseCompressedOops, "should only be used for compressed headers");
3291 assert (Universe::heap() != NULL, "java heap should be initialized");
3292 // Cannot assert, unverified entry point counts instructions (see .ad file)
3293 // vtableStubs also counts instructions in pd_code_size_limit.
3294 // Also do not verify_oop as this is called by verify_oop.
3295 if (Universe::narrow_oop_shift() != 0) {
3296 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3297 if (Universe::narrow_oop_base() != NULL) {
3298 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
3299 } else {
3300 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
3301 }
3302 } else {
3303 assert (Universe::narrow_oop_base() == NULL, "sanity");
3304 if (dst != src) {
3305 mov(dst, src);
3306 }
3307 }
3308 }
3309
3310 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
3311 if (Universe::narrow_klass_base() == NULL) {
3312 if (Universe::narrow_klass_shift() != 0) {
3313 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3314 lsr(dst, src, LogKlassAlignmentInBytes);
3315 } else {
3316 if (dst != src) mov(dst, src);
3317 }
3318 return;
3319 }
3320
3321 if (use_XOR_for_compressed_class_base) {
3322 if (Universe::narrow_klass_shift() != 0) {
3323 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3324 lsr(dst, dst, LogKlassAlignmentInBytes);
3325 } else {
3326 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3327 }
3328 return;
3329 }
3330
3331 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3332 && Universe::narrow_klass_shift() == 0) {
3333 movw(dst, src);
3334 return;
3335 }
3336
3337 #ifdef ASSERT
3338 verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?");
3339 #endif
3340
3341 Register rbase = dst;
3342 if (dst == src) rbase = rheapbase;
3343 mov(rbase, (uint64_t)Universe::narrow_klass_base());
3344 sub(dst, src, rbase);
3345 if (Universe::narrow_klass_shift() != 0) {
3346 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3347 lsr(dst, dst, LogKlassAlignmentInBytes);
3348 }
3349 if (dst == src) reinit_heapbase();
3350 }
3351
3352 void MacroAssembler::encode_klass_not_null(Register r) {
3353 encode_klass_not_null(r, r);
3354 }
3355
3356 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
3357 Register rbase = dst;
3358 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3359
3360 if (Universe::narrow_klass_base() == NULL) {
3361 if (Universe::narrow_klass_shift() != 0) {
3362 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3363 lsl(dst, src, LogKlassAlignmentInBytes);
3364 } else {
3365 if (dst != src) mov(dst, src);
3366 }
3367 return;
3368 }
3369
3370 if (use_XOR_for_compressed_class_base) {
3371 if (Universe::narrow_klass_shift() != 0) {
3372 lsl(dst, src, LogKlassAlignmentInBytes);
3373 eor(dst, dst, (uint64_t)Universe::narrow_klass_base());
3374 } else {
3375 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3376 }
3377 return;
3378 }
3379
3380 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3381 && Universe::narrow_klass_shift() == 0) {
3382 if (dst != src)
3383 movw(dst, src);
3384 movk(dst, (uint64_t)Universe::narrow_klass_base() >> 32, 32);
3385 return;
3386 }
3387
3388 // Cannot assert, unverified entry point counts instructions (see .ad file)
3389 // vtableStubs also counts instructions in pd_code_size_limit.
3390 // Also do not verify_oop as this is called by verify_oop.
3391 if (dst == src) rbase = rheapbase;
3392 mov(rbase, (uint64_t)Universe::narrow_klass_base());
3393 if (Universe::narrow_klass_shift() != 0) {
3394 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3395 add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes);
3396 } else {
3397 add(dst, rbase, src);
3398 }
3399 if (dst == src) reinit_heapbase();
3400 }
3401
3402 void MacroAssembler::decode_klass_not_null(Register r) {
3403 decode_klass_not_null(r, r);
3404 }
3405
3406 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
3407 assert (UseCompressedOops, "should only be used for compressed oops");
3408 assert (Universe::heap() != NULL, "java heap should be initialized");
3409 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
3410
3411 int oop_index = oop_recorder()->find_index(obj);
3412 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop");
3413
3414 InstructionMark im(this);
3415 RelocationHolder rspec = oop_Relocation::spec(oop_index);
3416 code_section()->relocate(inst_mark(), rspec);
3417 movz(dst, 0xDEAD, 16);
3418 movk(dst, 0xBEEF);
3419 }
3420
3421 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
3422 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3423 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
3424 int index = oop_recorder()->find_index(k);
3425 assert(! Universe::heap()->is_in_reserved(k), "should not be an oop");
3426
3427 InstructionMark im(this);
3428 RelocationHolder rspec = metadata_Relocation::spec(index);
3429 code_section()->relocate(inst_mark(), rspec);
3430 narrowKlass nk = Klass::encode_klass(k);
3431 movz(dst, (nk >> 16), 16);
3432 movk(dst, nk & 0xffff);
3433 }
3434
3435 void MacroAssembler::load_heap_oop(Register dst, Address src)
3436 {
3437 if (UseCompressedOops) {
3438 ldrw(dst, src);
3439 decode_heap_oop(dst);
3440 } else {
3441 ldr(dst, src);
3442 }
3443 }
3444
3445 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src)
3446 {
3447 if (UseCompressedOops) {
3448 ldrw(dst, src);
3449 decode_heap_oop_not_null(dst);
3450 } else {
3451 ldr(dst, src);
3452 }
3453 }
3454
3455 void MacroAssembler::store_heap_oop(Address dst, Register src) {
3456 if (UseCompressedOops) {
3457 assert(!dst.uses(src), "not enough registers");
3458 encode_heap_oop(src);
3459 strw(src, dst);
3460 } else
3461 str(src, dst);
3462 }
3463
3464 // Used for storing NULLs.
3465 void MacroAssembler::store_heap_oop_null(Address dst) {
3466 if (UseCompressedOops) {
3467 strw(zr, dst);
3468 } else
3469 str(zr, dst);
3470 }
3471
3472 #if INCLUDE_ALL_GCS
3473 void MacroAssembler::g1_write_barrier_pre(Register obj,
3474 Register pre_val,
3475 Register thread,
3476 Register tmp,
3477 bool tosca_live,
3478 bool expand_call) {
3479 // If expand_call is true then we expand the call_VM_leaf macro
3480 // directly to skip generating the check by
3481 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
3482
3483 assert(thread == rthread, "must be");
3484
3485 Label done;
3486 Label runtime;
3487
3488 assert(pre_val != noreg, "check this code");
3489
3490 if (obj != noreg)
3491 assert_different_registers(obj, pre_val, tmp);
3492
3493 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
3494 PtrQueue::byte_offset_of_active()));
3495 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
3496 PtrQueue::byte_offset_of_index()));
3497 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
3498 PtrQueue::byte_offset_of_buf()));
3499
3500
3501 // Is marking active?
3502 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
3503 ldrw(tmp, in_progress);
3504 } else {
3505 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
3506 ldrb(tmp, in_progress);
3507 }
3508 cbzw(tmp, done);
3509
3510 // Do we need to load the previous value?
3511 if (obj != noreg) {
3512 load_heap_oop(pre_val, Address(obj, 0));
3513 }
3514
3515 // Is the previous value null?
3516 cbz(pre_val, done);
3517
3518 // Can we store original value in the thread's buffer?
3519 // Is index == 0?
3520 // (The index field is typed as size_t.)
3521
3522 ldr(tmp, index); // tmp := *index_adr
3523 cbz(tmp, runtime); // tmp == 0?
3524 // If yes, goto runtime
3525
3526 sub(tmp, tmp, wordSize); // tmp := tmp - wordSize
3527 str(tmp, index); // *index_adr := tmp
3528 ldr(rscratch1, buffer);
3529 add(tmp, tmp, rscratch1); // tmp := tmp + *buffer_adr
3530
3531 // Record the previous value
3532 str(pre_val, Address(tmp, 0));
3533 b(done);
3534
3535 bind(runtime);
3536 // save the live input values
3537 push(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp);
3538
3539 // Calling the runtime using the regular call_VM_leaf mechanism generates
3540 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
3541 // that checks that the *(rfp+frame::interpreter_frame_last_sp) == NULL.
3542 //
3543 // If we care generating the pre-barrier without a frame (e.g. in the
3544 // intrinsified Reference.get() routine) then ebp might be pointing to
3545 // the caller frame and so this check will most likely fail at runtime.
3546 //
3547 // Expanding the call directly bypasses the generation of the check.
3548 // So when we do not have have a full interpreter frame on the stack
3549 // expand_call should be passed true.
3550
3551 if (expand_call) {
3552 assert(pre_val != c_rarg1, "smashed arg");
3553 pass_arg1(this, thread);
3554 pass_arg0(this, pre_val);
3555 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
3556 } else {
3557 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
3558 }
3559
3560 pop(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp);
3561
3562 bind(done);
3563 }
3564
3565 void MacroAssembler::g1_write_barrier_post(Register store_addr,
3566 Register new_val,
3567 Register thread,
3568 Register tmp,
3569 Register tmp2) {
3570 assert(thread == rthread, "must be");
3571
3572 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
3573 PtrQueue::byte_offset_of_index()));
3574 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
3575 PtrQueue::byte_offset_of_buf()));
3576
3577 BarrierSet* bs = Universe::heap()->barrier_set();
3578 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
3579 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3580
3581 Label done;
3582 Label runtime;
3583
3584 // Does store cross heap regions?
3585
3586 eor(tmp, store_addr, new_val);
3587 lsr(tmp, tmp, HeapRegion::LogOfHRGrainBytes);
3588 cbz(tmp, done);
3589
3590 // crosses regions, storing NULL?
3591
3592 cbz(new_val, done);
3593
3594 // storing region crossing non-NULL, is card already dirty?
3595
3596 ExternalAddress cardtable((address) ct->byte_map_base);
3597 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3598 const Register card_addr = tmp;
3599
3600 lsr(card_addr, store_addr, CardTableModRefBS::card_shift);
3601
3602 unsigned long offset;
3603 far_adrp(tmp2, cardtable, offset);
3604
3605 // get the address of the card
3606 add(card_addr, card_addr, tmp2);
3607 ldrb(tmp2, Address(card_addr, offset));
3608 cmpw(tmp2, (int)G1SATBCardTableModRefBS::g1_young_card_val());
3609 br(Assembler::EQ, done);
3610
3611 assert((int)CardTableModRefBS::dirty_card_val() == 0, "must be 0");
3612
3613 membar(Assembler::StoreLoad);
3614
3615 ldrb(tmp2, Address(card_addr, offset));
3616 cbzw(tmp2, done);
3617
3618 // storing a region crossing, non-NULL oop, card is clean.
3619 // dirty card and log.
3620
3621 strb(zr, Address(card_addr, offset));
3622
3623 ldr(rscratch1, queue_index);
3624 cbz(rscratch1, runtime);
3625 sub(rscratch1, rscratch1, wordSize);
3626 str(rscratch1, queue_index);
3627
3628 ldr(tmp2, buffer);
3629 str(card_addr, Address(tmp2, rscratch1));
3630 b(done);
3631
3632 bind(runtime);
3633 // save the live input values
3634 push(store_addr->bit(true) | new_val->bit(true), sp);
3635 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
3636 pop(store_addr->bit(true) | new_val->bit(true), sp);
3637
3638 bind(done);
3639 }
3640
3641 #endif // INCLUDE_ALL_GCS
3642
3643 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
3644 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
3645 int index = oop_recorder()->allocate_metadata_index(obj);
3646 RelocationHolder rspec = metadata_Relocation::spec(index);
3647 return Address((address)obj, rspec);
3648 }
3649
3650 // Move an oop into a register. immediate is true if we want
3651 // immediate instrcutions, i.e. we are not going to patch this
3652 // instruction while the code is being executed by another thread. In
3653 // that case we can use move immediates rather than the constant pool.
3654 void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) {
3655 int oop_index;
3656 if (obj == NULL) {
3657 oop_index = oop_recorder()->allocate_oop_index(obj);
3658 } else {
3659 oop_index = oop_recorder()->find_index(obj);
3660 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop");
3661 }
3662 RelocationHolder rspec = oop_Relocation::spec(oop_index);
3663 if (! immediate) {
3664 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
3665 ldr_constant(dst, Address(dummy, rspec));
3666 } else
3667 mov(dst, Address((address)obj, rspec));
3668 }
3669
3670 // Move a metadata address into a register.
3671 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
3672 int oop_index;
3673 if (obj == NULL) {
3674 oop_index = oop_recorder()->allocate_metadata_index(obj);
3675 } else {
3676 oop_index = oop_recorder()->find_index(obj);
3677 }
3678 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
3679 mov(dst, Address((address)obj, rspec));
3680 }
3681
3682 Address MacroAssembler::constant_oop_address(jobject obj) {
3683 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
3684 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop");
3685 int oop_index = oop_recorder()->find_index(obj);
3686 return Address((address)obj, oop_Relocation::spec(oop_index));
3687 }
3688
3689 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3690 void MacroAssembler::tlab_allocate(Register obj,
3691 Register var_size_in_bytes,
3692 int con_size_in_bytes,
3693 Register t1,
3694 Register t2,
3695 Label& slow_case) {
3696 assert_different_registers(obj, t2);
3697 assert_different_registers(obj, var_size_in_bytes);
3698 Register end = t2;
3699
3700 // verify_tlab();
3701
3702 ldr(obj, Address(rthread, JavaThread::tlab_top_offset()));
3703 if (var_size_in_bytes == noreg) {
3704 lea(end, Address(obj, con_size_in_bytes));
3705 } else {
3706 lea(end, Address(obj, var_size_in_bytes));
3707 }
3708 ldr(rscratch1, Address(rthread, JavaThread::tlab_end_offset()));
3709 cmp(end, rscratch1);
3710 br(Assembler::HI, slow_case);
3711
3712 // update the tlab top pointer
3713 str(end, Address(rthread, JavaThread::tlab_top_offset()));
3714
3715 // recover var_size_in_bytes if necessary
3716 if (var_size_in_bytes == end) {
3717 sub(var_size_in_bytes, var_size_in_bytes, obj);
3718 }
3719 // verify_tlab();
3720 }
3721
3722 // Preserves r19, and r3.
3723 Register MacroAssembler::tlab_refill(Label& retry,
3724 Label& try_eden,
3725 Label& slow_case) {
3726 Register top = r0;
3727 Register t1 = r2;
3728 Register t2 = r4;
3729 assert_different_registers(top, rthread, t1, t2, /* preserve: */ r19, r3);
3730 Label do_refill, discard_tlab;
3731
3732 if (!Universe::heap()->supports_inline_contig_alloc()) {
3733 // No allocation in the shared eden.
3734 b(slow_case);
3735 }
3736
3737 ldr(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3738 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
3739
3740 // calculate amount of free space
3741 sub(t1, t1, top);
3742 lsr(t1, t1, LogHeapWordSize);
3743
3744 // Retain tlab and allocate object in shared space if
3745 // the amount free in the tlab is too large to discard.
3746
3747 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
3748 cmp(t1, rscratch1);
3749 br(Assembler::LE, discard_tlab);
3750
3751 // Retain
3752 // ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
3753 mov(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
3754 add(rscratch1, rscratch1, t2);
3755 str(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
3756
3757 if (TLABStats) {
3758 // increment number of slow_allocations
3759 addmw(Address(rthread, in_bytes(JavaThread::tlab_slow_allocations_offset())),
3760 1, rscratch1);
3761 }
3762 b(try_eden);
3763
3764 bind(discard_tlab);
3765 if (TLABStats) {
3766 // increment number of refills
3767 addmw(Address(rthread, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1,
3768 rscratch1);
3769 // accumulate wastage -- t1 is amount free in tlab
3770 addmw(Address(rthread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1,
3771 rscratch1);
3772 }
3773
3774 // if tlab is currently allocated (top or end != null) then
3775 // fill [top, end + alignment_reserve) with array object
3776 cbz(top, do_refill);
3777
3778 // set up the mark word
3779 mov(rscratch1, (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
3780 str(rscratch1, Address(top, oopDesc::mark_offset_in_bytes()));
3781 // set the length to the remaining space
3782 sub(t1, t1, typeArrayOopDesc::header_size(T_INT));
3783 add(t1, t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
3784 lsl(t1, t1, log2_intptr(HeapWordSize/sizeof(jint)));
3785 strw(t1, Address(top, arrayOopDesc::length_offset_in_bytes()));
3786 // set klass to intArrayKlass
3787 {
3788 unsigned long offset;
3789 // dubious reloc why not an oop reloc?
3790 far_adrp(rscratch1, ExternalAddress((address)Universe::intArrayKlassObj_addr()),
3791 offset);
3792 ldr(t1, Address(rscratch1, offset));
3793 }
3794 // store klass last. concurrent gcs assumes klass length is valid if
3795 // klass field is not null.
3796 store_klass(top, t1);
3797
3798 mov(t1, top);
3799 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
3800 sub(t1, t1, rscratch1);
3801 incr_allocated_bytes(rthread, t1, 0, rscratch1);
3802
3803 // refill the tlab with an eden allocation
3804 bind(do_refill);
3805 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_size_offset())));
3806 lsl(t1, t1, LogHeapWordSize);
3807 // allocate new tlab, address returned in top
3808 eden_allocate(top, t1, 0, t2, slow_case);
3809
3810 // Check that t1 was preserved in eden_allocate.
3811 #ifdef ASSERT
3812 if (UseTLAB) {
3813 Label ok;
3814 Register tsize = r4;
3815 assert_different_registers(tsize, rthread, t1);
3816 str(tsize, Address(pre(sp, -16)));
3817 ldr(tsize, Address(rthread, in_bytes(JavaThread::tlab_size_offset())));
3818 lsl(tsize, tsize, LogHeapWordSize);
3819 cmp(t1, tsize);
3820 br(Assembler::EQ, ok);
3821 STOP("assert(t1 != tlab size)");
3822 should_not_reach_here();
3823
3824 bind(ok);
3825 ldr(tsize, Address(post(sp, 16)));
3826 }
3827 #endif
3828 str(top, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
3829 str(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3830 add(top, top, t1);
3831 sub(top, top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
3832 str(top, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
3833 verify_tlab();
3834 b(retry);
3835
3836 return rthread; // for use by caller
3837 }
3838
3839 // Defines obj, preserves var_size_in_bytes
3840 void MacroAssembler::eden_allocate(Register obj,
3841 Register var_size_in_bytes,
3842 int con_size_in_bytes,
3843 Register t1,
3844 Label& slow_case) {
3845 assert_different_registers(obj, var_size_in_bytes, t1);
3846 if (!Universe::heap()->supports_inline_contig_alloc()) {
3847 b(slow_case);
3848 } else {
3849 Register end = t1;
3850 Register heap_end = rscratch2;
3851 Label retry;
3852 bind(retry);
3853 {
3854 unsigned long offset;
3855 far_adrp(rscratch1, ExternalAddress((address) Universe::heap()->end_addr()), offset);
3856 ldr(heap_end, Address(rscratch1, offset));
3857 }
3858
3859 ExternalAddress heap_top((address) Universe::heap()->top_addr());
3860
3861 // Get the current top of the heap
3862 {
3863 unsigned long offset;
3864 far_adrp(rscratch1, heap_top, offset);
3865 // Use add() here after ARDP, rather than lea().
3866 // lea() does not generate anything if its offset is zero.
3867 // However, relocs expect to find either an ADD or a load/store
3868 // insn after an ADRP. add() always generates an ADD insn, even
3869 // for add(Rn, Rn, 0).
3870 add(rscratch1, rscratch1, offset);
3871 ldaxr(obj, rscratch1);
3872 }
3873
3874 // Adjust it my the size of our new object
3875 if (var_size_in_bytes == noreg) {
3876 lea(end, Address(obj, con_size_in_bytes));
3877 } else {
3878 lea(end, Address(obj, var_size_in_bytes));
3879 }
3880
3881 // if end < obj then we wrapped around high memory
3882 cmp(end, obj);
3883 br(Assembler::LO, slow_case);
3884
3885 cmp(end, heap_end);
3886 br(Assembler::HI, slow_case);
3887
3888 // If heap_top hasn't been changed by some other thread, update it.
3889 stlxr(rscratch2, end, rscratch1);
3890 cbnzw(rscratch2, retry);
3891 }
3892 }
3893
3894 void MacroAssembler::verify_tlab() {
3895 #ifdef ASSERT
3896 if (UseTLAB && VerifyOops) {
3897 Label next, ok;
3898
3899 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
3900
3901 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3902 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
3903 cmp(rscratch2, rscratch1);
3904 br(Assembler::HS, next);
3905 STOP("assert(top >= start)");
3906 should_not_reach_here();
3907
3908 bind(next);
3909 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
3910 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3911 cmp(rscratch2, rscratch1);
3912 br(Assembler::HS, ok);
3913 STOP("assert(top <= end)");
3914 should_not_reach_here();
3915
3916 bind(ok);
3917 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
3918 }
3919 #endif
3920 }
3921
3922 // Writes to stack successive pages until offset reached to check for
3923 // stack overflow + shadow pages. This clobbers tmp.
3924 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
3925 assert_different_registers(tmp, size, rscratch1);
3926 mov(tmp, sp);
3927 // Bang stack for total size given plus shadow page size.
3928 // Bang one page at a time because large size can bang beyond yellow and
3929 // red zones.
3930 Label loop;
3931 mov(rscratch1, os::vm_page_size());
3932 bind(loop);
3933 lea(tmp, Address(tmp, -os::vm_page_size()));
3934 subsw(size, size, rscratch1);
3935 str(size, Address(tmp));
3936 br(Assembler::GT, loop);
3937
3938 // Bang down shadow pages too.
3939 // At this point, (tmp-0) is the last address touched, so don't
3940 // touch it again. (It was touched as (tmp-pagesize) but then tmp
3941 // was post-decremented.) Skip this address by starting at i=1, and
3942 // touch a few more pages below. N.B. It is important to touch all
3943 // the way down to and including i=StackShadowPages.
3944 for (int i = 0; i< StackShadowPages-1; i++) {
3945 // this could be any sized move but this is can be a debugging crumb
3946 // so the bigger the better.
3947 lea(tmp, Address(tmp, -os::vm_page_size()));
3948 str(size, Address(tmp));
3949 }
3950 }
3951
3952
3953 address MacroAssembler::read_polling_page(Register r, address page, relocInfo::relocType rtype) {
3954 unsigned long off;
3955 far_adrp(r, Address(page, rtype), off);
3956 InstructionMark im(this);
3957 code_section()->relocate(inst_mark(), rtype);
3958 ldrw(zr, Address(r, off));
3959 return inst_mark();
3960 }
3961
3962 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
3963 InstructionMark im(this);
3964 code_section()->relocate(inst_mark(), rtype);
3965 ldrw(zr, Address(r, 0));
3966 return inst_mark();
3967 }
3968
3969 void MacroAssembler::far_adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
3970 uint64_t pc_page = (uint64_t)pc() >> 12;
3971 uint64_t adr_page = (uint64_t)dest.target() >> 12;
3972 int64_t offset = adr_page - pc_page;
3973
3974 InstructionMark im(this);
3975 code_section()->relocate(inst_mark(), dest.rspec());
3976 if (offset >= -(1<<20) && offset < (1<<20)) {
3977 _adrp(reg1, dest.target());
3978 nop();
3979 } else {
3980 offset = (offset & ((1<<20)-1)) << 12;
3981 _adrp(reg1, pc()+offset);
3982 movk(reg1, ((uint64_t)dest.target() >> 32) & 0xffff, 32);
3983 }
3984 byte_offset = (uint64_t)dest.target() & 0xfff;
3985 }
3986
3987 void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
3988 uint64_t pc_page = (uint64_t)pc() >> 12;
3989 uint64_t adr_page = (uint64_t)dest.target() >> 12;
3990 int64_t offset = adr_page - pc_page;
3991 guarantee(offset >= -(1<<20) && offset < (1<<20), "adrp out of range, use far_adrp");
3992 InstructionMark im(this);
3993 code_section()->relocate(inst_mark(), dest.rspec());
3994 byte_offset = (uint64_t)dest.target() & 0xfff;
3995 _adrp(reg1, dest.target());
3996 }
3997
3998 void MacroAssembler::build_frame(int framesize) {
3999 assert(framesize > 0, "framesize must be > 0");
4000 if (framesize < ((1 << 9) + 2 * wordSize)) {
4001 sub(sp, sp, framesize);
4002 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4003 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
4004 } else {
4005 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
4006 if (PreserveFramePointer) mov(rfp, sp);
4007 if (framesize < ((1 << 12) + 2 * wordSize))
4008 sub(sp, sp, framesize - 2 * wordSize);
4009 else {
4010 mov(rscratch1, framesize - 2 * wordSize);
4011 sub(sp, sp, rscratch1);
4012 }
4013 }
4014 }
4015
4016 void MacroAssembler::remove_frame(int framesize) {
4017 assert(framesize > 0, "framesize must be > 0");
4018 if (framesize < ((1 << 9) + 2 * wordSize)) {
4019 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4020 add(sp, sp, framesize);
4021 } else {
4022 if (framesize < ((1 << 12) + 2 * wordSize))
4023 add(sp, sp, framesize - 2 * wordSize);
4024 else {
4025 mov(rscratch1, framesize - 2 * wordSize);
4026 add(sp, sp, rscratch1);
4027 }
4028 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
4029 }
4030 }
4031
4032
4033 // Search for str1 in str2 and return index or -1
4034 void MacroAssembler::string_indexof(Register str2, Register str1,
4035 Register cnt2, Register cnt1,
4036 Register tmp1, Register tmp2,
4037 Register tmp3, Register tmp4,
4038 int icnt1, Register result) {
4039 Label BM, LINEARSEARCH, DONE, NOMATCH, MATCH;
4040
4041 Register ch1 = rscratch1;
4042 Register ch2 = rscratch2;
4043 Register cnt1tmp = tmp1;
4044 Register cnt2tmp = tmp2;
4045 Register cnt1_neg = cnt1;
4046 Register cnt2_neg = cnt2;
4047 Register result_tmp = tmp4;
4048
4049 // Note, inline_string_indexOf() generates checks:
4050 // if (substr.count > string.count) return -1;
4051 // if (substr.count == 0) return 0;
4052
4053 // We have two strings, a source string in str2, cnt2 and a pattern string
4054 // in str1, cnt1. Find the 1st occurence of pattern in source or return -1.
4055
4056 // For larger pattern and source we use a simplified Boyer Moore algorithm.
4057 // With a small pattern and source we use linear scan.
4058
4059 if (icnt1 == -1) {
4060 cmp(cnt1, 256); // Use Linear Scan if cnt1 < 8 || cnt1 >= 256
4061 ccmp(cnt1, 8, 0b0000, LO); // Can't handle skip >= 256 because we use
4062 br(LO, LINEARSEARCH); // a byte array.
4063 cmp(cnt1, cnt2, LSR, 2); // Source must be 4 * pattern for BM
4064 br(HS, LINEARSEARCH);
4065 }
4066
4067 // The Boyer Moore alogorithm is based on the description here:-
4068 //
4069 // http://en.wikipedia.org/wiki/Boyer%E2%80%93Moore_string_search_algorithm
4070 //
4071 // This describes and algorithm with 2 shift rules. The 'Bad Character' rule
4072 // and the 'Good Suffix' rule.
4073 //
4074 // These rules are essentially heuristics for how far we can shift the
4075 // pattern along the search string.
4076 //
4077 // The implementation here uses the 'Bad Character' rule only because of the
4078 // complexity of initialisation for the 'Good Suffix' rule.
4079 //
4080 // This is also known as the Boyer-Moore-Horspool algorithm:-
4081 //
4082 // http://en.wikipedia.org/wiki/Boyer-Moore-Horspool_algorithm
4083 //
4084 // #define ASIZE 128
4085 //
4086 // int bm(unsigned char *x, int m, unsigned char *y, int n) {
4087 // int i, j;
4088 // unsigned c;
4089 // unsigned char bc[ASIZE];
4090 //
4091 // /* Preprocessing */
4092 // for (i = 0; i < ASIZE; ++i)
4093 // bc[i] = 0;
4094 // for (i = 0; i < m - 1; ) {
4095 // c = x[i];
4096 // ++i;
4097 // if (c < ASIZE) bc[c] = i;
4098 // }
4099 //
4100 // /* Searching */
4101 // j = 0;
4102 // while (j <= n - m) {
4103 // c = y[i+j];
4104 // if (x[m-1] == c)
4105 // for (i = m - 2; i >= 0 && x[i] == y[i + j]; --i);
4106 // if (i < 0) return j;
4107 // if (c < ASIZE)
4108 // j = j - bc[y[j+m-1]] + m;
4109 // else
4110 // j += 1; // Advance by 1 only if char >= ASIZE
4111 // }
4112 // }
4113
4114 if (icnt1 == -1) {
4115 BIND(BM);
4116
4117 Label ZLOOP, BCLOOP, BCSKIP, BMLOOPSTR2, BMLOOPSTR1, BMSKIP;
4118 Label BMADV, BMMATCH, BMCHECKEND;
4119
4120 Register cnt1end = tmp2;
4121 Register str2end = cnt2;
4122 Register skipch = tmp2;
4123
4124 // Restrict ASIZE to 128 to reduce stack space/initialisation.
4125 // The presence of chars >= ASIZE in the target string does not affect
4126 // performance, but we must be careful not to initialise them in the stack
4127 // array.
4128 // The presence of chars >= ASIZE in the source string may adversely affect
4129 // performance since we can only advance by one when we encounter one.
4130
4131 stp(zr, zr, pre(sp, -128));
4132 for (int i = 1; i < 8; i++)
4133 stp(zr, zr, Address(sp, i*16));
4134
4135 mov(cnt1tmp, 0);
4136 sub(cnt1end, cnt1, 1);
4137 BIND(BCLOOP);
4138 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1)));
4139 cmp(ch1, 128);
4140 add(cnt1tmp, cnt1tmp, 1);
4141 br(HS, BCSKIP);
4142 strb(cnt1tmp, Address(sp, ch1));
4143 BIND(BCSKIP);
4144 cmp(cnt1tmp, cnt1end);
4145 br(LT, BCLOOP);
4146
4147 mov(result_tmp, str2);
4148
4149 sub(cnt2, cnt2, cnt1);
4150 add(str2end, str2, cnt2, LSL, 1);
4151 BIND(BMLOOPSTR2);
4152 sub(cnt1tmp, cnt1, 1);
4153 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1)));
4154 ldrh(skipch, Address(str2, cnt1tmp, Address::lsl(1)));
4155 cmp(ch1, skipch);
4156 br(NE, BMSKIP);
4157 subs(cnt1tmp, cnt1tmp, 1);
4158 br(LT, BMMATCH);
4159 BIND(BMLOOPSTR1);
4160 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1)));
4161 ldrh(ch2, Address(str2, cnt1tmp, Address::lsl(1)));
4162 cmp(ch1, ch2);
4163 br(NE, BMSKIP);
4164 subs(cnt1tmp, cnt1tmp, 1);
4165 br(GE, BMLOOPSTR1);
4166 BIND(BMMATCH);
4167 sub(result_tmp, str2, result_tmp);
4168 lsr(result, result_tmp, 1);
4169 add(sp, sp, 128);
4170 b(DONE);
4171 BIND(BMADV);
4172 add(str2, str2, 2);
4173 b(BMCHECKEND);
4174 BIND(BMSKIP);
4175 cmp(skipch, 128);
4176 br(HS, BMADV);
4177 ldrb(ch2, Address(sp, skipch));
4178 add(str2, str2, cnt1, LSL, 1);
4179 sub(str2, str2, ch2, LSL, 1);
4180 BIND(BMCHECKEND);
4181 cmp(str2, str2end);
4182 br(LE, BMLOOPSTR2);
4183 add(sp, sp, 128);
4184 b(NOMATCH);
4185 }
4186
4187 BIND(LINEARSEARCH);
4188 {
4189 Label DO1, DO2, DO3;
4190
4191 Register str2tmp = tmp2;
4192 Register first = tmp3;
4193
4194 if (icnt1 == -1)
4195 {
4196 Label DOSHORT, FIRST_LOOP, STR2_NEXT, STR1_LOOP, STR1_NEXT, LAST_WORD;
4197
4198 cmp(cnt1, 4);
4199 br(LT, DOSHORT);
4200
4201 sub(cnt2, cnt2, cnt1);
4202 sub(cnt1, cnt1, 4);
4203 mov(result_tmp, cnt2);
4204
4205 lea(str1, Address(str1, cnt1, Address::uxtw(1)));
4206 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4207 sub(cnt1_neg, zr, cnt1, LSL, 1);
4208 sub(cnt2_neg, zr, cnt2, LSL, 1);
4209 ldr(first, Address(str1, cnt1_neg));
4210
4211 BIND(FIRST_LOOP);
4212 ldr(ch2, Address(str2, cnt2_neg));
4213 cmp(first, ch2);
4214 br(EQ, STR1_LOOP);
4215 BIND(STR2_NEXT);
4216 adds(cnt2_neg, cnt2_neg, 2);
4217 br(LE, FIRST_LOOP);
4218 b(NOMATCH);
4219
4220 BIND(STR1_LOOP);
4221 adds(cnt1tmp, cnt1_neg, 8);
4222 add(cnt2tmp, cnt2_neg, 8);
4223 br(GE, LAST_WORD);
4224
4225 BIND(STR1_NEXT);
4226 ldr(ch1, Address(str1, cnt1tmp));
4227 ldr(ch2, Address(str2, cnt2tmp));
4228 cmp(ch1, ch2);
4229 br(NE, STR2_NEXT);
4230 adds(cnt1tmp, cnt1tmp, 8);
4231 add(cnt2tmp, cnt2tmp, 8);
4232 br(LT, STR1_NEXT);
4233
4234 BIND(LAST_WORD);
4235 ldr(ch1, Address(str1));
4236 sub(str2tmp, str2, cnt1_neg); // adjust to corresponding
4237 ldr(ch2, Address(str2tmp, cnt2_neg)); // word in str2
4238 cmp(ch1, ch2);
4239 br(NE, STR2_NEXT);
4240 b(MATCH);
4241
4242 BIND(DOSHORT);
4243 cmp(cnt1, 2);
4244 br(LT, DO1);
4245 br(GT, DO3);
4246 }
4247
4248 if (icnt1 == 4) {
4249 Label CH1_LOOP;
4250
4251 ldr(ch1, str1);
4252 sub(cnt2, cnt2, 4);
4253 mov(result_tmp, cnt2);
4254 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4255 sub(cnt2_neg, zr, cnt2, LSL, 1);
4256
4257 BIND(CH1_LOOP);
4258 ldr(ch2, Address(str2, cnt2_neg));
4259 cmp(ch1, ch2);
4260 br(EQ, MATCH);
4261 adds(cnt2_neg, cnt2_neg, 2);
4262 br(LE, CH1_LOOP);
4263 b(NOMATCH);
4264 }
4265
4266 if (icnt1 == -1 || icnt1 == 2) {
4267 Label CH1_LOOP;
4268
4269 BIND(DO2);
4270 ldrw(ch1, str1);
4271 sub(cnt2, cnt2, 2);
4272 mov(result_tmp, cnt2);
4273 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4274 sub(cnt2_neg, zr, cnt2, LSL, 1);
4275
4276 BIND(CH1_LOOP);
4277 ldrw(ch2, Address(str2, cnt2_neg));
4278 cmp(ch1, ch2);
4279 br(EQ, MATCH);
4280 adds(cnt2_neg, cnt2_neg, 2);
4281 br(LE, CH1_LOOP);
4282 b(NOMATCH);
4283 }
4284
4285 if (icnt1 == -1 || icnt1 == 3) {
4286 Label FIRST_LOOP, STR2_NEXT, STR1_LOOP;
4287
4288 BIND(DO3);
4289 ldrw(first, str1);
4290 ldrh(ch1, Address(str1, 4));
4291
4292 sub(cnt2, cnt2, 3);
4293 mov(result_tmp, cnt2);
4294 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4295 sub(cnt2_neg, zr, cnt2, LSL, 1);
4296
4297 BIND(FIRST_LOOP);
4298 ldrw(ch2, Address(str2, cnt2_neg));
4299 cmpw(first, ch2);
4300 br(EQ, STR1_LOOP);
4301 BIND(STR2_NEXT);
4302 adds(cnt2_neg, cnt2_neg, 2);
4303 br(LE, FIRST_LOOP);
4304 b(NOMATCH);
4305
4306 BIND(STR1_LOOP);
4307 add(cnt2tmp, cnt2_neg, 4);
4308 ldrh(ch2, Address(str2, cnt2tmp));
4309 cmp(ch1, ch2);
4310 br(NE, STR2_NEXT);
4311 b(MATCH);
4312 }
4313
4314 if (icnt1 == -1 || icnt1 == 1) {
4315 Label CH1_LOOP, HAS_ZERO;
4316 Label DO1_SHORT, DO1_LOOP;
4317
4318 BIND(DO1);
4319 ldrh(ch1, str1);
4320 cmp(cnt2, 4);
4321 br(LT, DO1_SHORT);
4322
4323 orr(ch1, ch1, ch1, LSL, 16);
4324 orr(ch1, ch1, ch1, LSL, 32);
4325
4326 sub(cnt2, cnt2, 4);
4327 mov(result_tmp, cnt2);
4328 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4329 sub(cnt2_neg, zr, cnt2, LSL, 1);
4330
4331 mov(tmp3, 0x0001000100010001);
4332 BIND(CH1_LOOP);
4333 ldr(ch2, Address(str2, cnt2_neg));
4334 eor(ch2, ch1, ch2);
4335 sub(tmp1, ch2, tmp3);
4336 orr(tmp2, ch2, 0x7fff7fff7fff7fff);
4337 bics(tmp1, tmp1, tmp2);
4338 br(NE, HAS_ZERO);
4339 adds(cnt2_neg, cnt2_neg, 8);
4340 br(LT, CH1_LOOP);
4341
4342 cmp(cnt2_neg, 8);
4343 mov(cnt2_neg, 0);
4344 br(LT, CH1_LOOP);
4345 b(NOMATCH);
4346
4347 BIND(HAS_ZERO);
4348 rev(tmp1, tmp1);
4349 clz(tmp1, tmp1);
4350 add(cnt2_neg, cnt2_neg, tmp1, LSR, 3);
4351 b(MATCH);
4352
4353 BIND(DO1_SHORT);
4354 mov(result_tmp, cnt2);
4355 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4356 sub(cnt2_neg, zr, cnt2, LSL, 1);
4357 BIND(DO1_LOOP);
4358 ldrh(ch2, Address(str2, cnt2_neg));
4359 cmpw(ch1, ch2);
4360 br(EQ, MATCH);
4361 adds(cnt2_neg, cnt2_neg, 2);
4362 br(LT, DO1_LOOP);
4363 }
4364 }
4365 BIND(NOMATCH);
4366 mov(result, -1);
4367 b(DONE);
4368 BIND(MATCH);
4369 add(result, result_tmp, cnt2_neg, ASR, 1);
4370 BIND(DONE);
4371 }
4372
4373 // Compare strings.
4374 void MacroAssembler::string_compare(Register str1, Register str2,
4375 Register cnt1, Register cnt2, Register result,
4376 Register tmp1) {
4377 Label LENGTH_DIFF, DONE, SHORT_LOOP, SHORT_STRING,
4378 NEXT_WORD, DIFFERENCE;
4379
4380 BLOCK_COMMENT("string_compare {");
4381
4382 // Compute the minimum of the string lengths and save the difference.
4383 subsw(tmp1, cnt1, cnt2);
4384 cselw(cnt2, cnt1, cnt2, Assembler::LE); // min
4385
4386 // A very short string
4387 cmpw(cnt2, 4);
4388 br(Assembler::LT, SHORT_STRING);
4389
4390 // Check if the strings start at the same location.
4391 cmp(str1, str2);
4392 br(Assembler::EQ, LENGTH_DIFF);
4393
4394 // Compare longwords
4395 {
4396 subw(cnt2, cnt2, 4); // The last longword is a special case
4397
4398 // Move both string pointers to the last longword of their
4399 // strings, negate the remaining count, and convert it to bytes.
4400 lea(str1, Address(str1, cnt2, Address::uxtw(1)));
4401 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4402 sub(cnt2, zr, cnt2, LSL, 1);
4403
4404 // Loop, loading longwords and comparing them into rscratch2.
4405 bind(NEXT_WORD);
4406 ldr(result, Address(str1, cnt2));
4407 ldr(cnt1, Address(str2, cnt2));
4408 adds(cnt2, cnt2, wordSize);
4409 eor(rscratch2, result, cnt1);
4410 cbnz(rscratch2, DIFFERENCE);
4411 br(Assembler::LT, NEXT_WORD);
4412
4413 // Last longword. In the case where length == 4 we compare the
4414 // same longword twice, but that's still faster than another
4415 // conditional branch.
4416
4417 ldr(result, Address(str1));
4418 ldr(cnt1, Address(str2));
4419 eor(rscratch2, result, cnt1);
4420 cbz(rscratch2, LENGTH_DIFF);
4421
4422 // Find the first different characters in the longwords and
4423 // compute their difference.
4424 bind(DIFFERENCE);
4425 rev(rscratch2, rscratch2);
4426 clz(rscratch2, rscratch2);
4427 andr(rscratch2, rscratch2, -16);
4428 lsrv(result, result, rscratch2);
4429 uxthw(result, result);
4430 lsrv(cnt1, cnt1, rscratch2);
4431 uxthw(cnt1, cnt1);
4432 subw(result, result, cnt1);
4433 b(DONE);
4434 }
4435
4436 bind(SHORT_STRING);
4437 // Is the minimum length zero?
4438 cbz(cnt2, LENGTH_DIFF);
4439
4440 bind(SHORT_LOOP);
4441 load_unsigned_short(result, Address(post(str1, 2)));
4442 load_unsigned_short(cnt1, Address(post(str2, 2)));
4443 subw(result, result, cnt1);
4444 cbnz(result, DONE);
4445 sub(cnt2, cnt2, 1);
4446 cbnz(cnt2, SHORT_LOOP);
4447
4448 // Strings are equal up to min length. Return the length difference.
4449 bind(LENGTH_DIFF);
4450 mov(result, tmp1);
4451
4452 // That's it
4453 bind(DONE);
4454
4455 BLOCK_COMMENT("} string_compare");
4456 }
4457
4458
4459 void MacroAssembler::string_equals(Register str1, Register str2,
4460 Register cnt, Register result,
4461 Register tmp1) {
4462 Label SAME_CHARS, DONE, SHORT_LOOP, SHORT_STRING,
4463 NEXT_WORD;
4464
4465 const Register tmp2 = rscratch1;
4466 assert_different_registers(str1, str2, cnt, result, tmp1, tmp2, rscratch2);
4467
4468 BLOCK_COMMENT("string_equals {");
4469
4470 // Start by assuming that the strings are not equal.
4471 mov(result, zr);
4472
4473 // A very short string
4474 cmpw(cnt, 4);
4475 br(Assembler::LT, SHORT_STRING);
4476
4477 // Check if the strings start at the same location.
4478 cmp(str1, str2);
4479 br(Assembler::EQ, SAME_CHARS);
4480
4481 // Compare longwords
4482 {
4483 subw(cnt, cnt, 4); // The last longword is a special case
4484
4485 // Move both string pointers to the last longword of their
4486 // strings, negate the remaining count, and convert it to bytes.
4487 lea(str1, Address(str1, cnt, Address::uxtw(1)));
4488 lea(str2, Address(str2, cnt, Address::uxtw(1)));
4489 sub(cnt, zr, cnt, LSL, 1);
4490
4491 // Loop, loading longwords and comparing them into rscratch2.
4492 bind(NEXT_WORD);
4493 ldr(tmp1, Address(str1, cnt));
4494 ldr(tmp2, Address(str2, cnt));
4495 adds(cnt, cnt, wordSize);
4496 eor(rscratch2, tmp1, tmp2);
4497 cbnz(rscratch2, DONE);
4498 br(Assembler::LT, NEXT_WORD);
4499
4500 // Last longword. In the case where length == 4 we compare the
4501 // same longword twice, but that's still faster than another
4502 // conditional branch.
4503
4504 ldr(tmp1, Address(str1));
4505 ldr(tmp2, Address(str2));
4506 eor(rscratch2, tmp1, tmp2);
4507 cbz(rscratch2, SAME_CHARS);
4508 b(DONE);
4509 }
4510
4511 bind(SHORT_STRING);
4512 // Is the length zero?
4513 cbz(cnt, SAME_CHARS);
4514
4515 bind(SHORT_LOOP);
4516 load_unsigned_short(tmp1, Address(post(str1, 2)));
4517 load_unsigned_short(tmp2, Address(post(str2, 2)));
4518 subw(tmp1, tmp1, tmp2);
4519 cbnz(tmp1, DONE);
4520 sub(cnt, cnt, 1);
4521 cbnz(cnt, SHORT_LOOP);
4522
4523 // Strings are equal.
4524 bind(SAME_CHARS);
4525 mov(result, true);
4526
4527 // That's it
4528 bind(DONE);
4529
4530 BLOCK_COMMENT("} string_equals");
4531 }
4532
4533 // Compare char[] arrays aligned to 4 bytes
4534 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2,
4535 Register result, Register tmp1)
4536 {
4537 Register cnt1 = rscratch1;
4538 Register cnt2 = rscratch2;
4539 Register tmp2 = rscratch2;
4540
4541 Label SAME, DIFFER, NEXT, TAIL03, TAIL01;
4542
4543 int length_offset = arrayOopDesc::length_offset_in_bytes();
4544 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
4545
4546 BLOCK_COMMENT("char_arrays_equals {");
4547
4548 // different until proven equal
4549 mov(result, false);
4550
4551 // same array?
4552 cmp(ary1, ary2);
4553 br(Assembler::EQ, SAME);
4554
4555 // ne if either null
4556 cbz(ary1, DIFFER);
4557 cbz(ary2, DIFFER);
4558
4559 // lengths ne?
4560 ldrw(cnt1, Address(ary1, length_offset));
4561 ldrw(cnt2, Address(ary2, length_offset));
4562 cmp(cnt1, cnt2);
4563 br(Assembler::NE, DIFFER);
4564
4565 lea(ary1, Address(ary1, base_offset));
4566 lea(ary2, Address(ary2, base_offset));
4567
4568 subs(cnt1, cnt1, 4);
4569 br(LT, TAIL03);
4570
4571 BIND(NEXT);
4572 ldr(tmp1, Address(post(ary1, 8)));
4573 ldr(tmp2, Address(post(ary2, 8)));
4574 subs(cnt1, cnt1, 4);
4575 eor(tmp1, tmp1, tmp2);
4576 cbnz(tmp1, DIFFER);
4577 br(GE, NEXT);
4578
4579 BIND(TAIL03); // 0-3 chars left, cnt1 = #chars left - 4
4580 tst(cnt1, 0b10);
4581 br(EQ, TAIL01);
4582 ldrw(tmp1, Address(post(ary1, 4)));
4583 ldrw(tmp2, Address(post(ary2, 4)));
4584 cmp(tmp1, tmp2);
4585 br(NE, DIFFER);
4586 BIND(TAIL01); // 0-1 chars left
4587 tst(cnt1, 0b01);
4588 br(EQ, SAME);
4589 ldrh(tmp1, ary1);
4590 ldrh(tmp2, ary2);
4591 cmp(tmp1, tmp2);
4592 br(NE, DIFFER);
4593
4594 BIND(SAME);
4595 mov(result, true);
4596 BIND(DIFFER); // result already set
4597
4598 BLOCK_COMMENT("} char_arrays_equals");
4599 }
4600
4601 // encode char[] to byte[] in ISO_8859_1
4602 void MacroAssembler::encode_iso_array(Register src, Register dst,
4603 Register len, Register result,
4604 FloatRegister Vtmp1, FloatRegister Vtmp2,
4605 FloatRegister Vtmp3, FloatRegister Vtmp4)
4606 {
4607 Label DONE, NEXT_32, LOOP_8, NEXT_8, LOOP_1, NEXT_1;
4608 Register tmp1 = rscratch1;
4609
4610 mov(result, len); // Save initial len
4611
4612 #ifndef BUILTIN_SIM
4613 subs(len, len, 32);
4614 br(LT, LOOP_8);
4615
4616 // The following code uses the SIMD 'uqxtn' and 'uqxtn2' instructions
4617 // to convert chars to bytes. These set the 'QC' bit in the FPSR if
4618 // any char could not fit in a byte, so clear the FPSR so we can test it.
4619 clear_fpsr();
4620
4621 BIND(NEXT_32);
4622 ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src);
4623 uqxtn(Vtmp1, T8B, Vtmp1, T8H); // uqxtn - write bottom half
4624 uqxtn(Vtmp1, T16B, Vtmp2, T8H); // uqxtn2 - write top half
4625 uqxtn(Vtmp2, T8B, Vtmp3, T8H);
4626 uqxtn(Vtmp2, T16B, Vtmp4, T8H); // uqxtn2
4627 get_fpsr(tmp1);
4628 cbnzw(tmp1, LOOP_8);
4629 st1(Vtmp1, Vtmp2, T16B, post(dst, 32));
4630 subs(len, len, 32);
4631 add(src, src, 64);
4632 br(GE, NEXT_32);
4633
4634 BIND(LOOP_8);
4635 adds(len, len, 32-8);
4636 br(LT, LOOP_1);
4637 clear_fpsr(); // QC may be set from loop above, clear again
4638 BIND(NEXT_8);
4639 ld1(Vtmp1, T8H, src);
4640 uqxtn(Vtmp1, T8B, Vtmp1, T8H);
4641 get_fpsr(tmp1);
4642 cbnzw(tmp1, LOOP_1);
4643 st1(Vtmp1, T8B, post(dst, 8));
4644 subs(len, len, 8);
4645 add(src, src, 16);
4646 br(GE, NEXT_8);
4647
4648 BIND(LOOP_1);
4649 adds(len, len, 8);
4650 br(LE, DONE);
4651 #else
4652 cbz(len, DONE);
4653 #endif
4654 BIND(NEXT_1);
4655 ldrh(tmp1, Address(post(src, 2)));
4656 tst(tmp1, 0xff00);
4657 br(NE, DONE);
4658 strb(tmp1, Address(post(dst, 1)));
4659 subs(len, len, 1);
4660 br(GT, NEXT_1);
4661
4662 BIND(DONE);
4663 sub(result, result, len); // Return index where we stopped
4664 }