1061 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1062 } \
1063 \
1064 void INSN(Register Rd, Register Rn, Register Rm) { \
1065 Assembler::INSN(Rd, Rn, Rm); \
1066 } \
1067 \
1068 void INSN(Register Rd, Register Rn, Register Rm, \
1069 ext::operation option, int amount = 0) { \
1070 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1071 }
1072
1073 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1074
1075 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1076 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1077 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1078 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1079
1080 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1081
1082 void tableswitch(Register index, jint lowbound, jint highbound,
1083 Label &jumptable, Label &jumptable_end, int stride = 1) {
1084 adr(rscratch1, jumptable);
1085 subsw(rscratch2, index, lowbound);
1086 subsw(zr, rscratch2, highbound - lowbound);
1087 br(Assembler::HS, jumptable_end);
1088 add(rscratch1, rscratch1, rscratch2,
1089 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1090 br(rscratch1);
1091 }
1092
1093 // Form an address from base + offset in Rd. Rd may or may not
1094 // actually be used: you must use the Address that is returned. It
1095 // is up to you to ensure that the shift provided matches the size
1096 // of your data.
1097 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1098
1099 // Prolog generator routines to support switch between x86 code and
1100 // generated ARM code
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1061 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1062 } \
1063 \
1064 void INSN(Register Rd, Register Rn, Register Rm) { \
1065 Assembler::INSN(Rd, Rn, Rm); \
1066 } \
1067 \
1068 void INSN(Register Rd, Register Rn, Register Rm, \
1069 ext::operation option, int amount = 0) { \
1070 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1071 }
1072
1073 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1074
1075 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1076 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1077 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1078 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1079
1080 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1081 void far_adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1082
1083 void tableswitch(Register index, jint lowbound, jint highbound,
1084 Label &jumptable, Label &jumptable_end, int stride = 1) {
1085 adr(rscratch1, jumptable);
1086 subsw(rscratch2, index, lowbound);
1087 subsw(zr, rscratch2, highbound - lowbound);
1088 br(Assembler::HS, jumptable_end);
1089 add(rscratch1, rscratch1, rscratch2,
1090 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1091 br(rscratch1);
1092 }
1093
1094 // Form an address from base + offset in Rd. Rd may or may not
1095 // actually be used: you must use the Address that is returned. It
1096 // is up to you to ensure that the shift provided matches the size
1097 // of your data.
1098 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1099
1100 // Prolog generator routines to support switch between x86 code and
1101 // generated ARM code
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