1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_aarch64.hpp"
33 #ifdef TARGET_OS_FAMILY_linux
34 # include "os_linux.inline.hpp"
35 #endif
36
37 #ifndef BUILTIN_SIM
38 #include <sys/auxv.h>
39 #include <asm/hwcap.h>
40 #else
41 #define getauxval(hwcap) 0
42 #endif
43
44 #ifndef HWCAP_AES
45 #define HWCAP_AES (1<<3)
46 #endif
47
48 #ifndef HWCAP_PMULL
49 #define HWCAP_PMULL (1<<4)
50 #endif
51
52 #ifndef HWCAP_SHA1
53 #define HWCAP_SHA1 (1<<5)
54 #endif
55
56 #ifndef HWCAP_SHA2
57 #define HWCAP_SHA2 (1<<6)
58 #endif
59
60 #ifndef HWCAP_CRC32
61 #define HWCAP_CRC32 (1<<7)
62 #endif
63
64 int VM_Version::_cpu;
65 int VM_Version::_model;
66 int VM_Version::_model2;
67 int VM_Version::_variant;
68 int VM_Version::_revision;
69 int VM_Version::_stepping;
70
71 static BufferBlob* stub_blob;
72 static const int stub_size = 550;
73
74 extern "C" {
75 typedef void (*getPsrInfo_stub_t)(void*);
76 }
77 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
78
79
80 class VM_Version_StubGenerator: public StubCodeGenerator {
81 public:
82
83 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
84
85 address generate_getPsrInfo() {
86 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
87 # define __ _masm->
88 address start = __ pc();
89
90 #ifdef BUILTIN_SIM
91 __ c_stub_prolog(1, 0, MacroAssembler::ret_type_void);
92 #endif
93
94 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
95
96 address entry = __ pc();
97
98 // TODO : redefine fields in CpuidInfo and generate
99 // code to fill them in
100
101 __ ret(lr);
102
103 # undef __
104
105 return start;
106 }
107 };
108
109
110 void VM_Version::get_processor_features() {
111 _supports_cx8 = true;
112 _supports_atomic_getset4 = true;
113 _supports_atomic_getadd4 = true;
114 _supports_atomic_getset8 = true;
115 _supports_atomic_getadd8 = true;
116
117 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
118 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
119 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
120 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, 64);
121 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 256);
122 FLAG_SET_DEFAULT(PrefetchFieldsAhead, 256);
123 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
124 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 256);
125 if ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768)) {
126 warning("PrefetchCopyIntervalInBytes must be a multiple of 8 and < 32768");
127 PrefetchCopyIntervalInBytes &= ~7;
128 if (PrefetchCopyIntervalInBytes >= 32768)
129 PrefetchCopyIntervalInBytes = 32760;
130 }
131
132 unsigned long auxv = getauxval(AT_HWCAP);
133
134 char buf[512];
135
136 _features = auxv;
137
138 int cpu_lines = 0;
139 if (FILE *f = fopen("/proc/cpuinfo", "r")) {
140 char buf[128], *p;
141 while (fgets(buf, sizeof (buf), f) != NULL) {
142 if (p = strchr(buf, ':')) {
143 long v = strtol(p+1, NULL, 0);
144 if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
145 _cpu = v;
146 cpu_lines++;
147 } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
148 _variant = v;
149 } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
150 if (_model != v) _model2 = _model;
151 _model = v;
152 } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
153 _revision = v;
154 }
155 }
156 }
157 fclose(f);
158 }
159
160 // Enable vendor specific features
161 if (_cpu == CPU_CAVIUM && _variant == 0) _features |= CPU_DMB_ATOMICS;
162 if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) _features |= CPU_A53MAC;
163 // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
164 // we assume the worst and assume we could be on a big little system and have
165 // undisclosed A53 cores which we could be swapped to at any stage
166 if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
167
168 sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
169 if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
170 if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
171 if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
172 if (auxv & HWCAP_AES) strcat(buf, ", aes");
173 if (auxv & HWCAP_SHA1) strcat(buf, ", sha1");
174 if (auxv & HWCAP_SHA2) strcat(buf, ", sha256");
175
176 _features_string = os::strdup(buf);
177
178 if (FLAG_IS_DEFAULT(UseCRC32)) {
179 UseCRC32 = (auxv & HWCAP_CRC32) != 0;
180 }
181 if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
182 warning("UseCRC32 specified, but not supported on this CPU");
183 }
184
185 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
186 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
187 }
188
189 if (UseVectorizedMismatchIntrinsic) {
190 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
191 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
192 }
193
194 if (auxv & HWCAP_AES) {
195 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
196 UseAESIntrinsics =
197 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
198 if (UseAESIntrinsics && !UseAES) {
199 warning("UseAESIntrinsics enabled, but UseAES not, enabling");
200 UseAES = true;
201 }
202 } else {
203 if (UseAES) {
204 warning("UseAES specified, but not supported on this CPU");
205 }
206 if (UseAESIntrinsics) {
207 warning("UseAESIntrinsics specified, but not supported on this CPU");
208 }
209 }
210
211 if (UseAESCTRIntrinsics) {
212 warning("AES/CTR intrinsics are not available on this CPU");
213 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
214 }
215
216 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
217 UseCRC32Intrinsics = true;
218 }
219
220 if (auxv & HWCAP_CRC32) {
221 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
222 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
223 }
224 } else if (UseCRC32CIntrinsics) {
225 warning("CRC32C is not available on the CPU");
226 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
227 }
228
229 if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
230 if (FLAG_IS_DEFAULT(UseSHA)) {
231 FLAG_SET_DEFAULT(UseSHA, true);
232 }
233 } else if (UseSHA) {
234 warning("SHA instructions are not available on this CPU");
235 FLAG_SET_DEFAULT(UseSHA, false);
236 }
237
238 if (UseSHA && (auxv & HWCAP_SHA1)) {
239 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
240 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
241 }
242 } else if (UseSHA1Intrinsics) {
243 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
244 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
245 }
246
247 if (UseSHA && (auxv & HWCAP_SHA2)) {
248 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
249 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
250 }
251 } else if (UseSHA256Intrinsics) {
252 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
253 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
254 }
255
256 if (UseSHA512Intrinsics) {
257 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
258 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
259 }
260
261 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
262 FLAG_SET_DEFAULT(UseSHA, false);
263 }
264
265 if (auxv & HWCAP_PMULL) {
266 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
267 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
268 }
269 } else if (UseGHASHIntrinsics) {
270 warning("GHASH intrinsics are not available on this CPU");
271 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
272 }
273
274 // This machine allows unaligned memory accesses
275 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
276 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
277 }
278
279 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
280 UseMultiplyToLenIntrinsic = true;
281 }
282
283 if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) {
284 UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0;
285 }
286
287 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
288 UsePopCountInstruction = true;
289 }
290
291 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
292 UseMontgomeryMultiplyIntrinsic = true;
293 }
294 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
295 UseMontgomerySquareIntrinsic = true;
296 }
297
298 #ifdef COMPILER2
299 if (FLAG_IS_DEFAULT(OptoScheduling)) {
300 OptoScheduling = true;
301 }
302 #endif
303 }
304
305 void VM_Version::initialize() {
306 ResourceMark rm;
307
308 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
309 if (stub_blob == NULL) {
310 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
311 }
312
313 CodeBuffer c(stub_blob);
314 VM_Version_StubGenerator g(&c);
315 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
316 g.generate_getPsrInfo());
317
318 get_processor_features();
319 }