1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include <sys/types.h> 27 28 #include "precompiled.hpp" 29 #include "asm/assembler.hpp" 30 #include "asm/assembler.inline.hpp" 31 #include "interpreter/interpreter.hpp" 32 33 #include "compiler/disassembler.hpp" 34 #include "memory/resourceArea.hpp" 35 #include "nativeInst_aarch64.hpp" 36 #include "oops/klass.inline.hpp" 37 #include "oops/oop.inline.hpp" 38 #include "opto/compile.hpp" 39 #include "opto/node.hpp" 40 #include "runtime/biasedLocking.hpp" 41 #include "runtime/icache.hpp" 42 #include "runtime/interfaceSupport.hpp" 43 #include "runtime/sharedRuntime.hpp" 44 #include "runtime/thread.hpp" 45 46 #if INCLUDE_ALL_GCS 47 #include "gc/g1/g1CollectedHeap.inline.hpp" 48 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 49 #include "gc/g1/heapRegion.hpp" 50 #endif 51 52 #ifdef PRODUCT 53 #define BLOCK_COMMENT(str) /* nothing */ 54 #define STOP(error) stop(error) 55 #else 56 #define BLOCK_COMMENT(str) block_comment(str) 57 #define STOP(error) block_comment(error); stop(error) 58 #endif 59 60 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 61 62 // Patch any kind of instruction; there may be several instructions. 63 // Return the total length (in bytes) of the instructions. 64 int MacroAssembler::pd_patch_instruction_size(address branch, address target) { 65 int instructions = 1; 66 assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant"); 67 long offset = (target - branch) >> 2; 68 unsigned insn = *(unsigned*)branch; 69 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) { 70 // Load register (literal) 71 Instruction_aarch64::spatch(branch, 23, 5, offset); 72 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { 73 // Unconditional branch (immediate) 74 Instruction_aarch64::spatch(branch, 25, 0, offset); 75 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { 76 // Conditional branch (immediate) 77 Instruction_aarch64::spatch(branch, 23, 5, offset); 78 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { 79 // Compare & branch (immediate) 80 Instruction_aarch64::spatch(branch, 23, 5, offset); 81 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { 82 // Test & branch (immediate) 83 Instruction_aarch64::spatch(branch, 18, 5, offset); 84 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) { 85 // PC-rel. addressing 86 offset = target-branch; 87 int shift = Instruction_aarch64::extract(insn, 31, 31); 88 if (shift) { 89 u_int64_t dest = (u_int64_t)target; 90 uint64_t pc_page = (uint64_t)branch >> 12; 91 uint64_t adr_page = (uint64_t)target >> 12; 92 unsigned offset_lo = dest & 0xfff; 93 offset = adr_page - pc_page; 94 95 // We handle 4 types of PC relative addressing 96 // 1 - adrp Rx, target_page 97 // ldr/str Ry, [Rx, #offset_in_page] 98 // 2 - adrp Rx, target_page 99 // add Ry, Rx, #offset_in_page 100 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0) 101 // movk Rx, #imm16<<32 102 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0) 103 // In the first 3 cases we must check that Rx is the same in the adrp and the 104 // subsequent ldr/str, add or movk instruction. Otherwise we could accidentally end 105 // up treating a type 4 relocation as a type 1, 2 or 3 just because it happened 106 // to be followed by a random unrelated ldr/str, add or movk instruction. 107 // 108 unsigned insn2 = ((unsigned*)branch)[1]; 109 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && 110 Instruction_aarch64::extract(insn, 4, 0) == 111 Instruction_aarch64::extract(insn2, 9, 5)) { 112 // Load/store register (unsigned immediate) 113 unsigned size = Instruction_aarch64::extract(insn2, 31, 30); 114 Instruction_aarch64::patch(branch + sizeof (unsigned), 115 21, 10, offset_lo >> size); 116 guarantee(((dest >> size) << size) == dest, "misaligned target"); 117 instructions = 2; 118 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && 119 Instruction_aarch64::extract(insn, 4, 0) == 120 Instruction_aarch64::extract(insn2, 4, 0)) { 121 // add (immediate) 122 Instruction_aarch64::patch(branch + sizeof (unsigned), 123 21, 10, offset_lo); 124 instructions = 2; 125 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && 126 Instruction_aarch64::extract(insn, 4, 0) == 127 Instruction_aarch64::extract(insn2, 4, 0)) { 128 // movk #imm16<<32 129 Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32); 130 long dest = ((long)target & 0xffffffffL) | ((long)branch & 0xffff00000000L); 131 long pc_page = (long)branch >> 12; 132 long adr_page = (long)dest >> 12; 133 offset = adr_page - pc_page; 134 instructions = 2; 135 } 136 } 137 int offset_lo = offset & 3; 138 offset >>= 2; 139 Instruction_aarch64::spatch(branch, 23, 5, offset); 140 Instruction_aarch64::patch(branch, 30, 29, offset_lo); 141 } else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) { 142 u_int64_t dest = (u_int64_t)target; 143 // Move wide constant 144 assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch"); 145 assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch"); 146 Instruction_aarch64::patch(branch, 20, 5, dest & 0xffff); 147 Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff); 148 Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff); 149 assert(target_addr_for_insn(branch) == target, "should be"); 150 instructions = 3; 151 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && 152 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { 153 // nothing to do 154 assert(target == 0, "did not expect to relocate target for polling page load"); 155 } else { 156 ShouldNotReachHere(); 157 } 158 return instructions * NativeInstruction::instruction_size; 159 } 160 161 int MacroAssembler::patch_oop(address insn_addr, address o) { 162 int instructions; 163 unsigned insn = *(unsigned*)insn_addr; 164 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch"); 165 166 // OOPs are either narrow (32 bits) or wide (48 bits). We encode 167 // narrow OOPs by setting the upper 16 bits in the first 168 // instruction. 169 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) { 170 // Move narrow OOP 171 narrowOop n = oopDesc::encode_heap_oop((oop)o); 172 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16); 173 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff); 174 instructions = 2; 175 } else { 176 // Move wide OOP 177 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch"); 178 uintptr_t dest = (uintptr_t)o; 179 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff); 180 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff); 181 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff); 182 instructions = 3; 183 } 184 return instructions * NativeInstruction::instruction_size; 185 } 186 187 address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) { 188 long offset = 0; 189 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) { 190 // Load register (literal) 191 offset = Instruction_aarch64::sextract(insn, 23, 5); 192 return address(((uint64_t)insn_addr + (offset << 2))); 193 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { 194 // Unconditional branch (immediate) 195 offset = Instruction_aarch64::sextract(insn, 25, 0); 196 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { 197 // Conditional branch (immediate) 198 offset = Instruction_aarch64::sextract(insn, 23, 5); 199 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { 200 // Compare & branch (immediate) 201 offset = Instruction_aarch64::sextract(insn, 23, 5); 202 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { 203 // Test & branch (immediate) 204 offset = Instruction_aarch64::sextract(insn, 18, 5); 205 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) { 206 // PC-rel. addressing 207 offset = Instruction_aarch64::extract(insn, 30, 29); 208 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2; 209 int shift = Instruction_aarch64::extract(insn, 31, 31) ? 12 : 0; 210 if (shift) { 211 offset <<= shift; 212 uint64_t target_page = ((uint64_t)insn_addr) + offset; 213 target_page &= ((uint64_t)-1) << shift; 214 // Return the target address for the following sequences 215 // 1 - adrp Rx, target_page 216 // ldr/str Ry, [Rx, #offset_in_page] 217 // 2 - adrp Rx, target_page 218 // add Ry, Rx, #offset_in_page 219 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0) 220 // movk Rx, #imm12<<32 221 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0) 222 // 223 // In the first two cases we check that the register is the same and 224 // return the target_page + the offset within the page. 225 // Otherwise we assume it is a page aligned relocation and return 226 // the target page only. 227 // 228 unsigned insn2 = ((unsigned*)insn_addr)[1]; 229 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && 230 Instruction_aarch64::extract(insn, 4, 0) == 231 Instruction_aarch64::extract(insn2, 9, 5)) { 232 // Load/store register (unsigned immediate) 233 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 234 unsigned int size = Instruction_aarch64::extract(insn2, 31, 30); 235 return address(target_page + (byte_offset << size)); 236 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && 237 Instruction_aarch64::extract(insn, 4, 0) == 238 Instruction_aarch64::extract(insn2, 4, 0)) { 239 // add (immediate) 240 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 241 return address(target_page + byte_offset); 242 } else { 243 if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && 244 Instruction_aarch64::extract(insn, 4, 0) == 245 Instruction_aarch64::extract(insn2, 4, 0)) { 246 target_page = (target_page & 0xffffffff) | 247 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32); 248 } 249 return (address)target_page; 250 } 251 } else { 252 ShouldNotReachHere(); 253 } 254 } else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) { 255 u_int32_t *insns = (u_int32_t *)insn_addr; 256 // Move wide constant: movz, movk, movk. See movptr(). 257 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch"); 258 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch"); 259 return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5)) 260 + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16) 261 + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32)); 262 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && 263 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { 264 return 0; 265 } else { 266 ShouldNotReachHere(); 267 } 268 return address(((uint64_t)insn_addr + (offset << 2))); 269 } 270 271 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 272 dsb(Assembler::SY); 273 } 274 275 276 void MacroAssembler::reset_last_Java_frame(bool clear_fp, 277 bool clear_pc) { 278 // we must set sp to zero to clear frame 279 str(zr, Address(rthread, JavaThread::last_Java_sp_offset())); 280 // must clear fp, so that compiled frames are not confused; it is 281 // possible that we need it only for debugging 282 if (clear_fp) { 283 str(zr, Address(rthread, JavaThread::last_Java_fp_offset())); 284 } 285 286 if (clear_pc) { 287 str(zr, Address(rthread, JavaThread::last_Java_pc_offset())); 288 } 289 } 290 291 // Calls to C land 292 // 293 // When entering C land, the rfp, & resp of the last Java frame have to be recorded 294 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 295 // has to be reset to 0. This is required to allow proper stack traversal. 296 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 297 Register last_java_fp, 298 Register last_java_pc, 299 Register scratch) { 300 301 if (last_java_pc->is_valid()) { 302 str(last_java_pc, Address(rthread, 303 JavaThread::frame_anchor_offset() 304 + JavaFrameAnchor::last_Java_pc_offset())); 305 } 306 307 // determine last_java_sp register 308 if (last_java_sp == sp) { 309 mov(scratch, sp); 310 last_java_sp = scratch; 311 } else if (!last_java_sp->is_valid()) { 312 last_java_sp = esp; 313 } 314 315 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset())); 316 317 // last_java_fp is optional 318 if (last_java_fp->is_valid()) { 319 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset())); 320 } 321 } 322 323 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 324 Register last_java_fp, 325 address last_java_pc, 326 Register scratch) { 327 if (last_java_pc != NULL) { 328 adr(scratch, last_java_pc); 329 } else { 330 // FIXME: This is almost never correct. We should delete all 331 // cases of set_last_Java_frame with last_java_pc=NULL and use the 332 // correct return address instead. 333 adr(scratch, pc()); 334 } 335 336 str(scratch, Address(rthread, 337 JavaThread::frame_anchor_offset() 338 + JavaFrameAnchor::last_Java_pc_offset())); 339 340 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch); 341 } 342 343 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 344 Register last_java_fp, 345 Label &L, 346 Register scratch) { 347 if (L.is_bound()) { 348 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch); 349 } else { 350 InstructionMark im(this); 351 L.add_patch_at(code(), locator()); 352 set_last_Java_frame(last_java_sp, last_java_fp, (address)NULL, scratch); 353 } 354 } 355 356 void MacroAssembler::far_call(Address entry, CodeBuffer *cbuf, Register tmp) { 357 assert(ReservedCodeCacheSize < 4*G, "branch out of range"); 358 assert(CodeCache::find_blob(entry.target()) != NULL, 359 "destination of far call not found in code cache"); 360 if (far_branches()) { 361 unsigned long offset; 362 // We can use ADRP here because we know that the total size of 363 // the code cache cannot exceed 2Gb. 364 adrp(tmp, entry, offset); 365 add(tmp, tmp, offset); 366 if (cbuf) cbuf->set_insts_mark(); 367 blr(tmp); 368 } else { 369 if (cbuf) cbuf->set_insts_mark(); 370 bl(entry); 371 } 372 } 373 374 void MacroAssembler::far_jump(Address entry, CodeBuffer *cbuf, Register tmp) { 375 assert(ReservedCodeCacheSize < 4*G, "branch out of range"); 376 assert(CodeCache::find_blob(entry.target()) != NULL, 377 "destination of far call not found in code cache"); 378 if (far_branches()) { 379 unsigned long offset; 380 // We can use ADRP here because we know that the total size of 381 // the code cache cannot exceed 2Gb. 382 adrp(tmp, entry, offset); 383 add(tmp, tmp, offset); 384 if (cbuf) cbuf->set_insts_mark(); 385 br(tmp); 386 } else { 387 if (cbuf) cbuf->set_insts_mark(); 388 b(entry); 389 } 390 } 391 392 int MacroAssembler::biased_locking_enter(Register lock_reg, 393 Register obj_reg, 394 Register swap_reg, 395 Register tmp_reg, 396 bool swap_reg_contains_mark, 397 Label& done, 398 Label* slow_case, 399 BiasedLockingCounters* counters) { 400 assert(UseBiasedLocking, "why call this otherwise?"); 401 assert_different_registers(lock_reg, obj_reg, swap_reg); 402 403 if (PrintBiasedLockingStatistics && counters == NULL) 404 counters = BiasedLocking::counters(); 405 406 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1, rscratch2, noreg); 407 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 408 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 409 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); 410 Address saved_mark_addr(lock_reg, 0); 411 412 // Biased locking 413 // See whether the lock is currently biased toward our thread and 414 // whether the epoch is still valid 415 // Note that the runtime guarantees sufficient alignment of JavaThread 416 // pointers to allow age to be placed into low bits 417 // First check to see whether biasing is even enabled for this object 418 Label cas_label; 419 int null_check_offset = -1; 420 if (!swap_reg_contains_mark) { 421 null_check_offset = offset(); 422 ldr(swap_reg, mark_addr); 423 } 424 andr(tmp_reg, swap_reg, markOopDesc::biased_lock_mask_in_place); 425 cmp(tmp_reg, markOopDesc::biased_lock_pattern); 426 br(Assembler::NE, cas_label); 427 // The bias pattern is present in the object's header. Need to check 428 // whether the bias owner and the epoch are both still current. 429 load_prototype_header(tmp_reg, obj_reg); 430 orr(tmp_reg, tmp_reg, rthread); 431 eor(tmp_reg, swap_reg, tmp_reg); 432 andr(tmp_reg, tmp_reg, ~((int) markOopDesc::age_mask_in_place)); 433 if (counters != NULL) { 434 Label around; 435 cbnz(tmp_reg, around); 436 atomic_incw(Address((address)counters->biased_lock_entry_count_addr()), tmp_reg, rscratch1, rscratch2); 437 b(done); 438 bind(around); 439 } else { 440 cbz(tmp_reg, done); 441 } 442 443 Label try_revoke_bias; 444 Label try_rebias; 445 446 // At this point we know that the header has the bias pattern and 447 // that we are not the bias owner in the current epoch. We need to 448 // figure out more details about the state of the header in order to 449 // know what operations can be legally performed on the object's 450 // header. 451 452 // If the low three bits in the xor result aren't clear, that means 453 // the prototype header is no longer biased and we have to revoke 454 // the bias on this object. 455 andr(rscratch1, tmp_reg, markOopDesc::biased_lock_mask_in_place); 456 cbnz(rscratch1, try_revoke_bias); 457 458 // Biasing is still enabled for this data type. See whether the 459 // epoch of the current bias is still valid, meaning that the epoch 460 // bits of the mark word are equal to the epoch bits of the 461 // prototype header. (Note that the prototype header's epoch bits 462 // only change at a safepoint.) If not, attempt to rebias the object 463 // toward the current thread. Note that we must be absolutely sure 464 // that the current epoch is invalid in order to do this because 465 // otherwise the manipulations it performs on the mark word are 466 // illegal. 467 andr(rscratch1, tmp_reg, markOopDesc::epoch_mask_in_place); 468 cbnz(rscratch1, try_rebias); 469 470 // The epoch of the current bias is still valid but we know nothing 471 // about the owner; it might be set or it might be clear. Try to 472 // acquire the bias of the object using an atomic operation. If this 473 // fails we will go in to the runtime to revoke the object's bias. 474 // Note that we first construct the presumed unbiased header so we 475 // don't accidentally blow away another thread's valid bias. 476 { 477 Label here; 478 mov(rscratch1, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 479 andr(swap_reg, swap_reg, rscratch1); 480 orr(tmp_reg, swap_reg, rthread); 481 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case); 482 // If the biasing toward our thread failed, this means that 483 // another thread succeeded in biasing it toward itself and we 484 // need to revoke that bias. The revocation will occur in the 485 // interpreter runtime in the slow case. 486 bind(here); 487 if (counters != NULL) { 488 atomic_incw(Address((address)counters->anonymously_biased_lock_entry_count_addr()), 489 tmp_reg, rscratch1, rscratch2); 490 } 491 } 492 b(done); 493 494 bind(try_rebias); 495 // At this point we know the epoch has expired, meaning that the 496 // current "bias owner", if any, is actually invalid. Under these 497 // circumstances _only_, we are allowed to use the current header's 498 // value as the comparison value when doing the cas to acquire the 499 // bias in the current epoch. In other words, we allow transfer of 500 // the bias from one thread to another directly in this situation. 501 // 502 // FIXME: due to a lack of registers we currently blow away the age 503 // bits in this situation. Should attempt to preserve them. 504 { 505 Label here; 506 load_prototype_header(tmp_reg, obj_reg); 507 orr(tmp_reg, rthread, tmp_reg); 508 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case); 509 // If the biasing toward our thread failed, then another thread 510 // succeeded in biasing it toward itself and we need to revoke that 511 // bias. The revocation will occur in the runtime in the slow case. 512 bind(here); 513 if (counters != NULL) { 514 atomic_incw(Address((address)counters->rebiased_lock_entry_count_addr()), 515 tmp_reg, rscratch1, rscratch2); 516 } 517 } 518 b(done); 519 520 bind(try_revoke_bias); 521 // The prototype mark in the klass doesn't have the bias bit set any 522 // more, indicating that objects of this data type are not supposed 523 // to be biased any more. We are going to try to reset the mark of 524 // this object to the prototype value and fall through to the 525 // CAS-based locking scheme. Note that if our CAS fails, it means 526 // that another thread raced us for the privilege of revoking the 527 // bias of this particular object, so it's okay to continue in the 528 // normal locking code. 529 // 530 // FIXME: due to a lack of registers we currently blow away the age 531 // bits in this situation. Should attempt to preserve them. 532 { 533 Label here, nope; 534 load_prototype_header(tmp_reg, obj_reg); 535 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, &nope); 536 bind(here); 537 538 // Fall through to the normal CAS-based lock, because no matter what 539 // the result of the above CAS, some thread must have succeeded in 540 // removing the bias bit from the object's header. 541 if (counters != NULL) { 542 atomic_incw(Address((address)counters->revoked_lock_entry_count_addr()), tmp_reg, 543 rscratch1, rscratch2); 544 } 545 bind(nope); 546 } 547 548 bind(cas_label); 549 550 return null_check_offset; 551 } 552 553 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 554 assert(UseBiasedLocking, "why call this otherwise?"); 555 556 // Check for biased locking unlock case, which is a no-op 557 // Note: we do not have to check the thread ID for two reasons. 558 // First, the interpreter checks for IllegalMonitorStateException at 559 // a higher level. Second, if the bias was revoked while we held the 560 // lock, the object could not be rebiased toward another thread, so 561 // the bias bit would be clear. 562 ldr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 563 andr(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place); 564 cmp(temp_reg, markOopDesc::biased_lock_pattern); 565 br(Assembler::EQ, done); 566 } 567 568 569 // added to make this compile 570 571 REGISTER_DEFINITION(Register, noreg); 572 573 static void pass_arg0(MacroAssembler* masm, Register arg) { 574 if (c_rarg0 != arg ) { 575 masm->mov(c_rarg0, arg); 576 } 577 } 578 579 static void pass_arg1(MacroAssembler* masm, Register arg) { 580 if (c_rarg1 != arg ) { 581 masm->mov(c_rarg1, arg); 582 } 583 } 584 585 static void pass_arg2(MacroAssembler* masm, Register arg) { 586 if (c_rarg2 != arg ) { 587 masm->mov(c_rarg2, arg); 588 } 589 } 590 591 static void pass_arg3(MacroAssembler* masm, Register arg) { 592 if (c_rarg3 != arg ) { 593 masm->mov(c_rarg3, arg); 594 } 595 } 596 597 void MacroAssembler::call_VM_base(Register oop_result, 598 Register java_thread, 599 Register last_java_sp, 600 address entry_point, 601 int number_of_arguments, 602 bool check_exceptions) { 603 // determine java_thread register 604 if (!java_thread->is_valid()) { 605 java_thread = rthread; 606 } 607 608 // determine last_java_sp register 609 if (!last_java_sp->is_valid()) { 610 last_java_sp = esp; 611 } 612 613 // debugging support 614 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 615 assert(java_thread == rthread, "unexpected register"); 616 #ifdef ASSERT 617 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 618 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?"); 619 #endif // ASSERT 620 621 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 622 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 623 624 // push java thread (becomes first argument of C function) 625 626 mov(c_rarg0, java_thread); 627 628 // set last Java frame before call 629 assert(last_java_sp != rfp, "can't use rfp"); 630 631 Label l; 632 set_last_Java_frame(last_java_sp, rfp, l, rscratch1); 633 634 // do the call, remove parameters 635 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l); 636 637 // reset last Java frame 638 // Only interpreter should have to clear fp 639 reset_last_Java_frame(true, true); 640 641 // C++ interp handles this in the interpreter 642 check_and_handle_popframe(java_thread); 643 check_and_handle_earlyret(java_thread); 644 645 if (check_exceptions) { 646 // check for pending exceptions (java_thread is set upon return) 647 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset()))); 648 Label ok; 649 cbz(rscratch1, ok); 650 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry())); 651 br(rscratch1); 652 bind(ok); 653 } 654 655 // get oop result if there is one and reset the value in the thread 656 if (oop_result->is_valid()) { 657 get_vm_result(oop_result, java_thread); 658 } 659 } 660 661 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 662 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); 663 } 664 665 // Maybe emit a call via a trampoline. If the code cache is small 666 // trampolines won't be emitted. 667 668 address MacroAssembler::trampoline_call(Address entry, CodeBuffer *cbuf) { 669 assert(entry.rspec().type() == relocInfo::runtime_call_type 670 || entry.rspec().type() == relocInfo::opt_virtual_call_type 671 || entry.rspec().type() == relocInfo::static_call_type 672 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type"); 673 674 unsigned int start_offset = offset(); 675 if (far_branches() && !Compile::current()->in_scratch_emit_size()) { 676 address stub = emit_trampoline_stub(start_offset, entry.target()); 677 if (stub == NULL) { 678 return NULL; // CodeCache is full 679 } 680 } 681 682 if (cbuf) cbuf->set_insts_mark(); 683 relocate(entry.rspec()); 684 if (!far_branches()) { 685 bl(entry.target()); 686 } else { 687 bl(pc()); 688 } 689 // just need to return a non-null address 690 return pc(); 691 } 692 693 694 // Emit a trampoline stub for a call to a target which is too far away. 695 // 696 // code sequences: 697 // 698 // call-site: 699 // branch-and-link to <destination> or <trampoline stub> 700 // 701 // Related trampoline stub for this call site in the stub section: 702 // load the call target from the constant pool 703 // branch (LR still points to the call site above) 704 705 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset, 706 address dest) { 707 address stub = start_a_stub(Compile::MAX_stubs_size/2); 708 if (stub == NULL) { 709 return NULL; // CodeBuffer::expand failed 710 } 711 712 // Create a trampoline stub relocation which relates this trampoline stub 713 // with the call instruction at insts_call_instruction_offset in the 714 // instructions code-section. 715 align(wordSize); 716 relocate(trampoline_stub_Relocation::spec(code()->insts()->start() 717 + insts_call_instruction_offset)); 718 const int stub_start_offset = offset(); 719 720 // Now, create the trampoline stub's code: 721 // - load the call 722 // - call 723 Label target; 724 ldr(rscratch1, target); 725 br(rscratch1); 726 bind(target); 727 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset, 728 "should be"); 729 emit_int64((int64_t)dest); 730 731 const address stub_start_addr = addr_at(stub_start_offset); 732 733 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline"); 734 735 end_a_stub(); 736 return stub; 737 } 738 739 address MacroAssembler::ic_call(address entry, jint method_index) { 740 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 741 // address const_ptr = long_constant((jlong)Universe::non_oop_word()); 742 // unsigned long offset; 743 // ldr_constant(rscratch2, const_ptr); 744 movptr(rscratch2, (uintptr_t)Universe::non_oop_word()); 745 return trampoline_call(Address(entry, rh)); 746 } 747 748 // Implementation of call_VM versions 749 750 void MacroAssembler::call_VM(Register oop_result, 751 address entry_point, 752 bool check_exceptions) { 753 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 754 } 755 756 void MacroAssembler::call_VM(Register oop_result, 757 address entry_point, 758 Register arg_1, 759 bool check_exceptions) { 760 pass_arg1(this, arg_1); 761 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 762 } 763 764 void MacroAssembler::call_VM(Register oop_result, 765 address entry_point, 766 Register arg_1, 767 Register arg_2, 768 bool check_exceptions) { 769 assert(arg_1 != c_rarg2, "smashed arg"); 770 pass_arg2(this, arg_2); 771 pass_arg1(this, arg_1); 772 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 773 } 774 775 void MacroAssembler::call_VM(Register oop_result, 776 address entry_point, 777 Register arg_1, 778 Register arg_2, 779 Register arg_3, 780 bool check_exceptions) { 781 assert(arg_1 != c_rarg3, "smashed arg"); 782 assert(arg_2 != c_rarg3, "smashed arg"); 783 pass_arg3(this, arg_3); 784 785 assert(arg_1 != c_rarg2, "smashed arg"); 786 pass_arg2(this, arg_2); 787 788 pass_arg1(this, arg_1); 789 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 790 } 791 792 void MacroAssembler::call_VM(Register oop_result, 793 Register last_java_sp, 794 address entry_point, 795 int number_of_arguments, 796 bool check_exceptions) { 797 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 798 } 799 800 void MacroAssembler::call_VM(Register oop_result, 801 Register last_java_sp, 802 address entry_point, 803 Register arg_1, 804 bool check_exceptions) { 805 pass_arg1(this, arg_1); 806 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 807 } 808 809 void MacroAssembler::call_VM(Register oop_result, 810 Register last_java_sp, 811 address entry_point, 812 Register arg_1, 813 Register arg_2, 814 bool check_exceptions) { 815 816 assert(arg_1 != c_rarg2, "smashed arg"); 817 pass_arg2(this, arg_2); 818 pass_arg1(this, arg_1); 819 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 820 } 821 822 void MacroAssembler::call_VM(Register oop_result, 823 Register last_java_sp, 824 address entry_point, 825 Register arg_1, 826 Register arg_2, 827 Register arg_3, 828 bool check_exceptions) { 829 assert(arg_1 != c_rarg3, "smashed arg"); 830 assert(arg_2 != c_rarg3, "smashed arg"); 831 pass_arg3(this, arg_3); 832 assert(arg_1 != c_rarg2, "smashed arg"); 833 pass_arg2(this, arg_2); 834 pass_arg1(this, arg_1); 835 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 836 } 837 838 839 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 840 ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 841 str(zr, Address(java_thread, JavaThread::vm_result_offset())); 842 verify_oop(oop_result, "broken oop in call_VM_base"); 843 } 844 845 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 846 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 847 str(zr, Address(java_thread, JavaThread::vm_result_2_offset())); 848 } 849 850 void MacroAssembler::align(int modulus) { 851 while (offset() % modulus != 0) nop(); 852 } 853 854 // these are no-ops overridden by InterpreterMacroAssembler 855 856 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { } 857 858 void MacroAssembler::check_and_handle_popframe(Register java_thread) { } 859 860 861 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 862 Register tmp, 863 int offset) { 864 intptr_t value = *delayed_value_addr; 865 if (value != 0) 866 return RegisterOrConstant(value + offset); 867 868 // load indirectly to solve generation ordering problem 869 ldr(tmp, ExternalAddress((address) delayed_value_addr)); 870 871 if (offset != 0) 872 add(tmp, tmp, offset); 873 874 return RegisterOrConstant(tmp); 875 } 876 877 878 void MacroAssembler:: notify(int type) { 879 if (type == bytecode_start) { 880 // set_last_Java_frame(esp, rfp, (address)NULL); 881 Assembler:: notify(type); 882 // reset_last_Java_frame(true, false); 883 } 884 else 885 Assembler:: notify(type); 886 } 887 888 // Look up the method for a megamorphic invokeinterface call. 889 // The target method is determined by <intf_klass, itable_index>. 890 // The receiver klass is in recv_klass. 891 // On success, the result will be in method_result, and execution falls through. 892 // On failure, execution transfers to the given label. 893 void MacroAssembler::lookup_interface_method(Register recv_klass, 894 Register intf_klass, 895 RegisterOrConstant itable_index, 896 Register method_result, 897 Register scan_temp, 898 Label& L_no_such_interface) { 899 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 900 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 901 "caller must use same register for non-constant itable index as for method"); 902 903 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 904 int vtable_base = in_bytes(Klass::vtable_start_offset()); 905 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 906 int scan_step = itableOffsetEntry::size() * wordSize; 907 int vte_size = vtableEntry::size_in_bytes(); 908 assert(vte_size == wordSize, "else adjust times_vte_scale"); 909 910 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 911 912 // %%% Could store the aligned, prescaled offset in the klassoop. 913 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 914 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3))); 915 add(scan_temp, scan_temp, vtable_base); 916 917 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 918 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 919 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 920 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3))); 921 if (itentry_off) 922 add(recv_klass, recv_klass, itentry_off); 923 924 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 925 // if (scan->interface() == intf) { 926 // result = (klass + scan->offset() + itable_index); 927 // } 928 // } 929 Label search, found_method; 930 931 for (int peel = 1; peel >= 0; peel--) { 932 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 933 cmp(intf_klass, method_result); 934 935 if (peel) { 936 br(Assembler::EQ, found_method); 937 } else { 938 br(Assembler::NE, search); 939 // (invert the test to fall through to found_method...) 940 } 941 942 if (!peel) break; 943 944 bind(search); 945 946 // Check that the previous entry is non-null. A null entry means that 947 // the receiver class doesn't implement the interface, and wasn't the 948 // same as when the caller was compiled. 949 cbz(method_result, L_no_such_interface); 950 add(scan_temp, scan_temp, scan_step); 951 } 952 953 bind(found_method); 954 955 // Got a hit. 956 ldr(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 957 ldr(method_result, Address(recv_klass, scan_temp)); 958 } 959 960 // virtual method calling 961 void MacroAssembler::lookup_virtual_method(Register recv_klass, 962 RegisterOrConstant vtable_index, 963 Register method_result) { 964 const int base = in_bytes(Klass::vtable_start_offset()); 965 assert(vtableEntry::size() * wordSize == 8, 966 "adjust the scaling in the code below"); 967 int vtable_offset_in_bytes = base + vtableEntry::method_offset_in_bytes(); 968 969 if (vtable_index.is_register()) { 970 lea(method_result, Address(recv_klass, 971 vtable_index.as_register(), 972 Address::lsl(LogBytesPerWord))); 973 ldr(method_result, Address(method_result, vtable_offset_in_bytes)); 974 } else { 975 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize; 976 ldr(method_result, Address(recv_klass, vtable_offset_in_bytes)); 977 } 978 } 979 980 void MacroAssembler::check_klass_subtype(Register sub_klass, 981 Register super_klass, 982 Register temp_reg, 983 Label& L_success) { 984 Label L_failure; 985 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 986 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 987 bind(L_failure); 988 } 989 990 991 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 992 Register super_klass, 993 Register temp_reg, 994 Label* L_success, 995 Label* L_failure, 996 Label* L_slow_path, 997 RegisterOrConstant super_check_offset) { 998 assert_different_registers(sub_klass, super_klass, temp_reg); 999 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 1000 if (super_check_offset.is_register()) { 1001 assert_different_registers(sub_klass, super_klass, 1002 super_check_offset.as_register()); 1003 } else if (must_load_sco) { 1004 assert(temp_reg != noreg, "supply either a temp or a register offset"); 1005 } 1006 1007 Label L_fallthrough; 1008 int label_nulls = 0; 1009 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 1010 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 1011 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 1012 assert(label_nulls <= 1, "at most one NULL in the batch"); 1013 1014 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 1015 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 1016 Address super_check_offset_addr(super_klass, sco_offset); 1017 1018 // Hacked jmp, which may only be used just before L_fallthrough. 1019 #define final_jmp(label) \ 1020 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 1021 else b(label) /*omit semi*/ 1022 1023 // If the pointers are equal, we are done (e.g., String[] elements). 1024 // This self-check enables sharing of secondary supertype arrays among 1025 // non-primary types such as array-of-interface. Otherwise, each such 1026 // type would need its own customized SSA. 1027 // We move this check to the front of the fast path because many 1028 // type checks are in fact trivially successful in this manner, 1029 // so we get a nicely predicted branch right at the start of the check. 1030 cmp(sub_klass, super_klass); 1031 br(Assembler::EQ, *L_success); 1032 1033 // Check the supertype display: 1034 if (must_load_sco) { 1035 ldrw(temp_reg, super_check_offset_addr); 1036 super_check_offset = RegisterOrConstant(temp_reg); 1037 } 1038 Address super_check_addr(sub_klass, super_check_offset); 1039 ldr(rscratch1, super_check_addr); 1040 cmp(super_klass, rscratch1); // load displayed supertype 1041 1042 // This check has worked decisively for primary supers. 1043 // Secondary supers are sought in the super_cache ('super_cache_addr'). 1044 // (Secondary supers are interfaces and very deeply nested subtypes.) 1045 // This works in the same check above because of a tricky aliasing 1046 // between the super_cache and the primary super display elements. 1047 // (The 'super_check_addr' can address either, as the case requires.) 1048 // Note that the cache is updated below if it does not help us find 1049 // what we need immediately. 1050 // So if it was a primary super, we can just fail immediately. 1051 // Otherwise, it's the slow path for us (no success at this point). 1052 1053 if (super_check_offset.is_register()) { 1054 br(Assembler::EQ, *L_success); 1055 cmp(super_check_offset.as_register(), sc_offset); 1056 if (L_failure == &L_fallthrough) { 1057 br(Assembler::EQ, *L_slow_path); 1058 } else { 1059 br(Assembler::NE, *L_failure); 1060 final_jmp(*L_slow_path); 1061 } 1062 } else if (super_check_offset.as_constant() == sc_offset) { 1063 // Need a slow path; fast failure is impossible. 1064 if (L_slow_path == &L_fallthrough) { 1065 br(Assembler::EQ, *L_success); 1066 } else { 1067 br(Assembler::NE, *L_slow_path); 1068 final_jmp(*L_success); 1069 } 1070 } else { 1071 // No slow path; it's a fast decision. 1072 if (L_failure == &L_fallthrough) { 1073 br(Assembler::EQ, *L_success); 1074 } else { 1075 br(Assembler::NE, *L_failure); 1076 final_jmp(*L_success); 1077 } 1078 } 1079 1080 bind(L_fallthrough); 1081 1082 #undef final_jmp 1083 } 1084 1085 // These two are taken from x86, but they look generally useful 1086 1087 // scans count pointer sized words at [addr] for occurence of value, 1088 // generic 1089 void MacroAssembler::repne_scan(Register addr, Register value, Register count, 1090 Register scratch) { 1091 Label Lloop, Lexit; 1092 cbz(count, Lexit); 1093 bind(Lloop); 1094 ldr(scratch, post(addr, wordSize)); 1095 cmp(value, scratch); 1096 br(EQ, Lexit); 1097 sub(count, count, 1); 1098 cbnz(count, Lloop); 1099 bind(Lexit); 1100 } 1101 1102 // scans count 4 byte words at [addr] for occurence of value, 1103 // generic 1104 void MacroAssembler::repne_scanw(Register addr, Register value, Register count, 1105 Register scratch) { 1106 Label Lloop, Lexit; 1107 cbz(count, Lexit); 1108 bind(Lloop); 1109 ldrw(scratch, post(addr, wordSize)); 1110 cmpw(value, scratch); 1111 br(EQ, Lexit); 1112 sub(count, count, 1); 1113 cbnz(count, Lloop); 1114 bind(Lexit); 1115 } 1116 1117 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 1118 Register super_klass, 1119 Register temp_reg, 1120 Register temp2_reg, 1121 Label* L_success, 1122 Label* L_failure, 1123 bool set_cond_codes) { 1124 assert_different_registers(sub_klass, super_klass, temp_reg); 1125 if (temp2_reg != noreg) 1126 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1); 1127 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 1128 1129 Label L_fallthrough; 1130 int label_nulls = 0; 1131 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 1132 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 1133 assert(label_nulls <= 1, "at most one NULL in the batch"); 1134 1135 // a couple of useful fields in sub_klass: 1136 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 1137 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 1138 Address secondary_supers_addr(sub_klass, ss_offset); 1139 Address super_cache_addr( sub_klass, sc_offset); 1140 1141 BLOCK_COMMENT("check_klass_subtype_slow_path"); 1142 1143 // Do a linear scan of the secondary super-klass chain. 1144 // This code is rarely used, so simplicity is a virtue here. 1145 // The repne_scan instruction uses fixed registers, which we must spill. 1146 // Don't worry too much about pre-existing connections with the input regs. 1147 1148 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super) 1149 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter) 1150 1151 // Get super_klass value into r0 (even if it was in r5 or r2). 1152 RegSet pushed_registers; 1153 if (!IS_A_TEMP(r2)) pushed_registers += r2; 1154 if (!IS_A_TEMP(r5)) pushed_registers += r5; 1155 1156 if (super_klass != r0 || UseCompressedOops) { 1157 if (!IS_A_TEMP(r0)) pushed_registers += r0; 1158 } 1159 1160 push(pushed_registers, sp); 1161 1162 #ifndef PRODUCT 1163 mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr); 1164 Address pst_counter_addr(rscratch2); 1165 ldr(rscratch1, pst_counter_addr); 1166 add(rscratch1, rscratch1, 1); 1167 str(rscratch1, pst_counter_addr); 1168 #endif //PRODUCT 1169 1170 // We will consult the secondary-super array. 1171 ldr(r5, secondary_supers_addr); 1172 // Load the array length. 1173 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes())); 1174 // Skip to start of data. 1175 add(r5, r5, Array<Klass*>::base_offset_in_bytes()); 1176 1177 cmp(sp, zr); // Clear Z flag; SP is never zero 1178 // Scan R2 words at [R5] for an occurrence of R0. 1179 // Set NZ/Z based on last compare. 1180 repne_scan(r5, r0, r2, rscratch1); 1181 1182 // Unspill the temp. registers: 1183 pop(pushed_registers, sp); 1184 1185 br(Assembler::NE, *L_failure); 1186 1187 // Success. Cache the super we found and proceed in triumph. 1188 str(super_klass, super_cache_addr); 1189 1190 if (L_success != &L_fallthrough) { 1191 b(*L_success); 1192 } 1193 1194 #undef IS_A_TEMP 1195 1196 bind(L_fallthrough); 1197 } 1198 1199 1200 void MacroAssembler::verify_oop(Register reg, const char* s) { 1201 if (!VerifyOops) return; 1202 1203 // Pass register number to verify_oop_subroutine 1204 const char* b = NULL; 1205 { 1206 ResourceMark rm; 1207 stringStream ss; 1208 ss.print("verify_oop: %s: %s", reg->name(), s); 1209 b = code_string(ss.as_string()); 1210 } 1211 BLOCK_COMMENT("verify_oop {"); 1212 1213 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); 1214 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); 1215 1216 mov(r0, reg); 1217 mov(rscratch1, (address)b); 1218 1219 // call indirectly to solve generation ordering problem 1220 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 1221 ldr(rscratch2, Address(rscratch2)); 1222 blr(rscratch2); 1223 1224 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); 1225 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); 1226 1227 BLOCK_COMMENT("} verify_oop"); 1228 } 1229 1230 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 1231 if (!VerifyOops) return; 1232 1233 const char* b = NULL; 1234 { 1235 ResourceMark rm; 1236 stringStream ss; 1237 ss.print("verify_oop_addr: %s", s); 1238 b = code_string(ss.as_string()); 1239 } 1240 BLOCK_COMMENT("verify_oop_addr {"); 1241 1242 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); 1243 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); 1244 1245 // addr may contain sp so we will have to adjust it based on the 1246 // pushes that we just did. 1247 if (addr.uses(sp)) { 1248 lea(r0, addr); 1249 ldr(r0, Address(r0, 4 * wordSize)); 1250 } else { 1251 ldr(r0, addr); 1252 } 1253 mov(rscratch1, (address)b); 1254 1255 // call indirectly to solve generation ordering problem 1256 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 1257 ldr(rscratch2, Address(rscratch2)); 1258 blr(rscratch2); 1259 1260 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); 1261 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); 1262 1263 BLOCK_COMMENT("} verify_oop_addr"); 1264 } 1265 1266 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 1267 int extra_slot_offset) { 1268 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 1269 int stackElementSize = Interpreter::stackElementSize; 1270 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 1271 #ifdef ASSERT 1272 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 1273 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 1274 #endif 1275 if (arg_slot.is_constant()) { 1276 return Address(esp, arg_slot.as_constant() * stackElementSize 1277 + offset); 1278 } else { 1279 add(rscratch1, esp, arg_slot.as_register(), 1280 ext::uxtx, exact_log2(stackElementSize)); 1281 return Address(rscratch1, offset); 1282 } 1283 } 1284 1285 void MacroAssembler::call_VM_leaf_base(address entry_point, 1286 int number_of_arguments, 1287 Label *retaddr) { 1288 call_VM_leaf_base1(entry_point, number_of_arguments, 0, ret_type_integral, retaddr); 1289 } 1290 1291 void MacroAssembler::call_VM_leaf_base1(address entry_point, 1292 int number_of_gp_arguments, 1293 int number_of_fp_arguments, 1294 ret_type type, 1295 Label *retaddr) { 1296 Label E, L; 1297 1298 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize))); 1299 1300 // We add 1 to number_of_arguments because the thread in arg0 is 1301 // not counted 1302 mov(rscratch1, entry_point); 1303 blrt(rscratch1, number_of_gp_arguments + 1, number_of_fp_arguments, type); 1304 if (retaddr) 1305 bind(*retaddr); 1306 1307 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize))); 1308 maybe_isb(); 1309 } 1310 1311 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 1312 call_VM_leaf_base(entry_point, number_of_arguments); 1313 } 1314 1315 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 1316 pass_arg0(this, arg_0); 1317 call_VM_leaf_base(entry_point, 1); 1318 } 1319 1320 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1321 pass_arg0(this, arg_0); 1322 pass_arg1(this, arg_1); 1323 call_VM_leaf_base(entry_point, 2); 1324 } 1325 1326 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, 1327 Register arg_1, Register arg_2) { 1328 pass_arg0(this, arg_0); 1329 pass_arg1(this, arg_1); 1330 pass_arg2(this, arg_2); 1331 call_VM_leaf_base(entry_point, 3); 1332 } 1333 1334 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 1335 pass_arg0(this, arg_0); 1336 MacroAssembler::call_VM_leaf_base(entry_point, 1); 1337 } 1338 1339 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1340 1341 assert(arg_0 != c_rarg1, "smashed arg"); 1342 pass_arg1(this, arg_1); 1343 pass_arg0(this, arg_0); 1344 MacroAssembler::call_VM_leaf_base(entry_point, 2); 1345 } 1346 1347 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 1348 assert(arg_0 != c_rarg2, "smashed arg"); 1349 assert(arg_1 != c_rarg2, "smashed arg"); 1350 pass_arg2(this, arg_2); 1351 assert(arg_0 != c_rarg1, "smashed arg"); 1352 pass_arg1(this, arg_1); 1353 pass_arg0(this, arg_0); 1354 MacroAssembler::call_VM_leaf_base(entry_point, 3); 1355 } 1356 1357 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 1358 assert(arg_0 != c_rarg3, "smashed arg"); 1359 assert(arg_1 != c_rarg3, "smashed arg"); 1360 assert(arg_2 != c_rarg3, "smashed arg"); 1361 pass_arg3(this, arg_3); 1362 assert(arg_0 != c_rarg2, "smashed arg"); 1363 assert(arg_1 != c_rarg2, "smashed arg"); 1364 pass_arg2(this, arg_2); 1365 assert(arg_0 != c_rarg1, "smashed arg"); 1366 pass_arg1(this, arg_1); 1367 pass_arg0(this, arg_0); 1368 MacroAssembler::call_VM_leaf_base(entry_point, 4); 1369 } 1370 1371 void MacroAssembler::null_check(Register reg, int offset) { 1372 if (needs_explicit_null_check(offset)) { 1373 // provoke OS NULL exception if reg = NULL by 1374 // accessing M[reg] w/o changing any registers 1375 // NOTE: this is plenty to provoke a segv 1376 ldr(zr, Address(reg)); 1377 } else { 1378 // nothing to do, (later) access of M[reg + offset] 1379 // will provoke OS NULL exception if reg = NULL 1380 } 1381 } 1382 1383 // MacroAssembler protected routines needed to implement 1384 // public methods 1385 1386 void MacroAssembler::mov(Register r, Address dest) { 1387 code_section()->relocate(pc(), dest.rspec()); 1388 u_int64_t imm64 = (u_int64_t)dest.target(); 1389 movptr(r, imm64); 1390 } 1391 1392 // Move a constant pointer into r. In AArch64 mode the virtual 1393 // address space is 48 bits in size, so we only need three 1394 // instructions to create a patchable instruction sequence that can 1395 // reach anywhere. 1396 void MacroAssembler::movptr(Register r, uintptr_t imm64) { 1397 #ifndef PRODUCT 1398 { 1399 char buffer[64]; 1400 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64); 1401 block_comment(buffer); 1402 } 1403 #endif 1404 assert(imm64 < (1ul << 48), "48-bit overflow in address constant"); 1405 movz(r, imm64 & 0xffff); 1406 imm64 >>= 16; 1407 movk(r, imm64 & 0xffff, 16); 1408 imm64 >>= 16; 1409 movk(r, imm64 & 0xffff, 32); 1410 } 1411 1412 // Macro to mov replicated immediate to vector register. 1413 // Vd will get the following values for different arrangements in T 1414 // imm32 == hex 000000gh T8B: Vd = ghghghghghghghgh 1415 // imm32 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh 1416 // imm32 == hex 0000efgh T4H: Vd = efghefghefghefgh 1417 // imm32 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh 1418 // imm32 == hex abcdefgh T2S: Vd = abcdefghabcdefgh 1419 // imm32 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh 1420 // T1D/T2D: invalid 1421 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) { 1422 assert(T != T1D && T != T2D, "invalid arrangement"); 1423 if (T == T8B || T == T16B) { 1424 assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)"); 1425 movi(Vd, T, imm32 & 0xff, 0); 1426 return; 1427 } 1428 u_int32_t nimm32 = ~imm32; 1429 if (T == T4H || T == T8H) { 1430 assert((imm32 & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)"); 1431 imm32 &= 0xffff; 1432 nimm32 &= 0xffff; 1433 } 1434 u_int32_t x = imm32; 1435 int movi_cnt = 0; 1436 int movn_cnt = 0; 1437 while (x) { if (x & 0xff) movi_cnt++; x >>= 8; } 1438 x = nimm32; 1439 while (x) { if (x & 0xff) movn_cnt++; x >>= 8; } 1440 if (movn_cnt < movi_cnt) imm32 = nimm32; 1441 unsigned lsl = 0; 1442 while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } 1443 if (movn_cnt < movi_cnt) 1444 mvni(Vd, T, imm32 & 0xff, lsl); 1445 else 1446 movi(Vd, T, imm32 & 0xff, lsl); 1447 imm32 >>= 8; lsl += 8; 1448 while (imm32) { 1449 while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } 1450 if (movn_cnt < movi_cnt) 1451 bici(Vd, T, imm32 & 0xff, lsl); 1452 else 1453 orri(Vd, T, imm32 & 0xff, lsl); 1454 lsl += 8; imm32 >>= 8; 1455 } 1456 } 1457 1458 void MacroAssembler::mov_immediate64(Register dst, u_int64_t imm64) 1459 { 1460 #ifndef PRODUCT 1461 { 1462 char buffer[64]; 1463 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64); 1464 block_comment(buffer); 1465 } 1466 #endif 1467 if (operand_valid_for_logical_immediate(false, imm64)) { 1468 orr(dst, zr, imm64); 1469 } else { 1470 // we can use a combination of MOVZ or MOVN with 1471 // MOVK to build up the constant 1472 u_int64_t imm_h[4]; 1473 int zero_count = 0; 1474 int neg_count = 0; 1475 int i; 1476 for (i = 0; i < 4; i++) { 1477 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL); 1478 if (imm_h[i] == 0) { 1479 zero_count++; 1480 } else if (imm_h[i] == 0xffffL) { 1481 neg_count++; 1482 } 1483 } 1484 if (zero_count == 4) { 1485 // one MOVZ will do 1486 movz(dst, 0); 1487 } else if (neg_count == 4) { 1488 // one MOVN will do 1489 movn(dst, 0); 1490 } else if (zero_count == 3) { 1491 for (i = 0; i < 4; i++) { 1492 if (imm_h[i] != 0L) { 1493 movz(dst, (u_int32_t)imm_h[i], (i << 4)); 1494 break; 1495 } 1496 } 1497 } else if (neg_count == 3) { 1498 // one MOVN will do 1499 for (int i = 0; i < 4; i++) { 1500 if (imm_h[i] != 0xffffL) { 1501 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1502 break; 1503 } 1504 } 1505 } else if (zero_count == 2) { 1506 // one MOVZ and one MOVK will do 1507 for (i = 0; i < 3; i++) { 1508 if (imm_h[i] != 0L) { 1509 movz(dst, (u_int32_t)imm_h[i], (i << 4)); 1510 i++; 1511 break; 1512 } 1513 } 1514 for (;i < 4; i++) { 1515 if (imm_h[i] != 0L) { 1516 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1517 } 1518 } 1519 } else if (neg_count == 2) { 1520 // one MOVN and one MOVK will do 1521 for (i = 0; i < 4; i++) { 1522 if (imm_h[i] != 0xffffL) { 1523 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1524 i++; 1525 break; 1526 } 1527 } 1528 for (;i < 4; i++) { 1529 if (imm_h[i] != 0xffffL) { 1530 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1531 } 1532 } 1533 } else if (zero_count == 1) { 1534 // one MOVZ and two MOVKs will do 1535 for (i = 0; i < 4; i++) { 1536 if (imm_h[i] != 0L) { 1537 movz(dst, (u_int32_t)imm_h[i], (i << 4)); 1538 i++; 1539 break; 1540 } 1541 } 1542 for (;i < 4; i++) { 1543 if (imm_h[i] != 0x0L) { 1544 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1545 } 1546 } 1547 } else if (neg_count == 1) { 1548 // one MOVN and two MOVKs will do 1549 for (i = 0; i < 4; i++) { 1550 if (imm_h[i] != 0xffffL) { 1551 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1552 i++; 1553 break; 1554 } 1555 } 1556 for (;i < 4; i++) { 1557 if (imm_h[i] != 0xffffL) { 1558 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1559 } 1560 } 1561 } else { 1562 // use a MOVZ and 3 MOVKs (makes it easier to debug) 1563 movz(dst, (u_int32_t)imm_h[0], 0); 1564 for (i = 1; i < 4; i++) { 1565 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1566 } 1567 } 1568 } 1569 } 1570 1571 void MacroAssembler::mov_immediate32(Register dst, u_int32_t imm32) 1572 { 1573 #ifndef PRODUCT 1574 { 1575 char buffer[64]; 1576 snprintf(buffer, sizeof(buffer), "0x%"PRIX32, imm32); 1577 block_comment(buffer); 1578 } 1579 #endif 1580 if (operand_valid_for_logical_immediate(true, imm32)) { 1581 orrw(dst, zr, imm32); 1582 } else { 1583 // we can use MOVZ, MOVN or two calls to MOVK to build up the 1584 // constant 1585 u_int32_t imm_h[2]; 1586 imm_h[0] = imm32 & 0xffff; 1587 imm_h[1] = ((imm32 >> 16) & 0xffff); 1588 if (imm_h[0] == 0) { 1589 movzw(dst, imm_h[1], 16); 1590 } else if (imm_h[0] == 0xffff) { 1591 movnw(dst, imm_h[1] ^ 0xffff, 16); 1592 } else if (imm_h[1] == 0) { 1593 movzw(dst, imm_h[0], 0); 1594 } else if (imm_h[1] == 0xffff) { 1595 movnw(dst, imm_h[0] ^ 0xffff, 0); 1596 } else { 1597 // use a MOVZ and MOVK (makes it easier to debug) 1598 movzw(dst, imm_h[0], 0); 1599 movkw(dst, imm_h[1], 16); 1600 } 1601 } 1602 } 1603 1604 // Form an address from base + offset in Rd. Rd may or may 1605 // not actually be used: you must use the Address that is returned. 1606 // It is up to you to ensure that the shift provided matches the size 1607 // of your data. 1608 Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) { 1609 if (Address::offset_ok_for_immed(byte_offset, shift)) 1610 // It fits; no need for any heroics 1611 return Address(base, byte_offset); 1612 1613 // Don't do anything clever with negative or misaligned offsets 1614 unsigned mask = (1 << shift) - 1; 1615 if (byte_offset < 0 || byte_offset & mask) { 1616 mov(Rd, byte_offset); 1617 add(Rd, base, Rd); 1618 return Address(Rd); 1619 } 1620 1621 // See if we can do this with two 12-bit offsets 1622 { 1623 unsigned long word_offset = byte_offset >> shift; 1624 unsigned long masked_offset = word_offset & 0xfff000; 1625 if (Address::offset_ok_for_immed(word_offset - masked_offset) 1626 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) { 1627 add(Rd, base, masked_offset << shift); 1628 word_offset -= masked_offset; 1629 return Address(Rd, word_offset << shift); 1630 } 1631 } 1632 1633 // Do it the hard way 1634 mov(Rd, byte_offset); 1635 add(Rd, base, Rd); 1636 return Address(Rd); 1637 } 1638 1639 void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) { 1640 Label retry_load; 1641 bind(retry_load); 1642 // flush and load exclusive from the memory location 1643 ldxrw(tmp, counter_addr); 1644 addw(tmp, tmp, 1); 1645 // if we store+flush with no intervening write tmp wil be zero 1646 stxrw(tmp2, tmp, counter_addr); 1647 cbnzw(tmp2, retry_load); 1648 } 1649 1650 1651 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb, 1652 bool want_remainder, Register scratch) 1653 { 1654 // Full implementation of Java idiv and irem. The function 1655 // returns the (pc) offset of the div instruction - may be needed 1656 // for implicit exceptions. 1657 // 1658 // constraint : ra/rb =/= scratch 1659 // normal case 1660 // 1661 // input : ra: dividend 1662 // rb: divisor 1663 // 1664 // result: either 1665 // quotient (= ra idiv rb) 1666 // remainder (= ra irem rb) 1667 1668 assert(ra != scratch && rb != scratch, "reg cannot be scratch"); 1669 1670 int idivl_offset = offset(); 1671 if (! want_remainder) { 1672 sdivw(result, ra, rb); 1673 } else { 1674 sdivw(scratch, ra, rb); 1675 Assembler::msubw(result, scratch, rb, ra); 1676 } 1677 1678 return idivl_offset; 1679 } 1680 1681 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb, 1682 bool want_remainder, Register scratch) 1683 { 1684 // Full implementation of Java ldiv and lrem. The function 1685 // returns the (pc) offset of the div instruction - may be needed 1686 // for implicit exceptions. 1687 // 1688 // constraint : ra/rb =/= scratch 1689 // normal case 1690 // 1691 // input : ra: dividend 1692 // rb: divisor 1693 // 1694 // result: either 1695 // quotient (= ra idiv rb) 1696 // remainder (= ra irem rb) 1697 1698 assert(ra != scratch && rb != scratch, "reg cannot be scratch"); 1699 1700 int idivq_offset = offset(); 1701 if (! want_remainder) { 1702 sdiv(result, ra, rb); 1703 } else { 1704 sdiv(scratch, ra, rb); 1705 Assembler::msub(result, scratch, rb, ra); 1706 } 1707 1708 return idivq_offset; 1709 } 1710 1711 void MacroAssembler::membar(Membar_mask_bits order_constraint) { 1712 address prev = pc() - NativeMembar::instruction_size; 1713 if (prev == code()->last_membar()) { 1714 NativeMembar *bar = NativeMembar_at(prev); 1715 // We are merging two memory barrier instructions. On AArch64 we 1716 // can do this simply by ORing them together. 1717 bar->set_kind(bar->get_kind() | order_constraint); 1718 BLOCK_COMMENT("merged membar"); 1719 } else { 1720 code()->set_last_membar(pc()); 1721 dmb(Assembler::barrier(order_constraint)); 1722 } 1723 } 1724 1725 // MacroAssembler routines found actually to be needed 1726 1727 void MacroAssembler::push(Register src) 1728 { 1729 str(src, Address(pre(esp, -1 * wordSize))); 1730 } 1731 1732 void MacroAssembler::pop(Register dst) 1733 { 1734 ldr(dst, Address(post(esp, 1 * wordSize))); 1735 } 1736 1737 // Note: load_unsigned_short used to be called load_unsigned_word. 1738 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 1739 int off = offset(); 1740 ldrh(dst, src); 1741 return off; 1742 } 1743 1744 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 1745 int off = offset(); 1746 ldrb(dst, src); 1747 return off; 1748 } 1749 1750 int MacroAssembler::load_signed_short(Register dst, Address src) { 1751 int off = offset(); 1752 ldrsh(dst, src); 1753 return off; 1754 } 1755 1756 int MacroAssembler::load_signed_byte(Register dst, Address src) { 1757 int off = offset(); 1758 ldrsb(dst, src); 1759 return off; 1760 } 1761 1762 int MacroAssembler::load_signed_short32(Register dst, Address src) { 1763 int off = offset(); 1764 ldrshw(dst, src); 1765 return off; 1766 } 1767 1768 int MacroAssembler::load_signed_byte32(Register dst, Address src) { 1769 int off = offset(); 1770 ldrsbw(dst, src); 1771 return off; 1772 } 1773 1774 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 1775 switch (size_in_bytes) { 1776 case 8: ldr(dst, src); break; 1777 case 4: ldrw(dst, src); break; 1778 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 1779 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 1780 default: ShouldNotReachHere(); 1781 } 1782 } 1783 1784 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 1785 switch (size_in_bytes) { 1786 case 8: str(src, dst); break; 1787 case 4: strw(src, dst); break; 1788 case 2: strh(src, dst); break; 1789 case 1: strb(src, dst); break; 1790 default: ShouldNotReachHere(); 1791 } 1792 } 1793 1794 void MacroAssembler::decrementw(Register reg, int value) 1795 { 1796 if (value < 0) { incrementw(reg, -value); return; } 1797 if (value == 0) { return; } 1798 if (value < (1 << 12)) { subw(reg, reg, value); return; } 1799 /* else */ { 1800 guarantee(reg != rscratch2, "invalid dst for register decrement"); 1801 movw(rscratch2, (unsigned)value); 1802 subw(reg, reg, rscratch2); 1803 } 1804 } 1805 1806 void MacroAssembler::decrement(Register reg, int value) 1807 { 1808 if (value < 0) { increment(reg, -value); return; } 1809 if (value == 0) { return; } 1810 if (value < (1 << 12)) { sub(reg, reg, value); return; } 1811 /* else */ { 1812 assert(reg != rscratch2, "invalid dst for register decrement"); 1813 mov(rscratch2, (unsigned long)value); 1814 sub(reg, reg, rscratch2); 1815 } 1816 } 1817 1818 void MacroAssembler::decrementw(Address dst, int value) 1819 { 1820 assert(!dst.uses(rscratch1), "invalid dst for address decrement"); 1821 ldrw(rscratch1, dst); 1822 decrementw(rscratch1, value); 1823 strw(rscratch1, dst); 1824 } 1825 1826 void MacroAssembler::decrement(Address dst, int value) 1827 { 1828 assert(!dst.uses(rscratch1), "invalid address for decrement"); 1829 ldr(rscratch1, dst); 1830 decrement(rscratch1, value); 1831 str(rscratch1, dst); 1832 } 1833 1834 void MacroAssembler::incrementw(Register reg, int value) 1835 { 1836 if (value < 0) { decrementw(reg, -value); return; } 1837 if (value == 0) { return; } 1838 if (value < (1 << 12)) { addw(reg, reg, value); return; } 1839 /* else */ { 1840 assert(reg != rscratch2, "invalid dst for register increment"); 1841 movw(rscratch2, (unsigned)value); 1842 addw(reg, reg, rscratch2); 1843 } 1844 } 1845 1846 void MacroAssembler::increment(Register reg, int value) 1847 { 1848 if (value < 0) { decrement(reg, -value); return; } 1849 if (value == 0) { return; } 1850 if (value < (1 << 12)) { add(reg, reg, value); return; } 1851 /* else */ { 1852 assert(reg != rscratch2, "invalid dst for register increment"); 1853 movw(rscratch2, (unsigned)value); 1854 add(reg, reg, rscratch2); 1855 } 1856 } 1857 1858 void MacroAssembler::incrementw(Address dst, int value) 1859 { 1860 assert(!dst.uses(rscratch1), "invalid dst for address increment"); 1861 ldrw(rscratch1, dst); 1862 incrementw(rscratch1, value); 1863 strw(rscratch1, dst); 1864 } 1865 1866 void MacroAssembler::increment(Address dst, int value) 1867 { 1868 assert(!dst.uses(rscratch1), "invalid dst for address increment"); 1869 ldr(rscratch1, dst); 1870 increment(rscratch1, value); 1871 str(rscratch1, dst); 1872 } 1873 1874 1875 void MacroAssembler::pusha() { 1876 push(0x7fffffff, sp); 1877 } 1878 1879 void MacroAssembler::popa() { 1880 pop(0x7fffffff, sp); 1881 } 1882 1883 // Push lots of registers in the bit set supplied. Don't push sp. 1884 // Return the number of words pushed 1885 int MacroAssembler::push(unsigned int bitset, Register stack) { 1886 int words_pushed = 0; 1887 1888 // Scan bitset to accumulate register pairs 1889 unsigned char regs[32]; 1890 int count = 0; 1891 for (int reg = 0; reg <= 30; reg++) { 1892 if (1 & bitset) 1893 regs[count++] = reg; 1894 bitset >>= 1; 1895 } 1896 regs[count++] = zr->encoding_nocheck(); 1897 count &= ~1; // Only push an even nuber of regs 1898 1899 if (count) { 1900 stp(as_Register(regs[0]), as_Register(regs[1]), 1901 Address(pre(stack, -count * wordSize))); 1902 words_pushed += 2; 1903 } 1904 for (int i = 2; i < count; i += 2) { 1905 stp(as_Register(regs[i]), as_Register(regs[i+1]), 1906 Address(stack, i * wordSize)); 1907 words_pushed += 2; 1908 } 1909 1910 assert(words_pushed == count, "oops, pushed != count"); 1911 1912 return count; 1913 } 1914 1915 int MacroAssembler::pop(unsigned int bitset, Register stack) { 1916 int words_pushed = 0; 1917 1918 // Scan bitset to accumulate register pairs 1919 unsigned char regs[32]; 1920 int count = 0; 1921 for (int reg = 0; reg <= 30; reg++) { 1922 if (1 & bitset) 1923 regs[count++] = reg; 1924 bitset >>= 1; 1925 } 1926 regs[count++] = zr->encoding_nocheck(); 1927 count &= ~1; 1928 1929 for (int i = 2; i < count; i += 2) { 1930 ldp(as_Register(regs[i]), as_Register(regs[i+1]), 1931 Address(stack, i * wordSize)); 1932 words_pushed += 2; 1933 } 1934 if (count) { 1935 ldp(as_Register(regs[0]), as_Register(regs[1]), 1936 Address(post(stack, count * wordSize))); 1937 words_pushed += 2; 1938 } 1939 1940 assert(words_pushed == count, "oops, pushed != count"); 1941 1942 return count; 1943 } 1944 #ifdef ASSERT 1945 void MacroAssembler::verify_heapbase(const char* msg) { 1946 #if 0 1947 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed"); 1948 assert (Universe::heap() != NULL, "java heap should be initialized"); 1949 if (CheckCompressedOops) { 1950 Label ok; 1951 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1 1952 cmpptr(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 1953 br(Assembler::EQ, ok); 1954 stop(msg); 1955 bind(ok); 1956 pop(1 << rscratch1->encoding(), sp); 1957 } 1958 #endif 1959 } 1960 #endif 1961 1962 void MacroAssembler::stop(const char* msg) { 1963 address ip = pc(); 1964 pusha(); 1965 mov(c_rarg0, (address)msg); 1966 mov(c_rarg1, (address)ip); 1967 mov(c_rarg2, sp); 1968 mov(c_rarg3, CAST_FROM_FN_PTR(address, MacroAssembler::debug64)); 1969 // call(c_rarg3); 1970 blrt(c_rarg3, 3, 0, 1); 1971 hlt(0); 1972 } 1973 1974 // If a constant does not fit in an immediate field, generate some 1975 // number of MOV instructions and then perform the operation. 1976 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm, 1977 add_sub_imm_insn insn1, 1978 add_sub_reg_insn insn2) { 1979 assert(Rd != zr, "Rd = zr and not setting flags?"); 1980 if (operand_valid_for_add_sub_immediate((int)imm)) { 1981 (this->*insn1)(Rd, Rn, imm); 1982 } else { 1983 if (uabs(imm) < (1 << 24)) { 1984 (this->*insn1)(Rd, Rn, imm & -(1 << 12)); 1985 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1)); 1986 } else { 1987 assert_different_registers(Rd, Rn); 1988 mov(Rd, (uint64_t)imm); 1989 (this->*insn2)(Rd, Rn, Rd, LSL, 0); 1990 } 1991 } 1992 } 1993 1994 // Seperate vsn which sets the flags. Optimisations are more restricted 1995 // because we must set the flags correctly. 1996 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm, 1997 add_sub_imm_insn insn1, 1998 add_sub_reg_insn insn2) { 1999 if (operand_valid_for_add_sub_immediate((int)imm)) { 2000 (this->*insn1)(Rd, Rn, imm); 2001 } else { 2002 assert_different_registers(Rd, Rn); 2003 assert(Rd != zr, "overflow in immediate operand"); 2004 mov(Rd, (uint64_t)imm); 2005 (this->*insn2)(Rd, Rn, Rd, LSL, 0); 2006 } 2007 } 2008 2009 2010 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) { 2011 if (increment.is_register()) { 2012 add(Rd, Rn, increment.as_register()); 2013 } else { 2014 add(Rd, Rn, increment.as_constant()); 2015 } 2016 } 2017 2018 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) { 2019 if (increment.is_register()) { 2020 addw(Rd, Rn, increment.as_register()); 2021 } else { 2022 addw(Rd, Rn, increment.as_constant()); 2023 } 2024 } 2025 2026 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) { 2027 if (decrement.is_register()) { 2028 sub(Rd, Rn, decrement.as_register()); 2029 } else { 2030 sub(Rd, Rn, decrement.as_constant()); 2031 } 2032 } 2033 2034 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) { 2035 if (decrement.is_register()) { 2036 subw(Rd, Rn, decrement.as_register()); 2037 } else { 2038 subw(Rd, Rn, decrement.as_constant()); 2039 } 2040 } 2041 2042 void MacroAssembler::reinit_heapbase() 2043 { 2044 if (UseCompressedOops) { 2045 if (Universe::is_fully_initialized()) { 2046 mov(rheapbase, Universe::narrow_ptrs_base()); 2047 } else { 2048 lea(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 2049 ldr(rheapbase, Address(rheapbase)); 2050 } 2051 } 2052 } 2053 2054 // this simulates the behaviour of the x86 cmpxchg instruction using a 2055 // load linked/store conditional pair. we use the acquire/release 2056 // versions of these instructions so that we flush pending writes as 2057 // per Java semantics. 2058 2059 // n.b the x86 version assumes the old value to be compared against is 2060 // in rax and updates rax with the value located in memory if the 2061 // cmpxchg fails. we supply a register for the old value explicitly 2062 2063 // the aarch64 load linked/store conditional instructions do not 2064 // accept an offset. so, unlike x86, we must provide a plain register 2065 // to identify the memory word to be compared/exchanged rather than a 2066 // register+offset Address. 2067 2068 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, 2069 Label &succeed, Label *fail) { 2070 // oldv holds comparison value 2071 // newv holds value to write in exchange 2072 // addr identifies memory word to compare against/update 2073 // tmp returns 0/1 for success/failure 2074 Label retry_load, nope; 2075 2076 bind(retry_load); 2077 // flush and load exclusive from the memory location 2078 // and fail if it is not what we expect 2079 ldaxr(tmp, addr); 2080 cmp(tmp, oldv); 2081 br(Assembler::NE, nope); 2082 // if we store+flush with no intervening write tmp wil be zero 2083 stlxr(tmp, newv, addr); 2084 cbzw(tmp, succeed); 2085 // retry so we only ever return after a load fails to compare 2086 // ensures we don't return a stale value after a failed write. 2087 b(retry_load); 2088 // if the memory word differs we return it in oldv and signal a fail 2089 bind(nope); 2090 membar(AnyAny); 2091 mov(oldv, tmp); 2092 if (fail) 2093 b(*fail); 2094 } 2095 2096 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, 2097 Label &succeed, Label *fail) { 2098 // oldv holds comparison value 2099 // newv holds value to write in exchange 2100 // addr identifies memory word to compare against/update 2101 // tmp returns 0/1 for success/failure 2102 Label retry_load, nope; 2103 2104 bind(retry_load); 2105 // flush and load exclusive from the memory location 2106 // and fail if it is not what we expect 2107 ldaxrw(tmp, addr); 2108 cmp(tmp, oldv); 2109 br(Assembler::NE, nope); 2110 // if we store+flush with no intervening write tmp wil be zero 2111 stlxrw(tmp, newv, addr); 2112 cbzw(tmp, succeed); 2113 // retry so we only ever return after a load fails to compare 2114 // ensures we don't return a stale value after a failed write. 2115 b(retry_load); 2116 // if the memory word differs we return it in oldv and signal a fail 2117 bind(nope); 2118 membar(AnyAny); 2119 mov(oldv, tmp); 2120 if (fail) 2121 b(*fail); 2122 } 2123 2124 static bool different(Register a, RegisterOrConstant b, Register c) { 2125 if (b.is_constant()) 2126 return a != c; 2127 else 2128 return a != b.as_register() && a != c && b.as_register() != c; 2129 } 2130 2131 #define ATOMIC_OP(LDXR, OP, IOP, STXR) \ 2132 void MacroAssembler::atomic_##OP(Register prev, RegisterOrConstant incr, Register addr) { \ 2133 Register result = rscratch2; \ 2134 if (prev->is_valid()) \ 2135 result = different(prev, incr, addr) ? prev : rscratch2; \ 2136 \ 2137 Label retry_load; \ 2138 bind(retry_load); \ 2139 LDXR(result, addr); \ 2140 OP(rscratch1, result, incr); \ 2141 STXR(rscratch2, rscratch1, addr); \ 2142 cbnzw(rscratch2, retry_load); \ 2143 if (prev->is_valid() && prev != result) { \ 2144 IOP(prev, rscratch1, incr); \ 2145 } \ 2146 } 2147 2148 ATOMIC_OP(ldxr, add, sub, stxr) 2149 ATOMIC_OP(ldxrw, addw, subw, stxrw) 2150 2151 #undef ATOMIC_OP 2152 2153 #define ATOMIC_XCHG(OP, LDXR, STXR) \ 2154 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \ 2155 Register result = rscratch2; \ 2156 if (prev->is_valid()) \ 2157 result = different(prev, newv, addr) ? prev : rscratch2; \ 2158 \ 2159 Label retry_load; \ 2160 bind(retry_load); \ 2161 LDXR(result, addr); \ 2162 STXR(rscratch1, newv, addr); \ 2163 cbnzw(rscratch1, retry_load); \ 2164 if (prev->is_valid() && prev != result) \ 2165 mov(prev, result); \ 2166 } 2167 2168 ATOMIC_XCHG(xchg, ldxr, stxr) 2169 ATOMIC_XCHG(xchgw, ldxrw, stxrw) 2170 2171 #undef ATOMIC_XCHG 2172 2173 void MacroAssembler::incr_allocated_bytes(Register thread, 2174 Register var_size_in_bytes, 2175 int con_size_in_bytes, 2176 Register t1) { 2177 if (!thread->is_valid()) { 2178 thread = rthread; 2179 } 2180 assert(t1->is_valid(), "need temp reg"); 2181 2182 ldr(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset()))); 2183 if (var_size_in_bytes->is_valid()) { 2184 add(t1, t1, var_size_in_bytes); 2185 } else { 2186 add(t1, t1, con_size_in_bytes); 2187 } 2188 str(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset()))); 2189 } 2190 2191 #ifndef PRODUCT 2192 extern "C" void findpc(intptr_t x); 2193 #endif 2194 2195 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) 2196 { 2197 // In order to get locks to work, we need to fake a in_VM state 2198 if (ShowMessageBoxOnError ) { 2199 JavaThread* thread = JavaThread::current(); 2200 JavaThreadState saved_state = thread->thread_state(); 2201 thread->set_thread_state(_thread_in_vm); 2202 #ifndef PRODUCT 2203 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 2204 ttyLocker ttyl; 2205 BytecodeCounter::print(); 2206 } 2207 #endif 2208 if (os::message_box(msg, "Execution stopped, print registers?")) { 2209 ttyLocker ttyl; 2210 tty->print_cr(" pc = 0x%016lx", pc); 2211 #ifndef PRODUCT 2212 tty->cr(); 2213 findpc(pc); 2214 tty->cr(); 2215 #endif 2216 tty->print_cr(" r0 = 0x%016lx", regs[0]); 2217 tty->print_cr(" r1 = 0x%016lx", regs[1]); 2218 tty->print_cr(" r2 = 0x%016lx", regs[2]); 2219 tty->print_cr(" r3 = 0x%016lx", regs[3]); 2220 tty->print_cr(" r4 = 0x%016lx", regs[4]); 2221 tty->print_cr(" r5 = 0x%016lx", regs[5]); 2222 tty->print_cr(" r6 = 0x%016lx", regs[6]); 2223 tty->print_cr(" r7 = 0x%016lx", regs[7]); 2224 tty->print_cr(" r8 = 0x%016lx", regs[8]); 2225 tty->print_cr(" r9 = 0x%016lx", regs[9]); 2226 tty->print_cr("r10 = 0x%016lx", regs[10]); 2227 tty->print_cr("r11 = 0x%016lx", regs[11]); 2228 tty->print_cr("r12 = 0x%016lx", regs[12]); 2229 tty->print_cr("r13 = 0x%016lx", regs[13]); 2230 tty->print_cr("r14 = 0x%016lx", regs[14]); 2231 tty->print_cr("r15 = 0x%016lx", regs[15]); 2232 tty->print_cr("r16 = 0x%016lx", regs[16]); 2233 tty->print_cr("r17 = 0x%016lx", regs[17]); 2234 tty->print_cr("r18 = 0x%016lx", regs[18]); 2235 tty->print_cr("r19 = 0x%016lx", regs[19]); 2236 tty->print_cr("r20 = 0x%016lx", regs[20]); 2237 tty->print_cr("r21 = 0x%016lx", regs[21]); 2238 tty->print_cr("r22 = 0x%016lx", regs[22]); 2239 tty->print_cr("r23 = 0x%016lx", regs[23]); 2240 tty->print_cr("r24 = 0x%016lx", regs[24]); 2241 tty->print_cr("r25 = 0x%016lx", regs[25]); 2242 tty->print_cr("r26 = 0x%016lx", regs[26]); 2243 tty->print_cr("r27 = 0x%016lx", regs[27]); 2244 tty->print_cr("r28 = 0x%016lx", regs[28]); 2245 tty->print_cr("r30 = 0x%016lx", regs[30]); 2246 tty->print_cr("r31 = 0x%016lx", regs[31]); 2247 BREAKPOINT; 2248 } 2249 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 2250 } else { 2251 ttyLocker ttyl; 2252 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 2253 msg); 2254 assert(false, "DEBUG MESSAGE: %s", msg); 2255 } 2256 } 2257 2258 #ifdef BUILTIN_SIM 2259 // routine to generate an x86 prolog for a stub function which 2260 // bootstraps into the generated ARM code which directly follows the 2261 // stub 2262 // 2263 // the argument encodes the number of general and fp registers 2264 // passed by the caller and the callng convention (currently just 2265 // the number of general registers and assumes C argument passing) 2266 2267 extern "C" { 2268 int aarch64_stub_prolog_size(); 2269 void aarch64_stub_prolog(); 2270 void aarch64_prolog(); 2271 } 2272 2273 void MacroAssembler::c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, 2274 address *prolog_ptr) 2275 { 2276 int calltype = (((ret_type & 0x3) << 8) | 2277 ((fp_arg_count & 0xf) << 4) | 2278 (gp_arg_count & 0xf)); 2279 2280 // the addresses for the x86 to ARM entry code we need to use 2281 address start = pc(); 2282 // printf("start = %lx\n", start); 2283 int byteCount = aarch64_stub_prolog_size(); 2284 // printf("byteCount = %x\n", byteCount); 2285 int instructionCount = (byteCount + 3)/ 4; 2286 // printf("instructionCount = %x\n", instructionCount); 2287 for (int i = 0; i < instructionCount; i++) { 2288 nop(); 2289 } 2290 2291 memcpy(start, (void*)aarch64_stub_prolog, byteCount); 2292 2293 // write the address of the setup routine and the call format at the 2294 // end of into the copied code 2295 u_int64_t *patch_end = (u_int64_t *)(start + byteCount); 2296 if (prolog_ptr) 2297 patch_end[-2] = (u_int64_t)prolog_ptr; 2298 patch_end[-1] = calltype; 2299 } 2300 #endif 2301 2302 void MacroAssembler::push_call_clobbered_registers() { 2303 push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); 2304 2305 // Push v0-v7, v16-v31. 2306 for (int i = 30; i >= 0; i -= 2) { 2307 if (i <= v7->encoding() || i >= v16->encoding()) { 2308 stpd(as_FloatRegister(i), as_FloatRegister(i+1), 2309 Address(pre(sp, -2 * wordSize))); 2310 } 2311 } 2312 } 2313 2314 void MacroAssembler::pop_call_clobbered_registers() { 2315 2316 for (int i = 0; i < 32; i += 2) { 2317 if (i <= v7->encoding() || i >= v16->encoding()) { 2318 ldpd(as_FloatRegister(i), as_FloatRegister(i+1), 2319 Address(post(sp, 2 * wordSize))); 2320 } 2321 } 2322 2323 pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); 2324 } 2325 2326 void MacroAssembler::push_CPU_state(bool save_vectors) { 2327 push(0x3fffffff, sp); // integer registers except lr & sp 2328 2329 if (!save_vectors) { 2330 for (int i = 30; i >= 0; i -= 2) 2331 stpd(as_FloatRegister(i), as_FloatRegister(i+1), 2332 Address(pre(sp, -2 * wordSize))); 2333 } else { 2334 for (int i = 30; i >= 0; i -= 2) 2335 stpq(as_FloatRegister(i), as_FloatRegister(i+1), 2336 Address(pre(sp, -4 * wordSize))); 2337 } 2338 } 2339 2340 void MacroAssembler::pop_CPU_state(bool restore_vectors) { 2341 if (!restore_vectors) { 2342 for (int i = 0; i < 32; i += 2) 2343 ldpd(as_FloatRegister(i), as_FloatRegister(i+1), 2344 Address(post(sp, 2 * wordSize))); 2345 } else { 2346 for (int i = 0; i < 32; i += 2) 2347 ldpq(as_FloatRegister(i), as_FloatRegister(i+1), 2348 Address(post(sp, 4 * wordSize))); 2349 } 2350 2351 pop(0x3fffffff, sp); // integer registers except lr & sp 2352 } 2353 2354 /** 2355 * Helpers for multiply_to_len(). 2356 */ 2357 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, 2358 Register src1, Register src2) { 2359 adds(dest_lo, dest_lo, src1); 2360 adc(dest_hi, dest_hi, zr); 2361 adds(dest_lo, dest_lo, src2); 2362 adc(final_dest_hi, dest_hi, zr); 2363 } 2364 2365 // Generate an address from (r + r1 extend offset). "size" is the 2366 // size of the operand. The result may be in rscratch2. 2367 Address MacroAssembler::offsetted_address(Register r, Register r1, 2368 Address::extend ext, int offset, int size) { 2369 if (offset || (ext.shift() % size != 0)) { 2370 lea(rscratch2, Address(r, r1, ext)); 2371 return Address(rscratch2, offset); 2372 } else { 2373 return Address(r, r1, ext); 2374 } 2375 } 2376 2377 Address MacroAssembler::spill_address(int size, int offset, Register tmp) 2378 { 2379 assert(offset >= 0, "spill to negative address?"); 2380 // Offset reachable ? 2381 // Not aligned - 9 bits signed offset 2382 // Aligned - 12 bits unsigned offset shifted 2383 Register base = sp; 2384 if ((offset & (size-1)) && offset >= (1<<8)) { 2385 add(tmp, base, offset & ((1<<12)-1)); 2386 base = tmp; 2387 offset &= -1<<12; 2388 } 2389 2390 if (offset >= (1<<12) * size) { 2391 add(tmp, base, offset & (((1<<12)-1)<<12)); 2392 base = tmp; 2393 offset &= ~(((1<<12)-1)<<12); 2394 } 2395 2396 return Address(base, offset); 2397 } 2398 2399 /** 2400 * Multiply 64 bit by 64 bit first loop. 2401 */ 2402 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 2403 Register y, Register y_idx, Register z, 2404 Register carry, Register product, 2405 Register idx, Register kdx) { 2406 // 2407 // jlong carry, x[], y[], z[]; 2408 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 2409 // huge_128 product = y[idx] * x[xstart] + carry; 2410 // z[kdx] = (jlong)product; 2411 // carry = (jlong)(product >>> 64); 2412 // } 2413 // z[xstart] = carry; 2414 // 2415 2416 Label L_first_loop, L_first_loop_exit; 2417 Label L_one_x, L_one_y, L_multiply; 2418 2419 subsw(xstart, xstart, 1); 2420 br(Assembler::MI, L_one_x); 2421 2422 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt))); 2423 ldr(x_xstart, Address(rscratch1)); 2424 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian 2425 2426 bind(L_first_loop); 2427 subsw(idx, idx, 1); 2428 br(Assembler::MI, L_first_loop_exit); 2429 subsw(idx, idx, 1); 2430 br(Assembler::MI, L_one_y); 2431 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2432 ldr(y_idx, Address(rscratch1)); 2433 ror(y_idx, y_idx, 32); // convert big-endian to little-endian 2434 bind(L_multiply); 2435 2436 // AArch64 has a multiply-accumulate instruction that we can't use 2437 // here because it has no way to process carries, so we have to use 2438 // separate add and adc instructions. Bah. 2439 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product 2440 mul(product, x_xstart, y_idx); 2441 adds(product, product, carry); 2442 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product 2443 2444 subw(kdx, kdx, 2); 2445 ror(product, product, 32); // back to big-endian 2446 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong)); 2447 2448 b(L_first_loop); 2449 2450 bind(L_one_y); 2451 ldrw(y_idx, Address(y, 0)); 2452 b(L_multiply); 2453 2454 bind(L_one_x); 2455 ldrw(x_xstart, Address(x, 0)); 2456 b(L_first_loop); 2457 2458 bind(L_first_loop_exit); 2459 } 2460 2461 /** 2462 * Multiply 128 bit by 128. Unrolled inner loop. 2463 * 2464 */ 2465 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z, 2466 Register carry, Register carry2, 2467 Register idx, Register jdx, 2468 Register yz_idx1, Register yz_idx2, 2469 Register tmp, Register tmp3, Register tmp4, 2470 Register tmp6, Register product_hi) { 2471 2472 // jlong carry, x[], y[], z[]; 2473 // int kdx = ystart+1; 2474 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 2475 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry; 2476 // jlong carry2 = (jlong)(tmp3 >>> 64); 2477 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2; 2478 // carry = (jlong)(tmp4 >>> 64); 2479 // z[kdx+idx+1] = (jlong)tmp3; 2480 // z[kdx+idx] = (jlong)tmp4; 2481 // } 2482 // idx += 2; 2483 // if (idx > 0) { 2484 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry; 2485 // z[kdx+idx] = (jlong)yz_idx1; 2486 // carry = (jlong)(yz_idx1 >>> 64); 2487 // } 2488 // 2489 2490 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 2491 2492 lsrw(jdx, idx, 2); 2493 2494 bind(L_third_loop); 2495 2496 subsw(jdx, jdx, 1); 2497 br(Assembler::MI, L_third_loop_exit); 2498 subw(idx, idx, 4); 2499 2500 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2501 2502 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0)); 2503 2504 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2505 2506 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 2507 ror(yz_idx2, yz_idx2, 32); 2508 2509 ldp(rscratch2, rscratch1, Address(tmp6, 0)); 2510 2511 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 2512 umulh(tmp4, product_hi, yz_idx1); 2513 2514 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian 2515 ror(rscratch2, rscratch2, 32); 2516 2517 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp 2518 umulh(carry2, product_hi, yz_idx2); 2519 2520 // propagate sum of both multiplications into carry:tmp4:tmp3 2521 adds(tmp3, tmp3, carry); 2522 adc(tmp4, tmp4, zr); 2523 adds(tmp3, tmp3, rscratch1); 2524 adcs(tmp4, tmp4, tmp); 2525 adc(carry, carry2, zr); 2526 adds(tmp4, tmp4, rscratch2); 2527 adc(carry, carry, zr); 2528 2529 ror(tmp3, tmp3, 32); // convert little-endian to big-endian 2530 ror(tmp4, tmp4, 32); 2531 stp(tmp4, tmp3, Address(tmp6, 0)); 2532 2533 b(L_third_loop); 2534 bind (L_third_loop_exit); 2535 2536 andw (idx, idx, 0x3); 2537 cbz(idx, L_post_third_loop_done); 2538 2539 Label L_check_1; 2540 subsw(idx, idx, 2); 2541 br(Assembler::MI, L_check_1); 2542 2543 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2544 ldr(yz_idx1, Address(rscratch1, 0)); 2545 ror(yz_idx1, yz_idx1, 32); 2546 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 2547 umulh(tmp4, product_hi, yz_idx1); 2548 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2549 ldr(yz_idx2, Address(rscratch1, 0)); 2550 ror(yz_idx2, yz_idx2, 32); 2551 2552 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2); 2553 2554 ror(tmp3, tmp3, 32); 2555 str(tmp3, Address(rscratch1, 0)); 2556 2557 bind (L_check_1); 2558 2559 andw (idx, idx, 0x1); 2560 subsw(idx, idx, 1); 2561 br(Assembler::MI, L_post_third_loop_done); 2562 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2563 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3 2564 umulh(carry2, tmp4, product_hi); 2565 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2566 2567 add2_with_carry(carry2, tmp3, tmp4, carry); 2568 2569 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2570 extr(carry, carry2, tmp3, 32); 2571 2572 bind(L_post_third_loop_done); 2573 } 2574 2575 /** 2576 * Code for BigInteger::multiplyToLen() instrinsic. 2577 * 2578 * r0: x 2579 * r1: xlen 2580 * r2: y 2581 * r3: ylen 2582 * r4: z 2583 * r5: zlen 2584 * r10: tmp1 2585 * r11: tmp2 2586 * r12: tmp3 2587 * r13: tmp4 2588 * r14: tmp5 2589 * r15: tmp6 2590 * r16: tmp7 2591 * 2592 */ 2593 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, 2594 Register z, Register zlen, 2595 Register tmp1, Register tmp2, Register tmp3, Register tmp4, 2596 Register tmp5, Register tmp6, Register product_hi) { 2597 2598 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6); 2599 2600 const Register idx = tmp1; 2601 const Register kdx = tmp2; 2602 const Register xstart = tmp3; 2603 2604 const Register y_idx = tmp4; 2605 const Register carry = tmp5; 2606 const Register product = xlen; 2607 const Register x_xstart = zlen; // reuse register 2608 2609 // First Loop. 2610 // 2611 // final static long LONG_MASK = 0xffffffffL; 2612 // int xstart = xlen - 1; 2613 // int ystart = ylen - 1; 2614 // long carry = 0; 2615 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 2616 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 2617 // z[kdx] = (int)product; 2618 // carry = product >>> 32; 2619 // } 2620 // z[xstart] = (int)carry; 2621 // 2622 2623 movw(idx, ylen); // idx = ylen; 2624 movw(kdx, zlen); // kdx = xlen+ylen; 2625 mov(carry, zr); // carry = 0; 2626 2627 Label L_done; 2628 2629 movw(xstart, xlen); 2630 subsw(xstart, xstart, 1); 2631 br(Assembler::MI, L_done); 2632 2633 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 2634 2635 Label L_second_loop; 2636 cbzw(kdx, L_second_loop); 2637 2638 Label L_carry; 2639 subw(kdx, kdx, 1); 2640 cbzw(kdx, L_carry); 2641 2642 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); 2643 lsr(carry, carry, 32); 2644 subw(kdx, kdx, 1); 2645 2646 bind(L_carry); 2647 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); 2648 2649 // Second and third (nested) loops. 2650 // 2651 // for (int i = xstart-1; i >= 0; i--) { // Second loop 2652 // carry = 0; 2653 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 2654 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 2655 // (z[k] & LONG_MASK) + carry; 2656 // z[k] = (int)product; 2657 // carry = product >>> 32; 2658 // } 2659 // z[i] = (int)carry; 2660 // } 2661 // 2662 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi 2663 2664 const Register jdx = tmp1; 2665 2666 bind(L_second_loop); 2667 mov(carry, zr); // carry = 0; 2668 movw(jdx, ylen); // j = ystart+1 2669 2670 subsw(xstart, xstart, 1); // i = xstart-1; 2671 br(Assembler::MI, L_done); 2672 2673 str(z, Address(pre(sp, -4 * wordSize))); 2674 2675 Label L_last_x; 2676 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j 2677 subsw(xstart, xstart, 1); // i = xstart-1; 2678 br(Assembler::MI, L_last_x); 2679 2680 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt))); 2681 ldr(product_hi, Address(rscratch1)); 2682 ror(product_hi, product_hi, 32); // convert big-endian to little-endian 2683 2684 Label L_third_loop_prologue; 2685 bind(L_third_loop_prologue); 2686 2687 str(ylen, Address(sp, wordSize)); 2688 stp(x, xstart, Address(sp, 2 * wordSize)); 2689 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product, 2690 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi); 2691 ldp(z, ylen, Address(post(sp, 2 * wordSize))); 2692 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen 2693 2694 addw(tmp3, xlen, 1); 2695 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); 2696 subsw(tmp3, tmp3, 1); 2697 br(Assembler::MI, L_done); 2698 2699 lsr(carry, carry, 32); 2700 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); 2701 b(L_second_loop); 2702 2703 // Next infrequent code is moved outside loops. 2704 bind(L_last_x); 2705 ldrw(product_hi, Address(x, 0)); 2706 b(L_third_loop_prologue); 2707 2708 bind(L_done); 2709 } 2710 2711 /** 2712 * Emits code to update CRC-32 with a byte value according to constants in table 2713 * 2714 * @param [in,out]crc Register containing the crc. 2715 * @param [in]val Register containing the byte to fold into the CRC. 2716 * @param [in]table Register containing the table of crc constants. 2717 * 2718 * uint32_t crc; 2719 * val = crc_table[(val ^ crc) & 0xFF]; 2720 * crc = val ^ (crc >> 8); 2721 * 2722 */ 2723 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 2724 eor(val, val, crc); 2725 andr(val, val, 0xff); 2726 ldrw(val, Address(table, val, Address::lsl(2))); 2727 eor(crc, val, crc, Assembler::LSR, 8); 2728 } 2729 2730 /** 2731 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3 2732 * 2733 * @param [in,out]crc Register containing the crc. 2734 * @param [in]v Register containing the 32-bit to fold into the CRC. 2735 * @param [in]table0 Register containing table 0 of crc constants. 2736 * @param [in]table1 Register containing table 1 of crc constants. 2737 * @param [in]table2 Register containing table 2 of crc constants. 2738 * @param [in]table3 Register containing table 3 of crc constants. 2739 * 2740 * uint32_t crc; 2741 * v = crc ^ v 2742 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24] 2743 * 2744 */ 2745 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp, 2746 Register table0, Register table1, Register table2, Register table3, 2747 bool upper) { 2748 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0); 2749 uxtb(tmp, v); 2750 ldrw(crc, Address(table3, tmp, Address::lsl(2))); 2751 ubfx(tmp, v, 8, 8); 2752 ldrw(tmp, Address(table2, tmp, Address::lsl(2))); 2753 eor(crc, crc, tmp); 2754 ubfx(tmp, v, 16, 8); 2755 ldrw(tmp, Address(table1, tmp, Address::lsl(2))); 2756 eor(crc, crc, tmp); 2757 ubfx(tmp, v, 24, 8); 2758 ldrw(tmp, Address(table0, tmp, Address::lsl(2))); 2759 eor(crc, crc, tmp); 2760 } 2761 2762 /** 2763 * @param crc register containing existing CRC (32-bit) 2764 * @param buf register pointing to input byte buffer (byte*) 2765 * @param len register containing number of bytes 2766 * @param table register that will contain address of CRC table 2767 * @param tmp scratch register 2768 */ 2769 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, 2770 Register table0, Register table1, Register table2, Register table3, 2771 Register tmp, Register tmp2, Register tmp3) { 2772 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit; 2773 unsigned long offset; 2774 2775 ornw(crc, zr, crc); 2776 2777 if (UseCRC32) { 2778 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop; 2779 2780 subs(len, len, 64); 2781 br(Assembler::GE, CRC_by64_loop); 2782 adds(len, len, 64-4); 2783 br(Assembler::GE, CRC_by4_loop); 2784 adds(len, len, 4); 2785 br(Assembler::GT, CRC_by1_loop); 2786 b(L_exit); 2787 2788 BIND(CRC_by4_loop); 2789 ldrw(tmp, Address(post(buf, 4))); 2790 subs(len, len, 4); 2791 crc32w(crc, crc, tmp); 2792 br(Assembler::GE, CRC_by4_loop); 2793 adds(len, len, 4); 2794 br(Assembler::LE, L_exit); 2795 BIND(CRC_by1_loop); 2796 ldrb(tmp, Address(post(buf, 1))); 2797 subs(len, len, 1); 2798 crc32b(crc, crc, tmp); 2799 br(Assembler::GT, CRC_by1_loop); 2800 b(L_exit); 2801 2802 align(CodeEntryAlignment); 2803 BIND(CRC_by64_loop); 2804 subs(len, len, 64); 2805 ldp(tmp, tmp3, Address(post(buf, 16))); 2806 crc32x(crc, crc, tmp); 2807 crc32x(crc, crc, tmp3); 2808 ldp(tmp, tmp3, Address(post(buf, 16))); 2809 crc32x(crc, crc, tmp); 2810 crc32x(crc, crc, tmp3); 2811 ldp(tmp, tmp3, Address(post(buf, 16))); 2812 crc32x(crc, crc, tmp); 2813 crc32x(crc, crc, tmp3); 2814 ldp(tmp, tmp3, Address(post(buf, 16))); 2815 crc32x(crc, crc, tmp); 2816 crc32x(crc, crc, tmp3); 2817 br(Assembler::GE, CRC_by64_loop); 2818 adds(len, len, 64-4); 2819 br(Assembler::GE, CRC_by4_loop); 2820 adds(len, len, 4); 2821 br(Assembler::GT, CRC_by1_loop); 2822 BIND(L_exit); 2823 ornw(crc, zr, crc); 2824 return; 2825 } 2826 2827 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset); 2828 if (offset) add(table0, table0, offset); 2829 add(table1, table0, 1*256*sizeof(juint)); 2830 add(table2, table0, 2*256*sizeof(juint)); 2831 add(table3, table0, 3*256*sizeof(juint)); 2832 2833 if (UseNeon) { 2834 cmp(len, 64); 2835 br(Assembler::LT, L_by16); 2836 eor(v16, T16B, v16, v16); 2837 2838 Label L_fold; 2839 2840 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants 2841 2842 ld1(v0, v1, T2D, post(buf, 32)); 2843 ld1r(v4, T2D, post(tmp, 8)); 2844 ld1r(v5, T2D, post(tmp, 8)); 2845 ld1r(v6, T2D, post(tmp, 8)); 2846 ld1r(v7, T2D, post(tmp, 8)); 2847 mov(v16, T4S, 0, crc); 2848 2849 eor(v0, T16B, v0, v16); 2850 sub(len, len, 64); 2851 2852 BIND(L_fold); 2853 pmull(v22, T8H, v0, v5, T8B); 2854 pmull(v20, T8H, v0, v7, T8B); 2855 pmull(v23, T8H, v0, v4, T8B); 2856 pmull(v21, T8H, v0, v6, T8B); 2857 2858 pmull2(v18, T8H, v0, v5, T16B); 2859 pmull2(v16, T8H, v0, v7, T16B); 2860 pmull2(v19, T8H, v0, v4, T16B); 2861 pmull2(v17, T8H, v0, v6, T16B); 2862 2863 uzp1(v24, v20, v22, T8H); 2864 uzp2(v25, v20, v22, T8H); 2865 eor(v20, T16B, v24, v25); 2866 2867 uzp1(v26, v16, v18, T8H); 2868 uzp2(v27, v16, v18, T8H); 2869 eor(v16, T16B, v26, v27); 2870 2871 ushll2(v22, T4S, v20, T8H, 8); 2872 ushll(v20, T4S, v20, T4H, 8); 2873 2874 ushll2(v18, T4S, v16, T8H, 8); 2875 ushll(v16, T4S, v16, T4H, 8); 2876 2877 eor(v22, T16B, v23, v22); 2878 eor(v18, T16B, v19, v18); 2879 eor(v20, T16B, v21, v20); 2880 eor(v16, T16B, v17, v16); 2881 2882 uzp1(v17, v16, v20, T2D); 2883 uzp2(v21, v16, v20, T2D); 2884 eor(v17, T16B, v17, v21); 2885 2886 ushll2(v20, T2D, v17, T4S, 16); 2887 ushll(v16, T2D, v17, T2S, 16); 2888 2889 eor(v20, T16B, v20, v22); 2890 eor(v16, T16B, v16, v18); 2891 2892 uzp1(v17, v20, v16, T2D); 2893 uzp2(v21, v20, v16, T2D); 2894 eor(v28, T16B, v17, v21); 2895 2896 pmull(v22, T8H, v1, v5, T8B); 2897 pmull(v20, T8H, v1, v7, T8B); 2898 pmull(v23, T8H, v1, v4, T8B); 2899 pmull(v21, T8H, v1, v6, T8B); 2900 2901 pmull2(v18, T8H, v1, v5, T16B); 2902 pmull2(v16, T8H, v1, v7, T16B); 2903 pmull2(v19, T8H, v1, v4, T16B); 2904 pmull2(v17, T8H, v1, v6, T16B); 2905 2906 ld1(v0, v1, T2D, post(buf, 32)); 2907 2908 uzp1(v24, v20, v22, T8H); 2909 uzp2(v25, v20, v22, T8H); 2910 eor(v20, T16B, v24, v25); 2911 2912 uzp1(v26, v16, v18, T8H); 2913 uzp2(v27, v16, v18, T8H); 2914 eor(v16, T16B, v26, v27); 2915 2916 ushll2(v22, T4S, v20, T8H, 8); 2917 ushll(v20, T4S, v20, T4H, 8); 2918 2919 ushll2(v18, T4S, v16, T8H, 8); 2920 ushll(v16, T4S, v16, T4H, 8); 2921 2922 eor(v22, T16B, v23, v22); 2923 eor(v18, T16B, v19, v18); 2924 eor(v20, T16B, v21, v20); 2925 eor(v16, T16B, v17, v16); 2926 2927 uzp1(v17, v16, v20, T2D); 2928 uzp2(v21, v16, v20, T2D); 2929 eor(v16, T16B, v17, v21); 2930 2931 ushll2(v20, T2D, v16, T4S, 16); 2932 ushll(v16, T2D, v16, T2S, 16); 2933 2934 eor(v20, T16B, v22, v20); 2935 eor(v16, T16B, v16, v18); 2936 2937 uzp1(v17, v20, v16, T2D); 2938 uzp2(v21, v20, v16, T2D); 2939 eor(v20, T16B, v17, v21); 2940 2941 shl(v16, T2D, v28, 1); 2942 shl(v17, T2D, v20, 1); 2943 2944 eor(v0, T16B, v0, v16); 2945 eor(v1, T16B, v1, v17); 2946 2947 subs(len, len, 32); 2948 br(Assembler::GE, L_fold); 2949 2950 mov(crc, 0); 2951 mov(tmp, v0, T1D, 0); 2952 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 2953 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 2954 mov(tmp, v0, T1D, 1); 2955 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 2956 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 2957 mov(tmp, v1, T1D, 0); 2958 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 2959 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 2960 mov(tmp, v1, T1D, 1); 2961 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 2962 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 2963 2964 add(len, len, 32); 2965 } 2966 2967 BIND(L_by16); 2968 subs(len, len, 16); 2969 br(Assembler::GE, L_by16_loop); 2970 adds(len, len, 16-4); 2971 br(Assembler::GE, L_by4_loop); 2972 adds(len, len, 4); 2973 br(Assembler::GT, L_by1_loop); 2974 b(L_exit); 2975 2976 BIND(L_by4_loop); 2977 ldrw(tmp, Address(post(buf, 4))); 2978 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3); 2979 subs(len, len, 4); 2980 br(Assembler::GE, L_by4_loop); 2981 adds(len, len, 4); 2982 br(Assembler::LE, L_exit); 2983 BIND(L_by1_loop); 2984 subs(len, len, 1); 2985 ldrb(tmp, Address(post(buf, 1))); 2986 update_byte_crc32(crc, tmp, table0); 2987 br(Assembler::GT, L_by1_loop); 2988 b(L_exit); 2989 2990 align(CodeEntryAlignment); 2991 BIND(L_by16_loop); 2992 subs(len, len, 16); 2993 ldp(tmp, tmp3, Address(post(buf, 16))); 2994 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 2995 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 2996 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false); 2997 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true); 2998 br(Assembler::GE, L_by16_loop); 2999 adds(len, len, 16-4); 3000 br(Assembler::GE, L_by4_loop); 3001 adds(len, len, 4); 3002 br(Assembler::GT, L_by1_loop); 3003 BIND(L_exit); 3004 ornw(crc, zr, crc); 3005 } 3006 3007 /** 3008 * @param crc register containing existing CRC (32-bit) 3009 * @param buf register pointing to input byte buffer (byte*) 3010 * @param len register containing number of bytes 3011 * @param table register that will contain address of CRC table 3012 * @param tmp scratch register 3013 */ 3014 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len, 3015 Register table0, Register table1, Register table2, Register table3, 3016 Register tmp, Register tmp2, Register tmp3) { 3017 Label L_exit; 3018 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop; 3019 3020 subs(len, len, 64); 3021 br(Assembler::GE, CRC_by64_loop); 3022 adds(len, len, 64-4); 3023 br(Assembler::GE, CRC_by4_loop); 3024 adds(len, len, 4); 3025 br(Assembler::GT, CRC_by1_loop); 3026 b(L_exit); 3027 3028 BIND(CRC_by4_loop); 3029 ldrw(tmp, Address(post(buf, 4))); 3030 subs(len, len, 4); 3031 crc32cw(crc, crc, tmp); 3032 br(Assembler::GE, CRC_by4_loop); 3033 adds(len, len, 4); 3034 br(Assembler::LE, L_exit); 3035 BIND(CRC_by1_loop); 3036 ldrb(tmp, Address(post(buf, 1))); 3037 subs(len, len, 1); 3038 crc32cb(crc, crc, tmp); 3039 br(Assembler::GT, CRC_by1_loop); 3040 b(L_exit); 3041 3042 align(CodeEntryAlignment); 3043 BIND(CRC_by64_loop); 3044 subs(len, len, 64); 3045 ldp(tmp, tmp3, Address(post(buf, 16))); 3046 crc32cx(crc, crc, tmp); 3047 crc32cx(crc, crc, tmp3); 3048 ldp(tmp, tmp3, Address(post(buf, 16))); 3049 crc32cx(crc, crc, tmp); 3050 crc32cx(crc, crc, tmp3); 3051 ldp(tmp, tmp3, Address(post(buf, 16))); 3052 crc32cx(crc, crc, tmp); 3053 crc32cx(crc, crc, tmp3); 3054 ldp(tmp, tmp3, Address(post(buf, 16))); 3055 crc32cx(crc, crc, tmp); 3056 crc32cx(crc, crc, tmp3); 3057 br(Assembler::GE, CRC_by64_loop); 3058 adds(len, len, 64-4); 3059 br(Assembler::GE, CRC_by4_loop); 3060 adds(len, len, 4); 3061 br(Assembler::GT, CRC_by1_loop); 3062 BIND(L_exit); 3063 return; 3064 } 3065 3066 SkipIfEqual::SkipIfEqual( 3067 MacroAssembler* masm, const bool* flag_addr, bool value) { 3068 _masm = masm; 3069 unsigned long offset; 3070 _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset); 3071 _masm->ldrb(rscratch1, Address(rscratch1, offset)); 3072 _masm->cbzw(rscratch1, _label); 3073 } 3074 3075 SkipIfEqual::~SkipIfEqual() { 3076 _masm->bind(_label); 3077 } 3078 3079 void MacroAssembler::addptr(const Address &dst, int32_t src) { 3080 Address adr; 3081 switch(dst.getMode()) { 3082 case Address::base_plus_offset: 3083 // This is the expected mode, although we allow all the other 3084 // forms below. 3085 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord); 3086 break; 3087 default: 3088 lea(rscratch2, dst); 3089 adr = Address(rscratch2); 3090 break; 3091 } 3092 ldr(rscratch1, adr); 3093 add(rscratch1, rscratch1, src); 3094 str(rscratch1, adr); 3095 } 3096 3097 void MacroAssembler::cmpptr(Register src1, Address src2) { 3098 unsigned long offset; 3099 adrp(rscratch1, src2, offset); 3100 ldr(rscratch1, Address(rscratch1, offset)); 3101 cmp(src1, rscratch1); 3102 } 3103 3104 void MacroAssembler::store_check(Register obj, Address dst) { 3105 store_check(obj); 3106 } 3107 3108 void MacroAssembler::store_check(Register obj) { 3109 // Does a store check for the oop in register obj. The content of 3110 // register obj is destroyed afterwards. 3111 3112 BarrierSet* bs = Universe::heap()->barrier_set(); 3113 assert(bs->kind() == BarrierSet::CardTableForRS || 3114 bs->kind() == BarrierSet::CardTableExtension, 3115 "Wrong barrier set kind"); 3116 3117 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs); 3118 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 3119 3120 lsr(obj, obj, CardTableModRefBS::card_shift); 3121 3122 assert(CardTableModRefBS::dirty_card_val() == 0, "must be"); 3123 3124 load_byte_map_base(rscratch1); 3125 3126 if (UseCondCardMark) { 3127 Label L_already_dirty; 3128 membar(StoreLoad); 3129 ldrb(rscratch2, Address(obj, rscratch1)); 3130 cbz(rscratch2, L_already_dirty); 3131 strb(zr, Address(obj, rscratch1)); 3132 bind(L_already_dirty); 3133 } else { 3134 if (UseConcMarkSweepGC && CMSPrecleaningEnabled) { 3135 membar(StoreStore); 3136 } 3137 strb(zr, Address(obj, rscratch1)); 3138 } 3139 } 3140 3141 void MacroAssembler::load_klass(Register dst, Register src) { 3142 if (UseCompressedClassPointers) { 3143 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes())); 3144 decode_klass_not_null(dst); 3145 } else { 3146 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 3147 } 3148 } 3149 3150 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) { 3151 if (UseCompressedClassPointers) { 3152 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); 3153 if (Universe::narrow_klass_base() == NULL) { 3154 cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift()); 3155 return; 3156 } else if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 3157 && Universe::narrow_klass_shift() == 0) { 3158 // Only the bottom 32 bits matter 3159 cmpw(trial_klass, tmp); 3160 return; 3161 } 3162 decode_klass_not_null(tmp); 3163 } else { 3164 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); 3165 } 3166 cmp(trial_klass, tmp); 3167 } 3168 3169 void MacroAssembler::load_prototype_header(Register dst, Register src) { 3170 load_klass(dst, src); 3171 ldr(dst, Address(dst, Klass::prototype_header_offset())); 3172 } 3173 3174 void MacroAssembler::store_klass(Register dst, Register src) { 3175 // FIXME: Should this be a store release? concurrent gcs assumes 3176 // klass length is valid if klass field is not null. 3177 if (UseCompressedClassPointers) { 3178 encode_klass_not_null(src); 3179 strw(src, Address(dst, oopDesc::klass_offset_in_bytes())); 3180 } else { 3181 str(src, Address(dst, oopDesc::klass_offset_in_bytes())); 3182 } 3183 } 3184 3185 void MacroAssembler::store_klass_gap(Register dst, Register src) { 3186 if (UseCompressedClassPointers) { 3187 // Store to klass gap in destination 3188 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes())); 3189 } 3190 } 3191 3192 // Algorithm must match oop.inline.hpp encode_heap_oop. 3193 void MacroAssembler::encode_heap_oop(Register d, Register s) { 3194 #ifdef ASSERT 3195 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 3196 #endif 3197 verify_oop(s, "broken oop in encode_heap_oop"); 3198 if (Universe::narrow_oop_base() == NULL) { 3199 if (Universe::narrow_oop_shift() != 0) { 3200 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3201 lsr(d, s, LogMinObjAlignmentInBytes); 3202 } else { 3203 mov(d, s); 3204 } 3205 } else { 3206 subs(d, s, rheapbase); 3207 csel(d, d, zr, Assembler::HS); 3208 lsr(d, d, LogMinObjAlignmentInBytes); 3209 3210 /* Old algorithm: is this any worse? 3211 Label nonnull; 3212 cbnz(r, nonnull); 3213 sub(r, r, rheapbase); 3214 bind(nonnull); 3215 lsr(r, r, LogMinObjAlignmentInBytes); 3216 */ 3217 } 3218 } 3219 3220 void MacroAssembler::encode_heap_oop_not_null(Register r) { 3221 #ifdef ASSERT 3222 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 3223 if (CheckCompressedOops) { 3224 Label ok; 3225 cbnz(r, ok); 3226 stop("null oop passed to encode_heap_oop_not_null"); 3227 bind(ok); 3228 } 3229 #endif 3230 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 3231 if (Universe::narrow_oop_base() != NULL) { 3232 sub(r, r, rheapbase); 3233 } 3234 if (Universe::narrow_oop_shift() != 0) { 3235 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3236 lsr(r, r, LogMinObjAlignmentInBytes); 3237 } 3238 } 3239 3240 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 3241 #ifdef ASSERT 3242 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 3243 if (CheckCompressedOops) { 3244 Label ok; 3245 cbnz(src, ok); 3246 stop("null oop passed to encode_heap_oop_not_null2"); 3247 bind(ok); 3248 } 3249 #endif 3250 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 3251 3252 Register data = src; 3253 if (Universe::narrow_oop_base() != NULL) { 3254 sub(dst, src, rheapbase); 3255 data = dst; 3256 } 3257 if (Universe::narrow_oop_shift() != 0) { 3258 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3259 lsr(dst, data, LogMinObjAlignmentInBytes); 3260 data = dst; 3261 } 3262 if (data == src) 3263 mov(dst, src); 3264 } 3265 3266 void MacroAssembler::decode_heap_oop(Register d, Register s) { 3267 #ifdef ASSERT 3268 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 3269 #endif 3270 if (Universe::narrow_oop_base() == NULL) { 3271 if (Universe::narrow_oop_shift() != 0 || d != s) { 3272 lsl(d, s, Universe::narrow_oop_shift()); 3273 } 3274 } else { 3275 Label done; 3276 if (d != s) 3277 mov(d, s); 3278 cbz(s, done); 3279 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes); 3280 bind(done); 3281 } 3282 verify_oop(d, "broken oop in decode_heap_oop"); 3283 } 3284 3285 void MacroAssembler::decode_heap_oop_not_null(Register r) { 3286 assert (UseCompressedOops, "should only be used for compressed headers"); 3287 assert (Universe::heap() != NULL, "java heap should be initialized"); 3288 // Cannot assert, unverified entry point counts instructions (see .ad file) 3289 // vtableStubs also counts instructions in pd_code_size_limit. 3290 // Also do not verify_oop as this is called by verify_oop. 3291 if (Universe::narrow_oop_shift() != 0) { 3292 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3293 if (Universe::narrow_oop_base() != NULL) { 3294 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes); 3295 } else { 3296 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes); 3297 } 3298 } else { 3299 assert (Universe::narrow_oop_base() == NULL, "sanity"); 3300 } 3301 } 3302 3303 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 3304 assert (UseCompressedOops, "should only be used for compressed headers"); 3305 assert (Universe::heap() != NULL, "java heap should be initialized"); 3306 // Cannot assert, unverified entry point counts instructions (see .ad file) 3307 // vtableStubs also counts instructions in pd_code_size_limit. 3308 // Also do not verify_oop as this is called by verify_oop. 3309 if (Universe::narrow_oop_shift() != 0) { 3310 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3311 if (Universe::narrow_oop_base() != NULL) { 3312 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes); 3313 } else { 3314 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes); 3315 } 3316 } else { 3317 assert (Universe::narrow_oop_base() == NULL, "sanity"); 3318 if (dst != src) { 3319 mov(dst, src); 3320 } 3321 } 3322 } 3323 3324 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 3325 if (Universe::narrow_klass_base() == NULL) { 3326 if (Universe::narrow_klass_shift() != 0) { 3327 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3328 lsr(dst, src, LogKlassAlignmentInBytes); 3329 } else { 3330 if (dst != src) mov(dst, src); 3331 } 3332 return; 3333 } 3334 3335 if (use_XOR_for_compressed_class_base) { 3336 if (Universe::narrow_klass_shift() != 0) { 3337 eor(dst, src, (uint64_t)Universe::narrow_klass_base()); 3338 lsr(dst, dst, LogKlassAlignmentInBytes); 3339 } else { 3340 eor(dst, src, (uint64_t)Universe::narrow_klass_base()); 3341 } 3342 return; 3343 } 3344 3345 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 3346 && Universe::narrow_klass_shift() == 0) { 3347 movw(dst, src); 3348 return; 3349 } 3350 3351 #ifdef ASSERT 3352 verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?"); 3353 #endif 3354 3355 Register rbase = dst; 3356 if (dst == src) rbase = rheapbase; 3357 mov(rbase, (uint64_t)Universe::narrow_klass_base()); 3358 sub(dst, src, rbase); 3359 if (Universe::narrow_klass_shift() != 0) { 3360 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3361 lsr(dst, dst, LogKlassAlignmentInBytes); 3362 } 3363 if (dst == src) reinit_heapbase(); 3364 } 3365 3366 void MacroAssembler::encode_klass_not_null(Register r) { 3367 encode_klass_not_null(r, r); 3368 } 3369 3370 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 3371 Register rbase = dst; 3372 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 3373 3374 if (Universe::narrow_klass_base() == NULL) { 3375 if (Universe::narrow_klass_shift() != 0) { 3376 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3377 lsl(dst, src, LogKlassAlignmentInBytes); 3378 } else { 3379 if (dst != src) mov(dst, src); 3380 } 3381 return; 3382 } 3383 3384 if (use_XOR_for_compressed_class_base) { 3385 if (Universe::narrow_klass_shift() != 0) { 3386 lsl(dst, src, LogKlassAlignmentInBytes); 3387 eor(dst, dst, (uint64_t)Universe::narrow_klass_base()); 3388 } else { 3389 eor(dst, src, (uint64_t)Universe::narrow_klass_base()); 3390 } 3391 return; 3392 } 3393 3394 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 3395 && Universe::narrow_klass_shift() == 0) { 3396 if (dst != src) 3397 movw(dst, src); 3398 movk(dst, (uint64_t)Universe::narrow_klass_base() >> 32, 32); 3399 return; 3400 } 3401 3402 // Cannot assert, unverified entry point counts instructions (see .ad file) 3403 // vtableStubs also counts instructions in pd_code_size_limit. 3404 // Also do not verify_oop as this is called by verify_oop. 3405 if (dst == src) rbase = rheapbase; 3406 mov(rbase, (uint64_t)Universe::narrow_klass_base()); 3407 if (Universe::narrow_klass_shift() != 0) { 3408 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3409 add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes); 3410 } else { 3411 add(dst, rbase, src); 3412 } 3413 if (dst == src) reinit_heapbase(); 3414 } 3415 3416 void MacroAssembler::decode_klass_not_null(Register r) { 3417 decode_klass_not_null(r, r); 3418 } 3419 3420 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 3421 assert (UseCompressedOops, "should only be used for compressed oops"); 3422 assert (Universe::heap() != NULL, "java heap should be initialized"); 3423 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 3424 3425 int oop_index = oop_recorder()->find_index(obj); 3426 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop"); 3427 3428 InstructionMark im(this); 3429 RelocationHolder rspec = oop_Relocation::spec(oop_index); 3430 code_section()->relocate(inst_mark(), rspec); 3431 movz(dst, 0xDEAD, 16); 3432 movk(dst, 0xBEEF); 3433 } 3434 3435 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 3436 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 3437 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 3438 int index = oop_recorder()->find_index(k); 3439 assert(! Universe::heap()->is_in_reserved(k), "should not be an oop"); 3440 3441 InstructionMark im(this); 3442 RelocationHolder rspec = metadata_Relocation::spec(index); 3443 code_section()->relocate(inst_mark(), rspec); 3444 narrowKlass nk = Klass::encode_klass(k); 3445 movz(dst, (nk >> 16), 16); 3446 movk(dst, nk & 0xffff); 3447 } 3448 3449 void MacroAssembler::load_heap_oop(Register dst, Address src) 3450 { 3451 if (UseCompressedOops) { 3452 ldrw(dst, src); 3453 decode_heap_oop(dst); 3454 } else { 3455 ldr(dst, src); 3456 } 3457 } 3458 3459 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) 3460 { 3461 if (UseCompressedOops) { 3462 ldrw(dst, src); 3463 decode_heap_oop_not_null(dst); 3464 } else { 3465 ldr(dst, src); 3466 } 3467 } 3468 3469 void MacroAssembler::store_heap_oop(Address dst, Register src) { 3470 if (UseCompressedOops) { 3471 assert(!dst.uses(src), "not enough registers"); 3472 encode_heap_oop(src); 3473 strw(src, dst); 3474 } else 3475 str(src, dst); 3476 } 3477 3478 // Used for storing NULLs. 3479 void MacroAssembler::store_heap_oop_null(Address dst) { 3480 if (UseCompressedOops) { 3481 strw(zr, dst); 3482 } else 3483 str(zr, dst); 3484 } 3485 3486 #if INCLUDE_ALL_GCS 3487 void MacroAssembler::g1_write_barrier_pre(Register obj, 3488 Register pre_val, 3489 Register thread, 3490 Register tmp, 3491 bool tosca_live, 3492 bool expand_call) { 3493 // If expand_call is true then we expand the call_VM_leaf macro 3494 // directly to skip generating the check by 3495 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 3496 3497 assert(thread == rthread, "must be"); 3498 3499 Label done; 3500 Label runtime; 3501 3502 assert(pre_val != noreg, "check this code"); 3503 3504 if (obj != noreg) 3505 assert_different_registers(obj, pre_val, tmp); 3506 3507 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 3508 SATBMarkQueue::byte_offset_of_active())); 3509 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 3510 SATBMarkQueue::byte_offset_of_index())); 3511 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 3512 SATBMarkQueue::byte_offset_of_buf())); 3513 3514 3515 // Is marking active? 3516 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { 3517 ldrw(tmp, in_progress); 3518 } else { 3519 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); 3520 ldrb(tmp, in_progress); 3521 } 3522 cbzw(tmp, done); 3523 3524 // Do we need to load the previous value? 3525 if (obj != noreg) { 3526 load_heap_oop(pre_val, Address(obj, 0)); 3527 } 3528 3529 // Is the previous value null? 3530 cbz(pre_val, done); 3531 3532 // Can we store original value in the thread's buffer? 3533 // Is index == 0? 3534 // (The index field is typed as size_t.) 3535 3536 ldr(tmp, index); // tmp := *index_adr 3537 cbz(tmp, runtime); // tmp == 0? 3538 // If yes, goto runtime 3539 3540 sub(tmp, tmp, wordSize); // tmp := tmp - wordSize 3541 str(tmp, index); // *index_adr := tmp 3542 ldr(rscratch1, buffer); 3543 add(tmp, tmp, rscratch1); // tmp := tmp + *buffer_adr 3544 3545 // Record the previous value 3546 str(pre_val, Address(tmp, 0)); 3547 b(done); 3548 3549 bind(runtime); 3550 // save the live input values 3551 push(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp); 3552 3553 // Calling the runtime using the regular call_VM_leaf mechanism generates 3554 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 3555 // that checks that the *(rfp+frame::interpreter_frame_last_sp) == NULL. 3556 // 3557 // If we care generating the pre-barrier without a frame (e.g. in the 3558 // intrinsified Reference.get() routine) then ebp might be pointing to 3559 // the caller frame and so this check will most likely fail at runtime. 3560 // 3561 // Expanding the call directly bypasses the generation of the check. 3562 // So when we do not have have a full interpreter frame on the stack 3563 // expand_call should be passed true. 3564 3565 if (expand_call) { 3566 assert(pre_val != c_rarg1, "smashed arg"); 3567 pass_arg1(this, thread); 3568 pass_arg0(this, pre_val); 3569 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 3570 } else { 3571 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 3572 } 3573 3574 pop(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp); 3575 3576 bind(done); 3577 } 3578 3579 void MacroAssembler::g1_write_barrier_post(Register store_addr, 3580 Register new_val, 3581 Register thread, 3582 Register tmp, 3583 Register tmp2) { 3584 assert(thread == rthread, "must be"); 3585 3586 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 3587 DirtyCardQueue::byte_offset_of_index())); 3588 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 3589 DirtyCardQueue::byte_offset_of_buf())); 3590 3591 BarrierSet* bs = Universe::heap()->barrier_set(); 3592 CardTableModRefBS* ct = (CardTableModRefBS*)bs; 3593 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 3594 3595 Label done; 3596 Label runtime; 3597 3598 // Does store cross heap regions? 3599 3600 eor(tmp, store_addr, new_val); 3601 lsr(tmp, tmp, HeapRegion::LogOfHRGrainBytes); 3602 cbz(tmp, done); 3603 3604 // crosses regions, storing NULL? 3605 3606 cbz(new_val, done); 3607 3608 // storing region crossing non-NULL, is card already dirty? 3609 3610 ExternalAddress cardtable((address) ct->byte_map_base); 3611 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 3612 const Register card_addr = tmp; 3613 3614 lsr(card_addr, store_addr, CardTableModRefBS::card_shift); 3615 3616 // get the address of the card 3617 load_byte_map_base(tmp2); 3618 add(card_addr, card_addr, tmp2); 3619 ldrb(tmp2, Address(card_addr)); 3620 cmpw(tmp2, (int)G1SATBCardTableModRefBS::g1_young_card_val()); 3621 br(Assembler::EQ, done); 3622 3623 assert((int)CardTableModRefBS::dirty_card_val() == 0, "must be 0"); 3624 3625 membar(Assembler::StoreLoad); 3626 3627 ldrb(tmp2, Address(card_addr)); 3628 cbzw(tmp2, done); 3629 3630 // storing a region crossing, non-NULL oop, card is clean. 3631 // dirty card and log. 3632 3633 strb(zr, Address(card_addr)); 3634 3635 ldr(rscratch1, queue_index); 3636 cbz(rscratch1, runtime); 3637 sub(rscratch1, rscratch1, wordSize); 3638 str(rscratch1, queue_index); 3639 3640 ldr(tmp2, buffer); 3641 str(card_addr, Address(tmp2, rscratch1)); 3642 b(done); 3643 3644 bind(runtime); 3645 // save the live input values 3646 push(store_addr->bit(true) | new_val->bit(true), sp); 3647 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 3648 pop(store_addr->bit(true) | new_val->bit(true), sp); 3649 3650 bind(done); 3651 } 3652 3653 #endif // INCLUDE_ALL_GCS 3654 3655 Address MacroAssembler::allocate_metadata_address(Metadata* obj) { 3656 assert(oop_recorder() != NULL, "this assembler needs a Recorder"); 3657 int index = oop_recorder()->allocate_metadata_index(obj); 3658 RelocationHolder rspec = metadata_Relocation::spec(index); 3659 return Address((address)obj, rspec); 3660 } 3661 3662 // Move an oop into a register. immediate is true if we want 3663 // immediate instrcutions, i.e. we are not going to patch this 3664 // instruction while the code is being executed by another thread. In 3665 // that case we can use move immediates rather than the constant pool. 3666 void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) { 3667 int oop_index; 3668 if (obj == NULL) { 3669 oop_index = oop_recorder()->allocate_oop_index(obj); 3670 } else { 3671 oop_index = oop_recorder()->find_index(obj); 3672 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop"); 3673 } 3674 RelocationHolder rspec = oop_Relocation::spec(oop_index); 3675 if (! immediate) { 3676 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address 3677 ldr_constant(dst, Address(dummy, rspec)); 3678 } else 3679 mov(dst, Address((address)obj, rspec)); 3680 } 3681 3682 // Move a metadata address into a register. 3683 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 3684 int oop_index; 3685 if (obj == NULL) { 3686 oop_index = oop_recorder()->allocate_metadata_index(obj); 3687 } else { 3688 oop_index = oop_recorder()->find_index(obj); 3689 } 3690 RelocationHolder rspec = metadata_Relocation::spec(oop_index); 3691 mov(dst, Address((address)obj, rspec)); 3692 } 3693 3694 Address MacroAssembler::constant_oop_address(jobject obj) { 3695 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); 3696 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop"); 3697 int oop_index = oop_recorder()->find_index(obj); 3698 return Address((address)obj, oop_Relocation::spec(oop_index)); 3699 } 3700 3701 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 3702 void MacroAssembler::tlab_allocate(Register obj, 3703 Register var_size_in_bytes, 3704 int con_size_in_bytes, 3705 Register t1, 3706 Register t2, 3707 Label& slow_case) { 3708 assert_different_registers(obj, t2); 3709 assert_different_registers(obj, var_size_in_bytes); 3710 Register end = t2; 3711 3712 // verify_tlab(); 3713 3714 ldr(obj, Address(rthread, JavaThread::tlab_top_offset())); 3715 if (var_size_in_bytes == noreg) { 3716 lea(end, Address(obj, con_size_in_bytes)); 3717 } else { 3718 lea(end, Address(obj, var_size_in_bytes)); 3719 } 3720 ldr(rscratch1, Address(rthread, JavaThread::tlab_end_offset())); 3721 cmp(end, rscratch1); 3722 br(Assembler::HI, slow_case); 3723 3724 // update the tlab top pointer 3725 str(end, Address(rthread, JavaThread::tlab_top_offset())); 3726 3727 // recover var_size_in_bytes if necessary 3728 if (var_size_in_bytes == end) { 3729 sub(var_size_in_bytes, var_size_in_bytes, obj); 3730 } 3731 // verify_tlab(); 3732 } 3733 3734 // Preserves r19, and r3. 3735 Register MacroAssembler::tlab_refill(Label& retry, 3736 Label& try_eden, 3737 Label& slow_case) { 3738 Register top = r0; 3739 Register t1 = r2; 3740 Register t2 = r4; 3741 assert_different_registers(top, rthread, t1, t2, /* preserve: */ r19, r3); 3742 Label do_refill, discard_tlab; 3743 3744 if (!Universe::heap()->supports_inline_contig_alloc()) { 3745 // No allocation in the shared eden. 3746 b(slow_case); 3747 } 3748 3749 ldr(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 3750 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 3751 3752 // calculate amount of free space 3753 sub(t1, t1, top); 3754 lsr(t1, t1, LogHeapWordSize); 3755 3756 // Retain tlab and allocate object in shared space if 3757 // the amount free in the tlab is too large to discard. 3758 3759 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 3760 cmp(t1, rscratch1); 3761 br(Assembler::LE, discard_tlab); 3762 3763 // Retain 3764 // ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 3765 mov(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 3766 add(rscratch1, rscratch1, t2); 3767 str(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 3768 3769 if (TLABStats) { 3770 // increment number of slow_allocations 3771 addmw(Address(rthread, in_bytes(JavaThread::tlab_slow_allocations_offset())), 3772 1, rscratch1); 3773 } 3774 b(try_eden); 3775 3776 bind(discard_tlab); 3777 if (TLABStats) { 3778 // increment number of refills 3779 addmw(Address(rthread, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1, 3780 rscratch1); 3781 // accumulate wastage -- t1 is amount free in tlab 3782 addmw(Address(rthread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1, 3783 rscratch1); 3784 } 3785 3786 // if tlab is currently allocated (top or end != null) then 3787 // fill [top, end + alignment_reserve) with array object 3788 cbz(top, do_refill); 3789 3790 // set up the mark word 3791 mov(rscratch1, (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 3792 str(rscratch1, Address(top, oopDesc::mark_offset_in_bytes())); 3793 // set the length to the remaining space 3794 sub(t1, t1, typeArrayOopDesc::header_size(T_INT)); 3795 add(t1, t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 3796 lsl(t1, t1, log2_intptr(HeapWordSize/sizeof(jint))); 3797 strw(t1, Address(top, arrayOopDesc::length_offset_in_bytes())); 3798 // set klass to intArrayKlass 3799 { 3800 unsigned long offset; 3801 // dubious reloc why not an oop reloc? 3802 adrp(rscratch1, ExternalAddress((address)Universe::intArrayKlassObj_addr()), 3803 offset); 3804 ldr(t1, Address(rscratch1, offset)); 3805 } 3806 // store klass last. concurrent gcs assumes klass length is valid if 3807 // klass field is not null. 3808 store_klass(top, t1); 3809 3810 mov(t1, top); 3811 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 3812 sub(t1, t1, rscratch1); 3813 incr_allocated_bytes(rthread, t1, 0, rscratch1); 3814 3815 // refill the tlab with an eden allocation 3816 bind(do_refill); 3817 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_size_offset()))); 3818 lsl(t1, t1, LogHeapWordSize); 3819 // allocate new tlab, address returned in top 3820 eden_allocate(top, t1, 0, t2, slow_case); 3821 3822 // Check that t1 was preserved in eden_allocate. 3823 #ifdef ASSERT 3824 if (UseTLAB) { 3825 Label ok; 3826 Register tsize = r4; 3827 assert_different_registers(tsize, rthread, t1); 3828 str(tsize, Address(pre(sp, -16))); 3829 ldr(tsize, Address(rthread, in_bytes(JavaThread::tlab_size_offset()))); 3830 lsl(tsize, tsize, LogHeapWordSize); 3831 cmp(t1, tsize); 3832 br(Assembler::EQ, ok); 3833 STOP("assert(t1 != tlab size)"); 3834 should_not_reach_here(); 3835 3836 bind(ok); 3837 ldr(tsize, Address(post(sp, 16))); 3838 } 3839 #endif 3840 str(top, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 3841 str(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 3842 add(top, top, t1); 3843 sub(top, top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 3844 str(top, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 3845 verify_tlab(); 3846 b(retry); 3847 3848 return rthread; // for use by caller 3849 } 3850 3851 // Defines obj, preserves var_size_in_bytes 3852 void MacroAssembler::eden_allocate(Register obj, 3853 Register var_size_in_bytes, 3854 int con_size_in_bytes, 3855 Register t1, 3856 Label& slow_case) { 3857 assert_different_registers(obj, var_size_in_bytes, t1); 3858 if (!Universe::heap()->supports_inline_contig_alloc()) { 3859 b(slow_case); 3860 } else { 3861 Register end = t1; 3862 Register heap_end = rscratch2; 3863 Label retry; 3864 bind(retry); 3865 { 3866 unsigned long offset; 3867 adrp(rscratch1, ExternalAddress((address) Universe::heap()->end_addr()), offset); 3868 ldr(heap_end, Address(rscratch1, offset)); 3869 } 3870 3871 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 3872 3873 // Get the current top of the heap 3874 { 3875 unsigned long offset; 3876 adrp(rscratch1, heap_top, offset); 3877 // Use add() here after ARDP, rather than lea(). 3878 // lea() does not generate anything if its offset is zero. 3879 // However, relocs expect to find either an ADD or a load/store 3880 // insn after an ADRP. add() always generates an ADD insn, even 3881 // for add(Rn, Rn, 0). 3882 add(rscratch1, rscratch1, offset); 3883 ldaxr(obj, rscratch1); 3884 } 3885 3886 // Adjust it my the size of our new object 3887 if (var_size_in_bytes == noreg) { 3888 lea(end, Address(obj, con_size_in_bytes)); 3889 } else { 3890 lea(end, Address(obj, var_size_in_bytes)); 3891 } 3892 3893 // if end < obj then we wrapped around high memory 3894 cmp(end, obj); 3895 br(Assembler::LO, slow_case); 3896 3897 cmp(end, heap_end); 3898 br(Assembler::HI, slow_case); 3899 3900 // If heap_top hasn't been changed by some other thread, update it. 3901 stlxr(rscratch2, end, rscratch1); 3902 cbnzw(rscratch2, retry); 3903 } 3904 } 3905 3906 void MacroAssembler::verify_tlab() { 3907 #ifdef ASSERT 3908 if (UseTLAB && VerifyOops) { 3909 Label next, ok; 3910 3911 stp(rscratch2, rscratch1, Address(pre(sp, -16))); 3912 3913 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 3914 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 3915 cmp(rscratch2, rscratch1); 3916 br(Assembler::HS, next); 3917 STOP("assert(top >= start)"); 3918 should_not_reach_here(); 3919 3920 bind(next); 3921 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 3922 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 3923 cmp(rscratch2, rscratch1); 3924 br(Assembler::HS, ok); 3925 STOP("assert(top <= end)"); 3926 should_not_reach_here(); 3927 3928 bind(ok); 3929 ldp(rscratch2, rscratch1, Address(post(sp, 16))); 3930 } 3931 #endif 3932 } 3933 3934 // Writes to stack successive pages until offset reached to check for 3935 // stack overflow + shadow pages. This clobbers tmp. 3936 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 3937 assert_different_registers(tmp, size, rscratch1); 3938 mov(tmp, sp); 3939 // Bang stack for total size given plus shadow page size. 3940 // Bang one page at a time because large size can bang beyond yellow and 3941 // red zones. 3942 Label loop; 3943 mov(rscratch1, os::vm_page_size()); 3944 bind(loop); 3945 lea(tmp, Address(tmp, -os::vm_page_size())); 3946 subsw(size, size, rscratch1); 3947 str(size, Address(tmp)); 3948 br(Assembler::GT, loop); 3949 3950 // Bang down shadow pages too. 3951 // At this point, (tmp-0) is the last address touched, so don't 3952 // touch it again. (It was touched as (tmp-pagesize) but then tmp 3953 // was post-decremented.) Skip this address by starting at i=1, and 3954 // touch a few more pages below. N.B. It is important to touch all 3955 // the way down to and including i=StackShadowPages. 3956 for (int i = 0; i < (int)(JavaThread::stack_shadow_zone_size() / os::vm_page_size()) - 1; i++) { 3957 // this could be any sized move but this is can be a debugging crumb 3958 // so the bigger the better. 3959 lea(tmp, Address(tmp, -os::vm_page_size())); 3960 str(size, Address(tmp)); 3961 } 3962 } 3963 3964 3965 address MacroAssembler::read_polling_page(Register r, address page, relocInfo::relocType rtype) { 3966 unsigned long off; 3967 adrp(r, Address(page, rtype), off); 3968 InstructionMark im(this); 3969 code_section()->relocate(inst_mark(), rtype); 3970 ldrw(zr, Address(r, off)); 3971 return inst_mark(); 3972 } 3973 3974 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) { 3975 InstructionMark im(this); 3976 code_section()->relocate(inst_mark(), rtype); 3977 ldrw(zr, Address(r, 0)); 3978 return inst_mark(); 3979 } 3980 3981 void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) { 3982 relocInfo::relocType rtype = dest.rspec().reloc()->type(); 3983 unsigned long low_page = (unsigned long)CodeCache::low_bound() >> 12; 3984 unsigned long high_page = (unsigned long)(CodeCache::high_bound()-1) >> 12; 3985 unsigned long dest_page = (unsigned long)dest.target() >> 12; 3986 long offset_low = dest_page - low_page; 3987 long offset_high = dest_page - high_page; 3988 3989 assert(is_valid_AArch64_address(dest.target()), "bad address"); 3990 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address"); 3991 3992 InstructionMark im(this); 3993 code_section()->relocate(inst_mark(), dest.rspec()); 3994 // 8143067: Ensure that the adrp can reach the dest from anywhere within 3995 // the code cache so that if it is relocated we know it will still reach 3996 if (offset_high >= -(1<<20) && offset_low < (1<<20)) { 3997 _adrp(reg1, dest.target()); 3998 } else { 3999 unsigned long target = (unsigned long)dest.target(); 4000 unsigned long adrp_target 4001 = (target & 0xffffffffUL) | ((unsigned long)pc() & 0xffff00000000UL); 4002 4003 _adrp(reg1, (address)adrp_target); 4004 movk(reg1, target >> 32, 32); 4005 } 4006 byte_offset = (unsigned long)dest.target() & 0xfff; 4007 } 4008 4009 void MacroAssembler::load_byte_map_base(Register reg) { 4010 jbyte *byte_map_base = 4011 ((CardTableModRefBS*)(Universe::heap()->barrier_set()))->byte_map_base; 4012 4013 if (is_valid_AArch64_address((address)byte_map_base)) { 4014 // Strictly speaking the byte_map_base isn't an address at all, 4015 // and it might even be negative. 4016 unsigned long offset; 4017 adrp(reg, ExternalAddress((address)byte_map_base), offset); 4018 assert(offset == 0, "misaligned card table base"); 4019 } else { 4020 mov(reg, (uint64_t)byte_map_base); 4021 } 4022 } 4023 4024 void MacroAssembler::build_frame(int framesize) { 4025 assert(framesize > 0, "framesize must be > 0"); 4026 if (framesize < ((1 << 9) + 2 * wordSize)) { 4027 sub(sp, sp, framesize); 4028 stp(rfp, lr, Address(sp, framesize - 2 * wordSize)); 4029 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize); 4030 } else { 4031 stp(rfp, lr, Address(pre(sp, -2 * wordSize))); 4032 if (PreserveFramePointer) mov(rfp, sp); 4033 if (framesize < ((1 << 12) + 2 * wordSize)) 4034 sub(sp, sp, framesize - 2 * wordSize); 4035 else { 4036 mov(rscratch1, framesize - 2 * wordSize); 4037 sub(sp, sp, rscratch1); 4038 } 4039 } 4040 } 4041 4042 void MacroAssembler::remove_frame(int framesize) { 4043 assert(framesize > 0, "framesize must be > 0"); 4044 if (framesize < ((1 << 9) + 2 * wordSize)) { 4045 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize)); 4046 add(sp, sp, framesize); 4047 } else { 4048 if (framesize < ((1 << 12) + 2 * wordSize)) 4049 add(sp, sp, framesize - 2 * wordSize); 4050 else { 4051 mov(rscratch1, framesize - 2 * wordSize); 4052 add(sp, sp, rscratch1); 4053 } 4054 ldp(rfp, lr, Address(post(sp, 2 * wordSize))); 4055 } 4056 } 4057 4058 4059 // Search for str1 in str2 and return index or -1 4060 void MacroAssembler::string_indexof(Register str2, Register str1, 4061 Register cnt2, Register cnt1, 4062 Register tmp1, Register tmp2, 4063 Register tmp3, Register tmp4, 4064 int icnt1, Register result) { 4065 Label BM, LINEARSEARCH, DONE, NOMATCH, MATCH; 4066 4067 Register ch1 = rscratch1; 4068 Register ch2 = rscratch2; 4069 Register cnt1tmp = tmp1; 4070 Register cnt2tmp = tmp2; 4071 Register cnt1_neg = cnt1; 4072 Register cnt2_neg = cnt2; 4073 Register result_tmp = tmp4; 4074 4075 // Note, inline_string_indexOf() generates checks: 4076 // if (substr.count > string.count) return -1; 4077 // if (substr.count == 0) return 0; 4078 4079 // We have two strings, a source string in str2, cnt2 and a pattern string 4080 // in str1, cnt1. Find the 1st occurence of pattern in source or return -1. 4081 4082 // For larger pattern and source we use a simplified Boyer Moore algorithm. 4083 // With a small pattern and source we use linear scan. 4084 4085 if (icnt1 == -1) { 4086 cmp(cnt1, 256); // Use Linear Scan if cnt1 < 8 || cnt1 >= 256 4087 ccmp(cnt1, 8, 0b0000, LO); // Can't handle skip >= 256 because we use 4088 br(LO, LINEARSEARCH); // a byte array. 4089 cmp(cnt1, cnt2, LSR, 2); // Source must be 4 * pattern for BM 4090 br(HS, LINEARSEARCH); 4091 } 4092 4093 // The Boyer Moore alogorithm is based on the description here:- 4094 // 4095 // http://en.wikipedia.org/wiki/Boyer%E2%80%93Moore_string_search_algorithm 4096 // 4097 // This describes and algorithm with 2 shift rules. The 'Bad Character' rule 4098 // and the 'Good Suffix' rule. 4099 // 4100 // These rules are essentially heuristics for how far we can shift the 4101 // pattern along the search string. 4102 // 4103 // The implementation here uses the 'Bad Character' rule only because of the 4104 // complexity of initialisation for the 'Good Suffix' rule. 4105 // 4106 // This is also known as the Boyer-Moore-Horspool algorithm:- 4107 // 4108 // http://en.wikipedia.org/wiki/Boyer-Moore-Horspool_algorithm 4109 // 4110 // #define ASIZE 128 4111 // 4112 // int bm(unsigned char *x, int m, unsigned char *y, int n) { 4113 // int i, j; 4114 // unsigned c; 4115 // unsigned char bc[ASIZE]; 4116 // 4117 // /* Preprocessing */ 4118 // for (i = 0; i < ASIZE; ++i) 4119 // bc[i] = 0; 4120 // for (i = 0; i < m - 1; ) { 4121 // c = x[i]; 4122 // ++i; 4123 // if (c < ASIZE) bc[c] = i; 4124 // } 4125 // 4126 // /* Searching */ 4127 // j = 0; 4128 // while (j <= n - m) { 4129 // c = y[i+j]; 4130 // if (x[m-1] == c) 4131 // for (i = m - 2; i >= 0 && x[i] == y[i + j]; --i); 4132 // if (i < 0) return j; 4133 // if (c < ASIZE) 4134 // j = j - bc[y[j+m-1]] + m; 4135 // else 4136 // j += 1; // Advance by 1 only if char >= ASIZE 4137 // } 4138 // } 4139 4140 if (icnt1 == -1) { 4141 BIND(BM); 4142 4143 Label ZLOOP, BCLOOP, BCSKIP, BMLOOPSTR2, BMLOOPSTR1, BMSKIP; 4144 Label BMADV, BMMATCH, BMCHECKEND; 4145 4146 Register cnt1end = tmp2; 4147 Register str2end = cnt2; 4148 Register skipch = tmp2; 4149 4150 // Restrict ASIZE to 128 to reduce stack space/initialisation. 4151 // The presence of chars >= ASIZE in the target string does not affect 4152 // performance, but we must be careful not to initialise them in the stack 4153 // array. 4154 // The presence of chars >= ASIZE in the source string may adversely affect 4155 // performance since we can only advance by one when we encounter one. 4156 4157 stp(zr, zr, pre(sp, -128)); 4158 for (int i = 1; i < 8; i++) 4159 stp(zr, zr, Address(sp, i*16)); 4160 4161 mov(cnt1tmp, 0); 4162 sub(cnt1end, cnt1, 1); 4163 BIND(BCLOOP); 4164 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1))); 4165 cmp(ch1, 128); 4166 add(cnt1tmp, cnt1tmp, 1); 4167 br(HS, BCSKIP); 4168 strb(cnt1tmp, Address(sp, ch1)); 4169 BIND(BCSKIP); 4170 cmp(cnt1tmp, cnt1end); 4171 br(LT, BCLOOP); 4172 4173 mov(result_tmp, str2); 4174 4175 sub(cnt2, cnt2, cnt1); 4176 add(str2end, str2, cnt2, LSL, 1); 4177 BIND(BMLOOPSTR2); 4178 sub(cnt1tmp, cnt1, 1); 4179 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1))); 4180 ldrh(skipch, Address(str2, cnt1tmp, Address::lsl(1))); 4181 cmp(ch1, skipch); 4182 br(NE, BMSKIP); 4183 subs(cnt1tmp, cnt1tmp, 1); 4184 br(LT, BMMATCH); 4185 BIND(BMLOOPSTR1); 4186 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1))); 4187 ldrh(ch2, Address(str2, cnt1tmp, Address::lsl(1))); 4188 cmp(ch1, ch2); 4189 br(NE, BMSKIP); 4190 subs(cnt1tmp, cnt1tmp, 1); 4191 br(GE, BMLOOPSTR1); 4192 BIND(BMMATCH); 4193 sub(result_tmp, str2, result_tmp); 4194 lsr(result, result_tmp, 1); 4195 add(sp, sp, 128); 4196 b(DONE); 4197 BIND(BMADV); 4198 add(str2, str2, 2); 4199 b(BMCHECKEND); 4200 BIND(BMSKIP); 4201 cmp(skipch, 128); 4202 br(HS, BMADV); 4203 ldrb(ch2, Address(sp, skipch)); 4204 add(str2, str2, cnt1, LSL, 1); 4205 sub(str2, str2, ch2, LSL, 1); 4206 BIND(BMCHECKEND); 4207 cmp(str2, str2end); 4208 br(LE, BMLOOPSTR2); 4209 add(sp, sp, 128); 4210 b(NOMATCH); 4211 } 4212 4213 BIND(LINEARSEARCH); 4214 { 4215 Label DO1, DO2, DO3; 4216 4217 Register str2tmp = tmp2; 4218 Register first = tmp3; 4219 4220 if (icnt1 == -1) 4221 { 4222 Label DOSHORT, FIRST_LOOP, STR2_NEXT, STR1_LOOP, STR1_NEXT, LAST_WORD; 4223 4224 cmp(cnt1, 4); 4225 br(LT, DOSHORT); 4226 4227 sub(cnt2, cnt2, cnt1); 4228 sub(cnt1, cnt1, 4); 4229 mov(result_tmp, cnt2); 4230 4231 lea(str1, Address(str1, cnt1, Address::uxtw(1))); 4232 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4233 sub(cnt1_neg, zr, cnt1, LSL, 1); 4234 sub(cnt2_neg, zr, cnt2, LSL, 1); 4235 ldr(first, Address(str1, cnt1_neg)); 4236 4237 BIND(FIRST_LOOP); 4238 ldr(ch2, Address(str2, cnt2_neg)); 4239 cmp(first, ch2); 4240 br(EQ, STR1_LOOP); 4241 BIND(STR2_NEXT); 4242 adds(cnt2_neg, cnt2_neg, 2); 4243 br(LE, FIRST_LOOP); 4244 b(NOMATCH); 4245 4246 BIND(STR1_LOOP); 4247 adds(cnt1tmp, cnt1_neg, 8); 4248 add(cnt2tmp, cnt2_neg, 8); 4249 br(GE, LAST_WORD); 4250 4251 BIND(STR1_NEXT); 4252 ldr(ch1, Address(str1, cnt1tmp)); 4253 ldr(ch2, Address(str2, cnt2tmp)); 4254 cmp(ch1, ch2); 4255 br(NE, STR2_NEXT); 4256 adds(cnt1tmp, cnt1tmp, 8); 4257 add(cnt2tmp, cnt2tmp, 8); 4258 br(LT, STR1_NEXT); 4259 4260 BIND(LAST_WORD); 4261 ldr(ch1, Address(str1)); 4262 sub(str2tmp, str2, cnt1_neg); // adjust to corresponding 4263 ldr(ch2, Address(str2tmp, cnt2_neg)); // word in str2 4264 cmp(ch1, ch2); 4265 br(NE, STR2_NEXT); 4266 b(MATCH); 4267 4268 BIND(DOSHORT); 4269 cmp(cnt1, 2); 4270 br(LT, DO1); 4271 br(GT, DO3); 4272 } 4273 4274 if (icnt1 == 4) { 4275 Label CH1_LOOP; 4276 4277 ldr(ch1, str1); 4278 sub(cnt2, cnt2, 4); 4279 mov(result_tmp, cnt2); 4280 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4281 sub(cnt2_neg, zr, cnt2, LSL, 1); 4282 4283 BIND(CH1_LOOP); 4284 ldr(ch2, Address(str2, cnt2_neg)); 4285 cmp(ch1, ch2); 4286 br(EQ, MATCH); 4287 adds(cnt2_neg, cnt2_neg, 2); 4288 br(LE, CH1_LOOP); 4289 b(NOMATCH); 4290 } 4291 4292 if (icnt1 == -1 || icnt1 == 2) { 4293 Label CH1_LOOP; 4294 4295 BIND(DO2); 4296 ldrw(ch1, str1); 4297 sub(cnt2, cnt2, 2); 4298 mov(result_tmp, cnt2); 4299 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4300 sub(cnt2_neg, zr, cnt2, LSL, 1); 4301 4302 BIND(CH1_LOOP); 4303 ldrw(ch2, Address(str2, cnt2_neg)); 4304 cmp(ch1, ch2); 4305 br(EQ, MATCH); 4306 adds(cnt2_neg, cnt2_neg, 2); 4307 br(LE, CH1_LOOP); 4308 b(NOMATCH); 4309 } 4310 4311 if (icnt1 == -1 || icnt1 == 3) { 4312 Label FIRST_LOOP, STR2_NEXT, STR1_LOOP; 4313 4314 BIND(DO3); 4315 ldrw(first, str1); 4316 ldrh(ch1, Address(str1, 4)); 4317 4318 sub(cnt2, cnt2, 3); 4319 mov(result_tmp, cnt2); 4320 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4321 sub(cnt2_neg, zr, cnt2, LSL, 1); 4322 4323 BIND(FIRST_LOOP); 4324 ldrw(ch2, Address(str2, cnt2_neg)); 4325 cmpw(first, ch2); 4326 br(EQ, STR1_LOOP); 4327 BIND(STR2_NEXT); 4328 adds(cnt2_neg, cnt2_neg, 2); 4329 br(LE, FIRST_LOOP); 4330 b(NOMATCH); 4331 4332 BIND(STR1_LOOP); 4333 add(cnt2tmp, cnt2_neg, 4); 4334 ldrh(ch2, Address(str2, cnt2tmp)); 4335 cmp(ch1, ch2); 4336 br(NE, STR2_NEXT); 4337 b(MATCH); 4338 } 4339 4340 if (icnt1 == -1 || icnt1 == 1) { 4341 Label CH1_LOOP, HAS_ZERO; 4342 Label DO1_SHORT, DO1_LOOP; 4343 4344 BIND(DO1); 4345 ldrh(ch1, str1); 4346 cmp(cnt2, 4); 4347 br(LT, DO1_SHORT); 4348 4349 orr(ch1, ch1, ch1, LSL, 16); 4350 orr(ch1, ch1, ch1, LSL, 32); 4351 4352 sub(cnt2, cnt2, 4); 4353 mov(result_tmp, cnt2); 4354 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4355 sub(cnt2_neg, zr, cnt2, LSL, 1); 4356 4357 mov(tmp3, 0x0001000100010001); 4358 BIND(CH1_LOOP); 4359 ldr(ch2, Address(str2, cnt2_neg)); 4360 eor(ch2, ch1, ch2); 4361 sub(tmp1, ch2, tmp3); 4362 orr(tmp2, ch2, 0x7fff7fff7fff7fff); 4363 bics(tmp1, tmp1, tmp2); 4364 br(NE, HAS_ZERO); 4365 adds(cnt2_neg, cnt2_neg, 8); 4366 br(LT, CH1_LOOP); 4367 4368 cmp(cnt2_neg, 8); 4369 mov(cnt2_neg, 0); 4370 br(LT, CH1_LOOP); 4371 b(NOMATCH); 4372 4373 BIND(HAS_ZERO); 4374 rev(tmp1, tmp1); 4375 clz(tmp1, tmp1); 4376 add(cnt2_neg, cnt2_neg, tmp1, LSR, 3); 4377 b(MATCH); 4378 4379 BIND(DO1_SHORT); 4380 mov(result_tmp, cnt2); 4381 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4382 sub(cnt2_neg, zr, cnt2, LSL, 1); 4383 BIND(DO1_LOOP); 4384 ldrh(ch2, Address(str2, cnt2_neg)); 4385 cmpw(ch1, ch2); 4386 br(EQ, MATCH); 4387 adds(cnt2_neg, cnt2_neg, 2); 4388 br(LT, DO1_LOOP); 4389 } 4390 } 4391 BIND(NOMATCH); 4392 mov(result, -1); 4393 b(DONE); 4394 BIND(MATCH); 4395 add(result, result_tmp, cnt2_neg, ASR, 1); 4396 BIND(DONE); 4397 } 4398 4399 // Compare strings. 4400 void MacroAssembler::string_compare(Register str1, Register str2, 4401 Register cnt1, Register cnt2, Register result, 4402 Register tmp1) { 4403 Label LENGTH_DIFF, DONE, SHORT_LOOP, SHORT_STRING, 4404 NEXT_WORD, DIFFERENCE; 4405 4406 BLOCK_COMMENT("string_compare {"); 4407 4408 // Compute the minimum of the string lengths and save the difference. 4409 subsw(tmp1, cnt1, cnt2); 4410 cselw(cnt2, cnt1, cnt2, Assembler::LE); // min 4411 4412 // A very short string 4413 cmpw(cnt2, 4); 4414 br(Assembler::LT, SHORT_STRING); 4415 4416 // Check if the strings start at the same location. 4417 cmp(str1, str2); 4418 br(Assembler::EQ, LENGTH_DIFF); 4419 4420 // Compare longwords 4421 { 4422 subw(cnt2, cnt2, 4); // The last longword is a special case 4423 4424 // Move both string pointers to the last longword of their 4425 // strings, negate the remaining count, and convert it to bytes. 4426 lea(str1, Address(str1, cnt2, Address::uxtw(1))); 4427 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4428 sub(cnt2, zr, cnt2, LSL, 1); 4429 4430 // Loop, loading longwords and comparing them into rscratch2. 4431 bind(NEXT_WORD); 4432 ldr(result, Address(str1, cnt2)); 4433 ldr(cnt1, Address(str2, cnt2)); 4434 adds(cnt2, cnt2, wordSize); 4435 eor(rscratch2, result, cnt1); 4436 cbnz(rscratch2, DIFFERENCE); 4437 br(Assembler::LT, NEXT_WORD); 4438 4439 // Last longword. In the case where length == 4 we compare the 4440 // same longword twice, but that's still faster than another 4441 // conditional branch. 4442 4443 ldr(result, Address(str1)); 4444 ldr(cnt1, Address(str2)); 4445 eor(rscratch2, result, cnt1); 4446 cbz(rscratch2, LENGTH_DIFF); 4447 4448 // Find the first different characters in the longwords and 4449 // compute their difference. 4450 bind(DIFFERENCE); 4451 rev(rscratch2, rscratch2); 4452 clz(rscratch2, rscratch2); 4453 andr(rscratch2, rscratch2, -16); 4454 lsrv(result, result, rscratch2); 4455 uxthw(result, result); 4456 lsrv(cnt1, cnt1, rscratch2); 4457 uxthw(cnt1, cnt1); 4458 subw(result, result, cnt1); 4459 b(DONE); 4460 } 4461 4462 bind(SHORT_STRING); 4463 // Is the minimum length zero? 4464 cbz(cnt2, LENGTH_DIFF); 4465 4466 bind(SHORT_LOOP); 4467 load_unsigned_short(result, Address(post(str1, 2))); 4468 load_unsigned_short(cnt1, Address(post(str2, 2))); 4469 subw(result, result, cnt1); 4470 cbnz(result, DONE); 4471 sub(cnt2, cnt2, 1); 4472 cbnz(cnt2, SHORT_LOOP); 4473 4474 // Strings are equal up to min length. Return the length difference. 4475 bind(LENGTH_DIFF); 4476 mov(result, tmp1); 4477 4478 // That's it 4479 bind(DONE); 4480 4481 BLOCK_COMMENT("} string_compare"); 4482 } 4483 4484 4485 void MacroAssembler::string_equals(Register str1, Register str2, 4486 Register cnt, Register result, 4487 Register tmp1) { 4488 Label SAME_CHARS, DONE, SHORT_LOOP, SHORT_STRING, 4489 NEXT_WORD; 4490 4491 const Register tmp2 = rscratch1; 4492 assert_different_registers(str1, str2, cnt, result, tmp1, tmp2, rscratch2); 4493 4494 BLOCK_COMMENT("string_equals {"); 4495 4496 // Start by assuming that the strings are not equal. 4497 mov(result, zr); 4498 4499 // A very short string 4500 cmpw(cnt, 4); 4501 br(Assembler::LT, SHORT_STRING); 4502 4503 // Check if the strings start at the same location. 4504 cmp(str1, str2); 4505 br(Assembler::EQ, SAME_CHARS); 4506 4507 // Compare longwords 4508 { 4509 subw(cnt, cnt, 4); // The last longword is a special case 4510 4511 // Move both string pointers to the last longword of their 4512 // strings, negate the remaining count, and convert it to bytes. 4513 lea(str1, Address(str1, cnt, Address::uxtw(1))); 4514 lea(str2, Address(str2, cnt, Address::uxtw(1))); 4515 sub(cnt, zr, cnt, LSL, 1); 4516 4517 // Loop, loading longwords and comparing them into rscratch2. 4518 bind(NEXT_WORD); 4519 ldr(tmp1, Address(str1, cnt)); 4520 ldr(tmp2, Address(str2, cnt)); 4521 adds(cnt, cnt, wordSize); 4522 eor(rscratch2, tmp1, tmp2); 4523 cbnz(rscratch2, DONE); 4524 br(Assembler::LT, NEXT_WORD); 4525 4526 // Last longword. In the case where length == 4 we compare the 4527 // same longword twice, but that's still faster than another 4528 // conditional branch. 4529 4530 ldr(tmp1, Address(str1)); 4531 ldr(tmp2, Address(str2)); 4532 eor(rscratch2, tmp1, tmp2); 4533 cbz(rscratch2, SAME_CHARS); 4534 b(DONE); 4535 } 4536 4537 bind(SHORT_STRING); 4538 // Is the length zero? 4539 cbz(cnt, SAME_CHARS); 4540 4541 bind(SHORT_LOOP); 4542 load_unsigned_short(tmp1, Address(post(str1, 2))); 4543 load_unsigned_short(tmp2, Address(post(str2, 2))); 4544 subw(tmp1, tmp1, tmp2); 4545 cbnz(tmp1, DONE); 4546 sub(cnt, cnt, 1); 4547 cbnz(cnt, SHORT_LOOP); 4548 4549 // Strings are equal. 4550 bind(SAME_CHARS); 4551 mov(result, true); 4552 4553 // That's it 4554 bind(DONE); 4555 4556 BLOCK_COMMENT("} string_equals"); 4557 } 4558 4559 4560 void MacroAssembler::byte_arrays_equals(Register ary1, Register ary2, 4561 Register result, Register tmp1) 4562 { 4563 Register cnt1 = rscratch1; 4564 Register cnt2 = rscratch2; 4565 Register tmp2 = rscratch2; 4566 4567 Label SAME, DIFFER, NEXT, TAIL07, TAIL03, TAIL01; 4568 4569 int length_offset = arrayOopDesc::length_offset_in_bytes(); 4570 int base_offset = arrayOopDesc::base_offset_in_bytes(T_BYTE); 4571 4572 BLOCK_COMMENT("byte_arrays_equals {"); 4573 4574 // different until proven equal 4575 mov(result, false); 4576 4577 // same array? 4578 cmp(ary1, ary2); 4579 br(Assembler::EQ, SAME); 4580 4581 // ne if either null 4582 cbz(ary1, DIFFER); 4583 cbz(ary2, DIFFER); 4584 4585 // lengths ne? 4586 ldrw(cnt1, Address(ary1, length_offset)); 4587 ldrw(cnt2, Address(ary2, length_offset)); 4588 cmp(cnt1, cnt2); 4589 br(Assembler::NE, DIFFER); 4590 4591 lea(ary1, Address(ary1, base_offset)); 4592 lea(ary2, Address(ary2, base_offset)); 4593 4594 subs(cnt1, cnt1, 8); 4595 br(LT, TAIL07); 4596 4597 BIND(NEXT); 4598 ldr(tmp1, Address(post(ary1, 8))); 4599 ldr(tmp2, Address(post(ary2, 8))); 4600 subs(cnt1, cnt1, 8); 4601 eor(tmp1, tmp1, tmp2); 4602 cbnz(tmp1, DIFFER); 4603 br(GE, NEXT); 4604 4605 BIND(TAIL07); // 0-7 bytes left, cnt1 = #bytes left - 4 4606 tst(cnt1, 0b100); 4607 br(EQ, TAIL03); 4608 ldrw(tmp1, Address(post(ary1, 4))); 4609 ldrw(tmp2, Address(post(ary2, 4))); 4610 cmp(tmp1, tmp2); 4611 br(NE, DIFFER); 4612 4613 BIND(TAIL03); // 0-3 bytes left, cnt1 = #bytes left - 4 4614 tst(cnt1, 0b10); 4615 br(EQ, TAIL01); 4616 ldrh(tmp1, Address(post(ary1, 2))); 4617 ldrh(tmp2, Address(post(ary2, 2))); 4618 cmp(tmp1, tmp2); 4619 br(NE, DIFFER); 4620 BIND(TAIL01); // 0-1 byte left 4621 tst(cnt1, 0b01); 4622 br(EQ, SAME); 4623 ldrb(tmp1, ary1); 4624 ldrb(tmp2, ary2); 4625 cmp(tmp1, tmp2); 4626 br(NE, DIFFER); 4627 4628 BIND(SAME); 4629 mov(result, true); 4630 BIND(DIFFER); // result already set 4631 4632 BLOCK_COMMENT("} byte_arrays_equals"); 4633 } 4634 4635 // Compare char[] arrays aligned to 4 bytes 4636 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2, 4637 Register result, Register tmp1) 4638 { 4639 Register cnt1 = rscratch1; 4640 Register cnt2 = rscratch2; 4641 Register tmp2 = rscratch2; 4642 4643 Label SAME, DIFFER, NEXT, TAIL03, TAIL01; 4644 4645 int length_offset = arrayOopDesc::length_offset_in_bytes(); 4646 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 4647 4648 BLOCK_COMMENT("char_arrays_equals {"); 4649 4650 // different until proven equal 4651 mov(result, false); 4652 4653 // same array? 4654 cmp(ary1, ary2); 4655 br(Assembler::EQ, SAME); 4656 4657 // ne if either null 4658 cbz(ary1, DIFFER); 4659 cbz(ary2, DIFFER); 4660 4661 // lengths ne? 4662 ldrw(cnt1, Address(ary1, length_offset)); 4663 ldrw(cnt2, Address(ary2, length_offset)); 4664 cmp(cnt1, cnt2); 4665 br(Assembler::NE, DIFFER); 4666 4667 lea(ary1, Address(ary1, base_offset)); 4668 lea(ary2, Address(ary2, base_offset)); 4669 4670 subs(cnt1, cnt1, 4); 4671 br(LT, TAIL03); 4672 4673 BIND(NEXT); 4674 ldr(tmp1, Address(post(ary1, 8))); 4675 ldr(tmp2, Address(post(ary2, 8))); 4676 subs(cnt1, cnt1, 4); 4677 eor(tmp1, tmp1, tmp2); 4678 cbnz(tmp1, DIFFER); 4679 br(GE, NEXT); 4680 4681 BIND(TAIL03); // 0-3 chars left, cnt1 = #chars left - 4 4682 tst(cnt1, 0b10); 4683 br(EQ, TAIL01); 4684 ldrw(tmp1, Address(post(ary1, 4))); 4685 ldrw(tmp2, Address(post(ary2, 4))); 4686 cmp(tmp1, tmp2); 4687 br(NE, DIFFER); 4688 BIND(TAIL01); // 0-1 chars left 4689 tst(cnt1, 0b01); 4690 br(EQ, SAME); 4691 ldrh(tmp1, ary1); 4692 ldrh(tmp2, ary2); 4693 cmp(tmp1, tmp2); 4694 br(NE, DIFFER); 4695 4696 BIND(SAME); 4697 mov(result, true); 4698 BIND(DIFFER); // result already set 4699 4700 BLOCK_COMMENT("} char_arrays_equals"); 4701 } 4702 4703 // encode char[] to byte[] in ISO_8859_1 4704 void MacroAssembler::encode_iso_array(Register src, Register dst, 4705 Register len, Register result, 4706 FloatRegister Vtmp1, FloatRegister Vtmp2, 4707 FloatRegister Vtmp3, FloatRegister Vtmp4) 4708 { 4709 Label DONE, NEXT_32, LOOP_8, NEXT_8, LOOP_1, NEXT_1; 4710 Register tmp1 = rscratch1; 4711 4712 mov(result, len); // Save initial len 4713 4714 #ifndef BUILTIN_SIM 4715 subs(len, len, 32); 4716 br(LT, LOOP_8); 4717 4718 // The following code uses the SIMD 'uqxtn' and 'uqxtn2' instructions 4719 // to convert chars to bytes. These set the 'QC' bit in the FPSR if 4720 // any char could not fit in a byte, so clear the FPSR so we can test it. 4721 clear_fpsr(); 4722 4723 BIND(NEXT_32); 4724 ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src); 4725 uqxtn(Vtmp1, T8B, Vtmp1, T8H); // uqxtn - write bottom half 4726 uqxtn(Vtmp1, T16B, Vtmp2, T8H); // uqxtn2 - write top half 4727 uqxtn(Vtmp2, T8B, Vtmp3, T8H); 4728 uqxtn(Vtmp2, T16B, Vtmp4, T8H); // uqxtn2 4729 get_fpsr(tmp1); 4730 cbnzw(tmp1, LOOP_8); 4731 st1(Vtmp1, Vtmp2, T16B, post(dst, 32)); 4732 subs(len, len, 32); 4733 add(src, src, 64); 4734 br(GE, NEXT_32); 4735 4736 BIND(LOOP_8); 4737 adds(len, len, 32-8); 4738 br(LT, LOOP_1); 4739 clear_fpsr(); // QC may be set from loop above, clear again 4740 BIND(NEXT_8); 4741 ld1(Vtmp1, T8H, src); 4742 uqxtn(Vtmp1, T8B, Vtmp1, T8H); 4743 get_fpsr(tmp1); 4744 cbnzw(tmp1, LOOP_1); 4745 st1(Vtmp1, T8B, post(dst, 8)); 4746 subs(len, len, 8); 4747 add(src, src, 16); 4748 br(GE, NEXT_8); 4749 4750 BIND(LOOP_1); 4751 adds(len, len, 8); 4752 br(LE, DONE); 4753 #else 4754 cbz(len, DONE); 4755 #endif 4756 BIND(NEXT_1); 4757 ldrh(tmp1, Address(post(src, 2))); 4758 tst(tmp1, 0xff00); 4759 br(NE, DONE); 4760 strb(tmp1, Address(post(dst, 1))); 4761 subs(len, len, 1); 4762 br(GT, NEXT_1); 4763 4764 BIND(DONE); 4765 sub(result, result, len); // Return index where we stopped 4766 } 4767 4768 // get_thread() can be called anywhere inside generated code so we 4769 // need to save whatever non-callee save context might get clobbered 4770 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed, 4771 // the call setup code. 4772 // 4773 // aarch64_get_thread_helper() clobbers only r0, r1, and flags. 4774 // 4775 void MacroAssembler::get_thread(Register dst) { 4776 RegSet saved_regs = RegSet::range(r0, r1) + lr - dst; 4777 push(saved_regs, sp); 4778 4779 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)); 4780 blrt(lr, 1, 0, 1); 4781 if (dst != c_rarg0) { 4782 mov(dst, c_rarg0); 4783 } 4784 4785 pop(saved_regs, sp); 4786 }