1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include <sys/types.h>
27
28 #include "precompiled.hpp"
29 #include "asm/assembler.hpp"
30 #include "asm/assembler.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32
33 #include "compiler/disassembler.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "nativeInst_aarch64.hpp"
36 #include "oops/klass.inline.hpp"
37 #include "oops/oop.inline.hpp"
38 #include "opto/compile.hpp"
39 #include "opto/node.hpp"
40 #include "runtime/biasedLocking.hpp"
41 #include "runtime/icache.hpp"
42 #include "runtime/interfaceSupport.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/thread.hpp"
45
46 #if INCLUDE_ALL_GCS
47 #include "gc/g1/g1CollectedHeap.inline.hpp"
48 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
49 #include "gc/g1/heapRegion.hpp"
50 #endif
51
52 #ifdef PRODUCT
53 #define BLOCK_COMMENT(str) /* nothing */
54 #define STOP(error) stop(error)
55 #else
56 #define BLOCK_COMMENT(str) block_comment(str)
57 #define STOP(error) block_comment(error); stop(error)
58 #endif
59
60 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
61
62 // Patch any kind of instruction; there may be several instructions.
63 // Return the total length (in bytes) of the instructions.
64 int MacroAssembler::pd_patch_instruction_size(address branch, address target) {
65 int instructions = 1;
66 assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant");
67 long offset = (target - branch) >> 2;
68 unsigned insn = *(unsigned*)branch;
69 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
70 // Load register (literal)
71 Instruction_aarch64::spatch(branch, 23, 5, offset);
72 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
73 // Unconditional branch (immediate)
74 Instruction_aarch64::spatch(branch, 25, 0, offset);
75 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
76 // Conditional branch (immediate)
77 Instruction_aarch64::spatch(branch, 23, 5, offset);
78 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
79 // Compare & branch (immediate)
80 Instruction_aarch64::spatch(branch, 23, 5, offset);
81 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
82 // Test & branch (immediate)
83 Instruction_aarch64::spatch(branch, 18, 5, offset);
84 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
85 // PC-rel. addressing
86 offset = target-branch;
87 int shift = Instruction_aarch64::extract(insn, 31, 31);
88 if (shift) {
89 u_int64_t dest = (u_int64_t)target;
90 uint64_t pc_page = (uint64_t)branch >> 12;
91 uint64_t adr_page = (uint64_t)target >> 12;
92 unsigned offset_lo = dest & 0xfff;
93 offset = adr_page - pc_page;
94
95 // We handle 4 types of PC relative addressing
96 // 1 - adrp Rx, target_page
97 // ldr/str Ry, [Rx, #offset_in_page]
98 // 2 - adrp Rx, target_page
99 // add Ry, Rx, #offset_in_page
100 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0)
101 // movk Rx, #imm16<<32
102 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0)
103 // In the first 3 cases we must check that Rx is the same in the adrp and the
104 // subsequent ldr/str, add or movk instruction. Otherwise we could accidentally end
105 // up treating a type 4 relocation as a type 1, 2 or 3 just because it happened
106 // to be followed by a random unrelated ldr/str, add or movk instruction.
107 //
108 unsigned insn2 = ((unsigned*)branch)[1];
109 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
110 Instruction_aarch64::extract(insn, 4, 0) ==
111 Instruction_aarch64::extract(insn2, 9, 5)) {
112 // Load/store register (unsigned immediate)
113 unsigned size = Instruction_aarch64::extract(insn2, 31, 30);
114 Instruction_aarch64::patch(branch + sizeof (unsigned),
115 21, 10, offset_lo >> size);
116 guarantee(((dest >> size) << size) == dest, "misaligned target");
117 instructions = 2;
118 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
119 Instruction_aarch64::extract(insn, 4, 0) ==
120 Instruction_aarch64::extract(insn2, 4, 0)) {
121 // add (immediate)
122 Instruction_aarch64::patch(branch + sizeof (unsigned),
123 21, 10, offset_lo);
124 instructions = 2;
125 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
126 Instruction_aarch64::extract(insn, 4, 0) ==
127 Instruction_aarch64::extract(insn2, 4, 0)) {
128 // movk #imm16<<32
129 Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32);
130 long dest = ((long)target & 0xffffffffL) | ((long)branch & 0xffff00000000L);
131 long pc_page = (long)branch >> 12;
132 long adr_page = (long)dest >> 12;
133 offset = adr_page - pc_page;
134 instructions = 2;
135 }
136 }
137 int offset_lo = offset & 3;
138 offset >>= 2;
139 Instruction_aarch64::spatch(branch, 23, 5, offset);
140 Instruction_aarch64::patch(branch, 30, 29, offset_lo);
141 } else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) {
142 u_int64_t dest = (u_int64_t)target;
143 // Move wide constant
144 assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch");
145 assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch");
146 Instruction_aarch64::patch(branch, 20, 5, dest & 0xffff);
147 Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff);
148 Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff);
149 assert(target_addr_for_insn(branch) == target, "should be");
150 instructions = 3;
151 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
152 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
153 // nothing to do
154 assert(target == 0, "did not expect to relocate target for polling page load");
155 } else {
156 ShouldNotReachHere();
157 }
158 return instructions * NativeInstruction::instruction_size;
159 }
160
161 int MacroAssembler::patch_oop(address insn_addr, address o) {
162 int instructions;
163 unsigned insn = *(unsigned*)insn_addr;
164 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
165
166 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
167 // narrow OOPs by setting the upper 16 bits in the first
168 // instruction.
169 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
170 // Move narrow OOP
171 narrowOop n = oopDesc::encode_heap_oop((oop)o);
172 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
173 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
174 instructions = 2;
175 } else {
176 // Move wide OOP
177 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
178 uintptr_t dest = (uintptr_t)o;
179 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
180 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
181 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
182 instructions = 3;
183 }
184 return instructions * NativeInstruction::instruction_size;
185 }
186
187 address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) {
188 long offset = 0;
189 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) {
190 // Load register (literal)
191 offset = Instruction_aarch64::sextract(insn, 23, 5);
192 return address(((uint64_t)insn_addr + (offset << 2)));
193 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
194 // Unconditional branch (immediate)
195 offset = Instruction_aarch64::sextract(insn, 25, 0);
196 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
197 // Conditional branch (immediate)
198 offset = Instruction_aarch64::sextract(insn, 23, 5);
199 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
200 // Compare & branch (immediate)
201 offset = Instruction_aarch64::sextract(insn, 23, 5);
202 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
203 // Test & branch (immediate)
204 offset = Instruction_aarch64::sextract(insn, 18, 5);
205 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
206 // PC-rel. addressing
207 offset = Instruction_aarch64::extract(insn, 30, 29);
208 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
209 int shift = Instruction_aarch64::extract(insn, 31, 31) ? 12 : 0;
210 if (shift) {
211 offset <<= shift;
212 uint64_t target_page = ((uint64_t)insn_addr) + offset;
213 target_page &= ((uint64_t)-1) << shift;
214 // Return the target address for the following sequences
215 // 1 - adrp Rx, target_page
216 // ldr/str Ry, [Rx, #offset_in_page]
217 // 2 - adrp Rx, target_page
218 // add Ry, Rx, #offset_in_page
219 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0)
220 // movk Rx, #imm12<<32
221 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0)
222 //
223 // In the first two cases we check that the register is the same and
224 // return the target_page + the offset within the page.
225 // Otherwise we assume it is a page aligned relocation and return
226 // the target page only.
227 //
228 unsigned insn2 = ((unsigned*)insn_addr)[1];
229 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
230 Instruction_aarch64::extract(insn, 4, 0) ==
231 Instruction_aarch64::extract(insn2, 9, 5)) {
232 // Load/store register (unsigned immediate)
233 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
234 unsigned int size = Instruction_aarch64::extract(insn2, 31, 30);
235 return address(target_page + (byte_offset << size));
236 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
237 Instruction_aarch64::extract(insn, 4, 0) ==
238 Instruction_aarch64::extract(insn2, 4, 0)) {
239 // add (immediate)
240 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
241 return address(target_page + byte_offset);
242 } else {
243 if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
244 Instruction_aarch64::extract(insn, 4, 0) ==
245 Instruction_aarch64::extract(insn2, 4, 0)) {
246 target_page = (target_page & 0xffffffff) |
247 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
248 }
249 return (address)target_page;
250 }
251 } else {
252 ShouldNotReachHere();
253 }
254 } else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) {
255 u_int32_t *insns = (u_int32_t *)insn_addr;
256 // Move wide constant: movz, movk, movk. See movptr().
257 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
258 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
259 return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5))
260 + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
261 + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
262 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
263 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
264 return 0;
265 } else {
266 ShouldNotReachHere();
267 }
268 return address(((uint64_t)insn_addr + (offset << 2)));
269 }
270
271 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
272 dsb(Assembler::SY);
273 }
274
275
276 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
277 bool clear_pc) {
278 // we must set sp to zero to clear frame
279 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
280 // must clear fp, so that compiled frames are not confused; it is
281 // possible that we need it only for debugging
282 if (clear_fp) {
283 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
284 }
285
286 if (clear_pc) {
287 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
288 }
289 }
290
291 // Calls to C land
292 //
293 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
294 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
295 // has to be reset to 0. This is required to allow proper stack traversal.
296 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
297 Register last_java_fp,
298 Register last_java_pc,
299 Register scratch) {
300
301 if (last_java_pc->is_valid()) {
302 str(last_java_pc, Address(rthread,
303 JavaThread::frame_anchor_offset()
304 + JavaFrameAnchor::last_Java_pc_offset()));
305 }
306
307 // determine last_java_sp register
308 if (last_java_sp == sp) {
309 mov(scratch, sp);
310 last_java_sp = scratch;
311 } else if (!last_java_sp->is_valid()) {
312 last_java_sp = esp;
313 }
314
315 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
316
317 // last_java_fp is optional
318 if (last_java_fp->is_valid()) {
319 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
320 }
321 }
322
323 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
324 Register last_java_fp,
325 address last_java_pc,
326 Register scratch) {
327 if (last_java_pc != NULL) {
328 adr(scratch, last_java_pc);
329 } else {
330 // FIXME: This is almost never correct. We should delete all
331 // cases of set_last_Java_frame with last_java_pc=NULL and use the
332 // correct return address instead.
333 adr(scratch, pc());
334 }
335
336 str(scratch, Address(rthread,
337 JavaThread::frame_anchor_offset()
338 + JavaFrameAnchor::last_Java_pc_offset()));
339
340 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
341 }
342
343 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
344 Register last_java_fp,
345 Label &L,
346 Register scratch) {
347 if (L.is_bound()) {
348 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
349 } else {
350 InstructionMark im(this);
351 L.add_patch_at(code(), locator());
352 set_last_Java_frame(last_java_sp, last_java_fp, (address)NULL, scratch);
353 }
354 }
355
356 void MacroAssembler::far_call(Address entry, CodeBuffer *cbuf, Register tmp) {
357 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
358 assert(CodeCache::find_blob(entry.target()) != NULL,
359 "destination of far call not found in code cache");
360 if (far_branches()) {
361 unsigned long offset;
362 // We can use ADRP here because we know that the total size of
363 // the code cache cannot exceed 2Gb.
364 adrp(tmp, entry, offset);
365 add(tmp, tmp, offset);
366 if (cbuf) cbuf->set_insts_mark();
367 blr(tmp);
368 } else {
369 if (cbuf) cbuf->set_insts_mark();
370 bl(entry);
371 }
372 }
373
374 void MacroAssembler::far_jump(Address entry, CodeBuffer *cbuf, Register tmp) {
375 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
376 assert(CodeCache::find_blob(entry.target()) != NULL,
377 "destination of far call not found in code cache");
378 if (far_branches()) {
379 unsigned long offset;
380 // We can use ADRP here because we know that the total size of
381 // the code cache cannot exceed 2Gb.
382 adrp(tmp, entry, offset);
383 add(tmp, tmp, offset);
384 if (cbuf) cbuf->set_insts_mark();
385 br(tmp);
386 } else {
387 if (cbuf) cbuf->set_insts_mark();
388 b(entry);
389 }
390 }
391
392 int MacroAssembler::biased_locking_enter(Register lock_reg,
393 Register obj_reg,
394 Register swap_reg,
395 Register tmp_reg,
396 bool swap_reg_contains_mark,
397 Label& done,
398 Label* slow_case,
399 BiasedLockingCounters* counters) {
400 assert(UseBiasedLocking, "why call this otherwise?");
401 assert_different_registers(lock_reg, obj_reg, swap_reg);
402
403 if (PrintBiasedLockingStatistics && counters == NULL)
404 counters = BiasedLocking::counters();
405
406 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1, rscratch2, noreg);
407 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
408 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
409 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
410 Address saved_mark_addr(lock_reg, 0);
411
412 // Biased locking
413 // See whether the lock is currently biased toward our thread and
414 // whether the epoch is still valid
415 // Note that the runtime guarantees sufficient alignment of JavaThread
416 // pointers to allow age to be placed into low bits
417 // First check to see whether biasing is even enabled for this object
418 Label cas_label;
419 int null_check_offset = -1;
420 if (!swap_reg_contains_mark) {
421 null_check_offset = offset();
422 ldr(swap_reg, mark_addr);
423 }
424 andr(tmp_reg, swap_reg, markOopDesc::biased_lock_mask_in_place);
425 cmp(tmp_reg, markOopDesc::biased_lock_pattern);
426 br(Assembler::NE, cas_label);
427 // The bias pattern is present in the object's header. Need to check
428 // whether the bias owner and the epoch are both still current.
429 load_prototype_header(tmp_reg, obj_reg);
430 orr(tmp_reg, tmp_reg, rthread);
431 eor(tmp_reg, swap_reg, tmp_reg);
432 andr(tmp_reg, tmp_reg, ~((int) markOopDesc::age_mask_in_place));
433 if (counters != NULL) {
434 Label around;
435 cbnz(tmp_reg, around);
436 atomic_incw(Address((address)counters->biased_lock_entry_count_addr()), tmp_reg, rscratch1, rscratch2);
437 b(done);
438 bind(around);
439 } else {
440 cbz(tmp_reg, done);
441 }
442
443 Label try_revoke_bias;
444 Label try_rebias;
445
446 // At this point we know that the header has the bias pattern and
447 // that we are not the bias owner in the current epoch. We need to
448 // figure out more details about the state of the header in order to
449 // know what operations can be legally performed on the object's
450 // header.
451
452 // If the low three bits in the xor result aren't clear, that means
453 // the prototype header is no longer biased and we have to revoke
454 // the bias on this object.
455 andr(rscratch1, tmp_reg, markOopDesc::biased_lock_mask_in_place);
456 cbnz(rscratch1, try_revoke_bias);
457
458 // Biasing is still enabled for this data type. See whether the
459 // epoch of the current bias is still valid, meaning that the epoch
460 // bits of the mark word are equal to the epoch bits of the
461 // prototype header. (Note that the prototype header's epoch bits
462 // only change at a safepoint.) If not, attempt to rebias the object
463 // toward the current thread. Note that we must be absolutely sure
464 // that the current epoch is invalid in order to do this because
465 // otherwise the manipulations it performs on the mark word are
466 // illegal.
467 andr(rscratch1, tmp_reg, markOopDesc::epoch_mask_in_place);
468 cbnz(rscratch1, try_rebias);
469
470 // The epoch of the current bias is still valid but we know nothing
471 // about the owner; it might be set or it might be clear. Try to
472 // acquire the bias of the object using an atomic operation. If this
473 // fails we will go in to the runtime to revoke the object's bias.
474 // Note that we first construct the presumed unbiased header so we
475 // don't accidentally blow away another thread's valid bias.
476 {
477 Label here;
478 mov(rscratch1, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
479 andr(swap_reg, swap_reg, rscratch1);
480 orr(tmp_reg, swap_reg, rthread);
481 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case);
482 // If the biasing toward our thread failed, this means that
483 // another thread succeeded in biasing it toward itself and we
484 // need to revoke that bias. The revocation will occur in the
485 // interpreter runtime in the slow case.
486 bind(here);
487 if (counters != NULL) {
488 atomic_incw(Address((address)counters->anonymously_biased_lock_entry_count_addr()),
489 tmp_reg, rscratch1, rscratch2);
490 }
491 }
492 b(done);
493
494 bind(try_rebias);
495 // At this point we know the epoch has expired, meaning that the
496 // current "bias owner", if any, is actually invalid. Under these
497 // circumstances _only_, we are allowed to use the current header's
498 // value as the comparison value when doing the cas to acquire the
499 // bias in the current epoch. In other words, we allow transfer of
500 // the bias from one thread to another directly in this situation.
501 //
502 // FIXME: due to a lack of registers we currently blow away the age
503 // bits in this situation. Should attempt to preserve them.
504 {
505 Label here;
506 load_prototype_header(tmp_reg, obj_reg);
507 orr(tmp_reg, rthread, tmp_reg);
508 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case);
509 // If the biasing toward our thread failed, then another thread
510 // succeeded in biasing it toward itself and we need to revoke that
511 // bias. The revocation will occur in the runtime in the slow case.
512 bind(here);
513 if (counters != NULL) {
514 atomic_incw(Address((address)counters->rebiased_lock_entry_count_addr()),
515 tmp_reg, rscratch1, rscratch2);
516 }
517 }
518 b(done);
519
520 bind(try_revoke_bias);
521 // The prototype mark in the klass doesn't have the bias bit set any
522 // more, indicating that objects of this data type are not supposed
523 // to be biased any more. We are going to try to reset the mark of
524 // this object to the prototype value and fall through to the
525 // CAS-based locking scheme. Note that if our CAS fails, it means
526 // that another thread raced us for the privilege of revoking the
527 // bias of this particular object, so it's okay to continue in the
528 // normal locking code.
529 //
530 // FIXME: due to a lack of registers we currently blow away the age
531 // bits in this situation. Should attempt to preserve them.
532 {
533 Label here, nope;
534 load_prototype_header(tmp_reg, obj_reg);
535 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, &nope);
536 bind(here);
537
538 // Fall through to the normal CAS-based lock, because no matter what
539 // the result of the above CAS, some thread must have succeeded in
540 // removing the bias bit from the object's header.
541 if (counters != NULL) {
542 atomic_incw(Address((address)counters->revoked_lock_entry_count_addr()), tmp_reg,
543 rscratch1, rscratch2);
544 }
545 bind(nope);
546 }
547
548 bind(cas_label);
549
550 return null_check_offset;
551 }
552
553 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
554 assert(UseBiasedLocking, "why call this otherwise?");
555
556 // Check for biased locking unlock case, which is a no-op
557 // Note: we do not have to check the thread ID for two reasons.
558 // First, the interpreter checks for IllegalMonitorStateException at
559 // a higher level. Second, if the bias was revoked while we held the
560 // lock, the object could not be rebiased toward another thread, so
561 // the bias bit would be clear.
562 ldr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
563 andr(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
564 cmp(temp_reg, markOopDesc::biased_lock_pattern);
565 br(Assembler::EQ, done);
566 }
567
568
569 // added to make this compile
570
571 REGISTER_DEFINITION(Register, noreg);
572
573 static void pass_arg0(MacroAssembler* masm, Register arg) {
574 if (c_rarg0 != arg ) {
575 masm->mov(c_rarg0, arg);
576 }
577 }
578
579 static void pass_arg1(MacroAssembler* masm, Register arg) {
580 if (c_rarg1 != arg ) {
581 masm->mov(c_rarg1, arg);
582 }
583 }
584
585 static void pass_arg2(MacroAssembler* masm, Register arg) {
586 if (c_rarg2 != arg ) {
587 masm->mov(c_rarg2, arg);
588 }
589 }
590
591 static void pass_arg3(MacroAssembler* masm, Register arg) {
592 if (c_rarg3 != arg ) {
593 masm->mov(c_rarg3, arg);
594 }
595 }
596
597 void MacroAssembler::call_VM_base(Register oop_result,
598 Register java_thread,
599 Register last_java_sp,
600 address entry_point,
601 int number_of_arguments,
602 bool check_exceptions) {
603 // determine java_thread register
604 if (!java_thread->is_valid()) {
605 java_thread = rthread;
606 }
607
608 // determine last_java_sp register
609 if (!last_java_sp->is_valid()) {
610 last_java_sp = esp;
611 }
612
613 // debugging support
614 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
615 assert(java_thread == rthread, "unexpected register");
616 #ifdef ASSERT
617 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
618 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
619 #endif // ASSERT
620
621 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
622 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
623
624 // push java thread (becomes first argument of C function)
625
626 mov(c_rarg0, java_thread);
627
628 // set last Java frame before call
629 assert(last_java_sp != rfp, "can't use rfp");
630
631 Label l;
632 set_last_Java_frame(last_java_sp, rfp, l, rscratch1);
633
634 // do the call, remove parameters
635 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
636
637 // reset last Java frame
638 // Only interpreter should have to clear fp
639 reset_last_Java_frame(true, true);
640
641 // C++ interp handles this in the interpreter
642 check_and_handle_popframe(java_thread);
643 check_and_handle_earlyret(java_thread);
644
645 if (check_exceptions) {
646 // check for pending exceptions (java_thread is set upon return)
647 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
648 Label ok;
649 cbz(rscratch1, ok);
650 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
651 br(rscratch1);
652 bind(ok);
653 }
654
655 // get oop result if there is one and reset the value in the thread
656 if (oop_result->is_valid()) {
657 get_vm_result(oop_result, java_thread);
658 }
659 }
660
661 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
662 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
663 }
664
665 // Maybe emit a call via a trampoline. If the code cache is small
666 // trampolines won't be emitted.
667
668 address MacroAssembler::trampoline_call(Address entry, CodeBuffer *cbuf) {
669 assert(entry.rspec().type() == relocInfo::runtime_call_type
670 || entry.rspec().type() == relocInfo::opt_virtual_call_type
671 || entry.rspec().type() == relocInfo::static_call_type
672 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
673
674 unsigned int start_offset = offset();
675 if (far_branches() && !Compile::current()->in_scratch_emit_size()) {
676 address stub = emit_trampoline_stub(start_offset, entry.target());
677 if (stub == NULL) {
678 return NULL; // CodeCache is full
679 }
680 }
681
682 if (cbuf) cbuf->set_insts_mark();
683 relocate(entry.rspec());
684 if (!far_branches()) {
685 bl(entry.target());
686 } else {
687 bl(pc());
688 }
689 // just need to return a non-null address
690 return pc();
691 }
692
693
694 // Emit a trampoline stub for a call to a target which is too far away.
695 //
696 // code sequences:
697 //
698 // call-site:
699 // branch-and-link to <destination> or <trampoline stub>
700 //
701 // Related trampoline stub for this call site in the stub section:
702 // load the call target from the constant pool
703 // branch (LR still points to the call site above)
704
705 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
706 address dest) {
707 address stub = start_a_stub(Compile::MAX_stubs_size/2);
708 if (stub == NULL) {
709 return NULL; // CodeBuffer::expand failed
710 }
711
712 // Create a trampoline stub relocation which relates this trampoline stub
713 // with the call instruction at insts_call_instruction_offset in the
714 // instructions code-section.
715 align(wordSize);
716 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
717 + insts_call_instruction_offset));
718 const int stub_start_offset = offset();
719
720 // Now, create the trampoline stub's code:
721 // - load the call
722 // - call
723 Label target;
724 ldr(rscratch1, target);
725 br(rscratch1);
726 bind(target);
727 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
728 "should be");
729 emit_int64((int64_t)dest);
730
731 const address stub_start_addr = addr_at(stub_start_offset);
732
733 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
734
735 end_a_stub();
736 return stub;
737 }
738
739 address MacroAssembler::ic_call(address entry, jint method_index) {
740 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
741 // address const_ptr = long_constant((jlong)Universe::non_oop_word());
742 // unsigned long offset;
743 // ldr_constant(rscratch2, const_ptr);
744 movptr(rscratch2, (uintptr_t)Universe::non_oop_word());
745 return trampoline_call(Address(entry, rh));
746 }
747
748 // Implementation of call_VM versions
749
750 void MacroAssembler::call_VM(Register oop_result,
751 address entry_point,
752 bool check_exceptions) {
753 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
754 }
755
756 void MacroAssembler::call_VM(Register oop_result,
757 address entry_point,
758 Register arg_1,
759 bool check_exceptions) {
760 pass_arg1(this, arg_1);
761 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
762 }
763
764 void MacroAssembler::call_VM(Register oop_result,
765 address entry_point,
766 Register arg_1,
767 Register arg_2,
768 bool check_exceptions) {
769 assert(arg_1 != c_rarg2, "smashed arg");
770 pass_arg2(this, arg_2);
771 pass_arg1(this, arg_1);
772 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
773 }
774
775 void MacroAssembler::call_VM(Register oop_result,
776 address entry_point,
777 Register arg_1,
778 Register arg_2,
779 Register arg_3,
780 bool check_exceptions) {
781 assert(arg_1 != c_rarg3, "smashed arg");
782 assert(arg_2 != c_rarg3, "smashed arg");
783 pass_arg3(this, arg_3);
784
785 assert(arg_1 != c_rarg2, "smashed arg");
786 pass_arg2(this, arg_2);
787
788 pass_arg1(this, arg_1);
789 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
790 }
791
792 void MacroAssembler::call_VM(Register oop_result,
793 Register last_java_sp,
794 address entry_point,
795 int number_of_arguments,
796 bool check_exceptions) {
797 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
798 }
799
800 void MacroAssembler::call_VM(Register oop_result,
801 Register last_java_sp,
802 address entry_point,
803 Register arg_1,
804 bool check_exceptions) {
805 pass_arg1(this, arg_1);
806 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
807 }
808
809 void MacroAssembler::call_VM(Register oop_result,
810 Register last_java_sp,
811 address entry_point,
812 Register arg_1,
813 Register arg_2,
814 bool check_exceptions) {
815
816 assert(arg_1 != c_rarg2, "smashed arg");
817 pass_arg2(this, arg_2);
818 pass_arg1(this, arg_1);
819 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
820 }
821
822 void MacroAssembler::call_VM(Register oop_result,
823 Register last_java_sp,
824 address entry_point,
825 Register arg_1,
826 Register arg_2,
827 Register arg_3,
828 bool check_exceptions) {
829 assert(arg_1 != c_rarg3, "smashed arg");
830 assert(arg_2 != c_rarg3, "smashed arg");
831 pass_arg3(this, arg_3);
832 assert(arg_1 != c_rarg2, "smashed arg");
833 pass_arg2(this, arg_2);
834 pass_arg1(this, arg_1);
835 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
836 }
837
838
839 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
840 ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
841 str(zr, Address(java_thread, JavaThread::vm_result_offset()));
842 verify_oop(oop_result, "broken oop in call_VM_base");
843 }
844
845 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
846 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
847 str(zr, Address(java_thread, JavaThread::vm_result_2_offset()));
848 }
849
850 void MacroAssembler::align(int modulus) {
851 while (offset() % modulus != 0) nop();
852 }
853
854 // these are no-ops overridden by InterpreterMacroAssembler
855
856 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
857
858 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
859
860
861 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
862 Register tmp,
863 int offset) {
864 intptr_t value = *delayed_value_addr;
865 if (value != 0)
866 return RegisterOrConstant(value + offset);
867
868 // load indirectly to solve generation ordering problem
869 ldr(tmp, ExternalAddress((address) delayed_value_addr));
870
871 if (offset != 0)
872 add(tmp, tmp, offset);
873
874 return RegisterOrConstant(tmp);
875 }
876
877
878 void MacroAssembler:: notify(int type) {
879 if (type == bytecode_start) {
880 // set_last_Java_frame(esp, rfp, (address)NULL);
881 Assembler:: notify(type);
882 // reset_last_Java_frame(true, false);
883 }
884 else
885 Assembler:: notify(type);
886 }
887
888 // Look up the method for a megamorphic invokeinterface call.
889 // The target method is determined by <intf_klass, itable_index>.
890 // The receiver klass is in recv_klass.
891 // On success, the result will be in method_result, and execution falls through.
892 // On failure, execution transfers to the given label.
893 void MacroAssembler::lookup_interface_method(Register recv_klass,
894 Register intf_klass,
895 RegisterOrConstant itable_index,
896 Register method_result,
897 Register scan_temp,
898 Label& L_no_such_interface) {
899 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
900 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
901 "caller must use same register for non-constant itable index as for method");
902
903 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
904 int vtable_base = in_bytes(Klass::vtable_start_offset());
905 int itentry_off = itableMethodEntry::method_offset_in_bytes();
906 int scan_step = itableOffsetEntry::size() * wordSize;
907 int vte_size = vtableEntry::size_in_bytes();
908 assert(vte_size == wordSize, "else adjust times_vte_scale");
909
910 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
911
912 // %%% Could store the aligned, prescaled offset in the klassoop.
913 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
914 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
915 add(scan_temp, scan_temp, vtable_base);
916
917 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
918 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
919 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
920 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
921 if (itentry_off)
922 add(recv_klass, recv_klass, itentry_off);
923
924 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
925 // if (scan->interface() == intf) {
926 // result = (klass + scan->offset() + itable_index);
927 // }
928 // }
929 Label search, found_method;
930
931 for (int peel = 1; peel >= 0; peel--) {
932 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
933 cmp(intf_klass, method_result);
934
935 if (peel) {
936 br(Assembler::EQ, found_method);
937 } else {
938 br(Assembler::NE, search);
939 // (invert the test to fall through to found_method...)
940 }
941
942 if (!peel) break;
943
944 bind(search);
945
946 // Check that the previous entry is non-null. A null entry means that
947 // the receiver class doesn't implement the interface, and wasn't the
948 // same as when the caller was compiled.
949 cbz(method_result, L_no_such_interface);
950 add(scan_temp, scan_temp, scan_step);
951 }
952
953 bind(found_method);
954
955 // Got a hit.
956 ldr(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
957 ldr(method_result, Address(recv_klass, scan_temp));
958 }
959
960 // virtual method calling
961 void MacroAssembler::lookup_virtual_method(Register recv_klass,
962 RegisterOrConstant vtable_index,
963 Register method_result) {
964 const int base = in_bytes(Klass::vtable_start_offset());
965 assert(vtableEntry::size() * wordSize == 8,
966 "adjust the scaling in the code below");
967 int vtable_offset_in_bytes = base + vtableEntry::method_offset_in_bytes();
968
969 if (vtable_index.is_register()) {
970 lea(method_result, Address(recv_klass,
971 vtable_index.as_register(),
972 Address::lsl(LogBytesPerWord)));
973 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
974 } else {
975 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
976 ldr(method_result, Address(recv_klass, vtable_offset_in_bytes));
977 }
978 }
979
980 void MacroAssembler::check_klass_subtype(Register sub_klass,
981 Register super_klass,
982 Register temp_reg,
983 Label& L_success) {
984 Label L_failure;
985 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
986 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
987 bind(L_failure);
988 }
989
990
991 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
992 Register super_klass,
993 Register temp_reg,
994 Label* L_success,
995 Label* L_failure,
996 Label* L_slow_path,
997 RegisterOrConstant super_check_offset) {
998 assert_different_registers(sub_klass, super_klass, temp_reg);
999 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
1000 if (super_check_offset.is_register()) {
1001 assert_different_registers(sub_klass, super_klass,
1002 super_check_offset.as_register());
1003 } else if (must_load_sco) {
1004 assert(temp_reg != noreg, "supply either a temp or a register offset");
1005 }
1006
1007 Label L_fallthrough;
1008 int label_nulls = 0;
1009 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
1010 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
1011 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
1012 assert(label_nulls <= 1, "at most one NULL in the batch");
1013
1014 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1015 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1016 Address super_check_offset_addr(super_klass, sco_offset);
1017
1018 // Hacked jmp, which may only be used just before L_fallthrough.
1019 #define final_jmp(label) \
1020 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1021 else b(label) /*omit semi*/
1022
1023 // If the pointers are equal, we are done (e.g., String[] elements).
1024 // This self-check enables sharing of secondary supertype arrays among
1025 // non-primary types such as array-of-interface. Otherwise, each such
1026 // type would need its own customized SSA.
1027 // We move this check to the front of the fast path because many
1028 // type checks are in fact trivially successful in this manner,
1029 // so we get a nicely predicted branch right at the start of the check.
1030 cmp(sub_klass, super_klass);
1031 br(Assembler::EQ, *L_success);
1032
1033 // Check the supertype display:
1034 if (must_load_sco) {
1035 ldrw(temp_reg, super_check_offset_addr);
1036 super_check_offset = RegisterOrConstant(temp_reg);
1037 }
1038 Address super_check_addr(sub_klass, super_check_offset);
1039 ldr(rscratch1, super_check_addr);
1040 cmp(super_klass, rscratch1); // load displayed supertype
1041
1042 // This check has worked decisively for primary supers.
1043 // Secondary supers are sought in the super_cache ('super_cache_addr').
1044 // (Secondary supers are interfaces and very deeply nested subtypes.)
1045 // This works in the same check above because of a tricky aliasing
1046 // between the super_cache and the primary super display elements.
1047 // (The 'super_check_addr' can address either, as the case requires.)
1048 // Note that the cache is updated below if it does not help us find
1049 // what we need immediately.
1050 // So if it was a primary super, we can just fail immediately.
1051 // Otherwise, it's the slow path for us (no success at this point).
1052
1053 if (super_check_offset.is_register()) {
1054 br(Assembler::EQ, *L_success);
1055 cmp(super_check_offset.as_register(), sc_offset);
1056 if (L_failure == &L_fallthrough) {
1057 br(Assembler::EQ, *L_slow_path);
1058 } else {
1059 br(Assembler::NE, *L_failure);
1060 final_jmp(*L_slow_path);
1061 }
1062 } else if (super_check_offset.as_constant() == sc_offset) {
1063 // Need a slow path; fast failure is impossible.
1064 if (L_slow_path == &L_fallthrough) {
1065 br(Assembler::EQ, *L_success);
1066 } else {
1067 br(Assembler::NE, *L_slow_path);
1068 final_jmp(*L_success);
1069 }
1070 } else {
1071 // No slow path; it's a fast decision.
1072 if (L_failure == &L_fallthrough) {
1073 br(Assembler::EQ, *L_success);
1074 } else {
1075 br(Assembler::NE, *L_failure);
1076 final_jmp(*L_success);
1077 }
1078 }
1079
1080 bind(L_fallthrough);
1081
1082 #undef final_jmp
1083 }
1084
1085 // These two are taken from x86, but they look generally useful
1086
1087 // scans count pointer sized words at [addr] for occurence of value,
1088 // generic
1089 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1090 Register scratch) {
1091 Label Lloop, Lexit;
1092 cbz(count, Lexit);
1093 bind(Lloop);
1094 ldr(scratch, post(addr, wordSize));
1095 cmp(value, scratch);
1096 br(EQ, Lexit);
1097 sub(count, count, 1);
1098 cbnz(count, Lloop);
1099 bind(Lexit);
1100 }
1101
1102 // scans count 4 byte words at [addr] for occurence of value,
1103 // generic
1104 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1105 Register scratch) {
1106 Label Lloop, Lexit;
1107 cbz(count, Lexit);
1108 bind(Lloop);
1109 ldrw(scratch, post(addr, wordSize));
1110 cmpw(value, scratch);
1111 br(EQ, Lexit);
1112 sub(count, count, 1);
1113 cbnz(count, Lloop);
1114 bind(Lexit);
1115 }
1116
1117 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1118 Register super_klass,
1119 Register temp_reg,
1120 Register temp2_reg,
1121 Label* L_success,
1122 Label* L_failure,
1123 bool set_cond_codes) {
1124 assert_different_registers(sub_klass, super_klass, temp_reg);
1125 if (temp2_reg != noreg)
1126 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1127 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1128
1129 Label L_fallthrough;
1130 int label_nulls = 0;
1131 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
1132 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
1133 assert(label_nulls <= 1, "at most one NULL in the batch");
1134
1135 // a couple of useful fields in sub_klass:
1136 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1137 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1138 Address secondary_supers_addr(sub_klass, ss_offset);
1139 Address super_cache_addr( sub_klass, sc_offset);
1140
1141 BLOCK_COMMENT("check_klass_subtype_slow_path");
1142
1143 // Do a linear scan of the secondary super-klass chain.
1144 // This code is rarely used, so simplicity is a virtue here.
1145 // The repne_scan instruction uses fixed registers, which we must spill.
1146 // Don't worry too much about pre-existing connections with the input regs.
1147
1148 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1149 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1150
1151 // Get super_klass value into r0 (even if it was in r5 or r2).
1152 RegSet pushed_registers;
1153 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1154 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1155
1156 if (super_klass != r0 || UseCompressedOops) {
1157 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1158 }
1159
1160 push(pushed_registers, sp);
1161
1162 #ifndef PRODUCT
1163 mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr);
1164 Address pst_counter_addr(rscratch2);
1165 ldr(rscratch1, pst_counter_addr);
1166 add(rscratch1, rscratch1, 1);
1167 str(rscratch1, pst_counter_addr);
1168 #endif //PRODUCT
1169
1170 // We will consult the secondary-super array.
1171 ldr(r5, secondary_supers_addr);
1172 // Load the array length.
1173 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1174 // Skip to start of data.
1175 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1176
1177 cmp(sp, zr); // Clear Z flag; SP is never zero
1178 // Scan R2 words at [R5] for an occurrence of R0.
1179 // Set NZ/Z based on last compare.
1180 repne_scan(r5, r0, r2, rscratch1);
1181
1182 // Unspill the temp. registers:
1183 pop(pushed_registers, sp);
1184
1185 br(Assembler::NE, *L_failure);
1186
1187 // Success. Cache the super we found and proceed in triumph.
1188 str(super_klass, super_cache_addr);
1189
1190 if (L_success != &L_fallthrough) {
1191 b(*L_success);
1192 }
1193
1194 #undef IS_A_TEMP
1195
1196 bind(L_fallthrough);
1197 }
1198
1199
1200 void MacroAssembler::verify_oop(Register reg, const char* s) {
1201 if (!VerifyOops) return;
1202
1203 // Pass register number to verify_oop_subroutine
1204 const char* b = NULL;
1205 {
1206 ResourceMark rm;
1207 stringStream ss;
1208 ss.print("verify_oop: %s: %s", reg->name(), s);
1209 b = code_string(ss.as_string());
1210 }
1211 BLOCK_COMMENT("verify_oop {");
1212
1213 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1214 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1215
1216 mov(r0, reg);
1217 mov(rscratch1, (address)b);
1218
1219 // call indirectly to solve generation ordering problem
1220 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1221 ldr(rscratch2, Address(rscratch2));
1222 blr(rscratch2);
1223
1224 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1225 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1226
1227 BLOCK_COMMENT("} verify_oop");
1228 }
1229
1230 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
1231 if (!VerifyOops) return;
1232
1233 const char* b = NULL;
1234 {
1235 ResourceMark rm;
1236 stringStream ss;
1237 ss.print("verify_oop_addr: %s", s);
1238 b = code_string(ss.as_string());
1239 }
1240 BLOCK_COMMENT("verify_oop_addr {");
1241
1242 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1243 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1244
1245 // addr may contain sp so we will have to adjust it based on the
1246 // pushes that we just did.
1247 if (addr.uses(sp)) {
1248 lea(r0, addr);
1249 ldr(r0, Address(r0, 4 * wordSize));
1250 } else {
1251 ldr(r0, addr);
1252 }
1253 mov(rscratch1, (address)b);
1254
1255 // call indirectly to solve generation ordering problem
1256 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1257 ldr(rscratch2, Address(rscratch2));
1258 blr(rscratch2);
1259
1260 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1261 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1262
1263 BLOCK_COMMENT("} verify_oop_addr");
1264 }
1265
1266 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
1267 int extra_slot_offset) {
1268 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
1269 int stackElementSize = Interpreter::stackElementSize;
1270 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
1271 #ifdef ASSERT
1272 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
1273 assert(offset1 - offset == stackElementSize, "correct arithmetic");
1274 #endif
1275 if (arg_slot.is_constant()) {
1276 return Address(esp, arg_slot.as_constant() * stackElementSize
1277 + offset);
1278 } else {
1279 add(rscratch1, esp, arg_slot.as_register(),
1280 ext::uxtx, exact_log2(stackElementSize));
1281 return Address(rscratch1, offset);
1282 }
1283 }
1284
1285 void MacroAssembler::call_VM_leaf_base(address entry_point,
1286 int number_of_arguments,
1287 Label *retaddr) {
1288 call_VM_leaf_base1(entry_point, number_of_arguments, 0, ret_type_integral, retaddr);
1289 }
1290
1291 void MacroAssembler::call_VM_leaf_base1(address entry_point,
1292 int number_of_gp_arguments,
1293 int number_of_fp_arguments,
1294 ret_type type,
1295 Label *retaddr) {
1296 Label E, L;
1297
1298 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
1299
1300 // We add 1 to number_of_arguments because the thread in arg0 is
1301 // not counted
1302 mov(rscratch1, entry_point);
1303 blrt(rscratch1, number_of_gp_arguments + 1, number_of_fp_arguments, type);
1304 if (retaddr)
1305 bind(*retaddr);
1306
1307 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
1308 maybe_isb();
1309 }
1310
1311 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1312 call_VM_leaf_base(entry_point, number_of_arguments);
1313 }
1314
1315 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1316 pass_arg0(this, arg_0);
1317 call_VM_leaf_base(entry_point, 1);
1318 }
1319
1320 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1321 pass_arg0(this, arg_0);
1322 pass_arg1(this, arg_1);
1323 call_VM_leaf_base(entry_point, 2);
1324 }
1325
1326 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1327 Register arg_1, Register arg_2) {
1328 pass_arg0(this, arg_0);
1329 pass_arg1(this, arg_1);
1330 pass_arg2(this, arg_2);
1331 call_VM_leaf_base(entry_point, 3);
1332 }
1333
1334 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1335 pass_arg0(this, arg_0);
1336 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1337 }
1338
1339 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1340
1341 assert(arg_0 != c_rarg1, "smashed arg");
1342 pass_arg1(this, arg_1);
1343 pass_arg0(this, arg_0);
1344 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1345 }
1346
1347 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1348 assert(arg_0 != c_rarg2, "smashed arg");
1349 assert(arg_1 != c_rarg2, "smashed arg");
1350 pass_arg2(this, arg_2);
1351 assert(arg_0 != c_rarg1, "smashed arg");
1352 pass_arg1(this, arg_1);
1353 pass_arg0(this, arg_0);
1354 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1355 }
1356
1357 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1358 assert(arg_0 != c_rarg3, "smashed arg");
1359 assert(arg_1 != c_rarg3, "smashed arg");
1360 assert(arg_2 != c_rarg3, "smashed arg");
1361 pass_arg3(this, arg_3);
1362 assert(arg_0 != c_rarg2, "smashed arg");
1363 assert(arg_1 != c_rarg2, "smashed arg");
1364 pass_arg2(this, arg_2);
1365 assert(arg_0 != c_rarg1, "smashed arg");
1366 pass_arg1(this, arg_1);
1367 pass_arg0(this, arg_0);
1368 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1369 }
1370
1371 void MacroAssembler::null_check(Register reg, int offset) {
1372 if (needs_explicit_null_check(offset)) {
1373 // provoke OS NULL exception if reg = NULL by
1374 // accessing M[reg] w/o changing any registers
1375 // NOTE: this is plenty to provoke a segv
1376 ldr(zr, Address(reg));
1377 } else {
1378 // nothing to do, (later) access of M[reg + offset]
1379 // will provoke OS NULL exception if reg = NULL
1380 }
1381 }
1382
1383 // MacroAssembler protected routines needed to implement
1384 // public methods
1385
1386 void MacroAssembler::mov(Register r, Address dest) {
1387 code_section()->relocate(pc(), dest.rspec());
1388 u_int64_t imm64 = (u_int64_t)dest.target();
1389 movptr(r, imm64);
1390 }
1391
1392 // Move a constant pointer into r. In AArch64 mode the virtual
1393 // address space is 48 bits in size, so we only need three
1394 // instructions to create a patchable instruction sequence that can
1395 // reach anywhere.
1396 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
1397 #ifndef PRODUCT
1398 {
1399 char buffer[64];
1400 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
1401 block_comment(buffer);
1402 }
1403 #endif
1404 assert(imm64 < (1ul << 48), "48-bit overflow in address constant");
1405 movz(r, imm64 & 0xffff);
1406 imm64 >>= 16;
1407 movk(r, imm64 & 0xffff, 16);
1408 imm64 >>= 16;
1409 movk(r, imm64 & 0xffff, 32);
1410 }
1411
1412 // Macro to mov replicated immediate to vector register.
1413 // Vd will get the following values for different arrangements in T
1414 // imm32 == hex 000000gh T8B: Vd = ghghghghghghghgh
1415 // imm32 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
1416 // imm32 == hex 0000efgh T4H: Vd = efghefghefghefgh
1417 // imm32 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
1418 // imm32 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
1419 // imm32 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
1420 // T1D/T2D: invalid
1421 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) {
1422 assert(T != T1D && T != T2D, "invalid arrangement");
1423 if (T == T8B || T == T16B) {
1424 assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)");
1425 movi(Vd, T, imm32 & 0xff, 0);
1426 return;
1427 }
1428 u_int32_t nimm32 = ~imm32;
1429 if (T == T4H || T == T8H) {
1430 assert((imm32 & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)");
1431 imm32 &= 0xffff;
1432 nimm32 &= 0xffff;
1433 }
1434 u_int32_t x = imm32;
1435 int movi_cnt = 0;
1436 int movn_cnt = 0;
1437 while (x) { if (x & 0xff) movi_cnt++; x >>= 8; }
1438 x = nimm32;
1439 while (x) { if (x & 0xff) movn_cnt++; x >>= 8; }
1440 if (movn_cnt < movi_cnt) imm32 = nimm32;
1441 unsigned lsl = 0;
1442 while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
1443 if (movn_cnt < movi_cnt)
1444 mvni(Vd, T, imm32 & 0xff, lsl);
1445 else
1446 movi(Vd, T, imm32 & 0xff, lsl);
1447 imm32 >>= 8; lsl += 8;
1448 while (imm32) {
1449 while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
1450 if (movn_cnt < movi_cnt)
1451 bici(Vd, T, imm32 & 0xff, lsl);
1452 else
1453 orri(Vd, T, imm32 & 0xff, lsl);
1454 lsl += 8; imm32 >>= 8;
1455 }
1456 }
1457
1458 void MacroAssembler::mov_immediate64(Register dst, u_int64_t imm64)
1459 {
1460 #ifndef PRODUCT
1461 {
1462 char buffer[64];
1463 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
1464 block_comment(buffer);
1465 }
1466 #endif
1467 if (operand_valid_for_logical_immediate(false, imm64)) {
1468 orr(dst, zr, imm64);
1469 } else {
1470 // we can use a combination of MOVZ or MOVN with
1471 // MOVK to build up the constant
1472 u_int64_t imm_h[4];
1473 int zero_count = 0;
1474 int neg_count = 0;
1475 int i;
1476 for (i = 0; i < 4; i++) {
1477 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
1478 if (imm_h[i] == 0) {
1479 zero_count++;
1480 } else if (imm_h[i] == 0xffffL) {
1481 neg_count++;
1482 }
1483 }
1484 if (zero_count == 4) {
1485 // one MOVZ will do
1486 movz(dst, 0);
1487 } else if (neg_count == 4) {
1488 // one MOVN will do
1489 movn(dst, 0);
1490 } else if (zero_count == 3) {
1491 for (i = 0; i < 4; i++) {
1492 if (imm_h[i] != 0L) {
1493 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1494 break;
1495 }
1496 }
1497 } else if (neg_count == 3) {
1498 // one MOVN will do
1499 for (int i = 0; i < 4; i++) {
1500 if (imm_h[i] != 0xffffL) {
1501 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1502 break;
1503 }
1504 }
1505 } else if (zero_count == 2) {
1506 // one MOVZ and one MOVK will do
1507 for (i = 0; i < 3; i++) {
1508 if (imm_h[i] != 0L) {
1509 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1510 i++;
1511 break;
1512 }
1513 }
1514 for (;i < 4; i++) {
1515 if (imm_h[i] != 0L) {
1516 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1517 }
1518 }
1519 } else if (neg_count == 2) {
1520 // one MOVN and one MOVK will do
1521 for (i = 0; i < 4; i++) {
1522 if (imm_h[i] != 0xffffL) {
1523 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1524 i++;
1525 break;
1526 }
1527 }
1528 for (;i < 4; i++) {
1529 if (imm_h[i] != 0xffffL) {
1530 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1531 }
1532 }
1533 } else if (zero_count == 1) {
1534 // one MOVZ and two MOVKs will do
1535 for (i = 0; i < 4; i++) {
1536 if (imm_h[i] != 0L) {
1537 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1538 i++;
1539 break;
1540 }
1541 }
1542 for (;i < 4; i++) {
1543 if (imm_h[i] != 0x0L) {
1544 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1545 }
1546 }
1547 } else if (neg_count == 1) {
1548 // one MOVN and two MOVKs will do
1549 for (i = 0; i < 4; i++) {
1550 if (imm_h[i] != 0xffffL) {
1551 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1552 i++;
1553 break;
1554 }
1555 }
1556 for (;i < 4; i++) {
1557 if (imm_h[i] != 0xffffL) {
1558 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1559 }
1560 }
1561 } else {
1562 // use a MOVZ and 3 MOVKs (makes it easier to debug)
1563 movz(dst, (u_int32_t)imm_h[0], 0);
1564 for (i = 1; i < 4; i++) {
1565 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1566 }
1567 }
1568 }
1569 }
1570
1571 void MacroAssembler::mov_immediate32(Register dst, u_int32_t imm32)
1572 {
1573 #ifndef PRODUCT
1574 {
1575 char buffer[64];
1576 snprintf(buffer, sizeof(buffer), "0x%"PRIX32, imm32);
1577 block_comment(buffer);
1578 }
1579 #endif
1580 if (operand_valid_for_logical_immediate(true, imm32)) {
1581 orrw(dst, zr, imm32);
1582 } else {
1583 // we can use MOVZ, MOVN or two calls to MOVK to build up the
1584 // constant
1585 u_int32_t imm_h[2];
1586 imm_h[0] = imm32 & 0xffff;
1587 imm_h[1] = ((imm32 >> 16) & 0xffff);
1588 if (imm_h[0] == 0) {
1589 movzw(dst, imm_h[1], 16);
1590 } else if (imm_h[0] == 0xffff) {
1591 movnw(dst, imm_h[1] ^ 0xffff, 16);
1592 } else if (imm_h[1] == 0) {
1593 movzw(dst, imm_h[0], 0);
1594 } else if (imm_h[1] == 0xffff) {
1595 movnw(dst, imm_h[0] ^ 0xffff, 0);
1596 } else {
1597 // use a MOVZ and MOVK (makes it easier to debug)
1598 movzw(dst, imm_h[0], 0);
1599 movkw(dst, imm_h[1], 16);
1600 }
1601 }
1602 }
1603
1604 // Form an address from base + offset in Rd. Rd may or may
1605 // not actually be used: you must use the Address that is returned.
1606 // It is up to you to ensure that the shift provided matches the size
1607 // of your data.
1608 Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) {
1609 if (Address::offset_ok_for_immed(byte_offset, shift))
1610 // It fits; no need for any heroics
1611 return Address(base, byte_offset);
1612
1613 // Don't do anything clever with negative or misaligned offsets
1614 unsigned mask = (1 << shift) - 1;
1615 if (byte_offset < 0 || byte_offset & mask) {
1616 mov(Rd, byte_offset);
1617 add(Rd, base, Rd);
1618 return Address(Rd);
1619 }
1620
1621 // See if we can do this with two 12-bit offsets
1622 {
1623 unsigned long word_offset = byte_offset >> shift;
1624 unsigned long masked_offset = word_offset & 0xfff000;
1625 if (Address::offset_ok_for_immed(word_offset - masked_offset)
1626 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
1627 add(Rd, base, masked_offset << shift);
1628 word_offset -= masked_offset;
1629 return Address(Rd, word_offset << shift);
1630 }
1631 }
1632
1633 // Do it the hard way
1634 mov(Rd, byte_offset);
1635 add(Rd, base, Rd);
1636 return Address(Rd);
1637 }
1638
1639 void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) {
1640 Label retry_load;
1641 bind(retry_load);
1642 // flush and load exclusive from the memory location
1643 ldxrw(tmp, counter_addr);
1644 addw(tmp, tmp, 1);
1645 // if we store+flush with no intervening write tmp wil be zero
1646 stxrw(tmp2, tmp, counter_addr);
1647 cbnzw(tmp2, retry_load);
1648 }
1649
1650
1651 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
1652 bool want_remainder, Register scratch)
1653 {
1654 // Full implementation of Java idiv and irem. The function
1655 // returns the (pc) offset of the div instruction - may be needed
1656 // for implicit exceptions.
1657 //
1658 // constraint : ra/rb =/= scratch
1659 // normal case
1660 //
1661 // input : ra: dividend
1662 // rb: divisor
1663 //
1664 // result: either
1665 // quotient (= ra idiv rb)
1666 // remainder (= ra irem rb)
1667
1668 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
1669
1670 int idivl_offset = offset();
1671 if (! want_remainder) {
1672 sdivw(result, ra, rb);
1673 } else {
1674 sdivw(scratch, ra, rb);
1675 Assembler::msubw(result, scratch, rb, ra);
1676 }
1677
1678 return idivl_offset;
1679 }
1680
1681 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
1682 bool want_remainder, Register scratch)
1683 {
1684 // Full implementation of Java ldiv and lrem. The function
1685 // returns the (pc) offset of the div instruction - may be needed
1686 // for implicit exceptions.
1687 //
1688 // constraint : ra/rb =/= scratch
1689 // normal case
1690 //
1691 // input : ra: dividend
1692 // rb: divisor
1693 //
1694 // result: either
1695 // quotient (= ra idiv rb)
1696 // remainder (= ra irem rb)
1697
1698 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
1699
1700 int idivq_offset = offset();
1701 if (! want_remainder) {
1702 sdiv(result, ra, rb);
1703 } else {
1704 sdiv(scratch, ra, rb);
1705 Assembler::msub(result, scratch, rb, ra);
1706 }
1707
1708 return idivq_offset;
1709 }
1710
1711 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
1712 address prev = pc() - NativeMembar::instruction_size;
1713 if (prev == code()->last_membar()) {
1714 NativeMembar *bar = NativeMembar_at(prev);
1715 // We are merging two memory barrier instructions. On AArch64 we
1716 // can do this simply by ORing them together.
1717 bar->set_kind(bar->get_kind() | order_constraint);
1718 BLOCK_COMMENT("merged membar");
1719 } else {
1720 code()->set_last_membar(pc());
1721 dmb(Assembler::barrier(order_constraint));
1722 }
1723 }
1724
1725 // MacroAssembler routines found actually to be needed
1726
1727 void MacroAssembler::push(Register src)
1728 {
1729 str(src, Address(pre(esp, -1 * wordSize)));
1730 }
1731
1732 void MacroAssembler::pop(Register dst)
1733 {
1734 ldr(dst, Address(post(esp, 1 * wordSize)));
1735 }
1736
1737 // Note: load_unsigned_short used to be called load_unsigned_word.
1738 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1739 int off = offset();
1740 ldrh(dst, src);
1741 return off;
1742 }
1743
1744 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1745 int off = offset();
1746 ldrb(dst, src);
1747 return off;
1748 }
1749
1750 int MacroAssembler::load_signed_short(Register dst, Address src) {
1751 int off = offset();
1752 ldrsh(dst, src);
1753 return off;
1754 }
1755
1756 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1757 int off = offset();
1758 ldrsb(dst, src);
1759 return off;
1760 }
1761
1762 int MacroAssembler::load_signed_short32(Register dst, Address src) {
1763 int off = offset();
1764 ldrshw(dst, src);
1765 return off;
1766 }
1767
1768 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
1769 int off = offset();
1770 ldrsbw(dst, src);
1771 return off;
1772 }
1773
1774 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1775 switch (size_in_bytes) {
1776 case 8: ldr(dst, src); break;
1777 case 4: ldrw(dst, src); break;
1778 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1779 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1780 default: ShouldNotReachHere();
1781 }
1782 }
1783
1784 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1785 switch (size_in_bytes) {
1786 case 8: str(src, dst); break;
1787 case 4: strw(src, dst); break;
1788 case 2: strh(src, dst); break;
1789 case 1: strb(src, dst); break;
1790 default: ShouldNotReachHere();
1791 }
1792 }
1793
1794 void MacroAssembler::decrementw(Register reg, int value)
1795 {
1796 if (value < 0) { incrementw(reg, -value); return; }
1797 if (value == 0) { return; }
1798 if (value < (1 << 12)) { subw(reg, reg, value); return; }
1799 /* else */ {
1800 guarantee(reg != rscratch2, "invalid dst for register decrement");
1801 movw(rscratch2, (unsigned)value);
1802 subw(reg, reg, rscratch2);
1803 }
1804 }
1805
1806 void MacroAssembler::decrement(Register reg, int value)
1807 {
1808 if (value < 0) { increment(reg, -value); return; }
1809 if (value == 0) { return; }
1810 if (value < (1 << 12)) { sub(reg, reg, value); return; }
1811 /* else */ {
1812 assert(reg != rscratch2, "invalid dst for register decrement");
1813 mov(rscratch2, (unsigned long)value);
1814 sub(reg, reg, rscratch2);
1815 }
1816 }
1817
1818 void MacroAssembler::decrementw(Address dst, int value)
1819 {
1820 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
1821 ldrw(rscratch1, dst);
1822 decrementw(rscratch1, value);
1823 strw(rscratch1, dst);
1824 }
1825
1826 void MacroAssembler::decrement(Address dst, int value)
1827 {
1828 assert(!dst.uses(rscratch1), "invalid address for decrement");
1829 ldr(rscratch1, dst);
1830 decrement(rscratch1, value);
1831 str(rscratch1, dst);
1832 }
1833
1834 void MacroAssembler::incrementw(Register reg, int value)
1835 {
1836 if (value < 0) { decrementw(reg, -value); return; }
1837 if (value == 0) { return; }
1838 if (value < (1 << 12)) { addw(reg, reg, value); return; }
1839 /* else */ {
1840 assert(reg != rscratch2, "invalid dst for register increment");
1841 movw(rscratch2, (unsigned)value);
1842 addw(reg, reg, rscratch2);
1843 }
1844 }
1845
1846 void MacroAssembler::increment(Register reg, int value)
1847 {
1848 if (value < 0) { decrement(reg, -value); return; }
1849 if (value == 0) { return; }
1850 if (value < (1 << 12)) { add(reg, reg, value); return; }
1851 /* else */ {
1852 assert(reg != rscratch2, "invalid dst for register increment");
1853 movw(rscratch2, (unsigned)value);
1854 add(reg, reg, rscratch2);
1855 }
1856 }
1857
1858 void MacroAssembler::incrementw(Address dst, int value)
1859 {
1860 assert(!dst.uses(rscratch1), "invalid dst for address increment");
1861 ldrw(rscratch1, dst);
1862 incrementw(rscratch1, value);
1863 strw(rscratch1, dst);
1864 }
1865
1866 void MacroAssembler::increment(Address dst, int value)
1867 {
1868 assert(!dst.uses(rscratch1), "invalid dst for address increment");
1869 ldr(rscratch1, dst);
1870 increment(rscratch1, value);
1871 str(rscratch1, dst);
1872 }
1873
1874
1875 void MacroAssembler::pusha() {
1876 push(0x7fffffff, sp);
1877 }
1878
1879 void MacroAssembler::popa() {
1880 pop(0x7fffffff, sp);
1881 }
1882
1883 // Push lots of registers in the bit set supplied. Don't push sp.
1884 // Return the number of words pushed
1885 int MacroAssembler::push(unsigned int bitset, Register stack) {
1886 int words_pushed = 0;
1887
1888 // Scan bitset to accumulate register pairs
1889 unsigned char regs[32];
1890 int count = 0;
1891 for (int reg = 0; reg <= 30; reg++) {
1892 if (1 & bitset)
1893 regs[count++] = reg;
1894 bitset >>= 1;
1895 }
1896 regs[count++] = zr->encoding_nocheck();
1897 count &= ~1; // Only push an even nuber of regs
1898
1899 if (count) {
1900 stp(as_Register(regs[0]), as_Register(regs[1]),
1901 Address(pre(stack, -count * wordSize)));
1902 words_pushed += 2;
1903 }
1904 for (int i = 2; i < count; i += 2) {
1905 stp(as_Register(regs[i]), as_Register(regs[i+1]),
1906 Address(stack, i * wordSize));
1907 words_pushed += 2;
1908 }
1909
1910 assert(words_pushed == count, "oops, pushed != count");
1911
1912 return count;
1913 }
1914
1915 int MacroAssembler::pop(unsigned int bitset, Register stack) {
1916 int words_pushed = 0;
1917
1918 // Scan bitset to accumulate register pairs
1919 unsigned char regs[32];
1920 int count = 0;
1921 for (int reg = 0; reg <= 30; reg++) {
1922 if (1 & bitset)
1923 regs[count++] = reg;
1924 bitset >>= 1;
1925 }
1926 regs[count++] = zr->encoding_nocheck();
1927 count &= ~1;
1928
1929 for (int i = 2; i < count; i += 2) {
1930 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
1931 Address(stack, i * wordSize));
1932 words_pushed += 2;
1933 }
1934 if (count) {
1935 ldp(as_Register(regs[0]), as_Register(regs[1]),
1936 Address(post(stack, count * wordSize)));
1937 words_pushed += 2;
1938 }
1939
1940 assert(words_pushed == count, "oops, pushed != count");
1941
1942 return count;
1943 }
1944 #ifdef ASSERT
1945 void MacroAssembler::verify_heapbase(const char* msg) {
1946 #if 0
1947 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
1948 assert (Universe::heap() != NULL, "java heap should be initialized");
1949 if (CheckCompressedOops) {
1950 Label ok;
1951 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
1952 cmpptr(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
1953 br(Assembler::EQ, ok);
1954 stop(msg);
1955 bind(ok);
1956 pop(1 << rscratch1->encoding(), sp);
1957 }
1958 #endif
1959 }
1960 #endif
1961
1962 void MacroAssembler::stop(const char* msg) {
1963 address ip = pc();
1964 pusha();
1965 mov(c_rarg0, (address)msg);
1966 mov(c_rarg1, (address)ip);
1967 mov(c_rarg2, sp);
1968 mov(c_rarg3, CAST_FROM_FN_PTR(address, MacroAssembler::debug64));
1969 // call(c_rarg3);
1970 blrt(c_rarg3, 3, 0, 1);
1971 hlt(0);
1972 }
1973
1974 // If a constant does not fit in an immediate field, generate some
1975 // number of MOV instructions and then perform the operation.
1976 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1977 add_sub_imm_insn insn1,
1978 add_sub_reg_insn insn2) {
1979 assert(Rd != zr, "Rd = zr and not setting flags?");
1980 if (operand_valid_for_add_sub_immediate((int)imm)) {
1981 (this->*insn1)(Rd, Rn, imm);
1982 } else {
1983 if (uabs(imm) < (1 << 24)) {
1984 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
1985 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
1986 } else {
1987 assert_different_registers(Rd, Rn);
1988 mov(Rd, (uint64_t)imm);
1989 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
1990 }
1991 }
1992 }
1993
1994 // Seperate vsn which sets the flags. Optimisations are more restricted
1995 // because we must set the flags correctly.
1996 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1997 add_sub_imm_insn insn1,
1998 add_sub_reg_insn insn2) {
1999 if (operand_valid_for_add_sub_immediate((int)imm)) {
2000 (this->*insn1)(Rd, Rn, imm);
2001 } else {
2002 assert_different_registers(Rd, Rn);
2003 assert(Rd != zr, "overflow in immediate operand");
2004 mov(Rd, (uint64_t)imm);
2005 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
2006 }
2007 }
2008
2009
2010 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
2011 if (increment.is_register()) {
2012 add(Rd, Rn, increment.as_register());
2013 } else {
2014 add(Rd, Rn, increment.as_constant());
2015 }
2016 }
2017
2018 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
2019 if (increment.is_register()) {
2020 addw(Rd, Rn, increment.as_register());
2021 } else {
2022 addw(Rd, Rn, increment.as_constant());
2023 }
2024 }
2025
2026 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
2027 if (decrement.is_register()) {
2028 sub(Rd, Rn, decrement.as_register());
2029 } else {
2030 sub(Rd, Rn, decrement.as_constant());
2031 }
2032 }
2033
2034 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
2035 if (decrement.is_register()) {
2036 subw(Rd, Rn, decrement.as_register());
2037 } else {
2038 subw(Rd, Rn, decrement.as_constant());
2039 }
2040 }
2041
2042 void MacroAssembler::reinit_heapbase()
2043 {
2044 if (UseCompressedOops) {
2045 if (Universe::is_fully_initialized()) {
2046 mov(rheapbase, Universe::narrow_ptrs_base());
2047 } else {
2048 lea(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
2049 ldr(rheapbase, Address(rheapbase));
2050 }
2051 }
2052 }
2053
2054 // this simulates the behaviour of the x86 cmpxchg instruction using a
2055 // load linked/store conditional pair. we use the acquire/release
2056 // versions of these instructions so that we flush pending writes as
2057 // per Java semantics.
2058
2059 // n.b the x86 version assumes the old value to be compared against is
2060 // in rax and updates rax with the value located in memory if the
2061 // cmpxchg fails. we supply a register for the old value explicitly
2062
2063 // the aarch64 load linked/store conditional instructions do not
2064 // accept an offset. so, unlike x86, we must provide a plain register
2065 // to identify the memory word to be compared/exchanged rather than a
2066 // register+offset Address.
2067
2068 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
2069 Label &succeed, Label *fail) {
2070 // oldv holds comparison value
2071 // newv holds value to write in exchange
2072 // addr identifies memory word to compare against/update
2073 if (UseLSE) {
2074 mov(tmp, oldv);
2075 casal(Assembler::xword, oldv, newv, addr);
2076 cmp(tmp, oldv);
2077 br(Assembler::EQ, succeed);
2078 membar(AnyAny);
2079 } else {
2080 Label retry_load, nope;
2081
2082 bind(retry_load);
2083 // flush and load exclusive from the memory location
2084 // and fail if it is not what we expect
2085 ldaxr(tmp, addr);
2086 cmp(tmp, oldv);
2087 br(Assembler::NE, nope);
2088 // if we store+flush with no intervening write tmp wil be zero
2089 stlxr(tmp, newv, addr);
2090 cbzw(tmp, succeed);
2091 // retry so we only ever return after a load fails to compare
2092 // ensures we don't return a stale value after a failed write.
2093 b(retry_load);
2094 // if the memory word differs we return it in oldv and signal a fail
2095 bind(nope);
2096 membar(AnyAny);
2097 mov(oldv, tmp);
2098 }
2099 if (fail)
2100 b(*fail);
2101 }
2102
2103 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
2104 Label &succeed, Label *fail) {
2105 // oldv holds comparison value
2106 // newv holds value to write in exchange
2107 // addr identifies memory word to compare against/update
2108 if (UseLSE) {
2109 mov(tmp, oldv);
2110 casal(Assembler::word, oldv, newv, addr);
2111 cmp(tmp, oldv);
2112 br(Assembler::EQ, succeed);
2113 membar(AnyAny);
2114 } else {
2115 Label retry_load, nope;
2116
2117 bind(retry_load);
2118 // flush and load exclusive from the memory location
2119 // and fail if it is not what we expect
2120 ldaxrw(tmp, addr);
2121 cmp(tmp, oldv);
2122 br(Assembler::NE, nope);
2123 // if we store+flush with no intervening write tmp wil be zero
2124 stlxrw(tmp, newv, addr);
2125 cbzw(tmp, succeed);
2126 // retry so we only ever return after a load fails to compare
2127 // ensures we don't return a stale value after a failed write.
2128 b(retry_load);
2129 // if the memory word differs we return it in oldv and signal a fail
2130 bind(nope);
2131 membar(AnyAny);
2132 mov(oldv, tmp);
2133 }
2134 if (fail)
2135 b(*fail);
2136 }
2137
2138 void MacroAssembler::cmpxchg(operand_size sz,
2139 Register oldv, Register newv, Register addr,
2140 bool acquire, bool release,
2141 Register tmp)
2142 {
2143 // oldv holds comparison value
2144 // newv holds value to write in exchange
2145 // addr identifies memory word to compare against/update
2146 // returns EQ == success, NE == failure
2147 if (UseLSE) {
2148 mov(tmp, oldv);
2149 compare_and_swap(tmp, newv, addr, sz, acquire?1:0, release?1:0);
2150 cmp(tmp, oldv);
2151 } else {
2152 Label retry_load, done;
2153
2154 bind(retry_load);
2155 // flush and load exclusive from the memory location
2156 // and fail if it is not what we expect
2157 cas_load(sz, tmp, addr, acquire?1:0);
2158 cmp(tmp, oldv);
2159 br(Assembler::NE, done);
2160 // if we store+flush with no intervening write tmp wil be zero
2161 cas_store(sz, tmp, newv, addr, release?1:0);
2162 cbnzw(tmp, retry_load);
2163 // if the memory word differs we return it in oldv and signal a fail
2164 bind(done);
2165 }
2166 }
2167
2168 static bool different(Register a, RegisterOrConstant b, Register c) {
2169 if (b.is_constant())
2170 return a != c;
2171 else
2172 return a != b.as_register() && a != c && b.as_register() != c;
2173 }
2174
2175 #define ATOMIC_OP(LDXR, OP, IOP, STXR) \
2176 void MacroAssembler::atomic_##OP(Register prev, RegisterOrConstant incr, Register addr) { \
2177 Register result = rscratch2; \
2178 if (prev->is_valid()) \
2179 result = different(prev, incr, addr) ? prev : rscratch2; \
2180 \
2181 Label retry_load; \
2182 bind(retry_load); \
2183 LDXR(result, addr); \
2184 OP(rscratch1, result, incr); \
2185 STXR(rscratch2, rscratch1, addr); \
2186 cbnzw(rscratch2, retry_load); \
2187 if (prev->is_valid() && prev != result) { \
2188 IOP(prev, rscratch1, incr); \
2189 } \
2190 }
2191
2192 ATOMIC_OP(ldxr, add, sub, stxr)
2193 ATOMIC_OP(ldxrw, addw, subw, stxrw)
2194
2195 #undef ATOMIC_OP
2196
2197 #define ATOMIC_XCHG(OP, LDXR, STXR) \
2198 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
2199 Register result = rscratch2; \
2200 if (prev->is_valid()) \
2201 result = different(prev, newv, addr) ? prev : rscratch2; \
2202 \
2203 Label retry_load; \
2204 bind(retry_load); \
2205 LDXR(result, addr); \
2206 STXR(rscratch1, newv, addr); \
2207 cbnzw(rscratch1, retry_load); \
2208 if (prev->is_valid() && prev != result) \
2209 mov(prev, result); \
2210 }
2211
2212 ATOMIC_XCHG(xchg, ldxr, stxr)
2213 ATOMIC_XCHG(xchgw, ldxrw, stxrw)
2214
2215 #undef ATOMIC_XCHG
2216
2217 void MacroAssembler::incr_allocated_bytes(Register thread,
2218 Register var_size_in_bytes,
2219 int con_size_in_bytes,
2220 Register t1) {
2221 if (!thread->is_valid()) {
2222 thread = rthread;
2223 }
2224 assert(t1->is_valid(), "need temp reg");
2225
2226 ldr(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset())));
2227 if (var_size_in_bytes->is_valid()) {
2228 add(t1, t1, var_size_in_bytes);
2229 } else {
2230 add(t1, t1, con_size_in_bytes);
2231 }
2232 str(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset())));
2233 }
2234
2235 #ifndef PRODUCT
2236 extern "C" void findpc(intptr_t x);
2237 #endif
2238
2239 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
2240 {
2241 // In order to get locks to work, we need to fake a in_VM state
2242 if (ShowMessageBoxOnError ) {
2243 JavaThread* thread = JavaThread::current();
2244 JavaThreadState saved_state = thread->thread_state();
2245 thread->set_thread_state(_thread_in_vm);
2246 #ifndef PRODUCT
2247 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
2248 ttyLocker ttyl;
2249 BytecodeCounter::print();
2250 }
2251 #endif
2252 if (os::message_box(msg, "Execution stopped, print registers?")) {
2253 ttyLocker ttyl;
2254 tty->print_cr(" pc = 0x%016lx", pc);
2255 #ifndef PRODUCT
2256 tty->cr();
2257 findpc(pc);
2258 tty->cr();
2259 #endif
2260 tty->print_cr(" r0 = 0x%016lx", regs[0]);
2261 tty->print_cr(" r1 = 0x%016lx", regs[1]);
2262 tty->print_cr(" r2 = 0x%016lx", regs[2]);
2263 tty->print_cr(" r3 = 0x%016lx", regs[3]);
2264 tty->print_cr(" r4 = 0x%016lx", regs[4]);
2265 tty->print_cr(" r5 = 0x%016lx", regs[5]);
2266 tty->print_cr(" r6 = 0x%016lx", regs[6]);
2267 tty->print_cr(" r7 = 0x%016lx", regs[7]);
2268 tty->print_cr(" r8 = 0x%016lx", regs[8]);
2269 tty->print_cr(" r9 = 0x%016lx", regs[9]);
2270 tty->print_cr("r10 = 0x%016lx", regs[10]);
2271 tty->print_cr("r11 = 0x%016lx", regs[11]);
2272 tty->print_cr("r12 = 0x%016lx", regs[12]);
2273 tty->print_cr("r13 = 0x%016lx", regs[13]);
2274 tty->print_cr("r14 = 0x%016lx", regs[14]);
2275 tty->print_cr("r15 = 0x%016lx", regs[15]);
2276 tty->print_cr("r16 = 0x%016lx", regs[16]);
2277 tty->print_cr("r17 = 0x%016lx", regs[17]);
2278 tty->print_cr("r18 = 0x%016lx", regs[18]);
2279 tty->print_cr("r19 = 0x%016lx", regs[19]);
2280 tty->print_cr("r20 = 0x%016lx", regs[20]);
2281 tty->print_cr("r21 = 0x%016lx", regs[21]);
2282 tty->print_cr("r22 = 0x%016lx", regs[22]);
2283 tty->print_cr("r23 = 0x%016lx", regs[23]);
2284 tty->print_cr("r24 = 0x%016lx", regs[24]);
2285 tty->print_cr("r25 = 0x%016lx", regs[25]);
2286 tty->print_cr("r26 = 0x%016lx", regs[26]);
2287 tty->print_cr("r27 = 0x%016lx", regs[27]);
2288 tty->print_cr("r28 = 0x%016lx", regs[28]);
2289 tty->print_cr("r30 = 0x%016lx", regs[30]);
2290 tty->print_cr("r31 = 0x%016lx", regs[31]);
2291 BREAKPOINT;
2292 }
2293 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
2294 } else {
2295 ttyLocker ttyl;
2296 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
2297 msg);
2298 assert(false, "DEBUG MESSAGE: %s", msg);
2299 }
2300 }
2301
2302 #ifdef BUILTIN_SIM
2303 // routine to generate an x86 prolog for a stub function which
2304 // bootstraps into the generated ARM code which directly follows the
2305 // stub
2306 //
2307 // the argument encodes the number of general and fp registers
2308 // passed by the caller and the callng convention (currently just
2309 // the number of general registers and assumes C argument passing)
2310
2311 extern "C" {
2312 int aarch64_stub_prolog_size();
2313 void aarch64_stub_prolog();
2314 void aarch64_prolog();
2315 }
2316
2317 void MacroAssembler::c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type,
2318 address *prolog_ptr)
2319 {
2320 int calltype = (((ret_type & 0x3) << 8) |
2321 ((fp_arg_count & 0xf) << 4) |
2322 (gp_arg_count & 0xf));
2323
2324 // the addresses for the x86 to ARM entry code we need to use
2325 address start = pc();
2326 // printf("start = %lx\n", start);
2327 int byteCount = aarch64_stub_prolog_size();
2328 // printf("byteCount = %x\n", byteCount);
2329 int instructionCount = (byteCount + 3)/ 4;
2330 // printf("instructionCount = %x\n", instructionCount);
2331 for (int i = 0; i < instructionCount; i++) {
2332 nop();
2333 }
2334
2335 memcpy(start, (void*)aarch64_stub_prolog, byteCount);
2336
2337 // write the address of the setup routine and the call format at the
2338 // end of into the copied code
2339 u_int64_t *patch_end = (u_int64_t *)(start + byteCount);
2340 if (prolog_ptr)
2341 patch_end[-2] = (u_int64_t)prolog_ptr;
2342 patch_end[-1] = calltype;
2343 }
2344 #endif
2345
2346 void MacroAssembler::push_call_clobbered_registers() {
2347 push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
2348
2349 // Push v0-v7, v16-v31.
2350 for (int i = 30; i >= 0; i -= 2) {
2351 if (i <= v7->encoding() || i >= v16->encoding()) {
2352 stpd(as_FloatRegister(i), as_FloatRegister(i+1),
2353 Address(pre(sp, -2 * wordSize)));
2354 }
2355 }
2356 }
2357
2358 void MacroAssembler::pop_call_clobbered_registers() {
2359
2360 for (int i = 0; i < 32; i += 2) {
2361 if (i <= v7->encoding() || i >= v16->encoding()) {
2362 ldpd(as_FloatRegister(i), as_FloatRegister(i+1),
2363 Address(post(sp, 2 * wordSize)));
2364 }
2365 }
2366
2367 pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
2368 }
2369
2370 void MacroAssembler::push_CPU_state(bool save_vectors) {
2371 push(0x3fffffff, sp); // integer registers except lr & sp
2372
2373 if (!save_vectors) {
2374 for (int i = 30; i >= 0; i -= 2)
2375 stpd(as_FloatRegister(i), as_FloatRegister(i+1),
2376 Address(pre(sp, -2 * wordSize)));
2377 } else {
2378 for (int i = 30; i >= 0; i -= 2)
2379 stpq(as_FloatRegister(i), as_FloatRegister(i+1),
2380 Address(pre(sp, -4 * wordSize)));
2381 }
2382 }
2383
2384 void MacroAssembler::pop_CPU_state(bool restore_vectors) {
2385 if (!restore_vectors) {
2386 for (int i = 0; i < 32; i += 2)
2387 ldpd(as_FloatRegister(i), as_FloatRegister(i+1),
2388 Address(post(sp, 2 * wordSize)));
2389 } else {
2390 for (int i = 0; i < 32; i += 2)
2391 ldpq(as_FloatRegister(i), as_FloatRegister(i+1),
2392 Address(post(sp, 4 * wordSize)));
2393 }
2394
2395 pop(0x3fffffff, sp); // integer registers except lr & sp
2396 }
2397
2398 /**
2399 * Helpers for multiply_to_len().
2400 */
2401 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
2402 Register src1, Register src2) {
2403 adds(dest_lo, dest_lo, src1);
2404 adc(dest_hi, dest_hi, zr);
2405 adds(dest_lo, dest_lo, src2);
2406 adc(final_dest_hi, dest_hi, zr);
2407 }
2408
2409 // Generate an address from (r + r1 extend offset). "size" is the
2410 // size of the operand. The result may be in rscratch2.
2411 Address MacroAssembler::offsetted_address(Register r, Register r1,
2412 Address::extend ext, int offset, int size) {
2413 if (offset || (ext.shift() % size != 0)) {
2414 lea(rscratch2, Address(r, r1, ext));
2415 return Address(rscratch2, offset);
2416 } else {
2417 return Address(r, r1, ext);
2418 }
2419 }
2420
2421 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
2422 {
2423 assert(offset >= 0, "spill to negative address?");
2424 // Offset reachable ?
2425 // Not aligned - 9 bits signed offset
2426 // Aligned - 12 bits unsigned offset shifted
2427 Register base = sp;
2428 if ((offset & (size-1)) && offset >= (1<<8)) {
2429 add(tmp, base, offset & ((1<<12)-1));
2430 base = tmp;
2431 offset &= -1<<12;
2432 }
2433
2434 if (offset >= (1<<12) * size) {
2435 add(tmp, base, offset & (((1<<12)-1)<<12));
2436 base = tmp;
2437 offset &= ~(((1<<12)-1)<<12);
2438 }
2439
2440 return Address(base, offset);
2441 }
2442
2443 /**
2444 * Multiply 64 bit by 64 bit first loop.
2445 */
2446 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
2447 Register y, Register y_idx, Register z,
2448 Register carry, Register product,
2449 Register idx, Register kdx) {
2450 //
2451 // jlong carry, x[], y[], z[];
2452 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
2453 // huge_128 product = y[idx] * x[xstart] + carry;
2454 // z[kdx] = (jlong)product;
2455 // carry = (jlong)(product >>> 64);
2456 // }
2457 // z[xstart] = carry;
2458 //
2459
2460 Label L_first_loop, L_first_loop_exit;
2461 Label L_one_x, L_one_y, L_multiply;
2462
2463 subsw(xstart, xstart, 1);
2464 br(Assembler::MI, L_one_x);
2465
2466 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
2467 ldr(x_xstart, Address(rscratch1));
2468 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
2469
2470 bind(L_first_loop);
2471 subsw(idx, idx, 1);
2472 br(Assembler::MI, L_first_loop_exit);
2473 subsw(idx, idx, 1);
2474 br(Assembler::MI, L_one_y);
2475 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2476 ldr(y_idx, Address(rscratch1));
2477 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
2478 bind(L_multiply);
2479
2480 // AArch64 has a multiply-accumulate instruction that we can't use
2481 // here because it has no way to process carries, so we have to use
2482 // separate add and adc instructions. Bah.
2483 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
2484 mul(product, x_xstart, y_idx);
2485 adds(product, product, carry);
2486 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
2487
2488 subw(kdx, kdx, 2);
2489 ror(product, product, 32); // back to big-endian
2490 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
2491
2492 b(L_first_loop);
2493
2494 bind(L_one_y);
2495 ldrw(y_idx, Address(y, 0));
2496 b(L_multiply);
2497
2498 bind(L_one_x);
2499 ldrw(x_xstart, Address(x, 0));
2500 b(L_first_loop);
2501
2502 bind(L_first_loop_exit);
2503 }
2504
2505 /**
2506 * Multiply 128 bit by 128. Unrolled inner loop.
2507 *
2508 */
2509 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
2510 Register carry, Register carry2,
2511 Register idx, Register jdx,
2512 Register yz_idx1, Register yz_idx2,
2513 Register tmp, Register tmp3, Register tmp4,
2514 Register tmp6, Register product_hi) {
2515
2516 // jlong carry, x[], y[], z[];
2517 // int kdx = ystart+1;
2518 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
2519 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
2520 // jlong carry2 = (jlong)(tmp3 >>> 64);
2521 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
2522 // carry = (jlong)(tmp4 >>> 64);
2523 // z[kdx+idx+1] = (jlong)tmp3;
2524 // z[kdx+idx] = (jlong)tmp4;
2525 // }
2526 // idx += 2;
2527 // if (idx > 0) {
2528 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
2529 // z[kdx+idx] = (jlong)yz_idx1;
2530 // carry = (jlong)(yz_idx1 >>> 64);
2531 // }
2532 //
2533
2534 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
2535
2536 lsrw(jdx, idx, 2);
2537
2538 bind(L_third_loop);
2539
2540 subsw(jdx, jdx, 1);
2541 br(Assembler::MI, L_third_loop_exit);
2542 subw(idx, idx, 4);
2543
2544 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2545
2546 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
2547
2548 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2549
2550 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
2551 ror(yz_idx2, yz_idx2, 32);
2552
2553 ldp(rscratch2, rscratch1, Address(tmp6, 0));
2554
2555 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
2556 umulh(tmp4, product_hi, yz_idx1);
2557
2558 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
2559 ror(rscratch2, rscratch2, 32);
2560
2561 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
2562 umulh(carry2, product_hi, yz_idx2);
2563
2564 // propagate sum of both multiplications into carry:tmp4:tmp3
2565 adds(tmp3, tmp3, carry);
2566 adc(tmp4, tmp4, zr);
2567 adds(tmp3, tmp3, rscratch1);
2568 adcs(tmp4, tmp4, tmp);
2569 adc(carry, carry2, zr);
2570 adds(tmp4, tmp4, rscratch2);
2571 adc(carry, carry, zr);
2572
2573 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
2574 ror(tmp4, tmp4, 32);
2575 stp(tmp4, tmp3, Address(tmp6, 0));
2576
2577 b(L_third_loop);
2578 bind (L_third_loop_exit);
2579
2580 andw (idx, idx, 0x3);
2581 cbz(idx, L_post_third_loop_done);
2582
2583 Label L_check_1;
2584 subsw(idx, idx, 2);
2585 br(Assembler::MI, L_check_1);
2586
2587 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2588 ldr(yz_idx1, Address(rscratch1, 0));
2589 ror(yz_idx1, yz_idx1, 32);
2590 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
2591 umulh(tmp4, product_hi, yz_idx1);
2592 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2593 ldr(yz_idx2, Address(rscratch1, 0));
2594 ror(yz_idx2, yz_idx2, 32);
2595
2596 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
2597
2598 ror(tmp3, tmp3, 32);
2599 str(tmp3, Address(rscratch1, 0));
2600
2601 bind (L_check_1);
2602
2603 andw (idx, idx, 0x1);
2604 subsw(idx, idx, 1);
2605 br(Assembler::MI, L_post_third_loop_done);
2606 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2607 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
2608 umulh(carry2, tmp4, product_hi);
2609 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2610
2611 add2_with_carry(carry2, tmp3, tmp4, carry);
2612
2613 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2614 extr(carry, carry2, tmp3, 32);
2615
2616 bind(L_post_third_loop_done);
2617 }
2618
2619 /**
2620 * Code for BigInteger::multiplyToLen() instrinsic.
2621 *
2622 * r0: x
2623 * r1: xlen
2624 * r2: y
2625 * r3: ylen
2626 * r4: z
2627 * r5: zlen
2628 * r10: tmp1
2629 * r11: tmp2
2630 * r12: tmp3
2631 * r13: tmp4
2632 * r14: tmp5
2633 * r15: tmp6
2634 * r16: tmp7
2635 *
2636 */
2637 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
2638 Register z, Register zlen,
2639 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
2640 Register tmp5, Register tmp6, Register product_hi) {
2641
2642 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6);
2643
2644 const Register idx = tmp1;
2645 const Register kdx = tmp2;
2646 const Register xstart = tmp3;
2647
2648 const Register y_idx = tmp4;
2649 const Register carry = tmp5;
2650 const Register product = xlen;
2651 const Register x_xstart = zlen; // reuse register
2652
2653 // First Loop.
2654 //
2655 // final static long LONG_MASK = 0xffffffffL;
2656 // int xstart = xlen - 1;
2657 // int ystart = ylen - 1;
2658 // long carry = 0;
2659 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
2660 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
2661 // z[kdx] = (int)product;
2662 // carry = product >>> 32;
2663 // }
2664 // z[xstart] = (int)carry;
2665 //
2666
2667 movw(idx, ylen); // idx = ylen;
2668 movw(kdx, zlen); // kdx = xlen+ylen;
2669 mov(carry, zr); // carry = 0;
2670
2671 Label L_done;
2672
2673 movw(xstart, xlen);
2674 subsw(xstart, xstart, 1);
2675 br(Assembler::MI, L_done);
2676
2677 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
2678
2679 Label L_second_loop;
2680 cbzw(kdx, L_second_loop);
2681
2682 Label L_carry;
2683 subw(kdx, kdx, 1);
2684 cbzw(kdx, L_carry);
2685
2686 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
2687 lsr(carry, carry, 32);
2688 subw(kdx, kdx, 1);
2689
2690 bind(L_carry);
2691 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
2692
2693 // Second and third (nested) loops.
2694 //
2695 // for (int i = xstart-1; i >= 0; i--) { // Second loop
2696 // carry = 0;
2697 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
2698 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
2699 // (z[k] & LONG_MASK) + carry;
2700 // z[k] = (int)product;
2701 // carry = product >>> 32;
2702 // }
2703 // z[i] = (int)carry;
2704 // }
2705 //
2706 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
2707
2708 const Register jdx = tmp1;
2709
2710 bind(L_second_loop);
2711 mov(carry, zr); // carry = 0;
2712 movw(jdx, ylen); // j = ystart+1
2713
2714 subsw(xstart, xstart, 1); // i = xstart-1;
2715 br(Assembler::MI, L_done);
2716
2717 str(z, Address(pre(sp, -4 * wordSize)));
2718
2719 Label L_last_x;
2720 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
2721 subsw(xstart, xstart, 1); // i = xstart-1;
2722 br(Assembler::MI, L_last_x);
2723
2724 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
2725 ldr(product_hi, Address(rscratch1));
2726 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
2727
2728 Label L_third_loop_prologue;
2729 bind(L_third_loop_prologue);
2730
2731 str(ylen, Address(sp, wordSize));
2732 stp(x, xstart, Address(sp, 2 * wordSize));
2733 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
2734 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
2735 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
2736 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
2737
2738 addw(tmp3, xlen, 1);
2739 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
2740 subsw(tmp3, tmp3, 1);
2741 br(Assembler::MI, L_done);
2742
2743 lsr(carry, carry, 32);
2744 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
2745 b(L_second_loop);
2746
2747 // Next infrequent code is moved outside loops.
2748 bind(L_last_x);
2749 ldrw(product_hi, Address(x, 0));
2750 b(L_third_loop_prologue);
2751
2752 bind(L_done);
2753 }
2754
2755 /**
2756 * Emits code to update CRC-32 with a byte value according to constants in table
2757 *
2758 * @param [in,out]crc Register containing the crc.
2759 * @param [in]val Register containing the byte to fold into the CRC.
2760 * @param [in]table Register containing the table of crc constants.
2761 *
2762 * uint32_t crc;
2763 * val = crc_table[(val ^ crc) & 0xFF];
2764 * crc = val ^ (crc >> 8);
2765 *
2766 */
2767 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
2768 eor(val, val, crc);
2769 andr(val, val, 0xff);
2770 ldrw(val, Address(table, val, Address::lsl(2)));
2771 eor(crc, val, crc, Assembler::LSR, 8);
2772 }
2773
2774 /**
2775 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
2776 *
2777 * @param [in,out]crc Register containing the crc.
2778 * @param [in]v Register containing the 32-bit to fold into the CRC.
2779 * @param [in]table0 Register containing table 0 of crc constants.
2780 * @param [in]table1 Register containing table 1 of crc constants.
2781 * @param [in]table2 Register containing table 2 of crc constants.
2782 * @param [in]table3 Register containing table 3 of crc constants.
2783 *
2784 * uint32_t crc;
2785 * v = crc ^ v
2786 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
2787 *
2788 */
2789 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
2790 Register table0, Register table1, Register table2, Register table3,
2791 bool upper) {
2792 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
2793 uxtb(tmp, v);
2794 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
2795 ubfx(tmp, v, 8, 8);
2796 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
2797 eor(crc, crc, tmp);
2798 ubfx(tmp, v, 16, 8);
2799 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
2800 eor(crc, crc, tmp);
2801 ubfx(tmp, v, 24, 8);
2802 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
2803 eor(crc, crc, tmp);
2804 }
2805
2806 /**
2807 * @param crc register containing existing CRC (32-bit)
2808 * @param buf register pointing to input byte buffer (byte*)
2809 * @param len register containing number of bytes
2810 * @param table register that will contain address of CRC table
2811 * @param tmp scratch register
2812 */
2813 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
2814 Register table0, Register table1, Register table2, Register table3,
2815 Register tmp, Register tmp2, Register tmp3) {
2816 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
2817 unsigned long offset;
2818
2819 ornw(crc, zr, crc);
2820
2821 if (UseCRC32) {
2822 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop;
2823
2824 subs(len, len, 64);
2825 br(Assembler::GE, CRC_by64_loop);
2826 adds(len, len, 64-4);
2827 br(Assembler::GE, CRC_by4_loop);
2828 adds(len, len, 4);
2829 br(Assembler::GT, CRC_by1_loop);
2830 b(L_exit);
2831
2832 BIND(CRC_by4_loop);
2833 ldrw(tmp, Address(post(buf, 4)));
2834 subs(len, len, 4);
2835 crc32w(crc, crc, tmp);
2836 br(Assembler::GE, CRC_by4_loop);
2837 adds(len, len, 4);
2838 br(Assembler::LE, L_exit);
2839 BIND(CRC_by1_loop);
2840 ldrb(tmp, Address(post(buf, 1)));
2841 subs(len, len, 1);
2842 crc32b(crc, crc, tmp);
2843 br(Assembler::GT, CRC_by1_loop);
2844 b(L_exit);
2845
2846 align(CodeEntryAlignment);
2847 BIND(CRC_by64_loop);
2848 subs(len, len, 64);
2849 ldp(tmp, tmp3, Address(post(buf, 16)));
2850 crc32x(crc, crc, tmp);
2851 crc32x(crc, crc, tmp3);
2852 ldp(tmp, tmp3, Address(post(buf, 16)));
2853 crc32x(crc, crc, tmp);
2854 crc32x(crc, crc, tmp3);
2855 ldp(tmp, tmp3, Address(post(buf, 16)));
2856 crc32x(crc, crc, tmp);
2857 crc32x(crc, crc, tmp3);
2858 ldp(tmp, tmp3, Address(post(buf, 16)));
2859 crc32x(crc, crc, tmp);
2860 crc32x(crc, crc, tmp3);
2861 br(Assembler::GE, CRC_by64_loop);
2862 adds(len, len, 64-4);
2863 br(Assembler::GE, CRC_by4_loop);
2864 adds(len, len, 4);
2865 br(Assembler::GT, CRC_by1_loop);
2866 BIND(L_exit);
2867 ornw(crc, zr, crc);
2868 return;
2869 }
2870
2871 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2872 if (offset) add(table0, table0, offset);
2873 add(table1, table0, 1*256*sizeof(juint));
2874 add(table2, table0, 2*256*sizeof(juint));
2875 add(table3, table0, 3*256*sizeof(juint));
2876
2877 if (UseNeon) {
2878 cmp(len, 64);
2879 br(Assembler::LT, L_by16);
2880 eor(v16, T16B, v16, v16);
2881
2882 Label L_fold;
2883
2884 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
2885
2886 ld1(v0, v1, T2D, post(buf, 32));
2887 ld1r(v4, T2D, post(tmp, 8));
2888 ld1r(v5, T2D, post(tmp, 8));
2889 ld1r(v6, T2D, post(tmp, 8));
2890 ld1r(v7, T2D, post(tmp, 8));
2891 mov(v16, T4S, 0, crc);
2892
2893 eor(v0, T16B, v0, v16);
2894 sub(len, len, 64);
2895
2896 BIND(L_fold);
2897 pmull(v22, T8H, v0, v5, T8B);
2898 pmull(v20, T8H, v0, v7, T8B);
2899 pmull(v23, T8H, v0, v4, T8B);
2900 pmull(v21, T8H, v0, v6, T8B);
2901
2902 pmull2(v18, T8H, v0, v5, T16B);
2903 pmull2(v16, T8H, v0, v7, T16B);
2904 pmull2(v19, T8H, v0, v4, T16B);
2905 pmull2(v17, T8H, v0, v6, T16B);
2906
2907 uzp1(v24, v20, v22, T8H);
2908 uzp2(v25, v20, v22, T8H);
2909 eor(v20, T16B, v24, v25);
2910
2911 uzp1(v26, v16, v18, T8H);
2912 uzp2(v27, v16, v18, T8H);
2913 eor(v16, T16B, v26, v27);
2914
2915 ushll2(v22, T4S, v20, T8H, 8);
2916 ushll(v20, T4S, v20, T4H, 8);
2917
2918 ushll2(v18, T4S, v16, T8H, 8);
2919 ushll(v16, T4S, v16, T4H, 8);
2920
2921 eor(v22, T16B, v23, v22);
2922 eor(v18, T16B, v19, v18);
2923 eor(v20, T16B, v21, v20);
2924 eor(v16, T16B, v17, v16);
2925
2926 uzp1(v17, v16, v20, T2D);
2927 uzp2(v21, v16, v20, T2D);
2928 eor(v17, T16B, v17, v21);
2929
2930 ushll2(v20, T2D, v17, T4S, 16);
2931 ushll(v16, T2D, v17, T2S, 16);
2932
2933 eor(v20, T16B, v20, v22);
2934 eor(v16, T16B, v16, v18);
2935
2936 uzp1(v17, v20, v16, T2D);
2937 uzp2(v21, v20, v16, T2D);
2938 eor(v28, T16B, v17, v21);
2939
2940 pmull(v22, T8H, v1, v5, T8B);
2941 pmull(v20, T8H, v1, v7, T8B);
2942 pmull(v23, T8H, v1, v4, T8B);
2943 pmull(v21, T8H, v1, v6, T8B);
2944
2945 pmull2(v18, T8H, v1, v5, T16B);
2946 pmull2(v16, T8H, v1, v7, T16B);
2947 pmull2(v19, T8H, v1, v4, T16B);
2948 pmull2(v17, T8H, v1, v6, T16B);
2949
2950 ld1(v0, v1, T2D, post(buf, 32));
2951
2952 uzp1(v24, v20, v22, T8H);
2953 uzp2(v25, v20, v22, T8H);
2954 eor(v20, T16B, v24, v25);
2955
2956 uzp1(v26, v16, v18, T8H);
2957 uzp2(v27, v16, v18, T8H);
2958 eor(v16, T16B, v26, v27);
2959
2960 ushll2(v22, T4S, v20, T8H, 8);
2961 ushll(v20, T4S, v20, T4H, 8);
2962
2963 ushll2(v18, T4S, v16, T8H, 8);
2964 ushll(v16, T4S, v16, T4H, 8);
2965
2966 eor(v22, T16B, v23, v22);
2967 eor(v18, T16B, v19, v18);
2968 eor(v20, T16B, v21, v20);
2969 eor(v16, T16B, v17, v16);
2970
2971 uzp1(v17, v16, v20, T2D);
2972 uzp2(v21, v16, v20, T2D);
2973 eor(v16, T16B, v17, v21);
2974
2975 ushll2(v20, T2D, v16, T4S, 16);
2976 ushll(v16, T2D, v16, T2S, 16);
2977
2978 eor(v20, T16B, v22, v20);
2979 eor(v16, T16B, v16, v18);
2980
2981 uzp1(v17, v20, v16, T2D);
2982 uzp2(v21, v20, v16, T2D);
2983 eor(v20, T16B, v17, v21);
2984
2985 shl(v16, T2D, v28, 1);
2986 shl(v17, T2D, v20, 1);
2987
2988 eor(v0, T16B, v0, v16);
2989 eor(v1, T16B, v1, v17);
2990
2991 subs(len, len, 32);
2992 br(Assembler::GE, L_fold);
2993
2994 mov(crc, 0);
2995 mov(tmp, v0, T1D, 0);
2996 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
2997 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
2998 mov(tmp, v0, T1D, 1);
2999 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3000 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3001 mov(tmp, v1, T1D, 0);
3002 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3003 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3004 mov(tmp, v1, T1D, 1);
3005 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3006 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3007
3008 add(len, len, 32);
3009 }
3010
3011 BIND(L_by16);
3012 subs(len, len, 16);
3013 br(Assembler::GE, L_by16_loop);
3014 adds(len, len, 16-4);
3015 br(Assembler::GE, L_by4_loop);
3016 adds(len, len, 4);
3017 br(Assembler::GT, L_by1_loop);
3018 b(L_exit);
3019
3020 BIND(L_by4_loop);
3021 ldrw(tmp, Address(post(buf, 4)));
3022 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
3023 subs(len, len, 4);
3024 br(Assembler::GE, L_by4_loop);
3025 adds(len, len, 4);
3026 br(Assembler::LE, L_exit);
3027 BIND(L_by1_loop);
3028 subs(len, len, 1);
3029 ldrb(tmp, Address(post(buf, 1)));
3030 update_byte_crc32(crc, tmp, table0);
3031 br(Assembler::GT, L_by1_loop);
3032 b(L_exit);
3033
3034 align(CodeEntryAlignment);
3035 BIND(L_by16_loop);
3036 subs(len, len, 16);
3037 ldp(tmp, tmp3, Address(post(buf, 16)));
3038 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3039 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3040 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
3041 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
3042 br(Assembler::GE, L_by16_loop);
3043 adds(len, len, 16-4);
3044 br(Assembler::GE, L_by4_loop);
3045 adds(len, len, 4);
3046 br(Assembler::GT, L_by1_loop);
3047 BIND(L_exit);
3048 ornw(crc, zr, crc);
3049 }
3050
3051 /**
3052 * @param crc register containing existing CRC (32-bit)
3053 * @param buf register pointing to input byte buffer (byte*)
3054 * @param len register containing number of bytes
3055 * @param table register that will contain address of CRC table
3056 * @param tmp scratch register
3057 */
3058 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
3059 Register table0, Register table1, Register table2, Register table3,
3060 Register tmp, Register tmp2, Register tmp3) {
3061 Label L_exit;
3062 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop;
3063
3064 subs(len, len, 64);
3065 br(Assembler::GE, CRC_by64_loop);
3066 adds(len, len, 64-4);
3067 br(Assembler::GE, CRC_by4_loop);
3068 adds(len, len, 4);
3069 br(Assembler::GT, CRC_by1_loop);
3070 b(L_exit);
3071
3072 BIND(CRC_by4_loop);
3073 ldrw(tmp, Address(post(buf, 4)));
3074 subs(len, len, 4);
3075 crc32cw(crc, crc, tmp);
3076 br(Assembler::GE, CRC_by4_loop);
3077 adds(len, len, 4);
3078 br(Assembler::LE, L_exit);
3079 BIND(CRC_by1_loop);
3080 ldrb(tmp, Address(post(buf, 1)));
3081 subs(len, len, 1);
3082 crc32cb(crc, crc, tmp);
3083 br(Assembler::GT, CRC_by1_loop);
3084 b(L_exit);
3085
3086 align(CodeEntryAlignment);
3087 BIND(CRC_by64_loop);
3088 subs(len, len, 64);
3089 ldp(tmp, tmp3, Address(post(buf, 16)));
3090 crc32cx(crc, crc, tmp);
3091 crc32cx(crc, crc, tmp3);
3092 ldp(tmp, tmp3, Address(post(buf, 16)));
3093 crc32cx(crc, crc, tmp);
3094 crc32cx(crc, crc, tmp3);
3095 ldp(tmp, tmp3, Address(post(buf, 16)));
3096 crc32cx(crc, crc, tmp);
3097 crc32cx(crc, crc, tmp3);
3098 ldp(tmp, tmp3, Address(post(buf, 16)));
3099 crc32cx(crc, crc, tmp);
3100 crc32cx(crc, crc, tmp3);
3101 br(Assembler::GE, CRC_by64_loop);
3102 adds(len, len, 64-4);
3103 br(Assembler::GE, CRC_by4_loop);
3104 adds(len, len, 4);
3105 br(Assembler::GT, CRC_by1_loop);
3106 BIND(L_exit);
3107 return;
3108 }
3109
3110 SkipIfEqual::SkipIfEqual(
3111 MacroAssembler* masm, const bool* flag_addr, bool value) {
3112 _masm = masm;
3113 unsigned long offset;
3114 _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset);
3115 _masm->ldrb(rscratch1, Address(rscratch1, offset));
3116 _masm->cbzw(rscratch1, _label);
3117 }
3118
3119 SkipIfEqual::~SkipIfEqual() {
3120 _masm->bind(_label);
3121 }
3122
3123 void MacroAssembler::addptr(const Address &dst, int32_t src) {
3124 Address adr;
3125 switch(dst.getMode()) {
3126 case Address::base_plus_offset:
3127 // This is the expected mode, although we allow all the other
3128 // forms below.
3129 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
3130 break;
3131 default:
3132 lea(rscratch2, dst);
3133 adr = Address(rscratch2);
3134 break;
3135 }
3136 ldr(rscratch1, adr);
3137 add(rscratch1, rscratch1, src);
3138 str(rscratch1, adr);
3139 }
3140
3141 void MacroAssembler::cmpptr(Register src1, Address src2) {
3142 unsigned long offset;
3143 adrp(rscratch1, src2, offset);
3144 ldr(rscratch1, Address(rscratch1, offset));
3145 cmp(src1, rscratch1);
3146 }
3147
3148 void MacroAssembler::store_check(Register obj, Address dst) {
3149 store_check(obj);
3150 }
3151
3152 void MacroAssembler::store_check(Register obj) {
3153 // Does a store check for the oop in register obj. The content of
3154 // register obj is destroyed afterwards.
3155
3156 BarrierSet* bs = Universe::heap()->barrier_set();
3157 assert(bs->kind() == BarrierSet::CardTableForRS ||
3158 bs->kind() == BarrierSet::CardTableExtension,
3159 "Wrong barrier set kind");
3160
3161 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
3162 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3163
3164 lsr(obj, obj, CardTableModRefBS::card_shift);
3165
3166 assert(CardTableModRefBS::dirty_card_val() == 0, "must be");
3167
3168 load_byte_map_base(rscratch1);
3169
3170 if (UseCondCardMark) {
3171 Label L_already_dirty;
3172 membar(StoreLoad);
3173 ldrb(rscratch2, Address(obj, rscratch1));
3174 cbz(rscratch2, L_already_dirty);
3175 strb(zr, Address(obj, rscratch1));
3176 bind(L_already_dirty);
3177 } else {
3178 if (UseConcMarkSweepGC && CMSPrecleaningEnabled) {
3179 membar(StoreStore);
3180 }
3181 strb(zr, Address(obj, rscratch1));
3182 }
3183 }
3184
3185 void MacroAssembler::load_klass(Register dst, Register src) {
3186 if (UseCompressedClassPointers) {
3187 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3188 decode_klass_not_null(dst);
3189 } else {
3190 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3191 }
3192 }
3193
3194 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
3195 if (UseCompressedClassPointers) {
3196 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3197 if (Universe::narrow_klass_base() == NULL) {
3198 cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift());
3199 return;
3200 } else if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3201 && Universe::narrow_klass_shift() == 0) {
3202 // Only the bottom 32 bits matter
3203 cmpw(trial_klass, tmp);
3204 return;
3205 }
3206 decode_klass_not_null(tmp);
3207 } else {
3208 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3209 }
3210 cmp(trial_klass, tmp);
3211 }
3212
3213 void MacroAssembler::load_prototype_header(Register dst, Register src) {
3214 load_klass(dst, src);
3215 ldr(dst, Address(dst, Klass::prototype_header_offset()));
3216 }
3217
3218 void MacroAssembler::store_klass(Register dst, Register src) {
3219 // FIXME: Should this be a store release? concurrent gcs assumes
3220 // klass length is valid if klass field is not null.
3221 if (UseCompressedClassPointers) {
3222 encode_klass_not_null(src);
3223 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3224 } else {
3225 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3226 }
3227 }
3228
3229 void MacroAssembler::store_klass_gap(Register dst, Register src) {
3230 if (UseCompressedClassPointers) {
3231 // Store to klass gap in destination
3232 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
3233 }
3234 }
3235
3236 // Algorithm must match oop.inline.hpp encode_heap_oop.
3237 void MacroAssembler::encode_heap_oop(Register d, Register s) {
3238 #ifdef ASSERT
3239 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
3240 #endif
3241 verify_oop(s, "broken oop in encode_heap_oop");
3242 if (Universe::narrow_oop_base() == NULL) {
3243 if (Universe::narrow_oop_shift() != 0) {
3244 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3245 lsr(d, s, LogMinObjAlignmentInBytes);
3246 } else {
3247 mov(d, s);
3248 }
3249 } else {
3250 subs(d, s, rheapbase);
3251 csel(d, d, zr, Assembler::HS);
3252 lsr(d, d, LogMinObjAlignmentInBytes);
3253
3254 /* Old algorithm: is this any worse?
3255 Label nonnull;
3256 cbnz(r, nonnull);
3257 sub(r, r, rheapbase);
3258 bind(nonnull);
3259 lsr(r, r, LogMinObjAlignmentInBytes);
3260 */
3261 }
3262 }
3263
3264 void MacroAssembler::encode_heap_oop_not_null(Register r) {
3265 #ifdef ASSERT
3266 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
3267 if (CheckCompressedOops) {
3268 Label ok;
3269 cbnz(r, ok);
3270 stop("null oop passed to encode_heap_oop_not_null");
3271 bind(ok);
3272 }
3273 #endif
3274 verify_oop(r, "broken oop in encode_heap_oop_not_null");
3275 if (Universe::narrow_oop_base() != NULL) {
3276 sub(r, r, rheapbase);
3277 }
3278 if (Universe::narrow_oop_shift() != 0) {
3279 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3280 lsr(r, r, LogMinObjAlignmentInBytes);
3281 }
3282 }
3283
3284 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
3285 #ifdef ASSERT
3286 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
3287 if (CheckCompressedOops) {
3288 Label ok;
3289 cbnz(src, ok);
3290 stop("null oop passed to encode_heap_oop_not_null2");
3291 bind(ok);
3292 }
3293 #endif
3294 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
3295
3296 Register data = src;
3297 if (Universe::narrow_oop_base() != NULL) {
3298 sub(dst, src, rheapbase);
3299 data = dst;
3300 }
3301 if (Universe::narrow_oop_shift() != 0) {
3302 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3303 lsr(dst, data, LogMinObjAlignmentInBytes);
3304 data = dst;
3305 }
3306 if (data == src)
3307 mov(dst, src);
3308 }
3309
3310 void MacroAssembler::decode_heap_oop(Register d, Register s) {
3311 #ifdef ASSERT
3312 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
3313 #endif
3314 if (Universe::narrow_oop_base() == NULL) {
3315 if (Universe::narrow_oop_shift() != 0 || d != s) {
3316 lsl(d, s, Universe::narrow_oop_shift());
3317 }
3318 } else {
3319 Label done;
3320 if (d != s)
3321 mov(d, s);
3322 cbz(s, done);
3323 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
3324 bind(done);
3325 }
3326 verify_oop(d, "broken oop in decode_heap_oop");
3327 }
3328
3329 void MacroAssembler::decode_heap_oop_not_null(Register r) {
3330 assert (UseCompressedOops, "should only be used for compressed headers");
3331 assert (Universe::heap() != NULL, "java heap should be initialized");
3332 // Cannot assert, unverified entry point counts instructions (see .ad file)
3333 // vtableStubs also counts instructions in pd_code_size_limit.
3334 // Also do not verify_oop as this is called by verify_oop.
3335 if (Universe::narrow_oop_shift() != 0) {
3336 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3337 if (Universe::narrow_oop_base() != NULL) {
3338 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
3339 } else {
3340 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
3341 }
3342 } else {
3343 assert (Universe::narrow_oop_base() == NULL, "sanity");
3344 }
3345 }
3346
3347 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
3348 assert (UseCompressedOops, "should only be used for compressed headers");
3349 assert (Universe::heap() != NULL, "java heap should be initialized");
3350 // Cannot assert, unverified entry point counts instructions (see .ad file)
3351 // vtableStubs also counts instructions in pd_code_size_limit.
3352 // Also do not verify_oop as this is called by verify_oop.
3353 if (Universe::narrow_oop_shift() != 0) {
3354 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3355 if (Universe::narrow_oop_base() != NULL) {
3356 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
3357 } else {
3358 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
3359 }
3360 } else {
3361 assert (Universe::narrow_oop_base() == NULL, "sanity");
3362 if (dst != src) {
3363 mov(dst, src);
3364 }
3365 }
3366 }
3367
3368 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
3369 if (Universe::narrow_klass_base() == NULL) {
3370 if (Universe::narrow_klass_shift() != 0) {
3371 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3372 lsr(dst, src, LogKlassAlignmentInBytes);
3373 } else {
3374 if (dst != src) mov(dst, src);
3375 }
3376 return;
3377 }
3378
3379 if (use_XOR_for_compressed_class_base) {
3380 if (Universe::narrow_klass_shift() != 0) {
3381 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3382 lsr(dst, dst, LogKlassAlignmentInBytes);
3383 } else {
3384 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3385 }
3386 return;
3387 }
3388
3389 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3390 && Universe::narrow_klass_shift() == 0) {
3391 movw(dst, src);
3392 return;
3393 }
3394
3395 #ifdef ASSERT
3396 verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?");
3397 #endif
3398
3399 Register rbase = dst;
3400 if (dst == src) rbase = rheapbase;
3401 mov(rbase, (uint64_t)Universe::narrow_klass_base());
3402 sub(dst, src, rbase);
3403 if (Universe::narrow_klass_shift() != 0) {
3404 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3405 lsr(dst, dst, LogKlassAlignmentInBytes);
3406 }
3407 if (dst == src) reinit_heapbase();
3408 }
3409
3410 void MacroAssembler::encode_klass_not_null(Register r) {
3411 encode_klass_not_null(r, r);
3412 }
3413
3414 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
3415 Register rbase = dst;
3416 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3417
3418 if (Universe::narrow_klass_base() == NULL) {
3419 if (Universe::narrow_klass_shift() != 0) {
3420 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3421 lsl(dst, src, LogKlassAlignmentInBytes);
3422 } else {
3423 if (dst != src) mov(dst, src);
3424 }
3425 return;
3426 }
3427
3428 if (use_XOR_for_compressed_class_base) {
3429 if (Universe::narrow_klass_shift() != 0) {
3430 lsl(dst, src, LogKlassAlignmentInBytes);
3431 eor(dst, dst, (uint64_t)Universe::narrow_klass_base());
3432 } else {
3433 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3434 }
3435 return;
3436 }
3437
3438 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3439 && Universe::narrow_klass_shift() == 0) {
3440 if (dst != src)
3441 movw(dst, src);
3442 movk(dst, (uint64_t)Universe::narrow_klass_base() >> 32, 32);
3443 return;
3444 }
3445
3446 // Cannot assert, unverified entry point counts instructions (see .ad file)
3447 // vtableStubs also counts instructions in pd_code_size_limit.
3448 // Also do not verify_oop as this is called by verify_oop.
3449 if (dst == src) rbase = rheapbase;
3450 mov(rbase, (uint64_t)Universe::narrow_klass_base());
3451 if (Universe::narrow_klass_shift() != 0) {
3452 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3453 add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes);
3454 } else {
3455 add(dst, rbase, src);
3456 }
3457 if (dst == src) reinit_heapbase();
3458 }
3459
3460 void MacroAssembler::decode_klass_not_null(Register r) {
3461 decode_klass_not_null(r, r);
3462 }
3463
3464 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
3465 assert (UseCompressedOops, "should only be used for compressed oops");
3466 assert (Universe::heap() != NULL, "java heap should be initialized");
3467 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
3468
3469 int oop_index = oop_recorder()->find_index(obj);
3470 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop");
3471
3472 InstructionMark im(this);
3473 RelocationHolder rspec = oop_Relocation::spec(oop_index);
3474 code_section()->relocate(inst_mark(), rspec);
3475 movz(dst, 0xDEAD, 16);
3476 movk(dst, 0xBEEF);
3477 }
3478
3479 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
3480 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3481 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
3482 int index = oop_recorder()->find_index(k);
3483 assert(! Universe::heap()->is_in_reserved(k), "should not be an oop");
3484
3485 InstructionMark im(this);
3486 RelocationHolder rspec = metadata_Relocation::spec(index);
3487 code_section()->relocate(inst_mark(), rspec);
3488 narrowKlass nk = Klass::encode_klass(k);
3489 movz(dst, (nk >> 16), 16);
3490 movk(dst, nk & 0xffff);
3491 }
3492
3493 void MacroAssembler::load_heap_oop(Register dst, Address src)
3494 {
3495 if (UseCompressedOops) {
3496 ldrw(dst, src);
3497 decode_heap_oop(dst);
3498 } else {
3499 ldr(dst, src);
3500 }
3501 }
3502
3503 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src)
3504 {
3505 if (UseCompressedOops) {
3506 ldrw(dst, src);
3507 decode_heap_oop_not_null(dst);
3508 } else {
3509 ldr(dst, src);
3510 }
3511 }
3512
3513 void MacroAssembler::store_heap_oop(Address dst, Register src) {
3514 if (UseCompressedOops) {
3515 assert(!dst.uses(src), "not enough registers");
3516 encode_heap_oop(src);
3517 strw(src, dst);
3518 } else
3519 str(src, dst);
3520 }
3521
3522 // Used for storing NULLs.
3523 void MacroAssembler::store_heap_oop_null(Address dst) {
3524 if (UseCompressedOops) {
3525 strw(zr, dst);
3526 } else
3527 str(zr, dst);
3528 }
3529
3530 #if INCLUDE_ALL_GCS
3531 void MacroAssembler::g1_write_barrier_pre(Register obj,
3532 Register pre_val,
3533 Register thread,
3534 Register tmp,
3535 bool tosca_live,
3536 bool expand_call) {
3537 // If expand_call is true then we expand the call_VM_leaf macro
3538 // directly to skip generating the check by
3539 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
3540
3541 assert(thread == rthread, "must be");
3542
3543 Label done;
3544 Label runtime;
3545
3546 assert(pre_val != noreg, "check this code");
3547
3548 if (obj != noreg)
3549 assert_different_registers(obj, pre_val, tmp);
3550
3551 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
3552 SATBMarkQueue::byte_offset_of_active()));
3553 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
3554 SATBMarkQueue::byte_offset_of_index()));
3555 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
3556 SATBMarkQueue::byte_offset_of_buf()));
3557
3558
3559 // Is marking active?
3560 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
3561 ldrw(tmp, in_progress);
3562 } else {
3563 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
3564 ldrb(tmp, in_progress);
3565 }
3566 cbzw(tmp, done);
3567
3568 // Do we need to load the previous value?
3569 if (obj != noreg) {
3570 load_heap_oop(pre_val, Address(obj, 0));
3571 }
3572
3573 // Is the previous value null?
3574 cbz(pre_val, done);
3575
3576 // Can we store original value in the thread's buffer?
3577 // Is index == 0?
3578 // (The index field is typed as size_t.)
3579
3580 ldr(tmp, index); // tmp := *index_adr
3581 cbz(tmp, runtime); // tmp == 0?
3582 // If yes, goto runtime
3583
3584 sub(tmp, tmp, wordSize); // tmp := tmp - wordSize
3585 str(tmp, index); // *index_adr := tmp
3586 ldr(rscratch1, buffer);
3587 add(tmp, tmp, rscratch1); // tmp := tmp + *buffer_adr
3588
3589 // Record the previous value
3590 str(pre_val, Address(tmp, 0));
3591 b(done);
3592
3593 bind(runtime);
3594 // save the live input values
3595 push(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp);
3596
3597 // Calling the runtime using the regular call_VM_leaf mechanism generates
3598 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
3599 // that checks that the *(rfp+frame::interpreter_frame_last_sp) == NULL.
3600 //
3601 // If we care generating the pre-barrier without a frame (e.g. in the
3602 // intrinsified Reference.get() routine) then ebp might be pointing to
3603 // the caller frame and so this check will most likely fail at runtime.
3604 //
3605 // Expanding the call directly bypasses the generation of the check.
3606 // So when we do not have have a full interpreter frame on the stack
3607 // expand_call should be passed true.
3608
3609 if (expand_call) {
3610 assert(pre_val != c_rarg1, "smashed arg");
3611 pass_arg1(this, thread);
3612 pass_arg0(this, pre_val);
3613 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
3614 } else {
3615 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
3616 }
3617
3618 pop(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp);
3619
3620 bind(done);
3621 }
3622
3623 void MacroAssembler::g1_write_barrier_post(Register store_addr,
3624 Register new_val,
3625 Register thread,
3626 Register tmp,
3627 Register tmp2) {
3628 assert(thread == rthread, "must be");
3629
3630 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
3631 DirtyCardQueue::byte_offset_of_index()));
3632 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
3633 DirtyCardQueue::byte_offset_of_buf()));
3634
3635 BarrierSet* bs = Universe::heap()->barrier_set();
3636 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
3637 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3638
3639 Label done;
3640 Label runtime;
3641
3642 // Does store cross heap regions?
3643
3644 eor(tmp, store_addr, new_val);
3645 lsr(tmp, tmp, HeapRegion::LogOfHRGrainBytes);
3646 cbz(tmp, done);
3647
3648 // crosses regions, storing NULL?
3649
3650 cbz(new_val, done);
3651
3652 // storing region crossing non-NULL, is card already dirty?
3653
3654 ExternalAddress cardtable((address) ct->byte_map_base);
3655 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3656 const Register card_addr = tmp;
3657
3658 lsr(card_addr, store_addr, CardTableModRefBS::card_shift);
3659
3660 // get the address of the card
3661 load_byte_map_base(tmp2);
3662 add(card_addr, card_addr, tmp2);
3663 ldrb(tmp2, Address(card_addr));
3664 cmpw(tmp2, (int)G1SATBCardTableModRefBS::g1_young_card_val());
3665 br(Assembler::EQ, done);
3666
3667 assert((int)CardTableModRefBS::dirty_card_val() == 0, "must be 0");
3668
3669 membar(Assembler::StoreLoad);
3670
3671 ldrb(tmp2, Address(card_addr));
3672 cbzw(tmp2, done);
3673
3674 // storing a region crossing, non-NULL oop, card is clean.
3675 // dirty card and log.
3676
3677 strb(zr, Address(card_addr));
3678
3679 ldr(rscratch1, queue_index);
3680 cbz(rscratch1, runtime);
3681 sub(rscratch1, rscratch1, wordSize);
3682 str(rscratch1, queue_index);
3683
3684 ldr(tmp2, buffer);
3685 str(card_addr, Address(tmp2, rscratch1));
3686 b(done);
3687
3688 bind(runtime);
3689 // save the live input values
3690 push(store_addr->bit(true) | new_val->bit(true), sp);
3691 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
3692 pop(store_addr->bit(true) | new_val->bit(true), sp);
3693
3694 bind(done);
3695 }
3696
3697 #endif // INCLUDE_ALL_GCS
3698
3699 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
3700 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
3701 int index = oop_recorder()->allocate_metadata_index(obj);
3702 RelocationHolder rspec = metadata_Relocation::spec(index);
3703 return Address((address)obj, rspec);
3704 }
3705
3706 // Move an oop into a register. immediate is true if we want
3707 // immediate instrcutions, i.e. we are not going to patch this
3708 // instruction while the code is being executed by another thread. In
3709 // that case we can use move immediates rather than the constant pool.
3710 void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) {
3711 int oop_index;
3712 if (obj == NULL) {
3713 oop_index = oop_recorder()->allocate_oop_index(obj);
3714 } else {
3715 oop_index = oop_recorder()->find_index(obj);
3716 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop");
3717 }
3718 RelocationHolder rspec = oop_Relocation::spec(oop_index);
3719 if (! immediate) {
3720 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
3721 ldr_constant(dst, Address(dummy, rspec));
3722 } else
3723 mov(dst, Address((address)obj, rspec));
3724 }
3725
3726 // Move a metadata address into a register.
3727 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
3728 int oop_index;
3729 if (obj == NULL) {
3730 oop_index = oop_recorder()->allocate_metadata_index(obj);
3731 } else {
3732 oop_index = oop_recorder()->find_index(obj);
3733 }
3734 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
3735 mov(dst, Address((address)obj, rspec));
3736 }
3737
3738 Address MacroAssembler::constant_oop_address(jobject obj) {
3739 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
3740 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop");
3741 int oop_index = oop_recorder()->find_index(obj);
3742 return Address((address)obj, oop_Relocation::spec(oop_index));
3743 }
3744
3745 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3746 void MacroAssembler::tlab_allocate(Register obj,
3747 Register var_size_in_bytes,
3748 int con_size_in_bytes,
3749 Register t1,
3750 Register t2,
3751 Label& slow_case) {
3752 assert_different_registers(obj, t2);
3753 assert_different_registers(obj, var_size_in_bytes);
3754 Register end = t2;
3755
3756 // verify_tlab();
3757
3758 ldr(obj, Address(rthread, JavaThread::tlab_top_offset()));
3759 if (var_size_in_bytes == noreg) {
3760 lea(end, Address(obj, con_size_in_bytes));
3761 } else {
3762 lea(end, Address(obj, var_size_in_bytes));
3763 }
3764 ldr(rscratch1, Address(rthread, JavaThread::tlab_end_offset()));
3765 cmp(end, rscratch1);
3766 br(Assembler::HI, slow_case);
3767
3768 // update the tlab top pointer
3769 str(end, Address(rthread, JavaThread::tlab_top_offset()));
3770
3771 // recover var_size_in_bytes if necessary
3772 if (var_size_in_bytes == end) {
3773 sub(var_size_in_bytes, var_size_in_bytes, obj);
3774 }
3775 // verify_tlab();
3776 }
3777
3778 // Preserves r19, and r3.
3779 Register MacroAssembler::tlab_refill(Label& retry,
3780 Label& try_eden,
3781 Label& slow_case) {
3782 Register top = r0;
3783 Register t1 = r2;
3784 Register t2 = r4;
3785 assert_different_registers(top, rthread, t1, t2, /* preserve: */ r19, r3);
3786 Label do_refill, discard_tlab;
3787
3788 if (!Universe::heap()->supports_inline_contig_alloc()) {
3789 // No allocation in the shared eden.
3790 b(slow_case);
3791 }
3792
3793 ldr(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3794 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
3795
3796 // calculate amount of free space
3797 sub(t1, t1, top);
3798 lsr(t1, t1, LogHeapWordSize);
3799
3800 // Retain tlab and allocate object in shared space if
3801 // the amount free in the tlab is too large to discard.
3802
3803 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
3804 cmp(t1, rscratch1);
3805 br(Assembler::LE, discard_tlab);
3806
3807 // Retain
3808 // ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
3809 mov(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
3810 add(rscratch1, rscratch1, t2);
3811 str(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
3812
3813 if (TLABStats) {
3814 // increment number of slow_allocations
3815 addmw(Address(rthread, in_bytes(JavaThread::tlab_slow_allocations_offset())),
3816 1, rscratch1);
3817 }
3818 b(try_eden);
3819
3820 bind(discard_tlab);
3821 if (TLABStats) {
3822 // increment number of refills
3823 addmw(Address(rthread, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1,
3824 rscratch1);
3825 // accumulate wastage -- t1 is amount free in tlab
3826 addmw(Address(rthread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1,
3827 rscratch1);
3828 }
3829
3830 // if tlab is currently allocated (top or end != null) then
3831 // fill [top, end + alignment_reserve) with array object
3832 cbz(top, do_refill);
3833
3834 // set up the mark word
3835 mov(rscratch1, (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
3836 str(rscratch1, Address(top, oopDesc::mark_offset_in_bytes()));
3837 // set the length to the remaining space
3838 sub(t1, t1, typeArrayOopDesc::header_size(T_INT));
3839 add(t1, t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
3840 lsl(t1, t1, log2_intptr(HeapWordSize/sizeof(jint)));
3841 strw(t1, Address(top, arrayOopDesc::length_offset_in_bytes()));
3842 // set klass to intArrayKlass
3843 {
3844 unsigned long offset;
3845 // dubious reloc why not an oop reloc?
3846 adrp(rscratch1, ExternalAddress((address)Universe::intArrayKlassObj_addr()),
3847 offset);
3848 ldr(t1, Address(rscratch1, offset));
3849 }
3850 // store klass last. concurrent gcs assumes klass length is valid if
3851 // klass field is not null.
3852 store_klass(top, t1);
3853
3854 mov(t1, top);
3855 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
3856 sub(t1, t1, rscratch1);
3857 incr_allocated_bytes(rthread, t1, 0, rscratch1);
3858
3859 // refill the tlab with an eden allocation
3860 bind(do_refill);
3861 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_size_offset())));
3862 lsl(t1, t1, LogHeapWordSize);
3863 // allocate new tlab, address returned in top
3864 eden_allocate(top, t1, 0, t2, slow_case);
3865
3866 // Check that t1 was preserved in eden_allocate.
3867 #ifdef ASSERT
3868 if (UseTLAB) {
3869 Label ok;
3870 Register tsize = r4;
3871 assert_different_registers(tsize, rthread, t1);
3872 str(tsize, Address(pre(sp, -16)));
3873 ldr(tsize, Address(rthread, in_bytes(JavaThread::tlab_size_offset())));
3874 lsl(tsize, tsize, LogHeapWordSize);
3875 cmp(t1, tsize);
3876 br(Assembler::EQ, ok);
3877 STOP("assert(t1 != tlab size)");
3878 should_not_reach_here();
3879
3880 bind(ok);
3881 ldr(tsize, Address(post(sp, 16)));
3882 }
3883 #endif
3884 str(top, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
3885 str(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3886 add(top, top, t1);
3887 sub(top, top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
3888 str(top, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
3889 verify_tlab();
3890 b(retry);
3891
3892 return rthread; // for use by caller
3893 }
3894
3895 // Defines obj, preserves var_size_in_bytes
3896 void MacroAssembler::eden_allocate(Register obj,
3897 Register var_size_in_bytes,
3898 int con_size_in_bytes,
3899 Register t1,
3900 Label& slow_case) {
3901 assert_different_registers(obj, var_size_in_bytes, t1);
3902 if (!Universe::heap()->supports_inline_contig_alloc()) {
3903 b(slow_case);
3904 } else {
3905 Register end = t1;
3906 Register heap_end = rscratch2;
3907 Label retry;
3908 bind(retry);
3909 {
3910 unsigned long offset;
3911 adrp(rscratch1, ExternalAddress((address) Universe::heap()->end_addr()), offset);
3912 ldr(heap_end, Address(rscratch1, offset));
3913 }
3914
3915 ExternalAddress heap_top((address) Universe::heap()->top_addr());
3916
3917 // Get the current top of the heap
3918 {
3919 unsigned long offset;
3920 adrp(rscratch1, heap_top, offset);
3921 // Use add() here after ARDP, rather than lea().
3922 // lea() does not generate anything if its offset is zero.
3923 // However, relocs expect to find either an ADD or a load/store
3924 // insn after an ADRP. add() always generates an ADD insn, even
3925 // for add(Rn, Rn, 0).
3926 add(rscratch1, rscratch1, offset);
3927 ldaxr(obj, rscratch1);
3928 }
3929
3930 // Adjust it my the size of our new object
3931 if (var_size_in_bytes == noreg) {
3932 lea(end, Address(obj, con_size_in_bytes));
3933 } else {
3934 lea(end, Address(obj, var_size_in_bytes));
3935 }
3936
3937 // if end < obj then we wrapped around high memory
3938 cmp(end, obj);
3939 br(Assembler::LO, slow_case);
3940
3941 cmp(end, heap_end);
3942 br(Assembler::HI, slow_case);
3943
3944 // If heap_top hasn't been changed by some other thread, update it.
3945 stlxr(rscratch2, end, rscratch1);
3946 cbnzw(rscratch2, retry);
3947 }
3948 }
3949
3950 void MacroAssembler::verify_tlab() {
3951 #ifdef ASSERT
3952 if (UseTLAB && VerifyOops) {
3953 Label next, ok;
3954
3955 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
3956
3957 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3958 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
3959 cmp(rscratch2, rscratch1);
3960 br(Assembler::HS, next);
3961 STOP("assert(top >= start)");
3962 should_not_reach_here();
3963
3964 bind(next);
3965 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
3966 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3967 cmp(rscratch2, rscratch1);
3968 br(Assembler::HS, ok);
3969 STOP("assert(top <= end)");
3970 should_not_reach_here();
3971
3972 bind(ok);
3973 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
3974 }
3975 #endif
3976 }
3977
3978 // Writes to stack successive pages until offset reached to check for
3979 // stack overflow + shadow pages. This clobbers tmp.
3980 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
3981 assert_different_registers(tmp, size, rscratch1);
3982 mov(tmp, sp);
3983 // Bang stack for total size given plus shadow page size.
3984 // Bang one page at a time because large size can bang beyond yellow and
3985 // red zones.
3986 Label loop;
3987 mov(rscratch1, os::vm_page_size());
3988 bind(loop);
3989 lea(tmp, Address(tmp, -os::vm_page_size()));
3990 subsw(size, size, rscratch1);
3991 str(size, Address(tmp));
3992 br(Assembler::GT, loop);
3993
3994 // Bang down shadow pages too.
3995 // At this point, (tmp-0) is the last address touched, so don't
3996 // touch it again. (It was touched as (tmp-pagesize) but then tmp
3997 // was post-decremented.) Skip this address by starting at i=1, and
3998 // touch a few more pages below. N.B. It is important to touch all
3999 // the way down to and including i=StackShadowPages.
4000 for (int i = 0; i < (int)(JavaThread::stack_shadow_zone_size() / os::vm_page_size()) - 1; i++) {
4001 // this could be any sized move but this is can be a debugging crumb
4002 // so the bigger the better.
4003 lea(tmp, Address(tmp, -os::vm_page_size()));
4004 str(size, Address(tmp));
4005 }
4006 }
4007
4008
4009 address MacroAssembler::read_polling_page(Register r, address page, relocInfo::relocType rtype) {
4010 unsigned long off;
4011 adrp(r, Address(page, rtype), off);
4012 InstructionMark im(this);
4013 code_section()->relocate(inst_mark(), rtype);
4014 ldrw(zr, Address(r, off));
4015 return inst_mark();
4016 }
4017
4018 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
4019 InstructionMark im(this);
4020 code_section()->relocate(inst_mark(), rtype);
4021 ldrw(zr, Address(r, 0));
4022 return inst_mark();
4023 }
4024
4025 void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
4026 relocInfo::relocType rtype = dest.rspec().reloc()->type();
4027 unsigned long low_page = (unsigned long)CodeCache::low_bound() >> 12;
4028 unsigned long high_page = (unsigned long)(CodeCache::high_bound()-1) >> 12;
4029 unsigned long dest_page = (unsigned long)dest.target() >> 12;
4030 long offset_low = dest_page - low_page;
4031 long offset_high = dest_page - high_page;
4032
4033 assert(is_valid_AArch64_address(dest.target()), "bad address");
4034 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
4035
4036 InstructionMark im(this);
4037 code_section()->relocate(inst_mark(), dest.rspec());
4038 // 8143067: Ensure that the adrp can reach the dest from anywhere within
4039 // the code cache so that if it is relocated we know it will still reach
4040 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
4041 _adrp(reg1, dest.target());
4042 } else {
4043 unsigned long target = (unsigned long)dest.target();
4044 unsigned long adrp_target
4045 = (target & 0xffffffffUL) | ((unsigned long)pc() & 0xffff00000000UL);
4046
4047 _adrp(reg1, (address)adrp_target);
4048 movk(reg1, target >> 32, 32);
4049 }
4050 byte_offset = (unsigned long)dest.target() & 0xfff;
4051 }
4052
4053 void MacroAssembler::load_byte_map_base(Register reg) {
4054 jbyte *byte_map_base =
4055 ((CardTableModRefBS*)(Universe::heap()->barrier_set()))->byte_map_base;
4056
4057 if (is_valid_AArch64_address((address)byte_map_base)) {
4058 // Strictly speaking the byte_map_base isn't an address at all,
4059 // and it might even be negative.
4060 unsigned long offset;
4061 adrp(reg, ExternalAddress((address)byte_map_base), offset);
4062 assert(offset == 0, "misaligned card table base");
4063 } else {
4064 mov(reg, (uint64_t)byte_map_base);
4065 }
4066 }
4067
4068 void MacroAssembler::build_frame(int framesize) {
4069 assert(framesize > 0, "framesize must be > 0");
4070 if (framesize < ((1 << 9) + 2 * wordSize)) {
4071 sub(sp, sp, framesize);
4072 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4073 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
4074 } else {
4075 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
4076 if (PreserveFramePointer) mov(rfp, sp);
4077 if (framesize < ((1 << 12) + 2 * wordSize))
4078 sub(sp, sp, framesize - 2 * wordSize);
4079 else {
4080 mov(rscratch1, framesize - 2 * wordSize);
4081 sub(sp, sp, rscratch1);
4082 }
4083 }
4084 }
4085
4086 void MacroAssembler::remove_frame(int framesize) {
4087 assert(framesize > 0, "framesize must be > 0");
4088 if (framesize < ((1 << 9) + 2 * wordSize)) {
4089 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4090 add(sp, sp, framesize);
4091 } else {
4092 if (framesize < ((1 << 12) + 2 * wordSize))
4093 add(sp, sp, framesize - 2 * wordSize);
4094 else {
4095 mov(rscratch1, framesize - 2 * wordSize);
4096 add(sp, sp, rscratch1);
4097 }
4098 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
4099 }
4100 }
4101
4102
4103 // Search for str1 in str2 and return index or -1
4104 void MacroAssembler::string_indexof(Register str2, Register str1,
4105 Register cnt2, Register cnt1,
4106 Register tmp1, Register tmp2,
4107 Register tmp3, Register tmp4,
4108 int icnt1, Register result) {
4109 Label BM, LINEARSEARCH, DONE, NOMATCH, MATCH;
4110
4111 Register ch1 = rscratch1;
4112 Register ch2 = rscratch2;
4113 Register cnt1tmp = tmp1;
4114 Register cnt2tmp = tmp2;
4115 Register cnt1_neg = cnt1;
4116 Register cnt2_neg = cnt2;
4117 Register result_tmp = tmp4;
4118
4119 // Note, inline_string_indexOf() generates checks:
4120 // if (substr.count > string.count) return -1;
4121 // if (substr.count == 0) return 0;
4122
4123 // We have two strings, a source string in str2, cnt2 and a pattern string
4124 // in str1, cnt1. Find the 1st occurence of pattern in source or return -1.
4125
4126 // For larger pattern and source we use a simplified Boyer Moore algorithm.
4127 // With a small pattern and source we use linear scan.
4128
4129 if (icnt1 == -1) {
4130 cmp(cnt1, 256); // Use Linear Scan if cnt1 < 8 || cnt1 >= 256
4131 ccmp(cnt1, 8, 0b0000, LO); // Can't handle skip >= 256 because we use
4132 br(LO, LINEARSEARCH); // a byte array.
4133 cmp(cnt1, cnt2, LSR, 2); // Source must be 4 * pattern for BM
4134 br(HS, LINEARSEARCH);
4135 }
4136
4137 // The Boyer Moore alogorithm is based on the description here:-
4138 //
4139 // http://en.wikipedia.org/wiki/Boyer%E2%80%93Moore_string_search_algorithm
4140 //
4141 // This describes and algorithm with 2 shift rules. The 'Bad Character' rule
4142 // and the 'Good Suffix' rule.
4143 //
4144 // These rules are essentially heuristics for how far we can shift the
4145 // pattern along the search string.
4146 //
4147 // The implementation here uses the 'Bad Character' rule only because of the
4148 // complexity of initialisation for the 'Good Suffix' rule.
4149 //
4150 // This is also known as the Boyer-Moore-Horspool algorithm:-
4151 //
4152 // http://en.wikipedia.org/wiki/Boyer-Moore-Horspool_algorithm
4153 //
4154 // #define ASIZE 128
4155 //
4156 // int bm(unsigned char *x, int m, unsigned char *y, int n) {
4157 // int i, j;
4158 // unsigned c;
4159 // unsigned char bc[ASIZE];
4160 //
4161 // /* Preprocessing */
4162 // for (i = 0; i < ASIZE; ++i)
4163 // bc[i] = 0;
4164 // for (i = 0; i < m - 1; ) {
4165 // c = x[i];
4166 // ++i;
4167 // if (c < ASIZE) bc[c] = i;
4168 // }
4169 //
4170 // /* Searching */
4171 // j = 0;
4172 // while (j <= n - m) {
4173 // c = y[i+j];
4174 // if (x[m-1] == c)
4175 // for (i = m - 2; i >= 0 && x[i] == y[i + j]; --i);
4176 // if (i < 0) return j;
4177 // if (c < ASIZE)
4178 // j = j - bc[y[j+m-1]] + m;
4179 // else
4180 // j += 1; // Advance by 1 only if char >= ASIZE
4181 // }
4182 // }
4183
4184 if (icnt1 == -1) {
4185 BIND(BM);
4186
4187 Label ZLOOP, BCLOOP, BCSKIP, BMLOOPSTR2, BMLOOPSTR1, BMSKIP;
4188 Label BMADV, BMMATCH, BMCHECKEND;
4189
4190 Register cnt1end = tmp2;
4191 Register str2end = cnt2;
4192 Register skipch = tmp2;
4193
4194 // Restrict ASIZE to 128 to reduce stack space/initialisation.
4195 // The presence of chars >= ASIZE in the target string does not affect
4196 // performance, but we must be careful not to initialise them in the stack
4197 // array.
4198 // The presence of chars >= ASIZE in the source string may adversely affect
4199 // performance since we can only advance by one when we encounter one.
4200
4201 stp(zr, zr, pre(sp, -128));
4202 for (int i = 1; i < 8; i++)
4203 stp(zr, zr, Address(sp, i*16));
4204
4205 mov(cnt1tmp, 0);
4206 sub(cnt1end, cnt1, 1);
4207 BIND(BCLOOP);
4208 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1)));
4209 cmp(ch1, 128);
4210 add(cnt1tmp, cnt1tmp, 1);
4211 br(HS, BCSKIP);
4212 strb(cnt1tmp, Address(sp, ch1));
4213 BIND(BCSKIP);
4214 cmp(cnt1tmp, cnt1end);
4215 br(LT, BCLOOP);
4216
4217 mov(result_tmp, str2);
4218
4219 sub(cnt2, cnt2, cnt1);
4220 add(str2end, str2, cnt2, LSL, 1);
4221 BIND(BMLOOPSTR2);
4222 sub(cnt1tmp, cnt1, 1);
4223 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1)));
4224 ldrh(skipch, Address(str2, cnt1tmp, Address::lsl(1)));
4225 cmp(ch1, skipch);
4226 br(NE, BMSKIP);
4227 subs(cnt1tmp, cnt1tmp, 1);
4228 br(LT, BMMATCH);
4229 BIND(BMLOOPSTR1);
4230 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1)));
4231 ldrh(ch2, Address(str2, cnt1tmp, Address::lsl(1)));
4232 cmp(ch1, ch2);
4233 br(NE, BMSKIP);
4234 subs(cnt1tmp, cnt1tmp, 1);
4235 br(GE, BMLOOPSTR1);
4236 BIND(BMMATCH);
4237 sub(result_tmp, str2, result_tmp);
4238 lsr(result, result_tmp, 1);
4239 add(sp, sp, 128);
4240 b(DONE);
4241 BIND(BMADV);
4242 add(str2, str2, 2);
4243 b(BMCHECKEND);
4244 BIND(BMSKIP);
4245 cmp(skipch, 128);
4246 br(HS, BMADV);
4247 ldrb(ch2, Address(sp, skipch));
4248 add(str2, str2, cnt1, LSL, 1);
4249 sub(str2, str2, ch2, LSL, 1);
4250 BIND(BMCHECKEND);
4251 cmp(str2, str2end);
4252 br(LE, BMLOOPSTR2);
4253 add(sp, sp, 128);
4254 b(NOMATCH);
4255 }
4256
4257 BIND(LINEARSEARCH);
4258 {
4259 Label DO1, DO2, DO3;
4260
4261 Register str2tmp = tmp2;
4262 Register first = tmp3;
4263
4264 if (icnt1 == -1)
4265 {
4266 Label DOSHORT, FIRST_LOOP, STR2_NEXT, STR1_LOOP, STR1_NEXT, LAST_WORD;
4267
4268 cmp(cnt1, 4);
4269 br(LT, DOSHORT);
4270
4271 sub(cnt2, cnt2, cnt1);
4272 sub(cnt1, cnt1, 4);
4273 mov(result_tmp, cnt2);
4274
4275 lea(str1, Address(str1, cnt1, Address::uxtw(1)));
4276 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4277 sub(cnt1_neg, zr, cnt1, LSL, 1);
4278 sub(cnt2_neg, zr, cnt2, LSL, 1);
4279 ldr(first, Address(str1, cnt1_neg));
4280
4281 BIND(FIRST_LOOP);
4282 ldr(ch2, Address(str2, cnt2_neg));
4283 cmp(first, ch2);
4284 br(EQ, STR1_LOOP);
4285 BIND(STR2_NEXT);
4286 adds(cnt2_neg, cnt2_neg, 2);
4287 br(LE, FIRST_LOOP);
4288 b(NOMATCH);
4289
4290 BIND(STR1_LOOP);
4291 adds(cnt1tmp, cnt1_neg, 8);
4292 add(cnt2tmp, cnt2_neg, 8);
4293 br(GE, LAST_WORD);
4294
4295 BIND(STR1_NEXT);
4296 ldr(ch1, Address(str1, cnt1tmp));
4297 ldr(ch2, Address(str2, cnt2tmp));
4298 cmp(ch1, ch2);
4299 br(NE, STR2_NEXT);
4300 adds(cnt1tmp, cnt1tmp, 8);
4301 add(cnt2tmp, cnt2tmp, 8);
4302 br(LT, STR1_NEXT);
4303
4304 BIND(LAST_WORD);
4305 ldr(ch1, Address(str1));
4306 sub(str2tmp, str2, cnt1_neg); // adjust to corresponding
4307 ldr(ch2, Address(str2tmp, cnt2_neg)); // word in str2
4308 cmp(ch1, ch2);
4309 br(NE, STR2_NEXT);
4310 b(MATCH);
4311
4312 BIND(DOSHORT);
4313 cmp(cnt1, 2);
4314 br(LT, DO1);
4315 br(GT, DO3);
4316 }
4317
4318 if (icnt1 == 4) {
4319 Label CH1_LOOP;
4320
4321 ldr(ch1, str1);
4322 sub(cnt2, cnt2, 4);
4323 mov(result_tmp, cnt2);
4324 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4325 sub(cnt2_neg, zr, cnt2, LSL, 1);
4326
4327 BIND(CH1_LOOP);
4328 ldr(ch2, Address(str2, cnt2_neg));
4329 cmp(ch1, ch2);
4330 br(EQ, MATCH);
4331 adds(cnt2_neg, cnt2_neg, 2);
4332 br(LE, CH1_LOOP);
4333 b(NOMATCH);
4334 }
4335
4336 if (icnt1 == -1 || icnt1 == 2) {
4337 Label CH1_LOOP;
4338
4339 BIND(DO2);
4340 ldrw(ch1, str1);
4341 sub(cnt2, cnt2, 2);
4342 mov(result_tmp, cnt2);
4343 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4344 sub(cnt2_neg, zr, cnt2, LSL, 1);
4345
4346 BIND(CH1_LOOP);
4347 ldrw(ch2, Address(str2, cnt2_neg));
4348 cmp(ch1, ch2);
4349 br(EQ, MATCH);
4350 adds(cnt2_neg, cnt2_neg, 2);
4351 br(LE, CH1_LOOP);
4352 b(NOMATCH);
4353 }
4354
4355 if (icnt1 == -1 || icnt1 == 3) {
4356 Label FIRST_LOOP, STR2_NEXT, STR1_LOOP;
4357
4358 BIND(DO3);
4359 ldrw(first, str1);
4360 ldrh(ch1, Address(str1, 4));
4361
4362 sub(cnt2, cnt2, 3);
4363 mov(result_tmp, cnt2);
4364 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4365 sub(cnt2_neg, zr, cnt2, LSL, 1);
4366
4367 BIND(FIRST_LOOP);
4368 ldrw(ch2, Address(str2, cnt2_neg));
4369 cmpw(first, ch2);
4370 br(EQ, STR1_LOOP);
4371 BIND(STR2_NEXT);
4372 adds(cnt2_neg, cnt2_neg, 2);
4373 br(LE, FIRST_LOOP);
4374 b(NOMATCH);
4375
4376 BIND(STR1_LOOP);
4377 add(cnt2tmp, cnt2_neg, 4);
4378 ldrh(ch2, Address(str2, cnt2tmp));
4379 cmp(ch1, ch2);
4380 br(NE, STR2_NEXT);
4381 b(MATCH);
4382 }
4383
4384 if (icnt1 == -1 || icnt1 == 1) {
4385 Label CH1_LOOP, HAS_ZERO;
4386 Label DO1_SHORT, DO1_LOOP;
4387
4388 BIND(DO1);
4389 ldrh(ch1, str1);
4390 cmp(cnt2, 4);
4391 br(LT, DO1_SHORT);
4392
4393 orr(ch1, ch1, ch1, LSL, 16);
4394 orr(ch1, ch1, ch1, LSL, 32);
4395
4396 sub(cnt2, cnt2, 4);
4397 mov(result_tmp, cnt2);
4398 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4399 sub(cnt2_neg, zr, cnt2, LSL, 1);
4400
4401 mov(tmp3, 0x0001000100010001);
4402 BIND(CH1_LOOP);
4403 ldr(ch2, Address(str2, cnt2_neg));
4404 eor(ch2, ch1, ch2);
4405 sub(tmp1, ch2, tmp3);
4406 orr(tmp2, ch2, 0x7fff7fff7fff7fff);
4407 bics(tmp1, tmp1, tmp2);
4408 br(NE, HAS_ZERO);
4409 adds(cnt2_neg, cnt2_neg, 8);
4410 br(LT, CH1_LOOP);
4411
4412 cmp(cnt2_neg, 8);
4413 mov(cnt2_neg, 0);
4414 br(LT, CH1_LOOP);
4415 b(NOMATCH);
4416
4417 BIND(HAS_ZERO);
4418 rev(tmp1, tmp1);
4419 clz(tmp1, tmp1);
4420 add(cnt2_neg, cnt2_neg, tmp1, LSR, 3);
4421 b(MATCH);
4422
4423 BIND(DO1_SHORT);
4424 mov(result_tmp, cnt2);
4425 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4426 sub(cnt2_neg, zr, cnt2, LSL, 1);
4427 BIND(DO1_LOOP);
4428 ldrh(ch2, Address(str2, cnt2_neg));
4429 cmpw(ch1, ch2);
4430 br(EQ, MATCH);
4431 adds(cnt2_neg, cnt2_neg, 2);
4432 br(LT, DO1_LOOP);
4433 }
4434 }
4435 BIND(NOMATCH);
4436 mov(result, -1);
4437 b(DONE);
4438 BIND(MATCH);
4439 add(result, result_tmp, cnt2_neg, ASR, 1);
4440 BIND(DONE);
4441 }
4442
4443 // Compare strings.
4444 void MacroAssembler::string_compare(Register str1, Register str2,
4445 Register cnt1, Register cnt2, Register result,
4446 Register tmp1) {
4447 Label LENGTH_DIFF, DONE, SHORT_LOOP, SHORT_STRING,
4448 NEXT_WORD, DIFFERENCE;
4449
4450 BLOCK_COMMENT("string_compare {");
4451
4452 // Compute the minimum of the string lengths and save the difference.
4453 subsw(tmp1, cnt1, cnt2);
4454 cselw(cnt2, cnt1, cnt2, Assembler::LE); // min
4455
4456 // A very short string
4457 cmpw(cnt2, 4);
4458 br(Assembler::LT, SHORT_STRING);
4459
4460 // Check if the strings start at the same location.
4461 cmp(str1, str2);
4462 br(Assembler::EQ, LENGTH_DIFF);
4463
4464 // Compare longwords
4465 {
4466 subw(cnt2, cnt2, 4); // The last longword is a special case
4467
4468 // Move both string pointers to the last longword of their
4469 // strings, negate the remaining count, and convert it to bytes.
4470 lea(str1, Address(str1, cnt2, Address::uxtw(1)));
4471 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4472 sub(cnt2, zr, cnt2, LSL, 1);
4473
4474 // Loop, loading longwords and comparing them into rscratch2.
4475 bind(NEXT_WORD);
4476 ldr(result, Address(str1, cnt2));
4477 ldr(cnt1, Address(str2, cnt2));
4478 adds(cnt2, cnt2, wordSize);
4479 eor(rscratch2, result, cnt1);
4480 cbnz(rscratch2, DIFFERENCE);
4481 br(Assembler::LT, NEXT_WORD);
4482
4483 // Last longword. In the case where length == 4 we compare the
4484 // same longword twice, but that's still faster than another
4485 // conditional branch.
4486
4487 ldr(result, Address(str1));
4488 ldr(cnt1, Address(str2));
4489 eor(rscratch2, result, cnt1);
4490 cbz(rscratch2, LENGTH_DIFF);
4491
4492 // Find the first different characters in the longwords and
4493 // compute their difference.
4494 bind(DIFFERENCE);
4495 rev(rscratch2, rscratch2);
4496 clz(rscratch2, rscratch2);
4497 andr(rscratch2, rscratch2, -16);
4498 lsrv(result, result, rscratch2);
4499 uxthw(result, result);
4500 lsrv(cnt1, cnt1, rscratch2);
4501 uxthw(cnt1, cnt1);
4502 subw(result, result, cnt1);
4503 b(DONE);
4504 }
4505
4506 bind(SHORT_STRING);
4507 // Is the minimum length zero?
4508 cbz(cnt2, LENGTH_DIFF);
4509
4510 bind(SHORT_LOOP);
4511 load_unsigned_short(result, Address(post(str1, 2)));
4512 load_unsigned_short(cnt1, Address(post(str2, 2)));
4513 subw(result, result, cnt1);
4514 cbnz(result, DONE);
4515 sub(cnt2, cnt2, 1);
4516 cbnz(cnt2, SHORT_LOOP);
4517
4518 // Strings are equal up to min length. Return the length difference.
4519 bind(LENGTH_DIFF);
4520 mov(result, tmp1);
4521
4522 // That's it
4523 bind(DONE);
4524
4525 BLOCK_COMMENT("} string_compare");
4526 }
4527
4528
4529 void MacroAssembler::string_equals(Register str1, Register str2,
4530 Register cnt, Register result,
4531 Register tmp1) {
4532 Label SAME_CHARS, DONE, SHORT_LOOP, SHORT_STRING,
4533 NEXT_WORD;
4534
4535 const Register tmp2 = rscratch1;
4536 assert_different_registers(str1, str2, cnt, result, tmp1, tmp2, rscratch2);
4537
4538 BLOCK_COMMENT("string_equals {");
4539
4540 // Start by assuming that the strings are not equal.
4541 mov(result, zr);
4542
4543 // A very short string
4544 cmpw(cnt, 4);
4545 br(Assembler::LT, SHORT_STRING);
4546
4547 // Check if the strings start at the same location.
4548 cmp(str1, str2);
4549 br(Assembler::EQ, SAME_CHARS);
4550
4551 // Compare longwords
4552 {
4553 subw(cnt, cnt, 4); // The last longword is a special case
4554
4555 // Move both string pointers to the last longword of their
4556 // strings, negate the remaining count, and convert it to bytes.
4557 lea(str1, Address(str1, cnt, Address::uxtw(1)));
4558 lea(str2, Address(str2, cnt, Address::uxtw(1)));
4559 sub(cnt, zr, cnt, LSL, 1);
4560
4561 // Loop, loading longwords and comparing them into rscratch2.
4562 bind(NEXT_WORD);
4563 ldr(tmp1, Address(str1, cnt));
4564 ldr(tmp2, Address(str2, cnt));
4565 adds(cnt, cnt, wordSize);
4566 eor(rscratch2, tmp1, tmp2);
4567 cbnz(rscratch2, DONE);
4568 br(Assembler::LT, NEXT_WORD);
4569
4570 // Last longword. In the case where length == 4 we compare the
4571 // same longword twice, but that's still faster than another
4572 // conditional branch.
4573
4574 ldr(tmp1, Address(str1));
4575 ldr(tmp2, Address(str2));
4576 eor(rscratch2, tmp1, tmp2);
4577 cbz(rscratch2, SAME_CHARS);
4578 b(DONE);
4579 }
4580
4581 bind(SHORT_STRING);
4582 // Is the length zero?
4583 cbz(cnt, SAME_CHARS);
4584
4585 bind(SHORT_LOOP);
4586 load_unsigned_short(tmp1, Address(post(str1, 2)));
4587 load_unsigned_short(tmp2, Address(post(str2, 2)));
4588 subw(tmp1, tmp1, tmp2);
4589 cbnz(tmp1, DONE);
4590 sub(cnt, cnt, 1);
4591 cbnz(cnt, SHORT_LOOP);
4592
4593 // Strings are equal.
4594 bind(SAME_CHARS);
4595 mov(result, true);
4596
4597 // That's it
4598 bind(DONE);
4599
4600 BLOCK_COMMENT("} string_equals");
4601 }
4602
4603
4604 void MacroAssembler::byte_arrays_equals(Register ary1, Register ary2,
4605 Register result, Register tmp1)
4606 {
4607 Register cnt1 = rscratch1;
4608 Register cnt2 = rscratch2;
4609 Register tmp2 = rscratch2;
4610
4611 Label SAME, DIFFER, NEXT, TAIL07, TAIL03, TAIL01;
4612
4613 int length_offset = arrayOopDesc::length_offset_in_bytes();
4614 int base_offset = arrayOopDesc::base_offset_in_bytes(T_BYTE);
4615
4616 BLOCK_COMMENT("byte_arrays_equals {");
4617
4618 // different until proven equal
4619 mov(result, false);
4620
4621 // same array?
4622 cmp(ary1, ary2);
4623 br(Assembler::EQ, SAME);
4624
4625 // ne if either null
4626 cbz(ary1, DIFFER);
4627 cbz(ary2, DIFFER);
4628
4629 // lengths ne?
4630 ldrw(cnt1, Address(ary1, length_offset));
4631 ldrw(cnt2, Address(ary2, length_offset));
4632 cmp(cnt1, cnt2);
4633 br(Assembler::NE, DIFFER);
4634
4635 lea(ary1, Address(ary1, base_offset));
4636 lea(ary2, Address(ary2, base_offset));
4637
4638 subs(cnt1, cnt1, 8);
4639 br(LT, TAIL07);
4640
4641 BIND(NEXT);
4642 ldr(tmp1, Address(post(ary1, 8)));
4643 ldr(tmp2, Address(post(ary2, 8)));
4644 subs(cnt1, cnt1, 8);
4645 eor(tmp1, tmp1, tmp2);
4646 cbnz(tmp1, DIFFER);
4647 br(GE, NEXT);
4648
4649 BIND(TAIL07); // 0-7 bytes left, cnt1 = #bytes left - 4
4650 tst(cnt1, 0b100);
4651 br(EQ, TAIL03);
4652 ldrw(tmp1, Address(post(ary1, 4)));
4653 ldrw(tmp2, Address(post(ary2, 4)));
4654 cmp(tmp1, tmp2);
4655 br(NE, DIFFER);
4656
4657 BIND(TAIL03); // 0-3 bytes left, cnt1 = #bytes left - 4
4658 tst(cnt1, 0b10);
4659 br(EQ, TAIL01);
4660 ldrh(tmp1, Address(post(ary1, 2)));
4661 ldrh(tmp2, Address(post(ary2, 2)));
4662 cmp(tmp1, tmp2);
4663 br(NE, DIFFER);
4664 BIND(TAIL01); // 0-1 byte left
4665 tst(cnt1, 0b01);
4666 br(EQ, SAME);
4667 ldrb(tmp1, ary1);
4668 ldrb(tmp2, ary2);
4669 cmp(tmp1, tmp2);
4670 br(NE, DIFFER);
4671
4672 BIND(SAME);
4673 mov(result, true);
4674 BIND(DIFFER); // result already set
4675
4676 BLOCK_COMMENT("} byte_arrays_equals");
4677 }
4678
4679 // Compare char[] arrays aligned to 4 bytes
4680 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2,
4681 Register result, Register tmp1)
4682 {
4683 Register cnt1 = rscratch1;
4684 Register cnt2 = rscratch2;
4685 Register tmp2 = rscratch2;
4686
4687 Label SAME, DIFFER, NEXT, TAIL03, TAIL01;
4688
4689 int length_offset = arrayOopDesc::length_offset_in_bytes();
4690 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
4691
4692 BLOCK_COMMENT("char_arrays_equals {");
4693
4694 // different until proven equal
4695 mov(result, false);
4696
4697 // same array?
4698 cmp(ary1, ary2);
4699 br(Assembler::EQ, SAME);
4700
4701 // ne if either null
4702 cbz(ary1, DIFFER);
4703 cbz(ary2, DIFFER);
4704
4705 // lengths ne?
4706 ldrw(cnt1, Address(ary1, length_offset));
4707 ldrw(cnt2, Address(ary2, length_offset));
4708 cmp(cnt1, cnt2);
4709 br(Assembler::NE, DIFFER);
4710
4711 lea(ary1, Address(ary1, base_offset));
4712 lea(ary2, Address(ary2, base_offset));
4713
4714 subs(cnt1, cnt1, 4);
4715 br(LT, TAIL03);
4716
4717 BIND(NEXT);
4718 ldr(tmp1, Address(post(ary1, 8)));
4719 ldr(tmp2, Address(post(ary2, 8)));
4720 subs(cnt1, cnt1, 4);
4721 eor(tmp1, tmp1, tmp2);
4722 cbnz(tmp1, DIFFER);
4723 br(GE, NEXT);
4724
4725 BIND(TAIL03); // 0-3 chars left, cnt1 = #chars left - 4
4726 tst(cnt1, 0b10);
4727 br(EQ, TAIL01);
4728 ldrw(tmp1, Address(post(ary1, 4)));
4729 ldrw(tmp2, Address(post(ary2, 4)));
4730 cmp(tmp1, tmp2);
4731 br(NE, DIFFER);
4732 BIND(TAIL01); // 0-1 chars left
4733 tst(cnt1, 0b01);
4734 br(EQ, SAME);
4735 ldrh(tmp1, ary1);
4736 ldrh(tmp2, ary2);
4737 cmp(tmp1, tmp2);
4738 br(NE, DIFFER);
4739
4740 BIND(SAME);
4741 mov(result, true);
4742 BIND(DIFFER); // result already set
4743
4744 BLOCK_COMMENT("} char_arrays_equals");
4745 }
4746
4747 // encode char[] to byte[] in ISO_8859_1
4748 void MacroAssembler::encode_iso_array(Register src, Register dst,
4749 Register len, Register result,
4750 FloatRegister Vtmp1, FloatRegister Vtmp2,
4751 FloatRegister Vtmp3, FloatRegister Vtmp4)
4752 {
4753 Label DONE, NEXT_32, LOOP_8, NEXT_8, LOOP_1, NEXT_1;
4754 Register tmp1 = rscratch1;
4755
4756 mov(result, len); // Save initial len
4757
4758 #ifndef BUILTIN_SIM
4759 subs(len, len, 32);
4760 br(LT, LOOP_8);
4761
4762 // The following code uses the SIMD 'uqxtn' and 'uqxtn2' instructions
4763 // to convert chars to bytes. These set the 'QC' bit in the FPSR if
4764 // any char could not fit in a byte, so clear the FPSR so we can test it.
4765 clear_fpsr();
4766
4767 BIND(NEXT_32);
4768 ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src);
4769 uqxtn(Vtmp1, T8B, Vtmp1, T8H); // uqxtn - write bottom half
4770 uqxtn(Vtmp1, T16B, Vtmp2, T8H); // uqxtn2 - write top half
4771 uqxtn(Vtmp2, T8B, Vtmp3, T8H);
4772 uqxtn(Vtmp2, T16B, Vtmp4, T8H); // uqxtn2
4773 get_fpsr(tmp1);
4774 cbnzw(tmp1, LOOP_8);
4775 st1(Vtmp1, Vtmp2, T16B, post(dst, 32));
4776 subs(len, len, 32);
4777 add(src, src, 64);
4778 br(GE, NEXT_32);
4779
4780 BIND(LOOP_8);
4781 adds(len, len, 32-8);
4782 br(LT, LOOP_1);
4783 clear_fpsr(); // QC may be set from loop above, clear again
4784 BIND(NEXT_8);
4785 ld1(Vtmp1, T8H, src);
4786 uqxtn(Vtmp1, T8B, Vtmp1, T8H);
4787 get_fpsr(tmp1);
4788 cbnzw(tmp1, LOOP_1);
4789 st1(Vtmp1, T8B, post(dst, 8));
4790 subs(len, len, 8);
4791 add(src, src, 16);
4792 br(GE, NEXT_8);
4793
4794 BIND(LOOP_1);
4795 adds(len, len, 8);
4796 br(LE, DONE);
4797 #else
4798 cbz(len, DONE);
4799 #endif
4800 BIND(NEXT_1);
4801 ldrh(tmp1, Address(post(src, 2)));
4802 tst(tmp1, 0xff00);
4803 br(NE, DONE);
4804 strb(tmp1, Address(post(dst, 1)));
4805 subs(len, len, 1);
4806 br(GT, NEXT_1);
4807
4808 BIND(DONE);
4809 sub(result, result, len); // Return index where we stopped
4810 }
4811
4812 // get_thread() can be called anywhere inside generated code so we
4813 // need to save whatever non-callee save context might get clobbered
4814 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
4815 // the call setup code.
4816 //
4817 // aarch64_get_thread_helper() clobbers only r0, r1, and flags.
4818 //
4819 void MacroAssembler::get_thread(Register dst) {
4820 RegSet saved_regs = RegSet::range(r0, r1) + lr - dst;
4821 push(saved_regs, sp);
4822
4823 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
4824 blrt(lr, 1, 0, 1);
4825 if (dst != c_rarg0) {
4826 mov(dst, c_rarg0);
4827 }
4828
4829 pop(saved_regs, sp);
4830 }