1 /* 2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP 27 #define CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP 28 29 #include "asm/register.hpp" 30 31 // definitions of various symbolic names for machine registers 32 33 // First intercalls between C and Java which use 8 general registers 34 // and 8 floating registers 35 36 // we also have to copy between x86 and ARM registers but that's a 37 // secondary complication -- not all code employing C call convention 38 // executes as x86 code though -- we generate some of it 39 40 class Argument VALUE_OBJ_CLASS_SPEC { 41 public: 42 enum { 43 n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...) 44 n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... ) 45 46 n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ... 47 n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ... 48 }; 49 }; 50 51 REGISTER_DECLARATION(Register, c_rarg0, r0); 52 REGISTER_DECLARATION(Register, c_rarg1, r1); 53 REGISTER_DECLARATION(Register, c_rarg2, r2); 54 REGISTER_DECLARATION(Register, c_rarg3, r3); 55 REGISTER_DECLARATION(Register, c_rarg4, r4); 56 REGISTER_DECLARATION(Register, c_rarg5, r5); 57 REGISTER_DECLARATION(Register, c_rarg6, r6); 58 REGISTER_DECLARATION(Register, c_rarg7, r7); 59 60 REGISTER_DECLARATION(FloatRegister, c_farg0, v0); 61 REGISTER_DECLARATION(FloatRegister, c_farg1, v1); 62 REGISTER_DECLARATION(FloatRegister, c_farg2, v2); 63 REGISTER_DECLARATION(FloatRegister, c_farg3, v3); 64 REGISTER_DECLARATION(FloatRegister, c_farg4, v4); 65 REGISTER_DECLARATION(FloatRegister, c_farg5, v5); 66 REGISTER_DECLARATION(FloatRegister, c_farg6, v6); 67 REGISTER_DECLARATION(FloatRegister, c_farg7, v7); 68 69 // Symbolically name the register arguments used by the Java calling convention. 70 // We have control over the convention for java so we can do what we please. 71 // What pleases us is to offset the java calling convention so that when 72 // we call a suitable jni method the arguments are lined up and we don't 73 // have to do much shuffling. A suitable jni method is non-static and a 74 // small number of arguments 75 // 76 // |--------------------------------------------------------------------| 77 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 | 78 // |--------------------------------------------------------------------| 79 // | r0 r1 r2 r3 r4 r5 r6 r7 | 80 // |--------------------------------------------------------------------| 81 // | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 | 82 // |--------------------------------------------------------------------| 83 84 85 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); 86 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); 87 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); 88 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); 89 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); 90 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6); 91 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7); 92 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0); 93 94 // Java floating args are passed as per C 95 96 REGISTER_DECLARATION(FloatRegister, j_farg0, v0); 97 REGISTER_DECLARATION(FloatRegister, j_farg1, v1); 98 REGISTER_DECLARATION(FloatRegister, j_farg2, v2); 99 REGISTER_DECLARATION(FloatRegister, j_farg3, v3); 100 REGISTER_DECLARATION(FloatRegister, j_farg4, v4); 101 REGISTER_DECLARATION(FloatRegister, j_farg5, v5); 102 REGISTER_DECLARATION(FloatRegister, j_farg6, v6); 103 REGISTER_DECLARATION(FloatRegister, j_farg7, v7); 104 105 // registers used to hold VM data either temporarily within a method 106 // or across method calls 107 108 // volatile (caller-save) registers 109 110 // r8 is used for indirect result location return 111 // we use it and r9 as scratch registers 112 REGISTER_DECLARATION(Register, rscratch1, r8); 113 REGISTER_DECLARATION(Register, rscratch2, r9); 114 115 // current method -- must be in a call-clobbered register 116 REGISTER_DECLARATION(Register, rmethod, r12); 117 118 // non-volatile (callee-save) registers are r16-29 119 // of which the following are dedicated global state 120 121 // link register 122 REGISTER_DECLARATION(Register, lr, r30); 123 // frame pointer 124 REGISTER_DECLARATION(Register, rfp, r29); 125 // current thread 126 REGISTER_DECLARATION(Register, rthread, r28); 127 // base of heap 128 REGISTER_DECLARATION(Register, rheapbase, r27); 129 // constant pool cache 130 REGISTER_DECLARATION(Register, rcpool, r26); 131 // monitors allocated on stack 132 REGISTER_DECLARATION(Register, rmonitors, r25); 133 // locals on stack 134 REGISTER_DECLARATION(Register, rlocals, r24); 135 // bytecode pointer 136 REGISTER_DECLARATION(Register, rbcp, r22); 137 // Dispatch table base 138 REGISTER_DECLARATION(Register, rdispatch, r21); 139 // Java stack pointer 140 REGISTER_DECLARATION(Register, esp, r20); 141 142 #define assert_cond(ARG1) assert(ARG1, #ARG1) 143 144 namespace asm_util { 145 uint32_t encode_logical_immediate(bool is32, uint64_t imm); 146 }; 147 148 using namespace asm_util; 149 150 151 class Assembler; 152 153 class Instruction_aarch64 { 154 unsigned insn; 155 #ifdef ASSERT 156 unsigned bits; 157 #endif 158 Assembler *assem; 159 160 public: 161 162 Instruction_aarch64(class Assembler *as) { 163 #ifdef ASSERT 164 bits = 0; 165 #endif 166 insn = 0; 167 assem = as; 168 } 169 170 inline ~Instruction_aarch64(); 171 172 unsigned &get_insn() { return insn; } 173 #ifdef ASSERT 174 unsigned &get_bits() { return bits; } 175 #endif 176 177 static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) { 178 union { 179 unsigned u; 180 int n; 181 }; 182 183 u = val << (31 - hi); 184 n = n >> (31 - hi + lo); 185 return n; 186 } 187 188 static inline uint32_t extract(uint32_t val, int msb, int lsb) { 189 int nbits = msb - lsb + 1; 190 assert_cond(msb >= lsb); 191 uint32_t mask = (1U << nbits) - 1; 192 uint32_t result = val >> lsb; 193 result &= mask; 194 return result; 195 } 196 197 static inline int32_t sextract(uint32_t val, int msb, int lsb) { 198 uint32_t uval = extract(val, msb, lsb); 199 return extend(uval, msb - lsb); 200 } 201 202 static void patch(address a, int msb, int lsb, unsigned long val) { 203 int nbits = msb - lsb + 1; 204 guarantee(val < (1U << nbits), "Field too big for insn"); 205 assert_cond(msb >= lsb); 206 unsigned mask = (1U << nbits) - 1; 207 val <<= lsb; 208 mask <<= lsb; 209 unsigned target = *(unsigned *)a; 210 target &= ~mask; 211 target |= val; 212 *(unsigned *)a = target; 213 } 214 215 static void spatch(address a, int msb, int lsb, long val) { 216 int nbits = msb - lsb + 1; 217 long chk = val >> (nbits - 1); 218 guarantee (chk == -1 || chk == 0, "Field too big for insn"); 219 unsigned uval = val; 220 unsigned mask = (1U << nbits) - 1; 221 uval &= mask; 222 uval <<= lsb; 223 mask <<= lsb; 224 unsigned target = *(unsigned *)a; 225 target &= ~mask; 226 target |= uval; 227 *(unsigned *)a = target; 228 } 229 230 void f(unsigned val, int msb, int lsb) { 231 int nbits = msb - lsb + 1; 232 guarantee(val < (1U << nbits), "Field too big for insn"); 233 assert_cond(msb >= lsb); 234 unsigned mask = (1U << nbits) - 1; 235 val <<= lsb; 236 mask <<= lsb; 237 insn |= val; 238 assert_cond((bits & mask) == 0); 239 #ifdef ASSERT 240 bits |= mask; 241 #endif 242 } 243 244 void f(unsigned val, int bit) { 245 f(val, bit, bit); 246 } 247 248 void sf(long val, int msb, int lsb) { 249 int nbits = msb - lsb + 1; 250 long chk = val >> (nbits - 1); 251 guarantee (chk == -1 || chk == 0, "Field too big for insn"); 252 unsigned uval = val; 253 unsigned mask = (1U << nbits) - 1; 254 uval &= mask; 255 f(uval, lsb + nbits - 1, lsb); 256 } 257 258 void rf(Register r, int lsb) { 259 f(r->encoding_nocheck(), lsb + 4, lsb); 260 } 261 262 // reg|ZR 263 void zrf(Register r, int lsb) { 264 f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb); 265 } 266 267 // reg|SP 268 void srf(Register r, int lsb) { 269 f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb); 270 } 271 272 void rf(FloatRegister r, int lsb) { 273 f(r->encoding_nocheck(), lsb + 4, lsb); 274 } 275 276 unsigned get(int msb = 31, int lsb = 0) { 277 int nbits = msb - lsb + 1; 278 unsigned mask = ((1U << nbits) - 1) << lsb; 279 assert_cond(bits & mask == mask); 280 return (insn & mask) >> lsb; 281 } 282 283 void fixed(unsigned value, unsigned mask) { 284 assert_cond ((mask & bits) == 0); 285 #ifdef ASSERT 286 bits |= mask; 287 #endif 288 insn |= value; 289 } 290 }; 291 292 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use) 293 294 class PrePost { 295 int _offset; 296 Register _r; 297 public: 298 PrePost(Register reg, int o) : _r(reg), _offset(o) { } 299 int offset() { return _offset; } 300 Register reg() { return _r; } 301 }; 302 303 class Pre : public PrePost { 304 public: 305 Pre(Register reg, int o) : PrePost(reg, o) { } 306 }; 307 class Post : public PrePost { 308 public: 309 Post(Register reg, int o) : PrePost(reg, o) { } 310 }; 311 312 namespace ext 313 { 314 enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx }; 315 }; 316 317 // abs methods which cannot overflow and so are well-defined across 318 // the entire domain of integer types. 319 static inline unsigned int uabs(unsigned int n) { 320 union { 321 unsigned int result; 322 int value; 323 }; 324 result = n; 325 if (value < 0) result = -result; 326 return result; 327 } 328 static inline unsigned long uabs(unsigned long n) { 329 union { 330 unsigned long result; 331 long value; 332 }; 333 result = n; 334 if (value < 0) result = -result; 335 return result; 336 } 337 static inline unsigned long uabs(long n) { return uabs((unsigned long)n); } 338 static inline unsigned long uabs(int n) { return uabs((unsigned int)n); } 339 340 // Addressing modes 341 class Address VALUE_OBJ_CLASS_SPEC { 342 public: 343 344 enum mode { no_mode, base_plus_offset, pre, post, pcrel, 345 base_plus_offset_reg, literal }; 346 347 // Shift and extend for base reg + reg offset addressing 348 class extend { 349 int _option, _shift; 350 ext::operation _op; 351 public: 352 extend() { } 353 extend(int s, int o, ext::operation op) : _shift(s), _option(o), _op(op) { } 354 int option() const{ return _option; } 355 int shift() const { return _shift; } 356 ext::operation op() const { return _op; } 357 }; 358 class uxtw : public extend { 359 public: 360 uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { } 361 }; 362 class lsl : public extend { 363 public: 364 lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { } 365 }; 366 class sxtw : public extend { 367 public: 368 sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { } 369 }; 370 class sxtx : public extend { 371 public: 372 sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { } 373 }; 374 375 private: 376 Register _base; 377 Register _index; 378 long _offset; 379 enum mode _mode; 380 extend _ext; 381 382 RelocationHolder _rspec; 383 384 // Typically we use AddressLiterals we want to use their rval 385 // However in some situations we want the lval (effect address) of 386 // the item. We provide a special factory for making those lvals. 387 bool _is_lval; 388 389 // If the target is far we'll need to load the ea of this to a 390 // register to reach it. Otherwise if near we can do PC-relative 391 // addressing. 392 address _target; 393 394 public: 395 Address() 396 : _mode(no_mode) { } 397 Address(Register r) 398 : _mode(base_plus_offset), _base(r), _offset(0), _index(noreg), _target(0) { } 399 Address(Register r, int o) 400 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { } 401 Address(Register r, long o) 402 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { } 403 Address(Register r, unsigned long o) 404 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { } 405 #ifdef ASSERT 406 Address(Register r, ByteSize disp) 407 : _mode(base_plus_offset), _base(r), _offset(in_bytes(disp)), 408 _index(noreg), _target(0) { } 409 #endif 410 Address(Register r, Register r1, extend ext = lsl()) 411 : _mode(base_plus_offset_reg), _base(r), _index(r1), 412 _ext(ext), _offset(0), _target(0) { } 413 Address(Pre p) 414 : _mode(pre), _base(p.reg()), _offset(p.offset()) { } 415 Address(Post p) 416 : _mode(post), _base(p.reg()), _offset(p.offset()), _target(0) { } 417 Address(address target, RelocationHolder const& rspec) 418 : _mode(literal), 419 _rspec(rspec), 420 _is_lval(false), 421 _target(target) { } 422 Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type); 423 Address(Register base, RegisterOrConstant index, extend ext = lsl()) 424 : _base (base), 425 _ext(ext), _offset(0), _target(0) { 426 if (index.is_register()) { 427 _mode = base_plus_offset_reg; 428 _index = index.as_register(); 429 } else { 430 guarantee(ext.option() == ext::uxtx, "should be"); 431 assert(index.is_constant(), "should be"); 432 _mode = base_plus_offset; 433 _offset = index.as_constant() << ext.shift(); 434 } 435 } 436 437 Register base() const { 438 guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg 439 | _mode == post), 440 "wrong mode"); 441 return _base; 442 } 443 long offset() const { 444 return _offset; 445 } 446 Register index() const { 447 return _index; 448 } 449 mode getMode() const { 450 return _mode; 451 } 452 bool uses(Register reg) const { return _base == reg || _index == reg; } 453 address target() const { return _target; } 454 const RelocationHolder& rspec() const { return _rspec; } 455 456 void encode(Instruction_aarch64 *i) const { 457 i->f(0b111, 29, 27); 458 i->srf(_base, 5); 459 460 switch(_mode) { 461 case base_plus_offset: 462 { 463 unsigned size = i->get(31, 30); 464 if (i->get(26, 26) && i->get(23, 23)) { 465 // SIMD Q Type - Size = 128 bits 466 assert(size == 0, "bad size"); 467 size = 0b100; 468 } 469 unsigned mask = (1 << size) - 1; 470 if (_offset < 0 || _offset & mask) 471 { 472 i->f(0b00, 25, 24); 473 i->f(0, 21), i->f(0b00, 11, 10); 474 i->sf(_offset, 20, 12); 475 } else { 476 i->f(0b01, 25, 24); 477 i->f(_offset >> size, 21, 10); 478 } 479 } 480 break; 481 482 case base_plus_offset_reg: 483 { 484 i->f(0b00, 25, 24); 485 i->f(1, 21); 486 i->rf(_index, 16); 487 i->f(_ext.option(), 15, 13); 488 unsigned size = i->get(31, 30); 489 if (i->get(26, 26) && i->get(23, 23)) { 490 // SIMD Q Type - Size = 128 bits 491 assert(size == 0, "bad size"); 492 size = 0b100; 493 } 494 if (size == 0) // It's a byte 495 i->f(_ext.shift() >= 0, 12); 496 else { 497 if (_ext.shift() > 0) 498 assert(_ext.shift() == (int)size, "bad shift"); 499 i->f(_ext.shift() > 0, 12); 500 } 501 i->f(0b10, 11, 10); 502 } 503 break; 504 505 case pre: 506 i->f(0b00, 25, 24); 507 i->f(0, 21), i->f(0b11, 11, 10); 508 i->sf(_offset, 20, 12); 509 break; 510 511 case post: 512 i->f(0b00, 25, 24); 513 i->f(0, 21), i->f(0b01, 11, 10); 514 i->sf(_offset, 20, 12); 515 break; 516 517 default: 518 ShouldNotReachHere(); 519 } 520 } 521 522 void encode_pair(Instruction_aarch64 *i) const { 523 switch(_mode) { 524 case base_plus_offset: 525 i->f(0b010, 25, 23); 526 break; 527 case pre: 528 i->f(0b011, 25, 23); 529 break; 530 case post: 531 i->f(0b001, 25, 23); 532 break; 533 default: 534 ShouldNotReachHere(); 535 } 536 537 unsigned size; // Operand shift in 32-bit words 538 539 if (i->get(26, 26)) { // float 540 switch(i->get(31, 30)) { 541 case 0b10: 542 size = 2; break; 543 case 0b01: 544 size = 1; break; 545 case 0b00: 546 size = 0; break; 547 default: 548 ShouldNotReachHere(); 549 size = 0; // unreachable 550 } 551 } else { 552 size = i->get(31, 31); 553 } 554 555 size = 4 << size; 556 guarantee(_offset % size == 0, "bad offset"); 557 i->sf(_offset / size, 21, 15); 558 i->srf(_base, 5); 559 } 560 561 void encode_nontemporal_pair(Instruction_aarch64 *i) const { 562 // Only base + offset is allowed 563 i->f(0b000, 25, 23); 564 unsigned size = i->get(31, 31); 565 size = 4 << size; 566 guarantee(_offset % size == 0, "bad offset"); 567 i->sf(_offset / size, 21, 15); 568 i->srf(_base, 5); 569 guarantee(_mode == Address::base_plus_offset, 570 "Bad addressing mode for non-temporal op"); 571 } 572 573 void lea(MacroAssembler *, Register) const; 574 575 static bool offset_ok_for_immed(long offset, int shift = 0) { 576 unsigned mask = (1 << shift) - 1; 577 if (offset < 0 || offset & mask) { 578 return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset 579 } else { 580 return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset 581 } 582 } 583 }; 584 585 // Convience classes 586 class RuntimeAddress: public Address { 587 588 public: 589 590 RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {} 591 592 }; 593 594 class OopAddress: public Address { 595 596 public: 597 598 OopAddress(address target) : Address(target, relocInfo::oop_type){} 599 600 }; 601 602 class ExternalAddress: public Address { 603 private: 604 static relocInfo::relocType reloc_for_target(address target) { 605 // Sometimes ExternalAddress is used for values which aren't 606 // exactly addresses, like the card table base. 607 // external_word_type can't be used for values in the first page 608 // so just skip the reloc in that case. 609 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; 610 } 611 612 public: 613 614 ExternalAddress(address target) : Address(target, reloc_for_target(target)) {} 615 616 }; 617 618 class InternalAddress: public Address { 619 620 public: 621 622 InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {} 623 }; 624 625 const int FPUStateSizeInWords = 32 * 2; 626 typedef enum { 627 PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM, 628 PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM, 629 PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM 630 } prfop; 631 632 class Assembler : public AbstractAssembler { 633 634 #ifndef PRODUCT 635 static const unsigned long asm_bp; 636 637 void emit_long(jint x) { 638 if ((unsigned long)pc() == asm_bp) 639 asm volatile ("nop"); 640 AbstractAssembler::emit_int32(x); 641 } 642 #else 643 void emit_long(jint x) { 644 AbstractAssembler::emit_int32(x); 645 } 646 #endif 647 648 public: 649 650 enum { instruction_size = 4 }; 651 652 Address adjust(Register base, int offset, bool preIncrement) { 653 if (preIncrement) 654 return Address(Pre(base, offset)); 655 else 656 return Address(Post(base, offset)); 657 } 658 659 Address pre(Register base, int offset) { 660 return adjust(base, offset, true); 661 } 662 663 Address post (Register base, int offset) { 664 return adjust(base, offset, false); 665 } 666 667 Instruction_aarch64* current; 668 669 void set_current(Instruction_aarch64* i) { current = i; } 670 671 void f(unsigned val, int msb, int lsb) { 672 current->f(val, msb, lsb); 673 } 674 void f(unsigned val, int msb) { 675 current->f(val, msb, msb); 676 } 677 void sf(long val, int msb, int lsb) { 678 current->sf(val, msb, lsb); 679 } 680 void rf(Register reg, int lsb) { 681 current->rf(reg, lsb); 682 } 683 void srf(Register reg, int lsb) { 684 current->srf(reg, lsb); 685 } 686 void zrf(Register reg, int lsb) { 687 current->zrf(reg, lsb); 688 } 689 void rf(FloatRegister reg, int lsb) { 690 current->rf(reg, lsb); 691 } 692 void fixed(unsigned value, unsigned mask) { 693 current->fixed(value, mask); 694 } 695 696 void emit() { 697 emit_long(current->get_insn()); 698 assert_cond(current->get_bits() == 0xffffffff); 699 current = NULL; 700 } 701 702 typedef void (Assembler::* uncond_branch_insn)(address dest); 703 typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest); 704 typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest); 705 typedef void (Assembler::* prefetch_insn)(address target, prfop); 706 707 void wrap_label(Label &L, uncond_branch_insn insn); 708 void wrap_label(Register r, Label &L, compare_and_branch_insn insn); 709 void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn); 710 void wrap_label(Label &L, prfop, prefetch_insn insn); 711 712 // PC-rel. addressing 713 714 void adr(Register Rd, address dest); 715 void _adrp(Register Rd, address dest); 716 717 void adr(Register Rd, const Address &dest); 718 void _adrp(Register Rd, const Address &dest); 719 720 void adr(Register Rd, Label &L) { 721 wrap_label(Rd, L, &Assembler::Assembler::adr); 722 } 723 void _adrp(Register Rd, Label &L) { 724 wrap_label(Rd, L, &Assembler::_adrp); 725 } 726 727 void adrp(Register Rd, const Address &dest, unsigned long &offset); 728 729 #undef INSN 730 731 void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op, 732 int negated_op); 733 734 // Add/subtract (immediate) 735 #define INSN(NAME, decode, negated) \ 736 void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \ 737 starti; \ 738 f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \ 739 zrf(Rd, 0), srf(Rn, 5); \ 740 } \ 741 \ 742 void NAME(Register Rd, Register Rn, unsigned imm) { \ 743 starti; \ 744 add_sub_immediate(Rd, Rn, imm, decode, negated); \ 745 } 746 747 INSN(addsw, 0b001, 0b011); 748 INSN(subsw, 0b011, 0b001); 749 INSN(adds, 0b101, 0b111); 750 INSN(subs, 0b111, 0b101); 751 752 #undef INSN 753 754 #define INSN(NAME, decode, negated) \ 755 void NAME(Register Rd, Register Rn, unsigned imm) { \ 756 starti; \ 757 add_sub_immediate(Rd, Rn, imm, decode, negated); \ 758 } 759 760 INSN(addw, 0b000, 0b010); 761 INSN(subw, 0b010, 0b000); 762 INSN(add, 0b100, 0b110); 763 INSN(sub, 0b110, 0b100); 764 765 #undef INSN 766 767 // Logical (immediate) 768 #define INSN(NAME, decode, is32) \ 769 void NAME(Register Rd, Register Rn, uint64_t imm) { \ 770 starti; \ 771 uint32_t val = encode_logical_immediate(is32, imm); \ 772 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \ 773 srf(Rd, 0), zrf(Rn, 5); \ 774 } 775 776 INSN(andw, 0b000, true); 777 INSN(orrw, 0b001, true); 778 INSN(eorw, 0b010, true); 779 INSN(andr, 0b100, false); 780 INSN(orr, 0b101, false); 781 INSN(eor, 0b110, false); 782 783 #undef INSN 784 785 #define INSN(NAME, decode, is32) \ 786 void NAME(Register Rd, Register Rn, uint64_t imm) { \ 787 starti; \ 788 uint32_t val = encode_logical_immediate(is32, imm); \ 789 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \ 790 zrf(Rd, 0), zrf(Rn, 5); \ 791 } 792 793 INSN(ands, 0b111, false); 794 INSN(andsw, 0b011, true); 795 796 #undef INSN 797 798 // Move wide (immediate) 799 #define INSN(NAME, opcode) \ 800 void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \ 801 assert_cond((shift/16)*16 == shift); \ 802 starti; \ 803 f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \ 804 f(imm, 20, 5); \ 805 rf(Rd, 0); \ 806 } 807 808 INSN(movnw, 0b000); 809 INSN(movzw, 0b010); 810 INSN(movkw, 0b011); 811 INSN(movn, 0b100); 812 INSN(movz, 0b110); 813 INSN(movk, 0b111); 814 815 #undef INSN 816 817 // Bitfield 818 #define INSN(NAME, opcode) \ 819 void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \ 820 starti; \ 821 f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \ 822 rf(Rn, 5), rf(Rd, 0); \ 823 } 824 825 INSN(sbfmw, 0b0001001100); 826 INSN(bfmw, 0b0011001100); 827 INSN(ubfmw, 0b0101001100); 828 INSN(sbfm, 0b1001001101); 829 INSN(bfm, 0b1011001101); 830 INSN(ubfm, 0b1101001101); 831 832 #undef INSN 833 834 // Extract 835 #define INSN(NAME, opcode) \ 836 void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \ 837 starti; \ 838 f(opcode, 31, 21), f(imms, 15, 10); \ 839 rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \ 840 } 841 842 INSN(extrw, 0b00010011100); 843 INSN(extr, 0b10010011110); 844 845 #undef INSN 846 847 // The maximum range of a branch is fixed for the AArch64 848 // architecture. In debug mode we shrink it in order to test 849 // trampolines, but not so small that branches in the interpreter 850 // are out of range. 851 static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M); 852 853 static bool reachable_from_branch_at(address branch, address target) { 854 return uabs(target - branch) < branch_range; 855 } 856 857 // Unconditional branch (immediate) 858 #define INSN(NAME, opcode) \ 859 void NAME(address dest) { \ 860 starti; \ 861 long offset = (dest - pc()) >> 2; \ 862 DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \ 863 f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \ 864 } \ 865 void NAME(Label &L) { \ 866 wrap_label(L, &Assembler::NAME); \ 867 } \ 868 void NAME(const Address &dest); 869 870 INSN(b, 0); 871 INSN(bl, 1); 872 873 #undef INSN 874 875 // Compare & branch (immediate) 876 #define INSN(NAME, opcode) \ 877 void NAME(Register Rt, address dest) { \ 878 long offset = (dest - pc()) >> 2; \ 879 starti; \ 880 f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \ 881 } \ 882 void NAME(Register Rt, Label &L) { \ 883 wrap_label(Rt, L, &Assembler::NAME); \ 884 } 885 886 INSN(cbzw, 0b00110100); 887 INSN(cbnzw, 0b00110101); 888 INSN(cbz, 0b10110100); 889 INSN(cbnz, 0b10110101); 890 891 #undef INSN 892 893 // Test & branch (immediate) 894 #define INSN(NAME, opcode) \ 895 void NAME(Register Rt, int bitpos, address dest) { \ 896 long offset = (dest - pc()) >> 2; \ 897 int b5 = bitpos >> 5; \ 898 bitpos &= 0x1f; \ 899 starti; \ 900 f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \ 901 rf(Rt, 0); \ 902 } \ 903 void NAME(Register Rt, int bitpos, Label &L) { \ 904 wrap_label(Rt, bitpos, L, &Assembler::NAME); \ 905 } 906 907 INSN(tbz, 0b0110110); 908 INSN(tbnz, 0b0110111); 909 910 #undef INSN 911 912 // Conditional branch (immediate) 913 enum Condition 914 {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV}; 915 916 void br(Condition cond, address dest) { 917 long offset = (dest - pc()) >> 2; 918 starti; 919 f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0); 920 } 921 922 #define INSN(NAME, cond) \ 923 void NAME(address dest) { \ 924 br(cond, dest); \ 925 } 926 927 INSN(beq, EQ); 928 INSN(bne, NE); 929 INSN(bhs, HS); 930 INSN(bcs, CS); 931 INSN(blo, LO); 932 INSN(bcc, CC); 933 INSN(bmi, MI); 934 INSN(bpl, PL); 935 INSN(bvs, VS); 936 INSN(bvc, VC); 937 INSN(bhi, HI); 938 INSN(bls, LS); 939 INSN(bge, GE); 940 INSN(blt, LT); 941 INSN(bgt, GT); 942 INSN(ble, LE); 943 INSN(bal, AL); 944 INSN(bnv, NV); 945 946 void br(Condition cc, Label &L); 947 948 #undef INSN 949 950 // Exception generation 951 void generate_exception(int opc, int op2, int LL, unsigned imm) { 952 starti; 953 f(0b11010100, 31, 24); 954 f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0); 955 } 956 957 #define INSN(NAME, opc, op2, LL) \ 958 void NAME(unsigned imm) { \ 959 generate_exception(opc, op2, LL, imm); \ 960 } 961 962 INSN(svc, 0b000, 0, 0b01); 963 INSN(hvc, 0b000, 0, 0b10); 964 INSN(smc, 0b000, 0, 0b11); 965 INSN(brk, 0b001, 0, 0b00); 966 INSN(hlt, 0b010, 0, 0b00); 967 INSN(dpcs1, 0b101, 0, 0b01); 968 INSN(dpcs2, 0b101, 0, 0b10); 969 INSN(dpcs3, 0b101, 0, 0b11); 970 971 #undef INSN 972 973 // System 974 void system(int op0, int op1, int CRn, int CRm, int op2, 975 Register rt = dummy_reg) 976 { 977 starti; 978 f(0b11010101000, 31, 21); 979 f(op0, 20, 19); 980 f(op1, 18, 16); 981 f(CRn, 15, 12); 982 f(CRm, 11, 8); 983 f(op2, 7, 5); 984 rf(rt, 0); 985 } 986 987 void hint(int imm) { 988 system(0b00, 0b011, 0b0010, imm, 0b000); 989 } 990 991 void nop() { 992 hint(0); 993 } 994 // we only provide mrs and msr for the special purpose system 995 // registers where op1 (instr[20:19]) == 11 and, (currently) only 996 // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1 997 998 void msr(int op1, int CRn, int CRm, int op2, Register rt) { 999 starti; 1000 f(0b1101010100011, 31, 19); 1001 f(op1, 18, 16); 1002 f(CRn, 15, 12); 1003 f(CRm, 11, 8); 1004 f(op2, 7, 5); 1005 // writing zr is ok 1006 zrf(rt, 0); 1007 } 1008 1009 void mrs(int op1, int CRn, int CRm, int op2, Register rt) { 1010 starti; 1011 f(0b1101010100111, 31, 19); 1012 f(op1, 18, 16); 1013 f(CRn, 15, 12); 1014 f(CRm, 11, 8); 1015 f(op2, 7, 5); 1016 // reading to zr is a mistake 1017 rf(rt, 0); 1018 } 1019 1020 enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH, 1021 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY}; 1022 1023 void dsb(barrier imm) { 1024 system(0b00, 0b011, 0b00011, imm, 0b100); 1025 } 1026 1027 void dmb(barrier imm) { 1028 system(0b00, 0b011, 0b00011, imm, 0b101); 1029 } 1030 1031 void isb() { 1032 system(0b00, 0b011, 0b00011, SY, 0b110); 1033 } 1034 1035 void dc(Register Rt) { 1036 system(0b01, 0b011, 0b0111, 0b1011, 0b001, Rt); 1037 } 1038 1039 void ic(Register Rt) { 1040 system(0b01, 0b011, 0b0111, 0b0101, 0b001, Rt); 1041 } 1042 1043 // A more convenient access to dmb for our purposes 1044 enum Membar_mask_bits { 1045 // We can use ISH for a barrier because the ARM ARM says "This 1046 // architecture assumes that all Processing Elements that use the 1047 // same operating system or hypervisor are in the same Inner 1048 // Shareable shareability domain." 1049 StoreStore = ISHST, 1050 LoadStore = ISHLD, 1051 LoadLoad = ISHLD, 1052 StoreLoad = ISH, 1053 AnyAny = ISH 1054 }; 1055 1056 void membar(Membar_mask_bits order_constraint) { 1057 dmb(Assembler::barrier(order_constraint)); 1058 } 1059 1060 // Unconditional branch (register) 1061 void branch_reg(Register R, int opc) { 1062 starti; 1063 f(0b1101011, 31, 25); 1064 f(opc, 24, 21); 1065 f(0b11111000000, 20, 10); 1066 rf(R, 5); 1067 f(0b00000, 4, 0); 1068 } 1069 1070 #define INSN(NAME, opc) \ 1071 void NAME(Register R) { \ 1072 branch_reg(R, opc); \ 1073 } 1074 1075 INSN(br, 0b0000); 1076 INSN(blr, 0b0001); 1077 INSN(ret, 0b0010); 1078 1079 void ret(void *p); // This forces a compile-time error for ret(0) 1080 1081 #undef INSN 1082 1083 #define INSN(NAME, opc) \ 1084 void NAME() { \ 1085 branch_reg(dummy_reg, opc); \ 1086 } 1087 1088 INSN(eret, 0b0100); 1089 INSN(drps, 0b0101); 1090 1091 #undef INSN 1092 1093 // Load/store exclusive 1094 enum operand_size { byte, halfword, word, xword }; 1095 1096 void load_store_exclusive(Register Rs, Register Rt1, Register Rt2, 1097 Register Rn, enum operand_size sz, int op, bool ordered) { 1098 starti; 1099 f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21); 1100 rf(Rs, 16), f(ordered, 15), rf(Rt2, 10), rf(Rn, 5), rf(Rt1, 0); 1101 } 1102 1103 void load_exclusive(Register dst, Register addr, 1104 enum operand_size sz, bool ordered) { 1105 load_store_exclusive(dummy_reg, dst, dummy_reg, addr, 1106 sz, 0b010, ordered); 1107 } 1108 1109 void store_exclusive(Register status, Register new_val, Register addr, 1110 enum operand_size sz, bool ordered) { 1111 load_store_exclusive(status, new_val, dummy_reg, addr, 1112 sz, 0b000, ordered); 1113 } 1114 1115 #define INSN4(NAME, sz, op, o0) /* Four registers */ \ 1116 void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \ 1117 guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \ 1118 load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \ 1119 } 1120 1121 #define INSN3(NAME, sz, op, o0) /* Three registers */ \ 1122 void NAME(Register Rs, Register Rt, Register Rn) { \ 1123 guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction"); \ 1124 load_store_exclusive(Rs, Rt, dummy_reg, Rn, sz, op, o0); \ 1125 } 1126 1127 #define INSN2(NAME, sz, op, o0) /* Two registers */ \ 1128 void NAME(Register Rt, Register Rn) { \ 1129 load_store_exclusive(dummy_reg, Rt, dummy_reg, \ 1130 Rn, sz, op, o0); \ 1131 } 1132 1133 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \ 1134 void NAME(Register Rt1, Register Rt2, Register Rn) { \ 1135 guarantee(Rt1 != Rt2, "unpredictable instruction"); \ 1136 load_store_exclusive(dummy_reg, Rt1, Rt2, Rn, sz, op, o0); \ 1137 } 1138 1139 // bytes 1140 INSN3(stxrb, byte, 0b000, 0); 1141 INSN3(stlxrb, byte, 0b000, 1); 1142 INSN2(ldxrb, byte, 0b010, 0); 1143 INSN2(ldaxrb, byte, 0b010, 1); 1144 INSN2(stlrb, byte, 0b100, 1); 1145 INSN2(ldarb, byte, 0b110, 1); 1146 1147 // halfwords 1148 INSN3(stxrh, halfword, 0b000, 0); 1149 INSN3(stlxrh, halfword, 0b000, 1); 1150 INSN2(ldxrh, halfword, 0b010, 0); 1151 INSN2(ldaxrh, halfword, 0b010, 1); 1152 INSN2(stlrh, halfword, 0b100, 1); 1153 INSN2(ldarh, halfword, 0b110, 1); 1154 1155 // words 1156 INSN3(stxrw, word, 0b000, 0); 1157 INSN3(stlxrw, word, 0b000, 1); 1158 INSN4(stxpw, word, 0b001, 0); 1159 INSN4(stlxpw, word, 0b001, 1); 1160 INSN2(ldxrw, word, 0b010, 0); 1161 INSN2(ldaxrw, word, 0b010, 1); 1162 INSN_FOO(ldxpw, word, 0b011, 0); 1163 INSN_FOO(ldaxpw, word, 0b011, 1); 1164 INSN2(stlrw, word, 0b100, 1); 1165 INSN2(ldarw, word, 0b110, 1); 1166 1167 // xwords 1168 INSN3(stxr, xword, 0b000, 0); 1169 INSN3(stlxr, xword, 0b000, 1); 1170 INSN4(stxp, xword, 0b001, 0); 1171 INSN4(stlxp, xword, 0b001, 1); 1172 INSN2(ldxr, xword, 0b010, 0); 1173 INSN2(ldaxr, xword, 0b010, 1); 1174 INSN_FOO(ldxp, xword, 0b011, 0); 1175 INSN_FOO(ldaxp, xword, 0b011, 1); 1176 INSN2(stlr, xword, 0b100, 1); 1177 INSN2(ldar, xword, 0b110, 1); 1178 1179 #undef INSN2 1180 #undef INSN3 1181 #undef INSN4 1182 #undef INSN_FOO 1183 1184 // 8.1 Compare and swap extensions 1185 void lse_cas(Register Rs, Register Rt, Register Rn, 1186 enum operand_size sz, bool a, bool r, bool not_pair) { 1187 starti; 1188 if (! not_pair) { // Pair 1189 assert(sz == word || sz == xword, "invalid size"); 1190 /* The size bit is in bit 30, not 31 */ 1191 sz = (operand_size)(sz == word ? 0b00:0b01); 1192 } 1193 f(sz, 31, 30), f(0b001000, 29, 24), f(1, 23), f(a, 22), f(1, 21); 1194 rf(Rs, 16), f(r, 15), f(0b11111, 14, 10), rf(Rn, 5), rf(Rt, 0); 1195 } 1196 1197 // CAS 1198 #define INSN(NAME, a, r) \ 1199 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \ 1200 assert(Rs != Rn && Rs != Rt, "unpredictable instruction"); \ 1201 lse_cas(Rs, Rt, Rn, sz, a, r, true); \ 1202 } 1203 INSN(cas, false, false) 1204 INSN(casa, true, false) 1205 INSN(casl, false, true) 1206 INSN(casal, true, true) 1207 #undef INSN 1208 1209 // CASP 1210 #define INSN(NAME, a, r) \ 1211 void NAME(operand_size sz, Register Rs, Register Rs1, \ 1212 Register Rt, Register Rt1, Register Rn) { \ 1213 assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 && \ 1214 Rs->successor() == Rs1 && Rt->successor() == Rt1 && \ 1215 Rs != Rn && Rs1 != Rn && Rs != Rt, "invalid registers"); \ 1216 lse_cas(Rs, Rt, Rn, sz, a, r, false); \ 1217 } 1218 INSN(casp, false, false) 1219 INSN(caspa, true, false) 1220 INSN(caspl, false, true) 1221 INSN(caspal, true, true) 1222 #undef INSN 1223 1224 // Load register (literal) 1225 #define INSN(NAME, opc, V) \ 1226 void NAME(Register Rt, address dest) { \ 1227 long offset = (dest - pc()) >> 2; \ 1228 starti; \ 1229 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ 1230 sf(offset, 23, 5); \ 1231 rf(Rt, 0); \ 1232 } \ 1233 void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \ 1234 InstructionMark im(this); \ 1235 guarantee(rtype == relocInfo::internal_word_type, \ 1236 "only internal_word_type relocs make sense here"); \ 1237 code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \ 1238 NAME(Rt, dest); \ 1239 } \ 1240 void NAME(Register Rt, Label &L) { \ 1241 wrap_label(Rt, L, &Assembler::NAME); \ 1242 } 1243 1244 INSN(ldrw, 0b00, 0); 1245 INSN(ldr, 0b01, 0); 1246 INSN(ldrsw, 0b10, 0); 1247 1248 #undef INSN 1249 1250 #define INSN(NAME, opc, V) \ 1251 void NAME(FloatRegister Rt, address dest) { \ 1252 long offset = (dest - pc()) >> 2; \ 1253 starti; \ 1254 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ 1255 sf(offset, 23, 5); \ 1256 rf((Register)Rt, 0); \ 1257 } 1258 1259 INSN(ldrs, 0b00, 1); 1260 INSN(ldrd, 0b01, 1); 1261 INSN(ldrq, 0b10, 1); 1262 1263 #undef INSN 1264 1265 #define INSN(NAME, opc, V) \ 1266 void NAME(address dest, prfop op = PLDL1KEEP) { \ 1267 long offset = (dest - pc()) >> 2; \ 1268 starti; \ 1269 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ 1270 sf(offset, 23, 5); \ 1271 f(op, 4, 0); \ 1272 } \ 1273 void NAME(Label &L, prfop op = PLDL1KEEP) { \ 1274 wrap_label(L, op, &Assembler::NAME); \ 1275 } 1276 1277 INSN(prfm, 0b11, 0); 1278 1279 #undef INSN 1280 1281 // Load/store 1282 void ld_st1(int opc, int p1, int V, int L, 1283 Register Rt1, Register Rt2, Address adr, bool no_allocate) { 1284 starti; 1285 f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22); 1286 zrf(Rt2, 10), zrf(Rt1, 0); 1287 if (no_allocate) { 1288 adr.encode_nontemporal_pair(current); 1289 } else { 1290 adr.encode_pair(current); 1291 } 1292 } 1293 1294 // Load/store register pair (offset) 1295 #define INSN(NAME, size, p1, V, L, no_allocate) \ 1296 void NAME(Register Rt1, Register Rt2, Address adr) { \ 1297 ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \ 1298 } 1299 1300 INSN(stpw, 0b00, 0b101, 0, 0, false); 1301 INSN(ldpw, 0b00, 0b101, 0, 1, false); 1302 INSN(ldpsw, 0b01, 0b101, 0, 1, false); 1303 INSN(stp, 0b10, 0b101, 0, 0, false); 1304 INSN(ldp, 0b10, 0b101, 0, 1, false); 1305 1306 // Load/store no-allocate pair (offset) 1307 INSN(stnpw, 0b00, 0b101, 0, 0, true); 1308 INSN(ldnpw, 0b00, 0b101, 0, 1, true); 1309 INSN(stnp, 0b10, 0b101, 0, 0, true); 1310 INSN(ldnp, 0b10, 0b101, 0, 1, true); 1311 1312 #undef INSN 1313 1314 #define INSN(NAME, size, p1, V, L, no_allocate) \ 1315 void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \ 1316 ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \ 1317 } 1318 1319 INSN(stps, 0b00, 0b101, 1, 0, false); 1320 INSN(ldps, 0b00, 0b101, 1, 1, false); 1321 INSN(stpd, 0b01, 0b101, 1, 0, false); 1322 INSN(ldpd, 0b01, 0b101, 1, 1, false); 1323 INSN(stpq, 0b10, 0b101, 1, 0, false); 1324 INSN(ldpq, 0b10, 0b101, 1, 1, false); 1325 1326 #undef INSN 1327 1328 // Load/store register (all modes) 1329 void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) { 1330 starti; 1331 1332 f(V, 26); // general reg? 1333 zrf(Rt, 0); 1334 1335 // Encoding for literal loads is done here (rather than pushed 1336 // down into Address::encode) because the encoding of this 1337 // instruction is too different from all of the other forms to 1338 // make it worth sharing. 1339 if (adr.getMode() == Address::literal) { 1340 assert(size == 0b10 || size == 0b11, "bad operand size in ldr"); 1341 assert(op == 0b01, "literal form can only be used with loads"); 1342 f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24); 1343 long offset = (adr.target() - pc()) >> 2; 1344 sf(offset, 23, 5); 1345 code_section()->relocate(pc(), adr.rspec()); 1346 return; 1347 } 1348 1349 f(size, 31, 30); 1350 f(op, 23, 22); // str 1351 adr.encode(current); 1352 } 1353 1354 #define INSN(NAME, size, op) \ 1355 void NAME(Register Rt, const Address &adr) { \ 1356 ld_st2(Rt, adr, size, op); \ 1357 } \ 1358 1359 INSN(str, 0b11, 0b00); 1360 INSN(strw, 0b10, 0b00); 1361 INSN(strb, 0b00, 0b00); 1362 INSN(strh, 0b01, 0b00); 1363 1364 INSN(ldr, 0b11, 0b01); 1365 INSN(ldrw, 0b10, 0b01); 1366 INSN(ldrb, 0b00, 0b01); 1367 INSN(ldrh, 0b01, 0b01); 1368 1369 INSN(ldrsb, 0b00, 0b10); 1370 INSN(ldrsbw, 0b00, 0b11); 1371 INSN(ldrsh, 0b01, 0b10); 1372 INSN(ldrshw, 0b01, 0b11); 1373 INSN(ldrsw, 0b10, 0b10); 1374 1375 #undef INSN 1376 1377 #define INSN(NAME, size, op) \ 1378 void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \ 1379 ld_st2((Register)pfop, adr, size, op); \ 1380 } 1381 1382 INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with 1383 // writeback modes, but the assembler 1384 // doesn't enfore that. 1385 1386 #undef INSN 1387 1388 #define INSN(NAME, size, op) \ 1389 void NAME(FloatRegister Rt, const Address &adr) { \ 1390 ld_st2((Register)Rt, adr, size, op, 1); \ 1391 } 1392 1393 INSN(strd, 0b11, 0b00); 1394 INSN(strs, 0b10, 0b00); 1395 INSN(ldrd, 0b11, 0b01); 1396 INSN(ldrs, 0b10, 0b01); 1397 INSN(strq, 0b00, 0b10); 1398 INSN(ldrq, 0x00, 0b11); 1399 1400 #undef INSN 1401 1402 enum shift_kind { LSL, LSR, ASR, ROR }; 1403 1404 void op_shifted_reg(unsigned decode, 1405 enum shift_kind kind, unsigned shift, 1406 unsigned size, unsigned op) { 1407 f(size, 31); 1408 f(op, 30, 29); 1409 f(decode, 28, 24); 1410 f(shift, 15, 10); 1411 f(kind, 23, 22); 1412 } 1413 1414 // Logical (shifted register) 1415 #define INSN(NAME, size, op, N) \ 1416 void NAME(Register Rd, Register Rn, Register Rm, \ 1417 enum shift_kind kind = LSL, unsigned shift = 0) { \ 1418 starti; \ 1419 f(N, 21); \ 1420 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \ 1421 op_shifted_reg(0b01010, kind, shift, size, op); \ 1422 } 1423 1424 INSN(andr, 1, 0b00, 0); 1425 INSN(orr, 1, 0b01, 0); 1426 INSN(eor, 1, 0b10, 0); 1427 INSN(ands, 1, 0b11, 0); 1428 INSN(andw, 0, 0b00, 0); 1429 INSN(orrw, 0, 0b01, 0); 1430 INSN(eorw, 0, 0b10, 0); 1431 INSN(andsw, 0, 0b11, 0); 1432 1433 INSN(bic, 1, 0b00, 1); 1434 INSN(orn, 1, 0b01, 1); 1435 INSN(eon, 1, 0b10, 1); 1436 INSN(bics, 1, 0b11, 1); 1437 INSN(bicw, 0, 0b00, 1); 1438 INSN(ornw, 0, 0b01, 1); 1439 INSN(eonw, 0, 0b10, 1); 1440 INSN(bicsw, 0, 0b11, 1); 1441 1442 #undef INSN 1443 1444 // Add/subtract (shifted register) 1445 #define INSN(NAME, size, op) \ 1446 void NAME(Register Rd, Register Rn, Register Rm, \ 1447 enum shift_kind kind, unsigned shift = 0) { \ 1448 starti; \ 1449 f(0, 21); \ 1450 assert_cond(kind != ROR); \ 1451 zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \ 1452 op_shifted_reg(0b01011, kind, shift, size, op); \ 1453 } 1454 1455 INSN(add, 1, 0b000); 1456 INSN(sub, 1, 0b10); 1457 INSN(addw, 0, 0b000); 1458 INSN(subw, 0, 0b10); 1459 1460 INSN(adds, 1, 0b001); 1461 INSN(subs, 1, 0b11); 1462 INSN(addsw, 0, 0b001); 1463 INSN(subsw, 0, 0b11); 1464 1465 #undef INSN 1466 1467 // Add/subtract (extended register) 1468 #define INSN(NAME, op) \ 1469 void NAME(Register Rd, Register Rn, Register Rm, \ 1470 ext::operation option, int amount = 0) { \ 1471 starti; \ 1472 zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \ 1473 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \ 1474 } 1475 1476 void add_sub_extended_reg(unsigned op, unsigned decode, 1477 Register Rd, Register Rn, Register Rm, 1478 unsigned opt, ext::operation option, unsigned imm) { 1479 guarantee(imm <= 4, "shift amount must be < 4"); 1480 f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21); 1481 f(option, 15, 13), f(imm, 12, 10); 1482 } 1483 1484 INSN(addw, 0b000); 1485 INSN(subw, 0b010); 1486 INSN(add, 0b100); 1487 INSN(sub, 0b110); 1488 1489 #undef INSN 1490 1491 #define INSN(NAME, op) \ 1492 void NAME(Register Rd, Register Rn, Register Rm, \ 1493 ext::operation option, int amount = 0) { \ 1494 starti; \ 1495 zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \ 1496 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \ 1497 } 1498 1499 INSN(addsw, 0b001); 1500 INSN(subsw, 0b011); 1501 INSN(adds, 0b101); 1502 INSN(subs, 0b111); 1503 1504 #undef INSN 1505 1506 // Aliases for short forms of add and sub 1507 #define INSN(NAME) \ 1508 void NAME(Register Rd, Register Rn, Register Rm) { \ 1509 if (Rd == sp || Rn == sp) \ 1510 NAME(Rd, Rn, Rm, ext::uxtx); \ 1511 else \ 1512 NAME(Rd, Rn, Rm, LSL); \ 1513 } 1514 1515 INSN(addw); 1516 INSN(subw); 1517 INSN(add); 1518 INSN(sub); 1519 1520 INSN(addsw); 1521 INSN(subsw); 1522 INSN(adds); 1523 INSN(subs); 1524 1525 #undef INSN 1526 1527 // Add/subtract (with carry) 1528 void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) { 1529 starti; 1530 f(op, 31, 29); 1531 f(0b11010000, 28, 21); 1532 f(0b000000, 15, 10); 1533 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); 1534 } 1535 1536 #define INSN(NAME, op) \ 1537 void NAME(Register Rd, Register Rn, Register Rm) { \ 1538 add_sub_carry(op, Rd, Rn, Rm); \ 1539 } 1540 1541 INSN(adcw, 0b000); 1542 INSN(adcsw, 0b001); 1543 INSN(sbcw, 0b010); 1544 INSN(sbcsw, 0b011); 1545 INSN(adc, 0b100); 1546 INSN(adcs, 0b101); 1547 INSN(sbc,0b110); 1548 INSN(sbcs, 0b111); 1549 1550 #undef INSN 1551 1552 // Conditional compare (both kinds) 1553 void conditional_compare(unsigned op, int o2, int o3, 1554 Register Rn, unsigned imm5, unsigned nzcv, 1555 unsigned cond) { 1556 f(op, 31, 29); 1557 f(0b11010010, 28, 21); 1558 f(cond, 15, 12); 1559 f(o2, 10); 1560 f(o3, 4); 1561 f(nzcv, 3, 0); 1562 f(imm5, 20, 16), rf(Rn, 5); 1563 } 1564 1565 #define INSN(NAME, op) \ 1566 void NAME(Register Rn, Register Rm, int imm, Condition cond) { \ 1567 starti; \ 1568 f(0, 11); \ 1569 conditional_compare(op, 0, 0, Rn, (uintptr_t)Rm, imm, cond); \ 1570 } \ 1571 \ 1572 void NAME(Register Rn, int imm5, int imm, Condition cond) { \ 1573 starti; \ 1574 f(1, 11); \ 1575 conditional_compare(op, 0, 0, Rn, imm5, imm, cond); \ 1576 } 1577 1578 INSN(ccmnw, 0b001); 1579 INSN(ccmpw, 0b011); 1580 INSN(ccmn, 0b101); 1581 INSN(ccmp, 0b111); 1582 1583 #undef INSN 1584 1585 // Conditional select 1586 void conditional_select(unsigned op, unsigned op2, 1587 Register Rd, Register Rn, Register Rm, 1588 unsigned cond) { 1589 starti; 1590 f(op, 31, 29); 1591 f(0b11010100, 28, 21); 1592 f(cond, 15, 12); 1593 f(op2, 11, 10); 1594 zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0); 1595 } 1596 1597 #define INSN(NAME, op, op2) \ 1598 void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \ 1599 conditional_select(op, op2, Rd, Rn, Rm, cond); \ 1600 } 1601 1602 INSN(cselw, 0b000, 0b00); 1603 INSN(csincw, 0b000, 0b01); 1604 INSN(csinvw, 0b010, 0b00); 1605 INSN(csnegw, 0b010, 0b01); 1606 INSN(csel, 0b100, 0b00); 1607 INSN(csinc, 0b100, 0b01); 1608 INSN(csinv, 0b110, 0b00); 1609 INSN(csneg, 0b110, 0b01); 1610 1611 #undef INSN 1612 1613 // Data processing 1614 void data_processing(unsigned op29, unsigned opcode, 1615 Register Rd, Register Rn) { 1616 f(op29, 31, 29), f(0b11010110, 28, 21); 1617 f(opcode, 15, 10); 1618 rf(Rn, 5), rf(Rd, 0); 1619 } 1620 1621 // (1 source) 1622 #define INSN(NAME, op29, opcode2, opcode) \ 1623 void NAME(Register Rd, Register Rn) { \ 1624 starti; \ 1625 f(opcode2, 20, 16); \ 1626 data_processing(op29, opcode, Rd, Rn); \ 1627 } 1628 1629 INSN(rbitw, 0b010, 0b00000, 0b00000); 1630 INSN(rev16w, 0b010, 0b00000, 0b00001); 1631 INSN(revw, 0b010, 0b00000, 0b00010); 1632 INSN(clzw, 0b010, 0b00000, 0b00100); 1633 INSN(clsw, 0b010, 0b00000, 0b00101); 1634 1635 INSN(rbit, 0b110, 0b00000, 0b00000); 1636 INSN(rev16, 0b110, 0b00000, 0b00001); 1637 INSN(rev32, 0b110, 0b00000, 0b00010); 1638 INSN(rev, 0b110, 0b00000, 0b00011); 1639 INSN(clz, 0b110, 0b00000, 0b00100); 1640 INSN(cls, 0b110, 0b00000, 0b00101); 1641 1642 #undef INSN 1643 1644 // (2 sources) 1645 #define INSN(NAME, op29, opcode) \ 1646 void NAME(Register Rd, Register Rn, Register Rm) { \ 1647 starti; \ 1648 rf(Rm, 16); \ 1649 data_processing(op29, opcode, Rd, Rn); \ 1650 } 1651 1652 INSN(udivw, 0b000, 0b000010); 1653 INSN(sdivw, 0b000, 0b000011); 1654 INSN(lslvw, 0b000, 0b001000); 1655 INSN(lsrvw, 0b000, 0b001001); 1656 INSN(asrvw, 0b000, 0b001010); 1657 INSN(rorvw, 0b000, 0b001011); 1658 1659 INSN(udiv, 0b100, 0b000010); 1660 INSN(sdiv, 0b100, 0b000011); 1661 INSN(lslv, 0b100, 0b001000); 1662 INSN(lsrv, 0b100, 0b001001); 1663 INSN(asrv, 0b100, 0b001010); 1664 INSN(rorv, 0b100, 0b001011); 1665 1666 #undef INSN 1667 1668 // (3 sources) 1669 void data_processing(unsigned op54, unsigned op31, unsigned o0, 1670 Register Rd, Register Rn, Register Rm, 1671 Register Ra) { 1672 starti; 1673 f(op54, 31, 29), f(0b11011, 28, 24); 1674 f(op31, 23, 21), f(o0, 15); 1675 zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0); 1676 } 1677 1678 #define INSN(NAME, op54, op31, o0) \ 1679 void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \ 1680 data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \ 1681 } 1682 1683 INSN(maddw, 0b000, 0b000, 0); 1684 INSN(msubw, 0b000, 0b000, 1); 1685 INSN(madd, 0b100, 0b000, 0); 1686 INSN(msub, 0b100, 0b000, 1); 1687 INSN(smaddl, 0b100, 0b001, 0); 1688 INSN(smsubl, 0b100, 0b001, 1); 1689 INSN(umaddl, 0b100, 0b101, 0); 1690 INSN(umsubl, 0b100, 0b101, 1); 1691 1692 #undef INSN 1693 1694 #define INSN(NAME, op54, op31, o0) \ 1695 void NAME(Register Rd, Register Rn, Register Rm) { \ 1696 data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \ 1697 } 1698 1699 INSN(smulh, 0b100, 0b010, 0); 1700 INSN(umulh, 0b100, 0b110, 0); 1701 1702 #undef INSN 1703 1704 // Floating-point data-processing (1 source) 1705 void data_processing(unsigned op31, unsigned type, unsigned opcode, 1706 FloatRegister Vd, FloatRegister Vn) { 1707 starti; 1708 f(op31, 31, 29); 1709 f(0b11110, 28, 24); 1710 f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10); 1711 rf(Vn, 5), rf(Vd, 0); 1712 } 1713 1714 #define INSN(NAME, op31, type, opcode) \ 1715 void NAME(FloatRegister Vd, FloatRegister Vn) { \ 1716 data_processing(op31, type, opcode, Vd, Vn); \ 1717 } 1718 1719 private: 1720 INSN(i_fmovs, 0b000, 0b00, 0b000000); 1721 public: 1722 INSN(fabss, 0b000, 0b00, 0b000001); 1723 INSN(fnegs, 0b000, 0b00, 0b000010); 1724 INSN(fsqrts, 0b000, 0b00, 0b000011); 1725 INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision 1726 1727 private: 1728 INSN(i_fmovd, 0b000, 0b01, 0b000000); 1729 public: 1730 INSN(fabsd, 0b000, 0b01, 0b000001); 1731 INSN(fnegd, 0b000, 0b01, 0b000010); 1732 INSN(fsqrtd, 0b000, 0b01, 0b000011); 1733 INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision 1734 1735 void fmovd(FloatRegister Vd, FloatRegister Vn) { 1736 assert(Vd != Vn, "should be"); 1737 i_fmovd(Vd, Vn); 1738 } 1739 1740 void fmovs(FloatRegister Vd, FloatRegister Vn) { 1741 assert(Vd != Vn, "should be"); 1742 i_fmovs(Vd, Vn); 1743 } 1744 1745 #undef INSN 1746 1747 // Floating-point data-processing (2 source) 1748 void data_processing(unsigned op31, unsigned type, unsigned opcode, 1749 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { 1750 starti; 1751 f(op31, 31, 29); 1752 f(0b11110, 28, 24); 1753 f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10); 1754 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); 1755 } 1756 1757 #define INSN(NAME, op31, type, opcode) \ 1758 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \ 1759 data_processing(op31, type, opcode, Vd, Vn, Vm); \ 1760 } 1761 1762 INSN(fmuls, 0b000, 0b00, 0b0000); 1763 INSN(fdivs, 0b000, 0b00, 0b0001); 1764 INSN(fadds, 0b000, 0b00, 0b0010); 1765 INSN(fsubs, 0b000, 0b00, 0b0011); 1766 INSN(fnmuls, 0b000, 0b00, 0b1000); 1767 1768 INSN(fmuld, 0b000, 0b01, 0b0000); 1769 INSN(fdivd, 0b000, 0b01, 0b0001); 1770 INSN(faddd, 0b000, 0b01, 0b0010); 1771 INSN(fsubd, 0b000, 0b01, 0b0011); 1772 INSN(fnmuld, 0b000, 0b01, 0b1000); 1773 1774 #undef INSN 1775 1776 // Floating-point data-processing (3 source) 1777 void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0, 1778 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, 1779 FloatRegister Va) { 1780 starti; 1781 f(op31, 31, 29); 1782 f(0b11111, 28, 24); 1783 f(type, 23, 22), f(o1, 21), f(o0, 15); 1784 rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0); 1785 } 1786 1787 #define INSN(NAME, op31, type, o1, o0) \ 1788 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \ 1789 FloatRegister Va) { \ 1790 data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \ 1791 } 1792 1793 INSN(fmadds, 0b000, 0b00, 0, 0); 1794 INSN(fmsubs, 0b000, 0b00, 0, 1); 1795 INSN(fnmadds, 0b000, 0b00, 1, 0); 1796 INSN(fnmsubs, 0b000, 0b00, 1, 1); 1797 1798 INSN(fmaddd, 0b000, 0b01, 0, 0); 1799 INSN(fmsubd, 0b000, 0b01, 0, 1); 1800 INSN(fnmaddd, 0b000, 0b01, 1, 0); 1801 INSN(fnmsub, 0b000, 0b01, 1, 1); 1802 1803 #undef INSN 1804 1805 // Floating-point conditional select 1806 void fp_conditional_select(unsigned op31, unsigned type, 1807 unsigned op1, unsigned op2, 1808 Condition cond, FloatRegister Vd, 1809 FloatRegister Vn, FloatRegister Vm) { 1810 starti; 1811 f(op31, 31, 29); 1812 f(0b11110, 28, 24); 1813 f(type, 23, 22); 1814 f(op1, 21, 21); 1815 f(op2, 11, 10); 1816 f(cond, 15, 12); 1817 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); 1818 } 1819 1820 #define INSN(NAME, op31, type, op1, op2) \ 1821 void NAME(FloatRegister Vd, FloatRegister Vn, \ 1822 FloatRegister Vm, Condition cond) { \ 1823 fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \ 1824 } 1825 1826 INSN(fcsels, 0b000, 0b00, 0b1, 0b11); 1827 INSN(fcseld, 0b000, 0b01, 0b1, 0b11); 1828 1829 #undef INSN 1830 1831 // Floating-point<->integer conversions 1832 void float_int_convert(unsigned op31, unsigned type, 1833 unsigned rmode, unsigned opcode, 1834 Register Rd, Register Rn) { 1835 starti; 1836 f(op31, 31, 29); 1837 f(0b11110, 28, 24); 1838 f(type, 23, 22), f(1, 21), f(rmode, 20, 19); 1839 f(opcode, 18, 16), f(0b000000, 15, 10); 1840 zrf(Rn, 5), zrf(Rd, 0); 1841 } 1842 1843 #define INSN(NAME, op31, type, rmode, opcode) \ 1844 void NAME(Register Rd, FloatRegister Vn) { \ 1845 float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \ 1846 } 1847 1848 INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000); 1849 INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000); 1850 INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000); 1851 INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000); 1852 1853 INSN(fmovs, 0b000, 0b00, 0b00, 0b110); 1854 INSN(fmovd, 0b100, 0b01, 0b00, 0b110); 1855 1856 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110); 1857 1858 #undef INSN 1859 1860 #define INSN(NAME, op31, type, rmode, opcode) \ 1861 void NAME(FloatRegister Vd, Register Rn) { \ 1862 float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \ 1863 } 1864 1865 INSN(fmovs, 0b000, 0b00, 0b00, 0b111); 1866 INSN(fmovd, 0b100, 0b01, 0b00, 0b111); 1867 1868 INSN(scvtfws, 0b000, 0b00, 0b00, 0b010); 1869 INSN(scvtfs, 0b100, 0b00, 0b00, 0b010); 1870 INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010); 1871 INSN(scvtfd, 0b100, 0b01, 0b00, 0b010); 1872 1873 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111); 1874 1875 #undef INSN 1876 1877 // Floating-point compare 1878 void float_compare(unsigned op31, unsigned type, 1879 unsigned op, unsigned op2, 1880 FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) { 1881 starti; 1882 f(op31, 31, 29); 1883 f(0b11110, 28, 24); 1884 f(type, 23, 22), f(1, 21); 1885 f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0); 1886 rf(Vn, 5), rf(Vm, 16); 1887 } 1888 1889 1890 #define INSN(NAME, op31, type, op, op2) \ 1891 void NAME(FloatRegister Vn, FloatRegister Vm) { \ 1892 float_compare(op31, type, op, op2, Vn, Vm); \ 1893 } 1894 1895 #define INSN1(NAME, op31, type, op, op2) \ 1896 void NAME(FloatRegister Vn, double d) { \ 1897 assert_cond(d == 0.0); \ 1898 float_compare(op31, type, op, op2, Vn); \ 1899 } 1900 1901 INSN(fcmps, 0b000, 0b00, 0b00, 0b00000); 1902 INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000); 1903 // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000); 1904 // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000); 1905 1906 INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000); 1907 INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000); 1908 // INSN(fcmped, 0b000, 0b01, 0b00, 0b10000); 1909 // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000); 1910 1911 #undef INSN 1912 #undef INSN1 1913 1914 // Floating-point Move (immediate) 1915 private: 1916 unsigned pack(double value); 1917 1918 void fmov_imm(FloatRegister Vn, double value, unsigned size) { 1919 starti; 1920 f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21); 1921 f(pack(value), 20, 13), f(0b10000000, 12, 5); 1922 rf(Vn, 0); 1923 } 1924 1925 public: 1926 1927 void fmovs(FloatRegister Vn, double value) { 1928 if (value) 1929 fmov_imm(Vn, value, 0b00); 1930 else 1931 fmovs(Vn, zr); 1932 } 1933 void fmovd(FloatRegister Vn, double value) { 1934 if (value) 1935 fmov_imm(Vn, value, 0b01); 1936 else 1937 fmovd(Vn, zr); 1938 } 1939 1940 /* SIMD extensions 1941 * 1942 * We just use FloatRegister in the following. They are exactly the same 1943 * as SIMD registers. 1944 */ 1945 public: 1946 1947 enum SIMD_Arrangement { 1948 T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q 1949 }; 1950 1951 enum SIMD_RegVariant { 1952 B, H, S, D, Q 1953 }; 1954 1955 #define INSN(NAME, op) \ 1956 void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \ 1957 ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \ 1958 } \ 1959 1960 INSN(ldr, 1); 1961 INSN(str, 0); 1962 1963 #undef INSN 1964 1965 private: 1966 1967 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) { 1968 starti; 1969 f(0,31), f((int)T & 1, 30); 1970 f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12); 1971 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0); 1972 } 1973 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, 1974 int imm, int op1, int op2) { 1975 starti; 1976 f(0,31), f((int)T & 1, 30); 1977 f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12); 1978 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0); 1979 } 1980 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, 1981 Register Xm, int op1, int op2) { 1982 starti; 1983 f(0,31), f((int)T & 1, 30); 1984 f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12); 1985 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0); 1986 } 1987 1988 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2) { 1989 switch (a.getMode()) { 1990 case Address::base_plus_offset: 1991 guarantee(a.offset() == 0, "no offset allowed here"); 1992 ld_st(Vt, T, a.base(), op1, op2); 1993 break; 1994 case Address::post: 1995 ld_st(Vt, T, a.base(), a.offset(), op1, op2); 1996 break; 1997 case Address::base_plus_offset_reg: 1998 ld_st(Vt, T, a.base(), a.index(), op1, op2); 1999 break; 2000 default: 2001 ShouldNotReachHere(); 2002 } 2003 } 2004 2005 public: 2006 2007 #define INSN1(NAME, op1, op2) \ 2008 void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \ 2009 ld_st(Vt, T, a, op1, op2); \ 2010 } 2011 2012 #define INSN2(NAME, op1, op2) \ 2013 void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \ 2014 assert(Vt->successor() == Vt2, "Registers must be ordered"); \ 2015 ld_st(Vt, T, a, op1, op2); \ 2016 } 2017 2018 #define INSN3(NAME, op1, op2) \ 2019 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \ 2020 SIMD_Arrangement T, const Address &a) { \ 2021 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \ 2022 "Registers must be ordered"); \ 2023 ld_st(Vt, T, a, op1, op2); \ 2024 } 2025 2026 #define INSN4(NAME, op1, op2) \ 2027 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \ 2028 FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \ 2029 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \ 2030 Vt3->successor() == Vt4, "Registers must be ordered"); \ 2031 ld_st(Vt, T, a, op1, op2); \ 2032 } 2033 2034 INSN1(ld1, 0b001100010, 0b0111); 2035 INSN2(ld1, 0b001100010, 0b1010); 2036 INSN3(ld1, 0b001100010, 0b0110); 2037 INSN4(ld1, 0b001100010, 0b0010); 2038 2039 INSN2(ld2, 0b001100010, 0b1000); 2040 INSN3(ld3, 0b001100010, 0b0100); 2041 INSN4(ld4, 0b001100010, 0b0000); 2042 2043 INSN1(st1, 0b001100000, 0b0111); 2044 INSN2(st1, 0b001100000, 0b1010); 2045 INSN3(st1, 0b001100000, 0b0110); 2046 INSN4(st1, 0b001100000, 0b0010); 2047 2048 INSN2(st2, 0b001100000, 0b1000); 2049 INSN3(st3, 0b001100000, 0b0100); 2050 INSN4(st4, 0b001100000, 0b0000); 2051 2052 INSN1(ld1r, 0b001101010, 0b1100); 2053 INSN2(ld2r, 0b001101011, 0b1100); 2054 INSN3(ld3r, 0b001101010, 0b1110); 2055 INSN4(ld4r, 0b001101011, 0b1110); 2056 2057 #undef INSN1 2058 #undef INSN2 2059 #undef INSN3 2060 #undef INSN4 2061 2062 #define INSN(NAME, opc) \ 2063 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2064 starti; \ 2065 assert(T == T8B || T == T16B, "must be T8B or T16B"); \ 2066 f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \ 2067 rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2068 } 2069 2070 INSN(eor, 0b101110001); 2071 INSN(orr, 0b001110101); 2072 INSN(andr, 0b001110001); 2073 INSN(bic, 0b001110011); 2074 INSN(bif, 0b101110111); 2075 INSN(bit, 0b101110101); 2076 INSN(bsl, 0b101110011); 2077 INSN(orn, 0b001110111); 2078 2079 #undef INSN 2080 2081 #define INSN(NAME, opc, opc2) \ 2082 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2083 starti; \ 2084 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \ 2085 f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \ 2086 rf(Vn, 5), rf(Vd, 0); \ 2087 } 2088 2089 INSN(addv, 0, 0b100001); 2090 INSN(subv, 1, 0b100001); 2091 INSN(mulv, 0, 0b100111); 2092 INSN(mlav, 0, 0b100101); 2093 INSN(mlsv, 1, 0b100101); 2094 INSN(sshl, 0, 0b010001); 2095 INSN(ushl, 1, 0b010001); 2096 2097 #undef INSN 2098 2099 #define INSN(NAME, opc, opc2) \ 2100 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ 2101 starti; \ 2102 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \ 2103 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \ 2104 rf(Vn, 5), rf(Vd, 0); \ 2105 } 2106 2107 INSN(absr, 0, 0b100000101110); 2108 INSN(negr, 1, 0b100000101110); 2109 INSN(notr, 1, 0b100000010110); 2110 INSN(addv, 0, 0b110001101110); 2111 INSN(cls, 0, 0b100000010010); 2112 INSN(clz, 1, 0b100000010010); 2113 INSN(cnt, 0, 0b100000010110); 2114 2115 #undef INSN 2116 2117 #define INSN(NAME, op0, cmode0) \ 2118 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \ 2119 unsigned cmode = cmode0; \ 2120 unsigned op = op0; \ 2121 starti; \ 2122 assert(lsl == 0 || \ 2123 ((T == T4H || T == T8H) && lsl == 8) || \ 2124 ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \ 2125 cmode |= lsl >> 2; \ 2126 if (T == T4H || T == T8H) cmode |= 0b1000; \ 2127 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \ 2128 assert(op == 0 && cmode0 == 0, "must be MOVI"); \ 2129 cmode = 0b1110; \ 2130 if (T == T1D || T == T2D) op = 1; \ 2131 } \ 2132 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \ 2133 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \ 2134 rf(Vd, 0); \ 2135 } 2136 2137 INSN(movi, 0, 0); 2138 INSN(orri, 0, 1); 2139 INSN(mvni, 1, 0); 2140 INSN(bici, 1, 1); 2141 2142 #undef INSN 2143 2144 #define INSN(NAME, op1, op2, op3) \ 2145 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2146 starti; \ 2147 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \ 2148 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \ 2149 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2150 } 2151 2152 INSN(fadd, 0, 0, 0b110101); 2153 INSN(fdiv, 1, 0, 0b111111); 2154 INSN(fmul, 1, 0, 0b110111); 2155 INSN(fsub, 0, 1, 0b110101); 2156 2157 #undef INSN 2158 2159 #define INSN(NAME, opc) \ 2160 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2161 starti; \ 2162 assert(T == T4S, "arrangement must be T4S"); \ 2163 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2164 } 2165 2166 INSN(sha1c, 0b000000); 2167 INSN(sha1m, 0b001000); 2168 INSN(sha1p, 0b000100); 2169 INSN(sha1su0, 0b001100); 2170 INSN(sha256h2, 0b010100); 2171 INSN(sha256h, 0b010000); 2172 INSN(sha256su1, 0b011000); 2173 2174 #undef INSN 2175 2176 #define INSN(NAME, opc) \ 2177 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ 2178 starti; \ 2179 assert(T == T4S, "arrangement must be T4S"); \ 2180 f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2181 } 2182 2183 INSN(sha1h, 0b000010); 2184 INSN(sha1su1, 0b000110); 2185 INSN(sha256su0, 0b001010); 2186 2187 #undef INSN 2188 2189 #define INSN(NAME, opc) \ 2190 void NAME(FloatRegister Vd, FloatRegister Vn) { \ 2191 starti; \ 2192 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \ 2193 } 2194 2195 INSN(aese, 0b0100111000101000010010); 2196 INSN(aesd, 0b0100111000101000010110); 2197 INSN(aesmc, 0b0100111000101000011010); 2198 INSN(aesimc, 0b0100111000101000011110); 2199 2200 #undef INSN 2201 2202 void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) { 2203 starti; 2204 assert(T != Q, "invalid register variant"); 2205 f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15); 2206 f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0); 2207 } 2208 2209 void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) { 2210 starti; 2211 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21); 2212 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10); 2213 rf(Vn, 5), rf(Rd, 0); 2214 } 2215 2216 #define INSN(NAME, opc, opc2) \ 2217 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \ 2218 starti; \ 2219 /* The encodings for the immh:immb fields (bits 22:16) are \ 2220 * 0001 xxx 8B/16B, shift = xxx \ 2221 * 001x xxx 4H/8H, shift = xxxx \ 2222 * 01xx xxx 2S/4S, shift = xxxxx \ 2223 * 1xxx xxx 1D/2D, shift = xxxxxx (1D is RESERVED) \ 2224 */ \ 2225 assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \ 2226 f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \ 2227 f((1 << ((T>>1)+3))|shift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2228 } 2229 2230 INSN(shl, 0, 0b010101); 2231 INSN(sshr, 0, 0b000001); 2232 INSN(ushr, 1, 0b000001); 2233 2234 #undef INSN 2235 2236 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { 2237 starti; 2238 /* The encodings for the immh:immb fields (bits 22:16) are 2239 * 0001 xxx 8H, 8B/16b shift = xxx 2240 * 001x xxx 4S, 4H/8H shift = xxxx 2241 * 01xx xxx 2D, 2S/4S shift = xxxxx 2242 * 1xxx xxx RESERVED 2243 */ 2244 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement"); 2245 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value"); 2246 f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16); 2247 f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0); 2248 } 2249 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { 2250 ushll(Vd, Ta, Vn, Tb, shift); 2251 } 2252 2253 void uzp1(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T, int op = 0){ 2254 starti; 2255 f(0, 31), f((T & 0x1), 30), f(0b001110, 29, 24), f((T >> 1), 23, 22), f(0, 21); 2256 rf(Vm, 16), f(0, 15), f(op, 14), f(0b0110, 13, 10), rf(Vn, 5), rf(Vd, 0); 2257 } 2258 void uzp2(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T){ 2259 uzp1(Vd, Vn, Vm, T, 1); 2260 } 2261 2262 // Move from general purpose register 2263 // mov Vd.T[index], Rn 2264 void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) { 2265 starti; 2266 f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); 2267 f(0b000111, 15, 10), rf(Xn, 5), rf(Vd, 0); 2268 } 2269 2270 // Move to general purpose register 2271 // mov Rd, Vn.T[index] 2272 void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) { 2273 starti; 2274 f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21); 2275 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); 2276 f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0); 2277 } 2278 2279 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) { 2280 starti; 2281 assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) || 2282 (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier"); 2283 int size = (Ta == T1Q) ? 0b11 : 0b00; 2284 f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22); 2285 f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0); 2286 } 2287 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) { 2288 assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier"); 2289 pmull(Vd, Ta, Vn, Vm, Tb); 2290 } 2291 2292 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) { 2293 starti; 2294 int size_b = (int)Tb >> 1; 2295 int size_a = (int)Ta >> 1; 2296 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier"); 2297 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22); 2298 f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0); 2299 } 2300 2301 void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs) 2302 { 2303 starti; 2304 assert(T != T1D, "reserved encoding"); 2305 f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21); 2306 f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), rf(Xs, 5), rf(Vd, 0); 2307 } 2308 2309 void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0) 2310 { 2311 starti; 2312 assert(T != T1D, "reserved encoding"); 2313 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21); 2314 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); 2315 f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0); 2316 } 2317 2318 // CRC32 instructions 2319 #define INSN(NAME, c, sf, sz) \ 2320 void NAME(Register Rd, Register Rn, Register Rm) { \ 2321 starti; \ 2322 f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12); \ 2323 f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \ 2324 } 2325 2326 INSN(crc32b, 0, 0, 0b00); 2327 INSN(crc32h, 0, 0, 0b01); 2328 INSN(crc32w, 0, 0, 0b10); 2329 INSN(crc32x, 0, 1, 0b11); 2330 INSN(crc32cb, 1, 0, 0b00); 2331 INSN(crc32ch, 1, 0, 0b01); 2332 INSN(crc32cw, 1, 0, 0b10); 2333 INSN(crc32cx, 1, 1, 0b11); 2334 2335 #undef INSN 2336 2337 // Table vector lookup 2338 #define INSN(NAME, op) \ 2339 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \ 2340 starti; \ 2341 assert(T == T8B || T == T16B, "invalid arrangement"); \ 2342 assert(0 < registers && registers <= 4, "invalid number of registers"); \ 2343 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \ 2344 f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \ 2345 } 2346 2347 INSN(tbl, 0); 2348 INSN(tbx, 1); 2349 2350 #undef INSN 2351 2352 // AdvSIMD two-reg misc 2353 #define INSN(NAME, U, opcode) \ 2354 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ 2355 starti; \ 2356 assert((ASSERTION), MSG); \ 2357 f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24); \ 2358 f((int)(T >> 1), 23, 22), f(0b10000, 21, 17), f(opcode, 16, 12); \ 2359 f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0); \ 2360 } 2361 2362 #define MSG "invalid arrangement" 2363 2364 #define ASSERTION (T == T2S || T == T4S || T == T2D) 2365 INSN(fsqrt, 1, 0b11111); 2366 INSN(fabs, 0, 0b01111); 2367 INSN(fneg, 1, 0b01111); 2368 #undef ASSERTION 2369 2370 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S) 2371 INSN(rev64, 0, 0b00000); 2372 #undef ASSERTION 2373 2374 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H) 2375 INSN(rev32, 1, 0b00000); 2376 private: 2377 INSN(_rbit, 1, 0b00101); 2378 public: 2379 2380 #undef ASSERTION 2381 2382 #define ASSERTION (T == T8B || T == T16B) 2383 INSN(rev16, 0, 0b00001); 2384 // RBIT only allows T8B and T16B but encodes them oddly. Argh... 2385 void rbit(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { 2386 assert((ASSERTION), MSG); 2387 _rbit(Vd, SIMD_Arrangement(T & 1 | 0b010), Vn); 2388 } 2389 #undef ASSERTION 2390 2391 #undef MSG 2392 2393 #undef INSN 2394 2395 void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index) 2396 { 2397 starti; 2398 assert(T == T8B || T == T16B, "invalid arrangement"); 2399 assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value"); 2400 f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21); 2401 rf(Vm, 16), f(0, 15), f(index, 14, 11); 2402 f(0, 10), rf(Vn, 5), rf(Vd, 0); 2403 } 2404 2405 /* Simulator extensions to the ISA 2406 2407 haltsim 2408 2409 takes no arguments, causes the sim to enter a debug break and then 2410 return from the simulator run() call with STATUS_HALT? The linking 2411 code will call fatal() when it sees STATUS_HALT. 2412 2413 blrt Xn, Wm 2414 blrt Xn, #gpargs, #fpargs, #type 2415 Xn holds the 64 bit x86 branch_address 2416 call format is encoded either as immediate data in the call 2417 or in register Wm. In the latter case 2418 Wm[13..6] = #gpargs, 2419 Wm[5..2] = #fpargs, 2420 Wm[1,0] = #type 2421 2422 calls the x86 code address 'branch_address' supplied in Xn passing 2423 arguments taken from the general and floating point registers according 2424 to the supplied counts 'gpargs' and 'fpargs'. may return a result in r0 2425 or v0 according to the the return type #type' where 2426 2427 address branch_address; 2428 uimm4 gpargs; 2429 uimm4 fpargs; 2430 enum ReturnType type; 2431 2432 enum ReturnType 2433 { 2434 void_ret = 0, 2435 int_ret = 1, 2436 long_ret = 1, 2437 obj_ret = 1, // i.e. same as long 2438 float_ret = 2, 2439 double_ret = 3 2440 } 2441 2442 notify 2443 2444 notifies the simulator of a transfer of control. instr[14:0] 2445 identifies the type of change of control. 2446 2447 0 ==> initial entry to a method. 2448 2449 1 ==> return into a method from a submethod call. 2450 2451 2 ==> exit out of Java method code. 2452 2453 3 ==> start execution for a new bytecode. 2454 2455 in cases 1 and 2 the simulator is expected to use a JVM callback to 2456 identify the name of the specific method being executed. in case 4 2457 the simulator is expected to use a JVM callback to identify the 2458 bytecode index. 2459 2460 Instruction encodings 2461 --------------------- 2462 2463 These are encoded in the space with instr[28:25] = 00 which is 2464 unallocated. Encodings are 2465 2466 10987654321098765432109876543210 2467 PSEUDO_HALT = 0x11100000000000000000000000000000 2468 PSEUDO_BLRT = 0x11000000000000000_______________ 2469 PSEUDO_BLRTR = 0x1100000000000000100000__________ 2470 PSEUDO_NOTIFY = 0x10100000000000000_______________ 2471 2472 instr[31,29] = op1 : 111 ==> HALT, 110 ==> BLRT/BLRTR, 101 ==> NOTIFY 2473 2474 for BLRT 2475 instr[14,11] = #gpargs, instr[10,7] = #fpargs 2476 instr[6,5] = #type, instr[4,0] = Rn 2477 for BLRTR 2478 instr[9,5] = Rm, instr[4,0] = Rn 2479 for NOTIFY 2480 instr[14:0] = type : 0 ==> entry, 1 ==> reentry, 2 ==> exit, 3 ==> bcstart 2481 */ 2482 2483 enum NotifyType { method_entry, method_reentry, method_exit, bytecode_start }; 2484 2485 virtual void notify(int type) { 2486 if (UseBuiltinSim) { 2487 starti; 2488 // 109 2489 f(0b101, 31, 29); 2490 // 87654321098765 2491 f(0b00000000000000, 28, 15); 2492 f(type, 14, 0); 2493 } 2494 } 2495 2496 void blrt(Register Rn, int gpargs, int fpargs, int type) { 2497 if (UseBuiltinSim) { 2498 starti; 2499 f(0b110, 31 ,29); 2500 f(0b00, 28, 25); 2501 // 4321098765 2502 f(0b0000000000, 24, 15); 2503 f(gpargs, 14, 11); 2504 f(fpargs, 10, 7); 2505 f(type, 6, 5); 2506 rf(Rn, 0); 2507 } else { 2508 blr(Rn); 2509 } 2510 } 2511 2512 void blrt(Register Rn, Register Rm) { 2513 if (UseBuiltinSim) { 2514 starti; 2515 f(0b110, 31 ,29); 2516 f(0b00, 28, 25); 2517 // 4321098765 2518 f(0b0000000001, 24, 15); 2519 // 43210 2520 f(0b00000, 14, 10); 2521 rf(Rm, 5); 2522 rf(Rn, 0); 2523 } else { 2524 blr(Rn); 2525 } 2526 } 2527 2528 void haltsim() { 2529 starti; 2530 f(0b111, 31 ,29); 2531 f(0b00, 28, 27); 2532 // 654321098765432109876543210 2533 f(0b000000000000000000000000000, 26, 0); 2534 } 2535 2536 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 2537 } 2538 2539 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 2540 Register tmp, 2541 int offset) { 2542 ShouldNotCallThis(); 2543 return RegisterOrConstant(); 2544 } 2545 2546 // Stack overflow checking 2547 virtual void bang_stack_with_offset(int offset); 2548 2549 static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm); 2550 static bool operand_valid_for_add_sub_immediate(long imm); 2551 static bool operand_valid_for_float_immediate(double imm); 2552 2553 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); 2554 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); 2555 }; 2556 2557 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a, 2558 Assembler::Membar_mask_bits b) { 2559 return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b)); 2560 } 2561 2562 Instruction_aarch64::~Instruction_aarch64() { 2563 assem->emit(); 2564 } 2565 2566 #undef starti 2567 2568 // Invert a condition 2569 inline const Assembler::Condition operator~(const Assembler::Condition cond) { 2570 return Assembler::Condition(int(cond) ^ 1); 2571 } 2572 2573 class BiasedLockingCounters; 2574 2575 extern "C" void das(uint64_t start, int len); 2576 2577 #endif // CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP