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src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
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rev 10437 : 8151775: aarch64: add support for 8.1 LSE atomic operations
Reviewed-by: aph
*** 3118,3137 ****
--- 3118,3139 ----
void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
Address addr = as_Address(src->as_address_ptr(), noreg);
BasicType type = src->type();
bool is_oop = type == T_OBJECT || type == T_ARRAY;
+ Assembler::operand_size sz = Assembler::xword;
void (MacroAssembler::* lda)(Register Rd, Register Ra);
void (MacroAssembler::* add)(Register Rd, Register Rn, RegisterOrConstant increment);
void (MacroAssembler::* stl)(Register Rs, Register Rt, Register Rn);
switch(type) {
case T_INT:
lda = &MacroAssembler::ldaxrw;
add = &MacroAssembler::addw;
stl = &MacroAssembler::stlxrw;
+ sz = Assembler::word;
break;
case T_LONG:
lda = &MacroAssembler::ldaxr;
add = &MacroAssembler::add;
stl = &MacroAssembler::stlxr;
*** 3140,3149 ****
--- 3142,3152 ----
case T_ARRAY:
if (UseCompressedOops) {
lda = &MacroAssembler::ldaxrw;
add = &MacroAssembler::addw;
stl = &MacroAssembler::stlxrw;
+ sz = Assembler::word;
} else {
lda = &MacroAssembler::ldaxr;
add = &MacroAssembler::add;
stl = &MacroAssembler::stlxr;
}
*** 3168,3185 ****
} else {
inc = RegisterOrConstant(as_reg(data));
assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
rscratch1, rscratch2);
}
- Label again;
__ lea(tmp, addr);
__ prfm(Address(tmp), PSTL1STRM);
__ bind(again);
(_masm->*lda)(dst, tmp);
(_masm->*add)(rscratch1, dst, inc);
(_masm->*stl)(rscratch2, rscratch1, tmp);
__ cbnzw(rscratch2, again);
break;
}
case lir_xchg:
{
Register tmp = tmp_op->as_register();
--- 3171,3197 ----
} else {
inc = RegisterOrConstant(as_reg(data));
assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
rscratch1, rscratch2);
}
__ lea(tmp, addr);
+ if (UseLSE) {
+ if (inc.is_register()) {
+ __ ldaddal(sz, inc.as_register(), dst, tmp);
+ } else {
+ __ mov(rscratch2, inc.as_constant());
+ __ ldaddal(sz, rscratch2, dst, tmp);
+ }
+ } else {
+ Label again;
__ prfm(Address(tmp), PSTL1STRM);
__ bind(again);
(_masm->*lda)(dst, tmp);
(_masm->*add)(rscratch1, dst, inc);
(_masm->*stl)(rscratch2, rscratch1, tmp);
__ cbnzw(rscratch2, again);
+ }
break;
}
case lir_xchg:
{
Register tmp = tmp_op->as_register();
*** 3188,3204 ****
if (is_oop && UseCompressedOops) {
__ encode_heap_oop(rscratch1, obj);
obj = rscratch1;
}
assert_different_registers(obj, addr.base(), tmp, rscratch2, dst);
- Label again;
__ lea(tmp, addr);
__ prfm(Address(tmp), PSTL1STRM);
__ bind(again);
(_masm->*lda)(dst, tmp);
(_masm->*stl)(rscratch2, obj, tmp);
__ cbnzw(rscratch2, again);
if (is_oop && UseCompressedOops) {
__ decode_heap_oop(dst);
}
}
break;
--- 3200,3220 ----
if (is_oop && UseCompressedOops) {
__ encode_heap_oop(rscratch1, obj);
obj = rscratch1;
}
assert_different_registers(obj, addr.base(), tmp, rscratch2, dst);
__ lea(tmp, addr);
+ if (UseLSE) {
+ __ swp(sz, obj, dst, tmp);
+ } else {
+ Label again;
__ prfm(Address(tmp), PSTL1STRM);
__ bind(again);
(_masm->*lda)(dst, tmp);
(_masm->*stl)(rscratch2, obj, tmp);
__ cbnzw(rscratch2, again);
+ }
if (is_oop && UseCompressedOops) {
__ decode_heap_oop(dst);
}
}
break;
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