1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include <sys/types.h>
27
28 #include "precompiled.hpp"
29 #include "asm/assembler.hpp"
30 #include "asm/assembler.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32
33 #include "compiler/disassembler.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "nativeInst_aarch64.hpp"
36 #include "oops/klass.inline.hpp"
37 #include "oops/oop.inline.hpp"
38 #include "opto/compile.hpp"
39 #include "opto/node.hpp"
40 #include "runtime/biasedLocking.hpp"
41 #include "runtime/icache.hpp"
42 #include "runtime/interfaceSupport.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/thread.hpp"
45
46 #if INCLUDE_ALL_GCS
47 #include "gc/g1/g1CollectedHeap.inline.hpp"
48 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
49 #include "gc/g1/heapRegion.hpp"
50 #endif
51
52 #ifdef PRODUCT
53 #define BLOCK_COMMENT(str) /* nothing */
54 #define STOP(error) stop(error)
55 #else
56 #define BLOCK_COMMENT(str) block_comment(str)
57 #define STOP(error) block_comment(error); stop(error)
58 #endif
59
60 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
61
62 // Patch any kind of instruction; there may be several instructions.
63 // Return the total length (in bytes) of the instructions.
64 int MacroAssembler::pd_patch_instruction_size(address branch, address target) {
65 int instructions = 1;
66 assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant");
67 long offset = (target - branch) >> 2;
68 unsigned insn = *(unsigned*)branch;
69 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
70 // Load register (literal)
71 Instruction_aarch64::spatch(branch, 23, 5, offset);
72 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
73 // Unconditional branch (immediate)
74 Instruction_aarch64::spatch(branch, 25, 0, offset);
75 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
76 // Conditional branch (immediate)
77 Instruction_aarch64::spatch(branch, 23, 5, offset);
78 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
79 // Compare & branch (immediate)
80 Instruction_aarch64::spatch(branch, 23, 5, offset);
81 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
82 // Test & branch (immediate)
83 Instruction_aarch64::spatch(branch, 18, 5, offset);
84 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
85 // PC-rel. addressing
86 offset = target-branch;
87 int shift = Instruction_aarch64::extract(insn, 31, 31);
88 if (shift) {
89 u_int64_t dest = (u_int64_t)target;
90 uint64_t pc_page = (uint64_t)branch >> 12;
91 uint64_t adr_page = (uint64_t)target >> 12;
92 unsigned offset_lo = dest & 0xfff;
93 offset = adr_page - pc_page;
94
95 // We handle 4 types of PC relative addressing
96 // 1 - adrp Rx, target_page
97 // ldr/str Ry, [Rx, #offset_in_page]
98 // 2 - adrp Rx, target_page
99 // add Ry, Rx, #offset_in_page
100 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0)
101 // movk Rx, #imm16<<32
102 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0)
103 // In the first 3 cases we must check that Rx is the same in the adrp and the
104 // subsequent ldr/str, add or movk instruction. Otherwise we could accidentally end
105 // up treating a type 4 relocation as a type 1, 2 or 3 just because it happened
106 // to be followed by a random unrelated ldr/str, add or movk instruction.
107 //
108 unsigned insn2 = ((unsigned*)branch)[1];
109 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
110 Instruction_aarch64::extract(insn, 4, 0) ==
111 Instruction_aarch64::extract(insn2, 9, 5)) {
112 // Load/store register (unsigned immediate)
113 unsigned size = Instruction_aarch64::extract(insn2, 31, 30);
114 Instruction_aarch64::patch(branch + sizeof (unsigned),
115 21, 10, offset_lo >> size);
116 guarantee(((dest >> size) << size) == dest, "misaligned target");
117 instructions = 2;
118 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
119 Instruction_aarch64::extract(insn, 4, 0) ==
120 Instruction_aarch64::extract(insn2, 4, 0)) {
121 // add (immediate)
122 Instruction_aarch64::patch(branch + sizeof (unsigned),
123 21, 10, offset_lo);
124 instructions = 2;
125 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
126 Instruction_aarch64::extract(insn, 4, 0) ==
127 Instruction_aarch64::extract(insn2, 4, 0)) {
128 // movk #imm16<<32
129 Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32);
130 long dest = ((long)target & 0xffffffffL) | ((long)branch & 0xffff00000000L);
131 long pc_page = (long)branch >> 12;
132 long adr_page = (long)dest >> 12;
133 offset = adr_page - pc_page;
134 instructions = 2;
135 }
136 }
137 int offset_lo = offset & 3;
138 offset >>= 2;
139 Instruction_aarch64::spatch(branch, 23, 5, offset);
140 Instruction_aarch64::patch(branch, 30, 29, offset_lo);
141 } else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) {
142 u_int64_t dest = (u_int64_t)target;
143 // Move wide constant
144 assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch");
145 assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch");
146 Instruction_aarch64::patch(branch, 20, 5, dest & 0xffff);
147 Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff);
148 Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff);
149 assert(target_addr_for_insn(branch) == target, "should be");
150 instructions = 3;
151 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
152 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
153 // nothing to do
154 assert(target == 0, "did not expect to relocate target for polling page load");
155 } else {
156 ShouldNotReachHere();
157 }
158 return instructions * NativeInstruction::instruction_size;
159 }
160
161 int MacroAssembler::patch_oop(address insn_addr, address o) {
162 int instructions;
163 unsigned insn = *(unsigned*)insn_addr;
164 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
165
166 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
167 // narrow OOPs by setting the upper 16 bits in the first
168 // instruction.
169 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
170 // Move narrow OOP
171 narrowOop n = oopDesc::encode_heap_oop((oop)o);
172 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
173 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
174 instructions = 2;
175 } else {
176 // Move wide OOP
177 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
178 uintptr_t dest = (uintptr_t)o;
179 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
180 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
181 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
182 instructions = 3;
183 }
184 return instructions * NativeInstruction::instruction_size;
185 }
186
187 address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) {
188 long offset = 0;
189 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) {
190 // Load register (literal)
191 offset = Instruction_aarch64::sextract(insn, 23, 5);
192 return address(((uint64_t)insn_addr + (offset << 2)));
193 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
194 // Unconditional branch (immediate)
195 offset = Instruction_aarch64::sextract(insn, 25, 0);
196 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
197 // Conditional branch (immediate)
198 offset = Instruction_aarch64::sextract(insn, 23, 5);
199 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
200 // Compare & branch (immediate)
201 offset = Instruction_aarch64::sextract(insn, 23, 5);
202 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
203 // Test & branch (immediate)
204 offset = Instruction_aarch64::sextract(insn, 18, 5);
205 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
206 // PC-rel. addressing
207 offset = Instruction_aarch64::extract(insn, 30, 29);
208 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
209 int shift = Instruction_aarch64::extract(insn, 31, 31) ? 12 : 0;
210 if (shift) {
211 offset <<= shift;
212 uint64_t target_page = ((uint64_t)insn_addr) + offset;
213 target_page &= ((uint64_t)-1) << shift;
214 // Return the target address for the following sequences
215 // 1 - adrp Rx, target_page
216 // ldr/str Ry, [Rx, #offset_in_page]
217 // 2 - adrp Rx, target_page
218 // add Ry, Rx, #offset_in_page
219 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0)
220 // movk Rx, #imm12<<32
221 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0)
222 //
223 // In the first two cases we check that the register is the same and
224 // return the target_page + the offset within the page.
225 // Otherwise we assume it is a page aligned relocation and return
226 // the target page only.
227 //
228 unsigned insn2 = ((unsigned*)insn_addr)[1];
229 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
230 Instruction_aarch64::extract(insn, 4, 0) ==
231 Instruction_aarch64::extract(insn2, 9, 5)) {
232 // Load/store register (unsigned immediate)
233 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
234 unsigned int size = Instruction_aarch64::extract(insn2, 31, 30);
235 return address(target_page + (byte_offset << size));
236 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
237 Instruction_aarch64::extract(insn, 4, 0) ==
238 Instruction_aarch64::extract(insn2, 4, 0)) {
239 // add (immediate)
240 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
241 return address(target_page + byte_offset);
242 } else {
243 if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
244 Instruction_aarch64::extract(insn, 4, 0) ==
245 Instruction_aarch64::extract(insn2, 4, 0)) {
246 target_page = (target_page & 0xffffffff) |
247 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
248 }
249 return (address)target_page;
250 }
251 } else {
252 ShouldNotReachHere();
253 }
254 } else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) {
255 u_int32_t *insns = (u_int32_t *)insn_addr;
256 // Move wide constant: movz, movk, movk. See movptr().
257 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
258 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
259 return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5))
260 + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
261 + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
262 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
263 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
264 return 0;
265 } else {
266 ShouldNotReachHere();
267 }
268 return address(((uint64_t)insn_addr + (offset << 2)));
269 }
270
271 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
272 dsb(Assembler::SY);
273 }
274
275
276 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
277 bool clear_pc) {
278 // we must set sp to zero to clear frame
279 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
280 // must clear fp, so that compiled frames are not confused; it is
281 // possible that we need it only for debugging
282 if (clear_fp) {
283 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
284 }
285
286 if (clear_pc) {
287 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
288 }
289 }
290
291 // Calls to C land
292 //
293 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
294 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
295 // has to be reset to 0. This is required to allow proper stack traversal.
296 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
297 Register last_java_fp,
298 Register last_java_pc,
299 Register scratch) {
300
301 if (last_java_pc->is_valid()) {
302 str(last_java_pc, Address(rthread,
303 JavaThread::frame_anchor_offset()
304 + JavaFrameAnchor::last_Java_pc_offset()));
305 }
306
307 // determine last_java_sp register
308 if (last_java_sp == sp) {
309 mov(scratch, sp);
310 last_java_sp = scratch;
311 } else if (!last_java_sp->is_valid()) {
312 last_java_sp = esp;
313 }
314
315 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
316
317 // last_java_fp is optional
318 if (last_java_fp->is_valid()) {
319 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
320 }
321 }
322
323 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
324 Register last_java_fp,
325 address last_java_pc,
326 Register scratch) {
327 if (last_java_pc != NULL) {
328 adr(scratch, last_java_pc);
329 } else {
330 // FIXME: This is almost never correct. We should delete all
331 // cases of set_last_Java_frame with last_java_pc=NULL and use the
332 // correct return address instead.
333 adr(scratch, pc());
334 }
335
336 str(scratch, Address(rthread,
337 JavaThread::frame_anchor_offset()
338 + JavaFrameAnchor::last_Java_pc_offset()));
339
340 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
341 }
342
343 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
344 Register last_java_fp,
345 Label &L,
346 Register scratch) {
347 if (L.is_bound()) {
348 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
349 } else {
350 InstructionMark im(this);
351 L.add_patch_at(code(), locator());
352 set_last_Java_frame(last_java_sp, last_java_fp, (address)NULL, scratch);
353 }
354 }
355
356 void MacroAssembler::far_call(Address entry, CodeBuffer *cbuf, Register tmp) {
357 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
358 assert(CodeCache::find_blob(entry.target()) != NULL,
359 "destination of far call not found in code cache");
360 if (far_branches()) {
361 unsigned long offset;
362 // We can use ADRP here because we know that the total size of
363 // the code cache cannot exceed 2Gb.
364 adrp(tmp, entry, offset);
365 add(tmp, tmp, offset);
366 if (cbuf) cbuf->set_insts_mark();
367 blr(tmp);
368 } else {
369 if (cbuf) cbuf->set_insts_mark();
370 bl(entry);
371 }
372 }
373
374 void MacroAssembler::far_jump(Address entry, CodeBuffer *cbuf, Register tmp) {
375 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
376 assert(CodeCache::find_blob(entry.target()) != NULL,
377 "destination of far call not found in code cache");
378 if (far_branches()) {
379 unsigned long offset;
380 // We can use ADRP here because we know that the total size of
381 // the code cache cannot exceed 2Gb.
382 adrp(tmp, entry, offset);
383 add(tmp, tmp, offset);
384 if (cbuf) cbuf->set_insts_mark();
385 br(tmp);
386 } else {
387 if (cbuf) cbuf->set_insts_mark();
388 b(entry);
389 }
390 }
391
392 int MacroAssembler::biased_locking_enter(Register lock_reg,
393 Register obj_reg,
394 Register swap_reg,
395 Register tmp_reg,
396 bool swap_reg_contains_mark,
397 Label& done,
398 Label* slow_case,
399 BiasedLockingCounters* counters) {
400 assert(UseBiasedLocking, "why call this otherwise?");
401 assert_different_registers(lock_reg, obj_reg, swap_reg);
402
403 if (PrintBiasedLockingStatistics && counters == NULL)
404 counters = BiasedLocking::counters();
405
406 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1, rscratch2, noreg);
407 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
408 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
409 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
410 Address saved_mark_addr(lock_reg, 0);
411
412 // Biased locking
413 // See whether the lock is currently biased toward our thread and
414 // whether the epoch is still valid
415 // Note that the runtime guarantees sufficient alignment of JavaThread
416 // pointers to allow age to be placed into low bits
417 // First check to see whether biasing is even enabled for this object
418 Label cas_label;
419 int null_check_offset = -1;
420 if (!swap_reg_contains_mark) {
421 null_check_offset = offset();
422 ldr(swap_reg, mark_addr);
423 }
424 andr(tmp_reg, swap_reg, markOopDesc::biased_lock_mask_in_place);
425 cmp(tmp_reg, markOopDesc::biased_lock_pattern);
426 br(Assembler::NE, cas_label);
427 // The bias pattern is present in the object's header. Need to check
428 // whether the bias owner and the epoch are both still current.
429 load_prototype_header(tmp_reg, obj_reg);
430 orr(tmp_reg, tmp_reg, rthread);
431 eor(tmp_reg, swap_reg, tmp_reg);
432 andr(tmp_reg, tmp_reg, ~((int) markOopDesc::age_mask_in_place));
433 if (counters != NULL) {
434 Label around;
435 cbnz(tmp_reg, around);
436 atomic_incw(Address((address)counters->biased_lock_entry_count_addr()), tmp_reg, rscratch1, rscratch2);
437 b(done);
438 bind(around);
439 } else {
440 cbz(tmp_reg, done);
441 }
442
443 Label try_revoke_bias;
444 Label try_rebias;
445
446 // At this point we know that the header has the bias pattern and
447 // that we are not the bias owner in the current epoch. We need to
448 // figure out more details about the state of the header in order to
449 // know what operations can be legally performed on the object's
450 // header.
451
452 // If the low three bits in the xor result aren't clear, that means
453 // the prototype header is no longer biased and we have to revoke
454 // the bias on this object.
455 andr(rscratch1, tmp_reg, markOopDesc::biased_lock_mask_in_place);
456 cbnz(rscratch1, try_revoke_bias);
457
458 // Biasing is still enabled for this data type. See whether the
459 // epoch of the current bias is still valid, meaning that the epoch
460 // bits of the mark word are equal to the epoch bits of the
461 // prototype header. (Note that the prototype header's epoch bits
462 // only change at a safepoint.) If not, attempt to rebias the object
463 // toward the current thread. Note that we must be absolutely sure
464 // that the current epoch is invalid in order to do this because
465 // otherwise the manipulations it performs on the mark word are
466 // illegal.
467 andr(rscratch1, tmp_reg, markOopDesc::epoch_mask_in_place);
468 cbnz(rscratch1, try_rebias);
469
470 // The epoch of the current bias is still valid but we know nothing
471 // about the owner; it might be set or it might be clear. Try to
472 // acquire the bias of the object using an atomic operation. If this
473 // fails we will go in to the runtime to revoke the object's bias.
474 // Note that we first construct the presumed unbiased header so we
475 // don't accidentally blow away another thread's valid bias.
476 {
477 Label here;
478 mov(rscratch1, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
479 andr(swap_reg, swap_reg, rscratch1);
480 orr(tmp_reg, swap_reg, rthread);
481 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case);
482 // If the biasing toward our thread failed, this means that
483 // another thread succeeded in biasing it toward itself and we
484 // need to revoke that bias. The revocation will occur in the
485 // interpreter runtime in the slow case.
486 bind(here);
487 if (counters != NULL) {
488 atomic_incw(Address((address)counters->anonymously_biased_lock_entry_count_addr()),
489 tmp_reg, rscratch1, rscratch2);
490 }
491 }
492 b(done);
493
494 bind(try_rebias);
495 // At this point we know the epoch has expired, meaning that the
496 // current "bias owner", if any, is actually invalid. Under these
497 // circumstances _only_, we are allowed to use the current header's
498 // value as the comparison value when doing the cas to acquire the
499 // bias in the current epoch. In other words, we allow transfer of
500 // the bias from one thread to another directly in this situation.
501 //
502 // FIXME: due to a lack of registers we currently blow away the age
503 // bits in this situation. Should attempt to preserve them.
504 {
505 Label here;
506 load_prototype_header(tmp_reg, obj_reg);
507 orr(tmp_reg, rthread, tmp_reg);
508 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case);
509 // If the biasing toward our thread failed, then another thread
510 // succeeded in biasing it toward itself and we need to revoke that
511 // bias. The revocation will occur in the runtime in the slow case.
512 bind(here);
513 if (counters != NULL) {
514 atomic_incw(Address((address)counters->rebiased_lock_entry_count_addr()),
515 tmp_reg, rscratch1, rscratch2);
516 }
517 }
518 b(done);
519
520 bind(try_revoke_bias);
521 // The prototype mark in the klass doesn't have the bias bit set any
522 // more, indicating that objects of this data type are not supposed
523 // to be biased any more. We are going to try to reset the mark of
524 // this object to the prototype value and fall through to the
525 // CAS-based locking scheme. Note that if our CAS fails, it means
526 // that another thread raced us for the privilege of revoking the
527 // bias of this particular object, so it's okay to continue in the
528 // normal locking code.
529 //
530 // FIXME: due to a lack of registers we currently blow away the age
531 // bits in this situation. Should attempt to preserve them.
532 {
533 Label here, nope;
534 load_prototype_header(tmp_reg, obj_reg);
535 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, &nope);
536 bind(here);
537
538 // Fall through to the normal CAS-based lock, because no matter what
539 // the result of the above CAS, some thread must have succeeded in
540 // removing the bias bit from the object's header.
541 if (counters != NULL) {
542 atomic_incw(Address((address)counters->revoked_lock_entry_count_addr()), tmp_reg,
543 rscratch1, rscratch2);
544 }
545 bind(nope);
546 }
547
548 bind(cas_label);
549
550 return null_check_offset;
551 }
552
553 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
554 assert(UseBiasedLocking, "why call this otherwise?");
555
556 // Check for biased locking unlock case, which is a no-op
557 // Note: we do not have to check the thread ID for two reasons.
558 // First, the interpreter checks for IllegalMonitorStateException at
559 // a higher level. Second, if the bias was revoked while we held the
560 // lock, the object could not be rebiased toward another thread, so
561 // the bias bit would be clear.
562 ldr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
563 andr(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
564 cmp(temp_reg, markOopDesc::biased_lock_pattern);
565 br(Assembler::EQ, done);
566 }
567
568
569 // added to make this compile
570
571 REGISTER_DEFINITION(Register, noreg);
572
573 static void pass_arg0(MacroAssembler* masm, Register arg) {
574 if (c_rarg0 != arg ) {
575 masm->mov(c_rarg0, arg);
576 }
577 }
578
579 static void pass_arg1(MacroAssembler* masm, Register arg) {
580 if (c_rarg1 != arg ) {
581 masm->mov(c_rarg1, arg);
582 }
583 }
584
585 static void pass_arg2(MacroAssembler* masm, Register arg) {
586 if (c_rarg2 != arg ) {
587 masm->mov(c_rarg2, arg);
588 }
589 }
590
591 static void pass_arg3(MacroAssembler* masm, Register arg) {
592 if (c_rarg3 != arg ) {
593 masm->mov(c_rarg3, arg);
594 }
595 }
596
597 void MacroAssembler::call_VM_base(Register oop_result,
598 Register java_thread,
599 Register last_java_sp,
600 address entry_point,
601 int number_of_arguments,
602 bool check_exceptions) {
603 // determine java_thread register
604 if (!java_thread->is_valid()) {
605 java_thread = rthread;
606 }
607
608 // determine last_java_sp register
609 if (!last_java_sp->is_valid()) {
610 last_java_sp = esp;
611 }
612
613 // debugging support
614 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
615 assert(java_thread == rthread, "unexpected register");
616 #ifdef ASSERT
617 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
618 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
619 #endif // ASSERT
620
621 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
622 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
623
624 // push java thread (becomes first argument of C function)
625
626 mov(c_rarg0, java_thread);
627
628 // set last Java frame before call
629 assert(last_java_sp != rfp, "can't use rfp");
630
631 Label l;
632 set_last_Java_frame(last_java_sp, rfp, l, rscratch1);
633
634 // do the call, remove parameters
635 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
636
637 // reset last Java frame
638 // Only interpreter should have to clear fp
639 reset_last_Java_frame(true, true);
640
641 // C++ interp handles this in the interpreter
642 check_and_handle_popframe(java_thread);
643 check_and_handle_earlyret(java_thread);
644
645 if (check_exceptions) {
646 // check for pending exceptions (java_thread is set upon return)
647 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
648 Label ok;
649 cbz(rscratch1, ok);
650 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
651 br(rscratch1);
652 bind(ok);
653 }
654
655 // get oop result if there is one and reset the value in the thread
656 if (oop_result->is_valid()) {
657 get_vm_result(oop_result, java_thread);
658 }
659 }
660
661 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
662 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
663 }
664
665 // Maybe emit a call via a trampoline. If the code cache is small
666 // trampolines won't be emitted.
667
668 address MacroAssembler::trampoline_call(Address entry, CodeBuffer *cbuf) {
669 assert(entry.rspec().type() == relocInfo::runtime_call_type
670 || entry.rspec().type() == relocInfo::opt_virtual_call_type
671 || entry.rspec().type() == relocInfo::static_call_type
672 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
673
674 unsigned int start_offset = offset();
675 if (far_branches() && !Compile::current()->in_scratch_emit_size()) {
676 address stub = emit_trampoline_stub(start_offset, entry.target());
677 if (stub == NULL) {
678 return NULL; // CodeCache is full
679 }
680 }
681
682 if (cbuf) cbuf->set_insts_mark();
683 relocate(entry.rspec());
684 if (!far_branches()) {
685 bl(entry.target());
686 } else {
687 bl(pc());
688 }
689 // just need to return a non-null address
690 return pc();
691 }
692
693
694 // Emit a trampoline stub for a call to a target which is too far away.
695 //
696 // code sequences:
697 //
698 // call-site:
699 // branch-and-link to <destination> or <trampoline stub>
700 //
701 // Related trampoline stub for this call site in the stub section:
702 // load the call target from the constant pool
703 // branch (LR still points to the call site above)
704
705 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
706 address dest) {
707 address stub = start_a_stub(Compile::MAX_stubs_size/2);
708 if (stub == NULL) {
709 return NULL; // CodeBuffer::expand failed
710 }
711
712 // Create a trampoline stub relocation which relates this trampoline stub
713 // with the call instruction at insts_call_instruction_offset in the
714 // instructions code-section.
715 align(wordSize);
716 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
717 + insts_call_instruction_offset));
718 const int stub_start_offset = offset();
719
720 // Now, create the trampoline stub's code:
721 // - load the call
722 // - call
723 Label target;
724 ldr(rscratch1, target);
725 br(rscratch1);
726 bind(target);
727 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
728 "should be");
729 emit_int64((int64_t)dest);
730
731 const address stub_start_addr = addr_at(stub_start_offset);
732
733 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
734
735 end_a_stub();
736 return stub;
737 }
738
739 address MacroAssembler::ic_call(address entry, jint method_index) {
740 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
741 // address const_ptr = long_constant((jlong)Universe::non_oop_word());
742 // unsigned long offset;
743 // ldr_constant(rscratch2, const_ptr);
744 movptr(rscratch2, (uintptr_t)Universe::non_oop_word());
745 return trampoline_call(Address(entry, rh));
746 }
747
748 // Implementation of call_VM versions
749
750 void MacroAssembler::call_VM(Register oop_result,
751 address entry_point,
752 bool check_exceptions) {
753 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
754 }
755
756 void MacroAssembler::call_VM(Register oop_result,
757 address entry_point,
758 Register arg_1,
759 bool check_exceptions) {
760 pass_arg1(this, arg_1);
761 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
762 }
763
764 void MacroAssembler::call_VM(Register oop_result,
765 address entry_point,
766 Register arg_1,
767 Register arg_2,
768 bool check_exceptions) {
769 assert(arg_1 != c_rarg2, "smashed arg");
770 pass_arg2(this, arg_2);
771 pass_arg1(this, arg_1);
772 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
773 }
774
775 void MacroAssembler::call_VM(Register oop_result,
776 address entry_point,
777 Register arg_1,
778 Register arg_2,
779 Register arg_3,
780 bool check_exceptions) {
781 assert(arg_1 != c_rarg3, "smashed arg");
782 assert(arg_2 != c_rarg3, "smashed arg");
783 pass_arg3(this, arg_3);
784
785 assert(arg_1 != c_rarg2, "smashed arg");
786 pass_arg2(this, arg_2);
787
788 pass_arg1(this, arg_1);
789 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
790 }
791
792 void MacroAssembler::call_VM(Register oop_result,
793 Register last_java_sp,
794 address entry_point,
795 int number_of_arguments,
796 bool check_exceptions) {
797 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
798 }
799
800 void MacroAssembler::call_VM(Register oop_result,
801 Register last_java_sp,
802 address entry_point,
803 Register arg_1,
804 bool check_exceptions) {
805 pass_arg1(this, arg_1);
806 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
807 }
808
809 void MacroAssembler::call_VM(Register oop_result,
810 Register last_java_sp,
811 address entry_point,
812 Register arg_1,
813 Register arg_2,
814 bool check_exceptions) {
815
816 assert(arg_1 != c_rarg2, "smashed arg");
817 pass_arg2(this, arg_2);
818 pass_arg1(this, arg_1);
819 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
820 }
821
822 void MacroAssembler::call_VM(Register oop_result,
823 Register last_java_sp,
824 address entry_point,
825 Register arg_1,
826 Register arg_2,
827 Register arg_3,
828 bool check_exceptions) {
829 assert(arg_1 != c_rarg3, "smashed arg");
830 assert(arg_2 != c_rarg3, "smashed arg");
831 pass_arg3(this, arg_3);
832 assert(arg_1 != c_rarg2, "smashed arg");
833 pass_arg2(this, arg_2);
834 pass_arg1(this, arg_1);
835 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
836 }
837
838
839 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
840 ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
841 str(zr, Address(java_thread, JavaThread::vm_result_offset()));
842 verify_oop(oop_result, "broken oop in call_VM_base");
843 }
844
845 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
846 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
847 str(zr, Address(java_thread, JavaThread::vm_result_2_offset()));
848 }
849
850 void MacroAssembler::align(int modulus) {
851 while (offset() % modulus != 0) nop();
852 }
853
854 // these are no-ops overridden by InterpreterMacroAssembler
855
856 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
857
858 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
859
860
861 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
862 Register tmp,
863 int offset) {
864 intptr_t value = *delayed_value_addr;
865 if (value != 0)
866 return RegisterOrConstant(value + offset);
867
868 // load indirectly to solve generation ordering problem
869 ldr(tmp, ExternalAddress((address) delayed_value_addr));
870
871 if (offset != 0)
872 add(tmp, tmp, offset);
873
874 return RegisterOrConstant(tmp);
875 }
876
877
878 void MacroAssembler:: notify(int type) {
879 if (type == bytecode_start) {
880 // set_last_Java_frame(esp, rfp, (address)NULL);
881 Assembler:: notify(type);
882 // reset_last_Java_frame(true, false);
883 }
884 else
885 Assembler:: notify(type);
886 }
887
888 // Look up the method for a megamorphic invokeinterface call.
889 // The target method is determined by <intf_klass, itable_index>.
890 // The receiver klass is in recv_klass.
891 // On success, the result will be in method_result, and execution falls through.
892 // On failure, execution transfers to the given label.
893 void MacroAssembler::lookup_interface_method(Register recv_klass,
894 Register intf_klass,
895 RegisterOrConstant itable_index,
896 Register method_result,
897 Register scan_temp,
898 Label& L_no_such_interface) {
899 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
900 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
901 "caller must use same register for non-constant itable index as for method");
902
903 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
904 int vtable_base = in_bytes(Klass::vtable_start_offset());
905 int itentry_off = itableMethodEntry::method_offset_in_bytes();
906 int scan_step = itableOffsetEntry::size() * wordSize;
907 int vte_size = vtableEntry::size_in_bytes();
908 assert(vte_size == wordSize, "else adjust times_vte_scale");
909
910 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
911
912 // %%% Could store the aligned, prescaled offset in the klassoop.
913 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
914 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
915 add(scan_temp, scan_temp, vtable_base);
916
917 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
918 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
919 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
920 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
921 if (itentry_off)
922 add(recv_klass, recv_klass, itentry_off);
923
924 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
925 // if (scan->interface() == intf) {
926 // result = (klass + scan->offset() + itable_index);
927 // }
928 // }
929 Label search, found_method;
930
931 for (int peel = 1; peel >= 0; peel--) {
932 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
933 cmp(intf_klass, method_result);
934
935 if (peel) {
936 br(Assembler::EQ, found_method);
937 } else {
938 br(Assembler::NE, search);
939 // (invert the test to fall through to found_method...)
940 }
941
942 if (!peel) break;
943
944 bind(search);
945
946 // Check that the previous entry is non-null. A null entry means that
947 // the receiver class doesn't implement the interface, and wasn't the
948 // same as when the caller was compiled.
949 cbz(method_result, L_no_such_interface);
950 add(scan_temp, scan_temp, scan_step);
951 }
952
953 bind(found_method);
954
955 // Got a hit.
956 ldr(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
957 ldr(method_result, Address(recv_klass, scan_temp));
958 }
959
960 // virtual method calling
961 void MacroAssembler::lookup_virtual_method(Register recv_klass,
962 RegisterOrConstant vtable_index,
963 Register method_result) {
964 const int base = in_bytes(Klass::vtable_start_offset());
965 assert(vtableEntry::size() * wordSize == 8,
966 "adjust the scaling in the code below");
967 int vtable_offset_in_bytes = base + vtableEntry::method_offset_in_bytes();
968
969 if (vtable_index.is_register()) {
970 lea(method_result, Address(recv_klass,
971 vtable_index.as_register(),
972 Address::lsl(LogBytesPerWord)));
973 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
974 } else {
975 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
976 ldr(method_result, Address(recv_klass, vtable_offset_in_bytes));
977 }
978 }
979
980 void MacroAssembler::check_klass_subtype(Register sub_klass,
981 Register super_klass,
982 Register temp_reg,
983 Label& L_success) {
984 Label L_failure;
985 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
986 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
987 bind(L_failure);
988 }
989
990
991 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
992 Register super_klass,
993 Register temp_reg,
994 Label* L_success,
995 Label* L_failure,
996 Label* L_slow_path,
997 RegisterOrConstant super_check_offset) {
998 assert_different_registers(sub_klass, super_klass, temp_reg);
999 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
1000 if (super_check_offset.is_register()) {
1001 assert_different_registers(sub_klass, super_klass,
1002 super_check_offset.as_register());
1003 } else if (must_load_sco) {
1004 assert(temp_reg != noreg, "supply either a temp or a register offset");
1005 }
1006
1007 Label L_fallthrough;
1008 int label_nulls = 0;
1009 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
1010 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
1011 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
1012 assert(label_nulls <= 1, "at most one NULL in the batch");
1013
1014 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1015 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1016 Address super_check_offset_addr(super_klass, sco_offset);
1017
1018 // Hacked jmp, which may only be used just before L_fallthrough.
1019 #define final_jmp(label) \
1020 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1021 else b(label) /*omit semi*/
1022
1023 // If the pointers are equal, we are done (e.g., String[] elements).
1024 // This self-check enables sharing of secondary supertype arrays among
1025 // non-primary types such as array-of-interface. Otherwise, each such
1026 // type would need its own customized SSA.
1027 // We move this check to the front of the fast path because many
1028 // type checks are in fact trivially successful in this manner,
1029 // so we get a nicely predicted branch right at the start of the check.
1030 cmp(sub_klass, super_klass);
1031 br(Assembler::EQ, *L_success);
1032
1033 // Check the supertype display:
1034 if (must_load_sco) {
1035 ldrw(temp_reg, super_check_offset_addr);
1036 super_check_offset = RegisterOrConstant(temp_reg);
1037 }
1038 Address super_check_addr(sub_klass, super_check_offset);
1039 ldr(rscratch1, super_check_addr);
1040 cmp(super_klass, rscratch1); // load displayed supertype
1041
1042 // This check has worked decisively for primary supers.
1043 // Secondary supers are sought in the super_cache ('super_cache_addr').
1044 // (Secondary supers are interfaces and very deeply nested subtypes.)
1045 // This works in the same check above because of a tricky aliasing
1046 // between the super_cache and the primary super display elements.
1047 // (The 'super_check_addr' can address either, as the case requires.)
1048 // Note that the cache is updated below if it does not help us find
1049 // what we need immediately.
1050 // So if it was a primary super, we can just fail immediately.
1051 // Otherwise, it's the slow path for us (no success at this point).
1052
1053 if (super_check_offset.is_register()) {
1054 br(Assembler::EQ, *L_success);
1055 cmp(super_check_offset.as_register(), sc_offset);
1056 if (L_failure == &L_fallthrough) {
1057 br(Assembler::EQ, *L_slow_path);
1058 } else {
1059 br(Assembler::NE, *L_failure);
1060 final_jmp(*L_slow_path);
1061 }
1062 } else if (super_check_offset.as_constant() == sc_offset) {
1063 // Need a slow path; fast failure is impossible.
1064 if (L_slow_path == &L_fallthrough) {
1065 br(Assembler::EQ, *L_success);
1066 } else {
1067 br(Assembler::NE, *L_slow_path);
1068 final_jmp(*L_success);
1069 }
1070 } else {
1071 // No slow path; it's a fast decision.
1072 if (L_failure == &L_fallthrough) {
1073 br(Assembler::EQ, *L_success);
1074 } else {
1075 br(Assembler::NE, *L_failure);
1076 final_jmp(*L_success);
1077 }
1078 }
1079
1080 bind(L_fallthrough);
1081
1082 #undef final_jmp
1083 }
1084
1085 // These two are taken from x86, but they look generally useful
1086
1087 // scans count pointer sized words at [addr] for occurence of value,
1088 // generic
1089 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1090 Register scratch) {
1091 Label Lloop, Lexit;
1092 cbz(count, Lexit);
1093 bind(Lloop);
1094 ldr(scratch, post(addr, wordSize));
1095 cmp(value, scratch);
1096 br(EQ, Lexit);
1097 sub(count, count, 1);
1098 cbnz(count, Lloop);
1099 bind(Lexit);
1100 }
1101
1102 // scans count 4 byte words at [addr] for occurence of value,
1103 // generic
1104 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1105 Register scratch) {
1106 Label Lloop, Lexit;
1107 cbz(count, Lexit);
1108 bind(Lloop);
1109 ldrw(scratch, post(addr, wordSize));
1110 cmpw(value, scratch);
1111 br(EQ, Lexit);
1112 sub(count, count, 1);
1113 cbnz(count, Lloop);
1114 bind(Lexit);
1115 }
1116
1117 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1118 Register super_klass,
1119 Register temp_reg,
1120 Register temp2_reg,
1121 Label* L_success,
1122 Label* L_failure,
1123 bool set_cond_codes) {
1124 assert_different_registers(sub_klass, super_klass, temp_reg);
1125 if (temp2_reg != noreg)
1126 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1127 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1128
1129 Label L_fallthrough;
1130 int label_nulls = 0;
1131 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
1132 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
1133 assert(label_nulls <= 1, "at most one NULL in the batch");
1134
1135 // a couple of useful fields in sub_klass:
1136 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1137 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1138 Address secondary_supers_addr(sub_klass, ss_offset);
1139 Address super_cache_addr( sub_klass, sc_offset);
1140
1141 BLOCK_COMMENT("check_klass_subtype_slow_path");
1142
1143 // Do a linear scan of the secondary super-klass chain.
1144 // This code is rarely used, so simplicity is a virtue here.
1145 // The repne_scan instruction uses fixed registers, which we must spill.
1146 // Don't worry too much about pre-existing connections with the input regs.
1147
1148 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1149 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1150
1151 // Get super_klass value into r0 (even if it was in r5 or r2).
1152 RegSet pushed_registers;
1153 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1154 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1155
1156 if (super_klass != r0 || UseCompressedOops) {
1157 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1158 }
1159
1160 push(pushed_registers, sp);
1161
1162 #ifndef PRODUCT
1163 mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr);
1164 Address pst_counter_addr(rscratch2);
1165 ldr(rscratch1, pst_counter_addr);
1166 add(rscratch1, rscratch1, 1);
1167 str(rscratch1, pst_counter_addr);
1168 #endif //PRODUCT
1169
1170 // We will consult the secondary-super array.
1171 ldr(r5, secondary_supers_addr);
1172 // Load the array length.
1173 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1174 // Skip to start of data.
1175 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1176
1177 cmp(sp, zr); // Clear Z flag; SP is never zero
1178 // Scan R2 words at [R5] for an occurrence of R0.
1179 // Set NZ/Z based on last compare.
1180 repne_scan(r5, r0, r2, rscratch1);
1181
1182 // Unspill the temp. registers:
1183 pop(pushed_registers, sp);
1184
1185 br(Assembler::NE, *L_failure);
1186
1187 // Success. Cache the super we found and proceed in triumph.
1188 str(super_klass, super_cache_addr);
1189
1190 if (L_success != &L_fallthrough) {
1191 b(*L_success);
1192 }
1193
1194 #undef IS_A_TEMP
1195
1196 bind(L_fallthrough);
1197 }
1198
1199
1200 void MacroAssembler::verify_oop(Register reg, const char* s) {
1201 if (!VerifyOops) return;
1202
1203 // Pass register number to verify_oop_subroutine
1204 const char* b = NULL;
1205 {
1206 ResourceMark rm;
1207 stringStream ss;
1208 ss.print("verify_oop: %s: %s", reg->name(), s);
1209 b = code_string(ss.as_string());
1210 }
1211 BLOCK_COMMENT("verify_oop {");
1212
1213 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1214 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1215
1216 mov(r0, reg);
1217 mov(rscratch1, (address)b);
1218
1219 // call indirectly to solve generation ordering problem
1220 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1221 ldr(rscratch2, Address(rscratch2));
1222 blr(rscratch2);
1223
1224 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1225 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1226
1227 BLOCK_COMMENT("} verify_oop");
1228 }
1229
1230 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
1231 if (!VerifyOops) return;
1232
1233 const char* b = NULL;
1234 {
1235 ResourceMark rm;
1236 stringStream ss;
1237 ss.print("verify_oop_addr: %s", s);
1238 b = code_string(ss.as_string());
1239 }
1240 BLOCK_COMMENT("verify_oop_addr {");
1241
1242 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1243 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1244
1245 // addr may contain sp so we will have to adjust it based on the
1246 // pushes that we just did.
1247 if (addr.uses(sp)) {
1248 lea(r0, addr);
1249 ldr(r0, Address(r0, 4 * wordSize));
1250 } else {
1251 ldr(r0, addr);
1252 }
1253 mov(rscratch1, (address)b);
1254
1255 // call indirectly to solve generation ordering problem
1256 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1257 ldr(rscratch2, Address(rscratch2));
1258 blr(rscratch2);
1259
1260 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1261 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1262
1263 BLOCK_COMMENT("} verify_oop_addr");
1264 }
1265
1266 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
1267 int extra_slot_offset) {
1268 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
1269 int stackElementSize = Interpreter::stackElementSize;
1270 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
1271 #ifdef ASSERT
1272 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
1273 assert(offset1 - offset == stackElementSize, "correct arithmetic");
1274 #endif
1275 if (arg_slot.is_constant()) {
1276 return Address(esp, arg_slot.as_constant() * stackElementSize
1277 + offset);
1278 } else {
1279 add(rscratch1, esp, arg_slot.as_register(),
1280 ext::uxtx, exact_log2(stackElementSize));
1281 return Address(rscratch1, offset);
1282 }
1283 }
1284
1285 void MacroAssembler::call_VM_leaf_base(address entry_point,
1286 int number_of_arguments,
1287 Label *retaddr) {
1288 call_VM_leaf_base1(entry_point, number_of_arguments, 0, ret_type_integral, retaddr);
1289 }
1290
1291 void MacroAssembler::call_VM_leaf_base1(address entry_point,
1292 int number_of_gp_arguments,
1293 int number_of_fp_arguments,
1294 ret_type type,
1295 Label *retaddr) {
1296 Label E, L;
1297
1298 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
1299
1300 // We add 1 to number_of_arguments because the thread in arg0 is
1301 // not counted
1302 mov(rscratch1, entry_point);
1303 blrt(rscratch1, number_of_gp_arguments + 1, number_of_fp_arguments, type);
1304 if (retaddr)
1305 bind(*retaddr);
1306
1307 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
1308 maybe_isb();
1309 }
1310
1311 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1312 call_VM_leaf_base(entry_point, number_of_arguments);
1313 }
1314
1315 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1316 pass_arg0(this, arg_0);
1317 call_VM_leaf_base(entry_point, 1);
1318 }
1319
1320 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1321 pass_arg0(this, arg_0);
1322 pass_arg1(this, arg_1);
1323 call_VM_leaf_base(entry_point, 2);
1324 }
1325
1326 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1327 Register arg_1, Register arg_2) {
1328 pass_arg0(this, arg_0);
1329 pass_arg1(this, arg_1);
1330 pass_arg2(this, arg_2);
1331 call_VM_leaf_base(entry_point, 3);
1332 }
1333
1334 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1335 pass_arg0(this, arg_0);
1336 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1337 }
1338
1339 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1340
1341 assert(arg_0 != c_rarg1, "smashed arg");
1342 pass_arg1(this, arg_1);
1343 pass_arg0(this, arg_0);
1344 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1345 }
1346
1347 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1348 assert(arg_0 != c_rarg2, "smashed arg");
1349 assert(arg_1 != c_rarg2, "smashed arg");
1350 pass_arg2(this, arg_2);
1351 assert(arg_0 != c_rarg1, "smashed arg");
1352 pass_arg1(this, arg_1);
1353 pass_arg0(this, arg_0);
1354 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1355 }
1356
1357 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1358 assert(arg_0 != c_rarg3, "smashed arg");
1359 assert(arg_1 != c_rarg3, "smashed arg");
1360 assert(arg_2 != c_rarg3, "smashed arg");
1361 pass_arg3(this, arg_3);
1362 assert(arg_0 != c_rarg2, "smashed arg");
1363 assert(arg_1 != c_rarg2, "smashed arg");
1364 pass_arg2(this, arg_2);
1365 assert(arg_0 != c_rarg1, "smashed arg");
1366 pass_arg1(this, arg_1);
1367 pass_arg0(this, arg_0);
1368 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1369 }
1370
1371 void MacroAssembler::null_check(Register reg, int offset) {
1372 if (needs_explicit_null_check(offset)) {
1373 // provoke OS NULL exception if reg = NULL by
1374 // accessing M[reg] w/o changing any registers
1375 // NOTE: this is plenty to provoke a segv
1376 ldr(zr, Address(reg));
1377 } else {
1378 // nothing to do, (later) access of M[reg + offset]
1379 // will provoke OS NULL exception if reg = NULL
1380 }
1381 }
1382
1383 // MacroAssembler protected routines needed to implement
1384 // public methods
1385
1386 void MacroAssembler::mov(Register r, Address dest) {
1387 code_section()->relocate(pc(), dest.rspec());
1388 u_int64_t imm64 = (u_int64_t)dest.target();
1389 movptr(r, imm64);
1390 }
1391
1392 // Move a constant pointer into r. In AArch64 mode the virtual
1393 // address space is 48 bits in size, so we only need three
1394 // instructions to create a patchable instruction sequence that can
1395 // reach anywhere.
1396 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
1397 #ifndef PRODUCT
1398 {
1399 char buffer[64];
1400 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
1401 block_comment(buffer);
1402 }
1403 #endif
1404 assert(imm64 < (1ul << 48), "48-bit overflow in address constant");
1405 movz(r, imm64 & 0xffff);
1406 imm64 >>= 16;
1407 movk(r, imm64 & 0xffff, 16);
1408 imm64 >>= 16;
1409 movk(r, imm64 & 0xffff, 32);
1410 }
1411
1412 // Macro to mov replicated immediate to vector register.
1413 // Vd will get the following values for different arrangements in T
1414 // imm32 == hex 000000gh T8B: Vd = ghghghghghghghgh
1415 // imm32 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
1416 // imm32 == hex 0000efgh T4H: Vd = efghefghefghefgh
1417 // imm32 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
1418 // imm32 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
1419 // imm32 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
1420 // T1D/T2D: invalid
1421 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) {
1422 assert(T != T1D && T != T2D, "invalid arrangement");
1423 if (T == T8B || T == T16B) {
1424 assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)");
1425 movi(Vd, T, imm32 & 0xff, 0);
1426 return;
1427 }
1428 u_int32_t nimm32 = ~imm32;
1429 if (T == T4H || T == T8H) {
1430 assert((imm32 & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)");
1431 imm32 &= 0xffff;
1432 nimm32 &= 0xffff;
1433 }
1434 u_int32_t x = imm32;
1435 int movi_cnt = 0;
1436 int movn_cnt = 0;
1437 while (x) { if (x & 0xff) movi_cnt++; x >>= 8; }
1438 x = nimm32;
1439 while (x) { if (x & 0xff) movn_cnt++; x >>= 8; }
1440 if (movn_cnt < movi_cnt) imm32 = nimm32;
1441 unsigned lsl = 0;
1442 while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
1443 if (movn_cnt < movi_cnt)
1444 mvni(Vd, T, imm32 & 0xff, lsl);
1445 else
1446 movi(Vd, T, imm32 & 0xff, lsl);
1447 imm32 >>= 8; lsl += 8;
1448 while (imm32) {
1449 while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
1450 if (movn_cnt < movi_cnt)
1451 bici(Vd, T, imm32 & 0xff, lsl);
1452 else
1453 orri(Vd, T, imm32 & 0xff, lsl);
1454 lsl += 8; imm32 >>= 8;
1455 }
1456 }
1457
1458 void MacroAssembler::mov_immediate64(Register dst, u_int64_t imm64)
1459 {
1460 #ifndef PRODUCT
1461 {
1462 char buffer[64];
1463 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
1464 block_comment(buffer);
1465 }
1466 #endif
1467 if (operand_valid_for_logical_immediate(false, imm64)) {
1468 orr(dst, zr, imm64);
1469 } else {
1470 // we can use a combination of MOVZ or MOVN with
1471 // MOVK to build up the constant
1472 u_int64_t imm_h[4];
1473 int zero_count = 0;
1474 int neg_count = 0;
1475 int i;
1476 for (i = 0; i < 4; i++) {
1477 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
1478 if (imm_h[i] == 0) {
1479 zero_count++;
1480 } else if (imm_h[i] == 0xffffL) {
1481 neg_count++;
1482 }
1483 }
1484 if (zero_count == 4) {
1485 // one MOVZ will do
1486 movz(dst, 0);
1487 } else if (neg_count == 4) {
1488 // one MOVN will do
1489 movn(dst, 0);
1490 } else if (zero_count == 3) {
1491 for (i = 0; i < 4; i++) {
1492 if (imm_h[i] != 0L) {
1493 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1494 break;
1495 }
1496 }
1497 } else if (neg_count == 3) {
1498 // one MOVN will do
1499 for (int i = 0; i < 4; i++) {
1500 if (imm_h[i] != 0xffffL) {
1501 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1502 break;
1503 }
1504 }
1505 } else if (zero_count == 2) {
1506 // one MOVZ and one MOVK will do
1507 for (i = 0; i < 3; i++) {
1508 if (imm_h[i] != 0L) {
1509 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1510 i++;
1511 break;
1512 }
1513 }
1514 for (;i < 4; i++) {
1515 if (imm_h[i] != 0L) {
1516 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1517 }
1518 }
1519 } else if (neg_count == 2) {
1520 // one MOVN and one MOVK will do
1521 for (i = 0; i < 4; i++) {
1522 if (imm_h[i] != 0xffffL) {
1523 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1524 i++;
1525 break;
1526 }
1527 }
1528 for (;i < 4; i++) {
1529 if (imm_h[i] != 0xffffL) {
1530 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1531 }
1532 }
1533 } else if (zero_count == 1) {
1534 // one MOVZ and two MOVKs will do
1535 for (i = 0; i < 4; i++) {
1536 if (imm_h[i] != 0L) {
1537 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1538 i++;
1539 break;
1540 }
1541 }
1542 for (;i < 4; i++) {
1543 if (imm_h[i] != 0x0L) {
1544 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1545 }
1546 }
1547 } else if (neg_count == 1) {
1548 // one MOVN and two MOVKs will do
1549 for (i = 0; i < 4; i++) {
1550 if (imm_h[i] != 0xffffL) {
1551 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1552 i++;
1553 break;
1554 }
1555 }
1556 for (;i < 4; i++) {
1557 if (imm_h[i] != 0xffffL) {
1558 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1559 }
1560 }
1561 } else {
1562 // use a MOVZ and 3 MOVKs (makes it easier to debug)
1563 movz(dst, (u_int32_t)imm_h[0], 0);
1564 for (i = 1; i < 4; i++) {
1565 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1566 }
1567 }
1568 }
1569 }
1570
1571 void MacroAssembler::mov_immediate32(Register dst, u_int32_t imm32)
1572 {
1573 #ifndef PRODUCT
1574 {
1575 char buffer[64];
1576 snprintf(buffer, sizeof(buffer), "0x%"PRIX32, imm32);
1577 block_comment(buffer);
1578 }
1579 #endif
1580 if (operand_valid_for_logical_immediate(true, imm32)) {
1581 orrw(dst, zr, imm32);
1582 } else {
1583 // we can use MOVZ, MOVN or two calls to MOVK to build up the
1584 // constant
1585 u_int32_t imm_h[2];
1586 imm_h[0] = imm32 & 0xffff;
1587 imm_h[1] = ((imm32 >> 16) & 0xffff);
1588 if (imm_h[0] == 0) {
1589 movzw(dst, imm_h[1], 16);
1590 } else if (imm_h[0] == 0xffff) {
1591 movnw(dst, imm_h[1] ^ 0xffff, 16);
1592 } else if (imm_h[1] == 0) {
1593 movzw(dst, imm_h[0], 0);
1594 } else if (imm_h[1] == 0xffff) {
1595 movnw(dst, imm_h[0] ^ 0xffff, 0);
1596 } else {
1597 // use a MOVZ and MOVK (makes it easier to debug)
1598 movzw(dst, imm_h[0], 0);
1599 movkw(dst, imm_h[1], 16);
1600 }
1601 }
1602 }
1603
1604 // Form an address from base + offset in Rd. Rd may or may
1605 // not actually be used: you must use the Address that is returned.
1606 // It is up to you to ensure that the shift provided matches the size
1607 // of your data.
1608 Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) {
1609 if (Address::offset_ok_for_immed(byte_offset, shift))
1610 // It fits; no need for any heroics
1611 return Address(base, byte_offset);
1612
1613 // Don't do anything clever with negative or misaligned offsets
1614 unsigned mask = (1 << shift) - 1;
1615 if (byte_offset < 0 || byte_offset & mask) {
1616 mov(Rd, byte_offset);
1617 add(Rd, base, Rd);
1618 return Address(Rd);
1619 }
1620
1621 // See if we can do this with two 12-bit offsets
1622 {
1623 unsigned long word_offset = byte_offset >> shift;
1624 unsigned long masked_offset = word_offset & 0xfff000;
1625 if (Address::offset_ok_for_immed(word_offset - masked_offset)
1626 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
1627 add(Rd, base, masked_offset << shift);
1628 word_offset -= masked_offset;
1629 return Address(Rd, word_offset << shift);
1630 }
1631 }
1632
1633 // Do it the hard way
1634 mov(Rd, byte_offset);
1635 add(Rd, base, Rd);
1636 return Address(Rd);
1637 }
1638
1639 void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) {
1640 if (UseLSE) {
1641 mov(tmp, 1);
1642 ldadd(Assembler::word, tmp, zr, counter_addr);
1643 return;
1644 }
1645 Label retry_load;
1646 prfm(Address(counter_addr), PSTL1STRM);
1647 bind(retry_load);
1648 // flush and load exclusive from the memory location
1649 ldxrw(tmp, counter_addr);
1650 addw(tmp, tmp, 1);
1651 // if we store+flush with no intervening write tmp wil be zero
1652 stxrw(tmp2, tmp, counter_addr);
1653 cbnzw(tmp2, retry_load);
1654 }
1655
1656
1657 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
1658 bool want_remainder, Register scratch)
1659 {
1660 // Full implementation of Java idiv and irem. The function
1661 // returns the (pc) offset of the div instruction - may be needed
1662 // for implicit exceptions.
1663 //
1664 // constraint : ra/rb =/= scratch
1665 // normal case
1666 //
1667 // input : ra: dividend
1668 // rb: divisor
1669 //
1670 // result: either
1671 // quotient (= ra idiv rb)
1672 // remainder (= ra irem rb)
1673
1674 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
1675
1676 int idivl_offset = offset();
1677 if (! want_remainder) {
1678 sdivw(result, ra, rb);
1679 } else {
1680 sdivw(scratch, ra, rb);
1681 Assembler::msubw(result, scratch, rb, ra);
1682 }
1683
1684 return idivl_offset;
1685 }
1686
1687 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
1688 bool want_remainder, Register scratch)
1689 {
1690 // Full implementation of Java ldiv and lrem. The function
1691 // returns the (pc) offset of the div instruction - may be needed
1692 // for implicit exceptions.
1693 //
1694 // constraint : ra/rb =/= scratch
1695 // normal case
1696 //
1697 // input : ra: dividend
1698 // rb: divisor
1699 //
1700 // result: either
1701 // quotient (= ra idiv rb)
1702 // remainder (= ra irem rb)
1703
1704 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
1705
1706 int idivq_offset = offset();
1707 if (! want_remainder) {
1708 sdiv(result, ra, rb);
1709 } else {
1710 sdiv(scratch, ra, rb);
1711 Assembler::msub(result, scratch, rb, ra);
1712 }
1713
1714 return idivq_offset;
1715 }
1716
1717 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
1718 address prev = pc() - NativeMembar::instruction_size;
1719 if (prev == code()->last_membar()) {
1720 NativeMembar *bar = NativeMembar_at(prev);
1721 // We are merging two memory barrier instructions. On AArch64 we
1722 // can do this simply by ORing them together.
1723 bar->set_kind(bar->get_kind() | order_constraint);
1724 BLOCK_COMMENT("merged membar");
1725 } else {
1726 code()->set_last_membar(pc());
1727 dmb(Assembler::barrier(order_constraint));
1728 }
1729 }
1730
1731 // MacroAssembler routines found actually to be needed
1732
1733 void MacroAssembler::push(Register src)
1734 {
1735 str(src, Address(pre(esp, -1 * wordSize)));
1736 }
1737
1738 void MacroAssembler::pop(Register dst)
1739 {
1740 ldr(dst, Address(post(esp, 1 * wordSize)));
1741 }
1742
1743 // Note: load_unsigned_short used to be called load_unsigned_word.
1744 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1745 int off = offset();
1746 ldrh(dst, src);
1747 return off;
1748 }
1749
1750 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1751 int off = offset();
1752 ldrb(dst, src);
1753 return off;
1754 }
1755
1756 int MacroAssembler::load_signed_short(Register dst, Address src) {
1757 int off = offset();
1758 ldrsh(dst, src);
1759 return off;
1760 }
1761
1762 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1763 int off = offset();
1764 ldrsb(dst, src);
1765 return off;
1766 }
1767
1768 int MacroAssembler::load_signed_short32(Register dst, Address src) {
1769 int off = offset();
1770 ldrshw(dst, src);
1771 return off;
1772 }
1773
1774 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
1775 int off = offset();
1776 ldrsbw(dst, src);
1777 return off;
1778 }
1779
1780 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1781 switch (size_in_bytes) {
1782 case 8: ldr(dst, src); break;
1783 case 4: ldrw(dst, src); break;
1784 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1785 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1786 default: ShouldNotReachHere();
1787 }
1788 }
1789
1790 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1791 switch (size_in_bytes) {
1792 case 8: str(src, dst); break;
1793 case 4: strw(src, dst); break;
1794 case 2: strh(src, dst); break;
1795 case 1: strb(src, dst); break;
1796 default: ShouldNotReachHere();
1797 }
1798 }
1799
1800 void MacroAssembler::decrementw(Register reg, int value)
1801 {
1802 if (value < 0) { incrementw(reg, -value); return; }
1803 if (value == 0) { return; }
1804 if (value < (1 << 12)) { subw(reg, reg, value); return; }
1805 /* else */ {
1806 guarantee(reg != rscratch2, "invalid dst for register decrement");
1807 movw(rscratch2, (unsigned)value);
1808 subw(reg, reg, rscratch2);
1809 }
1810 }
1811
1812 void MacroAssembler::decrement(Register reg, int value)
1813 {
1814 if (value < 0) { increment(reg, -value); return; }
1815 if (value == 0) { return; }
1816 if (value < (1 << 12)) { sub(reg, reg, value); return; }
1817 /* else */ {
1818 assert(reg != rscratch2, "invalid dst for register decrement");
1819 mov(rscratch2, (unsigned long)value);
1820 sub(reg, reg, rscratch2);
1821 }
1822 }
1823
1824 void MacroAssembler::decrementw(Address dst, int value)
1825 {
1826 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
1827 ldrw(rscratch1, dst);
1828 decrementw(rscratch1, value);
1829 strw(rscratch1, dst);
1830 }
1831
1832 void MacroAssembler::decrement(Address dst, int value)
1833 {
1834 assert(!dst.uses(rscratch1), "invalid address for decrement");
1835 ldr(rscratch1, dst);
1836 decrement(rscratch1, value);
1837 str(rscratch1, dst);
1838 }
1839
1840 void MacroAssembler::incrementw(Register reg, int value)
1841 {
1842 if (value < 0) { decrementw(reg, -value); return; }
1843 if (value == 0) { return; }
1844 if (value < (1 << 12)) { addw(reg, reg, value); return; }
1845 /* else */ {
1846 assert(reg != rscratch2, "invalid dst for register increment");
1847 movw(rscratch2, (unsigned)value);
1848 addw(reg, reg, rscratch2);
1849 }
1850 }
1851
1852 void MacroAssembler::increment(Register reg, int value)
1853 {
1854 if (value < 0) { decrement(reg, -value); return; }
1855 if (value == 0) { return; }
1856 if (value < (1 << 12)) { add(reg, reg, value); return; }
1857 /* else */ {
1858 assert(reg != rscratch2, "invalid dst for register increment");
1859 movw(rscratch2, (unsigned)value);
1860 add(reg, reg, rscratch2);
1861 }
1862 }
1863
1864 void MacroAssembler::incrementw(Address dst, int value)
1865 {
1866 assert(!dst.uses(rscratch1), "invalid dst for address increment");
1867 ldrw(rscratch1, dst);
1868 incrementw(rscratch1, value);
1869 strw(rscratch1, dst);
1870 }
1871
1872 void MacroAssembler::increment(Address dst, int value)
1873 {
1874 assert(!dst.uses(rscratch1), "invalid dst for address increment");
1875 ldr(rscratch1, dst);
1876 increment(rscratch1, value);
1877 str(rscratch1, dst);
1878 }
1879
1880
1881 void MacroAssembler::pusha() {
1882 push(0x7fffffff, sp);
1883 }
1884
1885 void MacroAssembler::popa() {
1886 pop(0x7fffffff, sp);
1887 }
1888
1889 // Push lots of registers in the bit set supplied. Don't push sp.
1890 // Return the number of words pushed
1891 int MacroAssembler::push(unsigned int bitset, Register stack) {
1892 int words_pushed = 0;
1893
1894 // Scan bitset to accumulate register pairs
1895 unsigned char regs[32];
1896 int count = 0;
1897 for (int reg = 0; reg <= 30; reg++) {
1898 if (1 & bitset)
1899 regs[count++] = reg;
1900 bitset >>= 1;
1901 }
1902 regs[count++] = zr->encoding_nocheck();
1903 count &= ~1; // Only push an even nuber of regs
1904
1905 if (count) {
1906 stp(as_Register(regs[0]), as_Register(regs[1]),
1907 Address(pre(stack, -count * wordSize)));
1908 words_pushed += 2;
1909 }
1910 for (int i = 2; i < count; i += 2) {
1911 stp(as_Register(regs[i]), as_Register(regs[i+1]),
1912 Address(stack, i * wordSize));
1913 words_pushed += 2;
1914 }
1915
1916 assert(words_pushed == count, "oops, pushed != count");
1917
1918 return count;
1919 }
1920
1921 int MacroAssembler::pop(unsigned int bitset, Register stack) {
1922 int words_pushed = 0;
1923
1924 // Scan bitset to accumulate register pairs
1925 unsigned char regs[32];
1926 int count = 0;
1927 for (int reg = 0; reg <= 30; reg++) {
1928 if (1 & bitset)
1929 regs[count++] = reg;
1930 bitset >>= 1;
1931 }
1932 regs[count++] = zr->encoding_nocheck();
1933 count &= ~1;
1934
1935 for (int i = 2; i < count; i += 2) {
1936 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
1937 Address(stack, i * wordSize));
1938 words_pushed += 2;
1939 }
1940 if (count) {
1941 ldp(as_Register(regs[0]), as_Register(regs[1]),
1942 Address(post(stack, count * wordSize)));
1943 words_pushed += 2;
1944 }
1945
1946 assert(words_pushed == count, "oops, pushed != count");
1947
1948 return count;
1949 }
1950 #ifdef ASSERT
1951 void MacroAssembler::verify_heapbase(const char* msg) {
1952 #if 0
1953 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
1954 assert (Universe::heap() != NULL, "java heap should be initialized");
1955 if (CheckCompressedOops) {
1956 Label ok;
1957 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
1958 cmpptr(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
1959 br(Assembler::EQ, ok);
1960 stop(msg);
1961 bind(ok);
1962 pop(1 << rscratch1->encoding(), sp);
1963 }
1964 #endif
1965 }
1966 #endif
1967
1968 void MacroAssembler::stop(const char* msg) {
1969 address ip = pc();
1970 pusha();
1971 mov(c_rarg0, (address)msg);
1972 mov(c_rarg1, (address)ip);
1973 mov(c_rarg2, sp);
1974 mov(c_rarg3, CAST_FROM_FN_PTR(address, MacroAssembler::debug64));
1975 // call(c_rarg3);
1976 blrt(c_rarg3, 3, 0, 1);
1977 hlt(0);
1978 }
1979
1980 // If a constant does not fit in an immediate field, generate some
1981 // number of MOV instructions and then perform the operation.
1982 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1983 add_sub_imm_insn insn1,
1984 add_sub_reg_insn insn2) {
1985 assert(Rd != zr, "Rd = zr and not setting flags?");
1986 if (operand_valid_for_add_sub_immediate((int)imm)) {
1987 (this->*insn1)(Rd, Rn, imm);
1988 } else {
1989 if (uabs(imm) < (1 << 24)) {
1990 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
1991 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
1992 } else {
1993 assert_different_registers(Rd, Rn);
1994 mov(Rd, (uint64_t)imm);
1995 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
1996 }
1997 }
1998 }
1999
2000 // Seperate vsn which sets the flags. Optimisations are more restricted
2001 // because we must set the flags correctly.
2002 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
2003 add_sub_imm_insn insn1,
2004 add_sub_reg_insn insn2) {
2005 if (operand_valid_for_add_sub_immediate((int)imm)) {
2006 (this->*insn1)(Rd, Rn, imm);
2007 } else {
2008 assert_different_registers(Rd, Rn);
2009 assert(Rd != zr, "overflow in immediate operand");
2010 mov(Rd, (uint64_t)imm);
2011 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
2012 }
2013 }
2014
2015
2016 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
2017 if (increment.is_register()) {
2018 add(Rd, Rn, increment.as_register());
2019 } else {
2020 add(Rd, Rn, increment.as_constant());
2021 }
2022 }
2023
2024 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
2025 if (increment.is_register()) {
2026 addw(Rd, Rn, increment.as_register());
2027 } else {
2028 addw(Rd, Rn, increment.as_constant());
2029 }
2030 }
2031
2032 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
2033 if (decrement.is_register()) {
2034 sub(Rd, Rn, decrement.as_register());
2035 } else {
2036 sub(Rd, Rn, decrement.as_constant());
2037 }
2038 }
2039
2040 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
2041 if (decrement.is_register()) {
2042 subw(Rd, Rn, decrement.as_register());
2043 } else {
2044 subw(Rd, Rn, decrement.as_constant());
2045 }
2046 }
2047
2048 void MacroAssembler::reinit_heapbase()
2049 {
2050 if (UseCompressedOops) {
2051 if (Universe::is_fully_initialized()) {
2052 mov(rheapbase, Universe::narrow_ptrs_base());
2053 } else {
2054 lea(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
2055 ldr(rheapbase, Address(rheapbase));
2056 }
2057 }
2058 }
2059
2060 // this simulates the behaviour of the x86 cmpxchg instruction using a
2061 // load linked/store conditional pair. we use the acquire/release
2062 // versions of these instructions so that we flush pending writes as
2063 // per Java semantics.
2064
2065 // n.b the x86 version assumes the old value to be compared against is
2066 // in rax and updates rax with the value located in memory if the
2067 // cmpxchg fails. we supply a register for the old value explicitly
2068
2069 // the aarch64 load linked/store conditional instructions do not
2070 // accept an offset. so, unlike x86, we must provide a plain register
2071 // to identify the memory word to be compared/exchanged rather than a
2072 // register+offset Address.
2073
2074 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
2075 Label &succeed, Label *fail) {
2076 // oldv holds comparison value
2077 // newv holds value to write in exchange
2078 // addr identifies memory word to compare against/update
2079 if (UseLSE) {
2080 mov(tmp, oldv);
2081 casal(Assembler::xword, oldv, newv, addr);
2082 cmp(tmp, oldv);
2083 br(Assembler::EQ, succeed);
2084 membar(AnyAny);
2085 } else {
2086 Label retry_load, nope;
2087 prfm(Address(addr), PSTL1STRM);
2088 bind(retry_load);
2089 // flush and load exclusive from the memory location
2090 // and fail if it is not what we expect
2091 ldaxr(tmp, addr);
2092 cmp(tmp, oldv);
2093 br(Assembler::NE, nope);
2094 // if we store+flush with no intervening write tmp wil be zero
2095 stlxr(tmp, newv, addr);
2096 cbzw(tmp, succeed);
2097 // retry so we only ever return after a load fails to compare
2098 // ensures we don't return a stale value after a failed write.
2099 b(retry_load);
2100 // if the memory word differs we return it in oldv and signal a fail
2101 bind(nope);
2102 membar(AnyAny);
2103 mov(oldv, tmp);
2104 }
2105 if (fail)
2106 b(*fail);
2107 }
2108
2109 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
2110 Label &succeed, Label *fail) {
2111 // oldv holds comparison value
2112 // newv holds value to write in exchange
2113 // addr identifies memory word to compare against/update
2114 // tmp returns 0/1 for success/failure
2115 if (UseLSE) {
2116 mov(tmp, oldv);
2117 casal(Assembler::word, oldv, newv, addr);
2118 cmp(tmp, oldv);
2119 br(Assembler::EQ, succeed);
2120 membar(AnyAny);
2121 } else {
2122 Label retry_load, nope;
2123 prfm(Address(addr), PSTL1STRM);
2124 bind(retry_load);
2125 // flush and load exclusive from the memory location
2126 // and fail if it is not what we expect
2127 ldaxrw(tmp, addr);
2128 cmp(tmp, oldv);
2129 br(Assembler::NE, nope);
2130 // if we store+flush with no intervening write tmp wil be zero
2131 stlxrw(tmp, newv, addr);
2132 cbzw(tmp, succeed);
2133 // retry so we only ever return after a load fails to compare
2134 // ensures we don't return a stale value after a failed write.
2135 b(retry_load);
2136 // if the memory word differs we return it in oldv and signal a fail
2137 bind(nope);
2138 membar(AnyAny);
2139 mov(oldv, tmp);
2140 }
2141 if (fail)
2142 b(*fail);
2143 }
2144
2145 // A generic CAS; success or failure is in the EQ flag.
2146 void MacroAssembler::cmpxchg(Register addr, Register expected,
2147 Register new_val,
2148 enum operand_size size,
2149 bool acquire, bool release,
2150 Register tmp) {
2151 if (UseLSE) {
2152 mov(tmp, expected);
2153 lse_cas(tmp, new_val, addr, size, acquire, release, /*not_pair*/ true);
2154 cmp(tmp, expected);
2155 } else {
2156 BLOCK_COMMENT("cmpxchg {");
2157 Label retry_load, done;
2158 prfm(Address(addr), PSTL1STRM);
2159 bind(retry_load);
2160 load_exclusive(tmp, addr, size, acquire);
2161 if (size == xword)
2162 cmp(tmp, expected);
2163 else
2164 cmpw(tmp, expected);
2165 br(Assembler::NE, done);
2166 store_exclusive(tmp, new_val, addr, size, release);
2167 cbnzw(tmp, retry_load);
2168 bind(done);
2169 BLOCK_COMMENT("} cmpxchg");
2170 }
2171 }
2172
2173 static bool different(Register a, RegisterOrConstant b, Register c) {
2174 if (b.is_constant())
2175 return a != c;
2176 else
2177 return a != b.as_register() && a != c && b.as_register() != c;
2178 }
2179
2180 #define ATOMIC_OP(LDXR, OP, IOP, AOP, STXR, sz) \
2181 void MacroAssembler::atomic_##OP(Register prev, RegisterOrConstant incr, Register addr) { \
2182 if (UseLSE) { \
2183 prev = prev->is_valid() ? prev : zr; \
2184 if (incr.is_register()) { \
2185 AOP(sz, incr.as_register(), prev, addr); \
2186 } else { \
2187 mov(rscratch2, incr.as_constant()); \
2188 AOP(sz, rscratch2, prev, addr); \
2189 } \
2190 return; \
2191 } \
2192 Register result = rscratch2; \
2193 if (prev->is_valid()) \
2194 result = different(prev, incr, addr) ? prev : rscratch2; \
2195 \
2196 Label retry_load; \
2197 prfm(Address(addr), PSTL1STRM); \
2198 bind(retry_load); \
2199 LDXR(result, addr); \
2200 OP(rscratch1, result, incr); \
2201 STXR(rscratch2, rscratch1, addr); \
2202 cbnzw(rscratch2, retry_load); \
2203 if (prev->is_valid() && prev != result) { \
2204 IOP(prev, rscratch1, incr); \
2205 } \
2206 }
2207
2208 ATOMIC_OP(ldxr, add, sub, ldadd, stxr, Assembler::xword)
2209 ATOMIC_OP(ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
2210
2211 #undef ATOMIC_OP
2212
2213 #define ATOMIC_XCHG(OP, LDXR, STXR, sz) \
2214 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
2215 if (UseLSE) { \
2216 prev = prev->is_valid() ? prev : zr; \
2217 swp(sz, newv, prev, addr); \
2218 return; \
2219 } \
2220 Register result = rscratch2; \
2221 if (prev->is_valid()) \
2222 result = different(prev, newv, addr) ? prev : rscratch2; \
2223 \
2224 Label retry_load; \
2225 prfm(Address(addr), PSTL1STRM); \
2226 bind(retry_load); \
2227 LDXR(result, addr); \
2228 STXR(rscratch1, newv, addr); \
2229 cbnzw(rscratch1, retry_load); \
2230 if (prev->is_valid() && prev != result) \
2231 mov(prev, result); \
2232 }
2233
2234 ATOMIC_XCHG(xchg, ldxr, stxr, Assembler::xword)
2235 ATOMIC_XCHG(xchgw, ldxrw, stxrw, Assembler::word)
2236
2237 #undef ATOMIC_XCHG
2238
2239 void MacroAssembler::incr_allocated_bytes(Register thread,
2240 Register var_size_in_bytes,
2241 int con_size_in_bytes,
2242 Register t1) {
2243 if (!thread->is_valid()) {
2244 thread = rthread;
2245 }
2246 assert(t1->is_valid(), "need temp reg");
2247
2248 ldr(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset())));
2249 if (var_size_in_bytes->is_valid()) {
2250 add(t1, t1, var_size_in_bytes);
2251 } else {
2252 add(t1, t1, con_size_in_bytes);
2253 }
2254 str(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset())));
2255 }
2256
2257 #ifndef PRODUCT
2258 extern "C" void findpc(intptr_t x);
2259 #endif
2260
2261 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
2262 {
2263 // In order to get locks to work, we need to fake a in_VM state
2264 if (ShowMessageBoxOnError ) {
2265 JavaThread* thread = JavaThread::current();
2266 JavaThreadState saved_state = thread->thread_state();
2267 thread->set_thread_state(_thread_in_vm);
2268 #ifndef PRODUCT
2269 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
2270 ttyLocker ttyl;
2271 BytecodeCounter::print();
2272 }
2273 #endif
2274 if (os::message_box(msg, "Execution stopped, print registers?")) {
2275 ttyLocker ttyl;
2276 tty->print_cr(" pc = 0x%016lx", pc);
2277 #ifndef PRODUCT
2278 tty->cr();
2279 findpc(pc);
2280 tty->cr();
2281 #endif
2282 tty->print_cr(" r0 = 0x%016lx", regs[0]);
2283 tty->print_cr(" r1 = 0x%016lx", regs[1]);
2284 tty->print_cr(" r2 = 0x%016lx", regs[2]);
2285 tty->print_cr(" r3 = 0x%016lx", regs[3]);
2286 tty->print_cr(" r4 = 0x%016lx", regs[4]);
2287 tty->print_cr(" r5 = 0x%016lx", regs[5]);
2288 tty->print_cr(" r6 = 0x%016lx", regs[6]);
2289 tty->print_cr(" r7 = 0x%016lx", regs[7]);
2290 tty->print_cr(" r8 = 0x%016lx", regs[8]);
2291 tty->print_cr(" r9 = 0x%016lx", regs[9]);
2292 tty->print_cr("r10 = 0x%016lx", regs[10]);
2293 tty->print_cr("r11 = 0x%016lx", regs[11]);
2294 tty->print_cr("r12 = 0x%016lx", regs[12]);
2295 tty->print_cr("r13 = 0x%016lx", regs[13]);
2296 tty->print_cr("r14 = 0x%016lx", regs[14]);
2297 tty->print_cr("r15 = 0x%016lx", regs[15]);
2298 tty->print_cr("r16 = 0x%016lx", regs[16]);
2299 tty->print_cr("r17 = 0x%016lx", regs[17]);
2300 tty->print_cr("r18 = 0x%016lx", regs[18]);
2301 tty->print_cr("r19 = 0x%016lx", regs[19]);
2302 tty->print_cr("r20 = 0x%016lx", regs[20]);
2303 tty->print_cr("r21 = 0x%016lx", regs[21]);
2304 tty->print_cr("r22 = 0x%016lx", regs[22]);
2305 tty->print_cr("r23 = 0x%016lx", regs[23]);
2306 tty->print_cr("r24 = 0x%016lx", regs[24]);
2307 tty->print_cr("r25 = 0x%016lx", regs[25]);
2308 tty->print_cr("r26 = 0x%016lx", regs[26]);
2309 tty->print_cr("r27 = 0x%016lx", regs[27]);
2310 tty->print_cr("r28 = 0x%016lx", regs[28]);
2311 tty->print_cr("r30 = 0x%016lx", regs[30]);
2312 tty->print_cr("r31 = 0x%016lx", regs[31]);
2313 BREAKPOINT;
2314 }
2315 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
2316 } else {
2317 ttyLocker ttyl;
2318 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
2319 msg);
2320 assert(false, "DEBUG MESSAGE: %s", msg);
2321 }
2322 }
2323
2324 #ifdef BUILTIN_SIM
2325 // routine to generate an x86 prolog for a stub function which
2326 // bootstraps into the generated ARM code which directly follows the
2327 // stub
2328 //
2329 // the argument encodes the number of general and fp registers
2330 // passed by the caller and the callng convention (currently just
2331 // the number of general registers and assumes C argument passing)
2332
2333 extern "C" {
2334 int aarch64_stub_prolog_size();
2335 void aarch64_stub_prolog();
2336 void aarch64_prolog();
2337 }
2338
2339 void MacroAssembler::c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type,
2340 address *prolog_ptr)
2341 {
2342 int calltype = (((ret_type & 0x3) << 8) |
2343 ((fp_arg_count & 0xf) << 4) |
2344 (gp_arg_count & 0xf));
2345
2346 // the addresses for the x86 to ARM entry code we need to use
2347 address start = pc();
2348 // printf("start = %lx\n", start);
2349 int byteCount = aarch64_stub_prolog_size();
2350 // printf("byteCount = %x\n", byteCount);
2351 int instructionCount = (byteCount + 3)/ 4;
2352 // printf("instructionCount = %x\n", instructionCount);
2353 for (int i = 0; i < instructionCount; i++) {
2354 nop();
2355 }
2356
2357 memcpy(start, (void*)aarch64_stub_prolog, byteCount);
2358
2359 // write the address of the setup routine and the call format at the
2360 // end of into the copied code
2361 u_int64_t *patch_end = (u_int64_t *)(start + byteCount);
2362 if (prolog_ptr)
2363 patch_end[-2] = (u_int64_t)prolog_ptr;
2364 patch_end[-1] = calltype;
2365 }
2366 #endif
2367
2368 void MacroAssembler::push_call_clobbered_registers() {
2369 push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
2370
2371 // Push v0-v7, v16-v31.
2372 for (int i = 30; i >= 0; i -= 2) {
2373 if (i <= v7->encoding() || i >= v16->encoding()) {
2374 stpd(as_FloatRegister(i), as_FloatRegister(i+1),
2375 Address(pre(sp, -2 * wordSize)));
2376 }
2377 }
2378 }
2379
2380 void MacroAssembler::pop_call_clobbered_registers() {
2381
2382 for (int i = 0; i < 32; i += 2) {
2383 if (i <= v7->encoding() || i >= v16->encoding()) {
2384 ldpd(as_FloatRegister(i), as_FloatRegister(i+1),
2385 Address(post(sp, 2 * wordSize)));
2386 }
2387 }
2388
2389 pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
2390 }
2391
2392 void MacroAssembler::push_CPU_state(bool save_vectors) {
2393 push(0x3fffffff, sp); // integer registers except lr & sp
2394
2395 if (!save_vectors) {
2396 for (int i = 30; i >= 0; i -= 2)
2397 stpd(as_FloatRegister(i), as_FloatRegister(i+1),
2398 Address(pre(sp, -2 * wordSize)));
2399 } else {
2400 for (int i = 30; i >= 0; i -= 2)
2401 stpq(as_FloatRegister(i), as_FloatRegister(i+1),
2402 Address(pre(sp, -4 * wordSize)));
2403 }
2404 }
2405
2406 void MacroAssembler::pop_CPU_state(bool restore_vectors) {
2407 if (!restore_vectors) {
2408 for (int i = 0; i < 32; i += 2)
2409 ldpd(as_FloatRegister(i), as_FloatRegister(i+1),
2410 Address(post(sp, 2 * wordSize)));
2411 } else {
2412 for (int i = 0; i < 32; i += 2)
2413 ldpq(as_FloatRegister(i), as_FloatRegister(i+1),
2414 Address(post(sp, 4 * wordSize)));
2415 }
2416
2417 pop(0x3fffffff, sp); // integer registers except lr & sp
2418 }
2419
2420 /**
2421 * Helpers for multiply_to_len().
2422 */
2423 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
2424 Register src1, Register src2) {
2425 adds(dest_lo, dest_lo, src1);
2426 adc(dest_hi, dest_hi, zr);
2427 adds(dest_lo, dest_lo, src2);
2428 adc(final_dest_hi, dest_hi, zr);
2429 }
2430
2431 // Generate an address from (r + r1 extend offset). "size" is the
2432 // size of the operand. The result may be in rscratch2.
2433 Address MacroAssembler::offsetted_address(Register r, Register r1,
2434 Address::extend ext, int offset, int size) {
2435 if (offset || (ext.shift() % size != 0)) {
2436 lea(rscratch2, Address(r, r1, ext));
2437 return Address(rscratch2, offset);
2438 } else {
2439 return Address(r, r1, ext);
2440 }
2441 }
2442
2443 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
2444 {
2445 assert(offset >= 0, "spill to negative address?");
2446 // Offset reachable ?
2447 // Not aligned - 9 bits signed offset
2448 // Aligned - 12 bits unsigned offset shifted
2449 Register base = sp;
2450 if ((offset & (size-1)) && offset >= (1<<8)) {
2451 add(tmp, base, offset & ((1<<12)-1));
2452 base = tmp;
2453 offset &= -1<<12;
2454 }
2455
2456 if (offset >= (1<<12) * size) {
2457 add(tmp, base, offset & (((1<<12)-1)<<12));
2458 base = tmp;
2459 offset &= ~(((1<<12)-1)<<12);
2460 }
2461
2462 return Address(base, offset);
2463 }
2464
2465 /**
2466 * Multiply 64 bit by 64 bit first loop.
2467 */
2468 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
2469 Register y, Register y_idx, Register z,
2470 Register carry, Register product,
2471 Register idx, Register kdx) {
2472 //
2473 // jlong carry, x[], y[], z[];
2474 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
2475 // huge_128 product = y[idx] * x[xstart] + carry;
2476 // z[kdx] = (jlong)product;
2477 // carry = (jlong)(product >>> 64);
2478 // }
2479 // z[xstart] = carry;
2480 //
2481
2482 Label L_first_loop, L_first_loop_exit;
2483 Label L_one_x, L_one_y, L_multiply;
2484
2485 subsw(xstart, xstart, 1);
2486 br(Assembler::MI, L_one_x);
2487
2488 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
2489 ldr(x_xstart, Address(rscratch1));
2490 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
2491
2492 bind(L_first_loop);
2493 subsw(idx, idx, 1);
2494 br(Assembler::MI, L_first_loop_exit);
2495 subsw(idx, idx, 1);
2496 br(Assembler::MI, L_one_y);
2497 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2498 ldr(y_idx, Address(rscratch1));
2499 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
2500 bind(L_multiply);
2501
2502 // AArch64 has a multiply-accumulate instruction that we can't use
2503 // here because it has no way to process carries, so we have to use
2504 // separate add and adc instructions. Bah.
2505 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
2506 mul(product, x_xstart, y_idx);
2507 adds(product, product, carry);
2508 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
2509
2510 subw(kdx, kdx, 2);
2511 ror(product, product, 32); // back to big-endian
2512 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
2513
2514 b(L_first_loop);
2515
2516 bind(L_one_y);
2517 ldrw(y_idx, Address(y, 0));
2518 b(L_multiply);
2519
2520 bind(L_one_x);
2521 ldrw(x_xstart, Address(x, 0));
2522 b(L_first_loop);
2523
2524 bind(L_first_loop_exit);
2525 }
2526
2527 /**
2528 * Multiply 128 bit by 128. Unrolled inner loop.
2529 *
2530 */
2531 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
2532 Register carry, Register carry2,
2533 Register idx, Register jdx,
2534 Register yz_idx1, Register yz_idx2,
2535 Register tmp, Register tmp3, Register tmp4,
2536 Register tmp6, Register product_hi) {
2537
2538 // jlong carry, x[], y[], z[];
2539 // int kdx = ystart+1;
2540 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
2541 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
2542 // jlong carry2 = (jlong)(tmp3 >>> 64);
2543 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
2544 // carry = (jlong)(tmp4 >>> 64);
2545 // z[kdx+idx+1] = (jlong)tmp3;
2546 // z[kdx+idx] = (jlong)tmp4;
2547 // }
2548 // idx += 2;
2549 // if (idx > 0) {
2550 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
2551 // z[kdx+idx] = (jlong)yz_idx1;
2552 // carry = (jlong)(yz_idx1 >>> 64);
2553 // }
2554 //
2555
2556 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
2557
2558 lsrw(jdx, idx, 2);
2559
2560 bind(L_third_loop);
2561
2562 subsw(jdx, jdx, 1);
2563 br(Assembler::MI, L_third_loop_exit);
2564 subw(idx, idx, 4);
2565
2566 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2567
2568 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
2569
2570 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2571
2572 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
2573 ror(yz_idx2, yz_idx2, 32);
2574
2575 ldp(rscratch2, rscratch1, Address(tmp6, 0));
2576
2577 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
2578 umulh(tmp4, product_hi, yz_idx1);
2579
2580 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
2581 ror(rscratch2, rscratch2, 32);
2582
2583 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
2584 umulh(carry2, product_hi, yz_idx2);
2585
2586 // propagate sum of both multiplications into carry:tmp4:tmp3
2587 adds(tmp3, tmp3, carry);
2588 adc(tmp4, tmp4, zr);
2589 adds(tmp3, tmp3, rscratch1);
2590 adcs(tmp4, tmp4, tmp);
2591 adc(carry, carry2, zr);
2592 adds(tmp4, tmp4, rscratch2);
2593 adc(carry, carry, zr);
2594
2595 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
2596 ror(tmp4, tmp4, 32);
2597 stp(tmp4, tmp3, Address(tmp6, 0));
2598
2599 b(L_third_loop);
2600 bind (L_third_loop_exit);
2601
2602 andw (idx, idx, 0x3);
2603 cbz(idx, L_post_third_loop_done);
2604
2605 Label L_check_1;
2606 subsw(idx, idx, 2);
2607 br(Assembler::MI, L_check_1);
2608
2609 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2610 ldr(yz_idx1, Address(rscratch1, 0));
2611 ror(yz_idx1, yz_idx1, 32);
2612 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
2613 umulh(tmp4, product_hi, yz_idx1);
2614 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2615 ldr(yz_idx2, Address(rscratch1, 0));
2616 ror(yz_idx2, yz_idx2, 32);
2617
2618 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
2619
2620 ror(tmp3, tmp3, 32);
2621 str(tmp3, Address(rscratch1, 0));
2622
2623 bind (L_check_1);
2624
2625 andw (idx, idx, 0x1);
2626 subsw(idx, idx, 1);
2627 br(Assembler::MI, L_post_third_loop_done);
2628 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2629 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
2630 umulh(carry2, tmp4, product_hi);
2631 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2632
2633 add2_with_carry(carry2, tmp3, tmp4, carry);
2634
2635 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2636 extr(carry, carry2, tmp3, 32);
2637
2638 bind(L_post_third_loop_done);
2639 }
2640
2641 /**
2642 * Code for BigInteger::multiplyToLen() instrinsic.
2643 *
2644 * r0: x
2645 * r1: xlen
2646 * r2: y
2647 * r3: ylen
2648 * r4: z
2649 * r5: zlen
2650 * r10: tmp1
2651 * r11: tmp2
2652 * r12: tmp3
2653 * r13: tmp4
2654 * r14: tmp5
2655 * r15: tmp6
2656 * r16: tmp7
2657 *
2658 */
2659 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
2660 Register z, Register zlen,
2661 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
2662 Register tmp5, Register tmp6, Register product_hi) {
2663
2664 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6);
2665
2666 const Register idx = tmp1;
2667 const Register kdx = tmp2;
2668 const Register xstart = tmp3;
2669
2670 const Register y_idx = tmp4;
2671 const Register carry = tmp5;
2672 const Register product = xlen;
2673 const Register x_xstart = zlen; // reuse register
2674
2675 // First Loop.
2676 //
2677 // final static long LONG_MASK = 0xffffffffL;
2678 // int xstart = xlen - 1;
2679 // int ystart = ylen - 1;
2680 // long carry = 0;
2681 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
2682 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
2683 // z[kdx] = (int)product;
2684 // carry = product >>> 32;
2685 // }
2686 // z[xstart] = (int)carry;
2687 //
2688
2689 movw(idx, ylen); // idx = ylen;
2690 movw(kdx, zlen); // kdx = xlen+ylen;
2691 mov(carry, zr); // carry = 0;
2692
2693 Label L_done;
2694
2695 movw(xstart, xlen);
2696 subsw(xstart, xstart, 1);
2697 br(Assembler::MI, L_done);
2698
2699 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
2700
2701 Label L_second_loop;
2702 cbzw(kdx, L_second_loop);
2703
2704 Label L_carry;
2705 subw(kdx, kdx, 1);
2706 cbzw(kdx, L_carry);
2707
2708 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
2709 lsr(carry, carry, 32);
2710 subw(kdx, kdx, 1);
2711
2712 bind(L_carry);
2713 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
2714
2715 // Second and third (nested) loops.
2716 //
2717 // for (int i = xstart-1; i >= 0; i--) { // Second loop
2718 // carry = 0;
2719 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
2720 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
2721 // (z[k] & LONG_MASK) + carry;
2722 // z[k] = (int)product;
2723 // carry = product >>> 32;
2724 // }
2725 // z[i] = (int)carry;
2726 // }
2727 //
2728 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
2729
2730 const Register jdx = tmp1;
2731
2732 bind(L_second_loop);
2733 mov(carry, zr); // carry = 0;
2734 movw(jdx, ylen); // j = ystart+1
2735
2736 subsw(xstart, xstart, 1); // i = xstart-1;
2737 br(Assembler::MI, L_done);
2738
2739 str(z, Address(pre(sp, -4 * wordSize)));
2740
2741 Label L_last_x;
2742 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
2743 subsw(xstart, xstart, 1); // i = xstart-1;
2744 br(Assembler::MI, L_last_x);
2745
2746 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
2747 ldr(product_hi, Address(rscratch1));
2748 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
2749
2750 Label L_third_loop_prologue;
2751 bind(L_third_loop_prologue);
2752
2753 str(ylen, Address(sp, wordSize));
2754 stp(x, xstart, Address(sp, 2 * wordSize));
2755 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
2756 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
2757 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
2758 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
2759
2760 addw(tmp3, xlen, 1);
2761 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
2762 subsw(tmp3, tmp3, 1);
2763 br(Assembler::MI, L_done);
2764
2765 lsr(carry, carry, 32);
2766 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
2767 b(L_second_loop);
2768
2769 // Next infrequent code is moved outside loops.
2770 bind(L_last_x);
2771 ldrw(product_hi, Address(x, 0));
2772 b(L_third_loop_prologue);
2773
2774 bind(L_done);
2775 }
2776
2777 /**
2778 * Emits code to update CRC-32 with a byte value according to constants in table
2779 *
2780 * @param [in,out]crc Register containing the crc.
2781 * @param [in]val Register containing the byte to fold into the CRC.
2782 * @param [in]table Register containing the table of crc constants.
2783 *
2784 * uint32_t crc;
2785 * val = crc_table[(val ^ crc) & 0xFF];
2786 * crc = val ^ (crc >> 8);
2787 *
2788 */
2789 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
2790 eor(val, val, crc);
2791 andr(val, val, 0xff);
2792 ldrw(val, Address(table, val, Address::lsl(2)));
2793 eor(crc, val, crc, Assembler::LSR, 8);
2794 }
2795
2796 /**
2797 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
2798 *
2799 * @param [in,out]crc Register containing the crc.
2800 * @param [in]v Register containing the 32-bit to fold into the CRC.
2801 * @param [in]table0 Register containing table 0 of crc constants.
2802 * @param [in]table1 Register containing table 1 of crc constants.
2803 * @param [in]table2 Register containing table 2 of crc constants.
2804 * @param [in]table3 Register containing table 3 of crc constants.
2805 *
2806 * uint32_t crc;
2807 * v = crc ^ v
2808 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
2809 *
2810 */
2811 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
2812 Register table0, Register table1, Register table2, Register table3,
2813 bool upper) {
2814 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
2815 uxtb(tmp, v);
2816 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
2817 ubfx(tmp, v, 8, 8);
2818 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
2819 eor(crc, crc, tmp);
2820 ubfx(tmp, v, 16, 8);
2821 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
2822 eor(crc, crc, tmp);
2823 ubfx(tmp, v, 24, 8);
2824 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
2825 eor(crc, crc, tmp);
2826 }
2827
2828 /**
2829 * @param crc register containing existing CRC (32-bit)
2830 * @param buf register pointing to input byte buffer (byte*)
2831 * @param len register containing number of bytes
2832 * @param table register that will contain address of CRC table
2833 * @param tmp scratch register
2834 */
2835 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
2836 Register table0, Register table1, Register table2, Register table3,
2837 Register tmp, Register tmp2, Register tmp3) {
2838 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
2839 unsigned long offset;
2840
2841 ornw(crc, zr, crc);
2842
2843 if (UseCRC32) {
2844 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop;
2845
2846 subs(len, len, 64);
2847 br(Assembler::GE, CRC_by64_loop);
2848 adds(len, len, 64-4);
2849 br(Assembler::GE, CRC_by4_loop);
2850 adds(len, len, 4);
2851 br(Assembler::GT, CRC_by1_loop);
2852 b(L_exit);
2853
2854 BIND(CRC_by4_loop);
2855 ldrw(tmp, Address(post(buf, 4)));
2856 subs(len, len, 4);
2857 crc32w(crc, crc, tmp);
2858 br(Assembler::GE, CRC_by4_loop);
2859 adds(len, len, 4);
2860 br(Assembler::LE, L_exit);
2861 BIND(CRC_by1_loop);
2862 ldrb(tmp, Address(post(buf, 1)));
2863 subs(len, len, 1);
2864 crc32b(crc, crc, tmp);
2865 br(Assembler::GT, CRC_by1_loop);
2866 b(L_exit);
2867
2868 align(CodeEntryAlignment);
2869 BIND(CRC_by64_loop);
2870 subs(len, len, 64);
2871 ldp(tmp, tmp3, Address(post(buf, 16)));
2872 crc32x(crc, crc, tmp);
2873 crc32x(crc, crc, tmp3);
2874 ldp(tmp, tmp3, Address(post(buf, 16)));
2875 crc32x(crc, crc, tmp);
2876 crc32x(crc, crc, tmp3);
2877 ldp(tmp, tmp3, Address(post(buf, 16)));
2878 crc32x(crc, crc, tmp);
2879 crc32x(crc, crc, tmp3);
2880 ldp(tmp, tmp3, Address(post(buf, 16)));
2881 crc32x(crc, crc, tmp);
2882 crc32x(crc, crc, tmp3);
2883 br(Assembler::GE, CRC_by64_loop);
2884 adds(len, len, 64-4);
2885 br(Assembler::GE, CRC_by4_loop);
2886 adds(len, len, 4);
2887 br(Assembler::GT, CRC_by1_loop);
2888 BIND(L_exit);
2889 ornw(crc, zr, crc);
2890 return;
2891 }
2892
2893 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2894 if (offset) add(table0, table0, offset);
2895 add(table1, table0, 1*256*sizeof(juint));
2896 add(table2, table0, 2*256*sizeof(juint));
2897 add(table3, table0, 3*256*sizeof(juint));
2898
2899 if (UseNeon) {
2900 cmp(len, 64);
2901 br(Assembler::LT, L_by16);
2902 eor(v16, T16B, v16, v16);
2903
2904 Label L_fold;
2905
2906 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
2907
2908 ld1(v0, v1, T2D, post(buf, 32));
2909 ld1r(v4, T2D, post(tmp, 8));
2910 ld1r(v5, T2D, post(tmp, 8));
2911 ld1r(v6, T2D, post(tmp, 8));
2912 ld1r(v7, T2D, post(tmp, 8));
2913 mov(v16, T4S, 0, crc);
2914
2915 eor(v0, T16B, v0, v16);
2916 sub(len, len, 64);
2917
2918 BIND(L_fold);
2919 pmull(v22, T8H, v0, v5, T8B);
2920 pmull(v20, T8H, v0, v7, T8B);
2921 pmull(v23, T8H, v0, v4, T8B);
2922 pmull(v21, T8H, v0, v6, T8B);
2923
2924 pmull2(v18, T8H, v0, v5, T16B);
2925 pmull2(v16, T8H, v0, v7, T16B);
2926 pmull2(v19, T8H, v0, v4, T16B);
2927 pmull2(v17, T8H, v0, v6, T16B);
2928
2929 uzp1(v24, v20, v22, T8H);
2930 uzp2(v25, v20, v22, T8H);
2931 eor(v20, T16B, v24, v25);
2932
2933 uzp1(v26, v16, v18, T8H);
2934 uzp2(v27, v16, v18, T8H);
2935 eor(v16, T16B, v26, v27);
2936
2937 ushll2(v22, T4S, v20, T8H, 8);
2938 ushll(v20, T4S, v20, T4H, 8);
2939
2940 ushll2(v18, T4S, v16, T8H, 8);
2941 ushll(v16, T4S, v16, T4H, 8);
2942
2943 eor(v22, T16B, v23, v22);
2944 eor(v18, T16B, v19, v18);
2945 eor(v20, T16B, v21, v20);
2946 eor(v16, T16B, v17, v16);
2947
2948 uzp1(v17, v16, v20, T2D);
2949 uzp2(v21, v16, v20, T2D);
2950 eor(v17, T16B, v17, v21);
2951
2952 ushll2(v20, T2D, v17, T4S, 16);
2953 ushll(v16, T2D, v17, T2S, 16);
2954
2955 eor(v20, T16B, v20, v22);
2956 eor(v16, T16B, v16, v18);
2957
2958 uzp1(v17, v20, v16, T2D);
2959 uzp2(v21, v20, v16, T2D);
2960 eor(v28, T16B, v17, v21);
2961
2962 pmull(v22, T8H, v1, v5, T8B);
2963 pmull(v20, T8H, v1, v7, T8B);
2964 pmull(v23, T8H, v1, v4, T8B);
2965 pmull(v21, T8H, v1, v6, T8B);
2966
2967 pmull2(v18, T8H, v1, v5, T16B);
2968 pmull2(v16, T8H, v1, v7, T16B);
2969 pmull2(v19, T8H, v1, v4, T16B);
2970 pmull2(v17, T8H, v1, v6, T16B);
2971
2972 ld1(v0, v1, T2D, post(buf, 32));
2973
2974 uzp1(v24, v20, v22, T8H);
2975 uzp2(v25, v20, v22, T8H);
2976 eor(v20, T16B, v24, v25);
2977
2978 uzp1(v26, v16, v18, T8H);
2979 uzp2(v27, v16, v18, T8H);
2980 eor(v16, T16B, v26, v27);
2981
2982 ushll2(v22, T4S, v20, T8H, 8);
2983 ushll(v20, T4S, v20, T4H, 8);
2984
2985 ushll2(v18, T4S, v16, T8H, 8);
2986 ushll(v16, T4S, v16, T4H, 8);
2987
2988 eor(v22, T16B, v23, v22);
2989 eor(v18, T16B, v19, v18);
2990 eor(v20, T16B, v21, v20);
2991 eor(v16, T16B, v17, v16);
2992
2993 uzp1(v17, v16, v20, T2D);
2994 uzp2(v21, v16, v20, T2D);
2995 eor(v16, T16B, v17, v21);
2996
2997 ushll2(v20, T2D, v16, T4S, 16);
2998 ushll(v16, T2D, v16, T2S, 16);
2999
3000 eor(v20, T16B, v22, v20);
3001 eor(v16, T16B, v16, v18);
3002
3003 uzp1(v17, v20, v16, T2D);
3004 uzp2(v21, v20, v16, T2D);
3005 eor(v20, T16B, v17, v21);
3006
3007 shl(v16, T2D, v28, 1);
3008 shl(v17, T2D, v20, 1);
3009
3010 eor(v0, T16B, v0, v16);
3011 eor(v1, T16B, v1, v17);
3012
3013 subs(len, len, 32);
3014 br(Assembler::GE, L_fold);
3015
3016 mov(crc, 0);
3017 mov(tmp, v0, T1D, 0);
3018 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3019 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3020 mov(tmp, v0, T1D, 1);
3021 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3022 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3023 mov(tmp, v1, T1D, 0);
3024 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3025 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3026 mov(tmp, v1, T1D, 1);
3027 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3028 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3029
3030 add(len, len, 32);
3031 }
3032
3033 BIND(L_by16);
3034 subs(len, len, 16);
3035 br(Assembler::GE, L_by16_loop);
3036 adds(len, len, 16-4);
3037 br(Assembler::GE, L_by4_loop);
3038 adds(len, len, 4);
3039 br(Assembler::GT, L_by1_loop);
3040 b(L_exit);
3041
3042 BIND(L_by4_loop);
3043 ldrw(tmp, Address(post(buf, 4)));
3044 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
3045 subs(len, len, 4);
3046 br(Assembler::GE, L_by4_loop);
3047 adds(len, len, 4);
3048 br(Assembler::LE, L_exit);
3049 BIND(L_by1_loop);
3050 subs(len, len, 1);
3051 ldrb(tmp, Address(post(buf, 1)));
3052 update_byte_crc32(crc, tmp, table0);
3053 br(Assembler::GT, L_by1_loop);
3054 b(L_exit);
3055
3056 align(CodeEntryAlignment);
3057 BIND(L_by16_loop);
3058 subs(len, len, 16);
3059 ldp(tmp, tmp3, Address(post(buf, 16)));
3060 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3061 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3062 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
3063 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
3064 br(Assembler::GE, L_by16_loop);
3065 adds(len, len, 16-4);
3066 br(Assembler::GE, L_by4_loop);
3067 adds(len, len, 4);
3068 br(Assembler::GT, L_by1_loop);
3069 BIND(L_exit);
3070 ornw(crc, zr, crc);
3071 }
3072
3073 /**
3074 * @param crc register containing existing CRC (32-bit)
3075 * @param buf register pointing to input byte buffer (byte*)
3076 * @param len register containing number of bytes
3077 * @param table register that will contain address of CRC table
3078 * @param tmp scratch register
3079 */
3080 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
3081 Register table0, Register table1, Register table2, Register table3,
3082 Register tmp, Register tmp2, Register tmp3) {
3083 Label L_exit;
3084 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop;
3085
3086 subs(len, len, 64);
3087 br(Assembler::GE, CRC_by64_loop);
3088 adds(len, len, 64-4);
3089 br(Assembler::GE, CRC_by4_loop);
3090 adds(len, len, 4);
3091 br(Assembler::GT, CRC_by1_loop);
3092 b(L_exit);
3093
3094 BIND(CRC_by4_loop);
3095 ldrw(tmp, Address(post(buf, 4)));
3096 subs(len, len, 4);
3097 crc32cw(crc, crc, tmp);
3098 br(Assembler::GE, CRC_by4_loop);
3099 adds(len, len, 4);
3100 br(Assembler::LE, L_exit);
3101 BIND(CRC_by1_loop);
3102 ldrb(tmp, Address(post(buf, 1)));
3103 subs(len, len, 1);
3104 crc32cb(crc, crc, tmp);
3105 br(Assembler::GT, CRC_by1_loop);
3106 b(L_exit);
3107
3108 align(CodeEntryAlignment);
3109 BIND(CRC_by64_loop);
3110 subs(len, len, 64);
3111 ldp(tmp, tmp3, Address(post(buf, 16)));
3112 crc32cx(crc, crc, tmp);
3113 crc32cx(crc, crc, tmp3);
3114 ldp(tmp, tmp3, Address(post(buf, 16)));
3115 crc32cx(crc, crc, tmp);
3116 crc32cx(crc, crc, tmp3);
3117 ldp(tmp, tmp3, Address(post(buf, 16)));
3118 crc32cx(crc, crc, tmp);
3119 crc32cx(crc, crc, tmp3);
3120 ldp(tmp, tmp3, Address(post(buf, 16)));
3121 crc32cx(crc, crc, tmp);
3122 crc32cx(crc, crc, tmp3);
3123 br(Assembler::GE, CRC_by64_loop);
3124 adds(len, len, 64-4);
3125 br(Assembler::GE, CRC_by4_loop);
3126 adds(len, len, 4);
3127 br(Assembler::GT, CRC_by1_loop);
3128 BIND(L_exit);
3129 return;
3130 }
3131
3132 SkipIfEqual::SkipIfEqual(
3133 MacroAssembler* masm, const bool* flag_addr, bool value) {
3134 _masm = masm;
3135 unsigned long offset;
3136 _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset);
3137 _masm->ldrb(rscratch1, Address(rscratch1, offset));
3138 _masm->cbzw(rscratch1, _label);
3139 }
3140
3141 SkipIfEqual::~SkipIfEqual() {
3142 _masm->bind(_label);
3143 }
3144
3145 void MacroAssembler::addptr(const Address &dst, int32_t src) {
3146 Address adr;
3147 switch(dst.getMode()) {
3148 case Address::base_plus_offset:
3149 // This is the expected mode, although we allow all the other
3150 // forms below.
3151 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
3152 break;
3153 default:
3154 lea(rscratch2, dst);
3155 adr = Address(rscratch2);
3156 break;
3157 }
3158 ldr(rscratch1, adr);
3159 add(rscratch1, rscratch1, src);
3160 str(rscratch1, adr);
3161 }
3162
3163 void MacroAssembler::cmpptr(Register src1, Address src2) {
3164 unsigned long offset;
3165 adrp(rscratch1, src2, offset);
3166 ldr(rscratch1, Address(rscratch1, offset));
3167 cmp(src1, rscratch1);
3168 }
3169
3170 void MacroAssembler::store_check(Register obj, Address dst) {
3171 store_check(obj);
3172 }
3173
3174 void MacroAssembler::store_check(Register obj) {
3175 // Does a store check for the oop in register obj. The content of
3176 // register obj is destroyed afterwards.
3177
3178 BarrierSet* bs = Universe::heap()->barrier_set();
3179 assert(bs->kind() == BarrierSet::CardTableForRS ||
3180 bs->kind() == BarrierSet::CardTableExtension,
3181 "Wrong barrier set kind");
3182
3183 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
3184 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3185
3186 lsr(obj, obj, CardTableModRefBS::card_shift);
3187
3188 assert(CardTableModRefBS::dirty_card_val() == 0, "must be");
3189
3190 load_byte_map_base(rscratch1);
3191
3192 if (UseCondCardMark) {
3193 Label L_already_dirty;
3194 membar(StoreLoad);
3195 ldrb(rscratch2, Address(obj, rscratch1));
3196 cbz(rscratch2, L_already_dirty);
3197 strb(zr, Address(obj, rscratch1));
3198 bind(L_already_dirty);
3199 } else {
3200 if (UseConcMarkSweepGC && CMSPrecleaningEnabled) {
3201 membar(StoreStore);
3202 }
3203 strb(zr, Address(obj, rscratch1));
3204 }
3205 }
3206
3207 void MacroAssembler::load_klass(Register dst, Register src) {
3208 if (UseCompressedClassPointers) {
3209 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3210 decode_klass_not_null(dst);
3211 } else {
3212 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3213 }
3214 }
3215
3216 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
3217 if (UseCompressedClassPointers) {
3218 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3219 if (Universe::narrow_klass_base() == NULL) {
3220 cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift());
3221 return;
3222 } else if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3223 && Universe::narrow_klass_shift() == 0) {
3224 // Only the bottom 32 bits matter
3225 cmpw(trial_klass, tmp);
3226 return;
3227 }
3228 decode_klass_not_null(tmp);
3229 } else {
3230 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3231 }
3232 cmp(trial_klass, tmp);
3233 }
3234
3235 void MacroAssembler::load_prototype_header(Register dst, Register src) {
3236 load_klass(dst, src);
3237 ldr(dst, Address(dst, Klass::prototype_header_offset()));
3238 }
3239
3240 void MacroAssembler::store_klass(Register dst, Register src) {
3241 // FIXME: Should this be a store release? concurrent gcs assumes
3242 // klass length is valid if klass field is not null.
3243 if (UseCompressedClassPointers) {
3244 encode_klass_not_null(src);
3245 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3246 } else {
3247 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3248 }
3249 }
3250
3251 void MacroAssembler::store_klass_gap(Register dst, Register src) {
3252 if (UseCompressedClassPointers) {
3253 // Store to klass gap in destination
3254 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
3255 }
3256 }
3257
3258 // Algorithm must match oop.inline.hpp encode_heap_oop.
3259 void MacroAssembler::encode_heap_oop(Register d, Register s) {
3260 #ifdef ASSERT
3261 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
3262 #endif
3263 verify_oop(s, "broken oop in encode_heap_oop");
3264 if (Universe::narrow_oop_base() == NULL) {
3265 if (Universe::narrow_oop_shift() != 0) {
3266 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3267 lsr(d, s, LogMinObjAlignmentInBytes);
3268 } else {
3269 mov(d, s);
3270 }
3271 } else {
3272 subs(d, s, rheapbase);
3273 csel(d, d, zr, Assembler::HS);
3274 lsr(d, d, LogMinObjAlignmentInBytes);
3275
3276 /* Old algorithm: is this any worse?
3277 Label nonnull;
3278 cbnz(r, nonnull);
3279 sub(r, r, rheapbase);
3280 bind(nonnull);
3281 lsr(r, r, LogMinObjAlignmentInBytes);
3282 */
3283 }
3284 }
3285
3286 void MacroAssembler::encode_heap_oop_not_null(Register r) {
3287 #ifdef ASSERT
3288 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
3289 if (CheckCompressedOops) {
3290 Label ok;
3291 cbnz(r, ok);
3292 stop("null oop passed to encode_heap_oop_not_null");
3293 bind(ok);
3294 }
3295 #endif
3296 verify_oop(r, "broken oop in encode_heap_oop_not_null");
3297 if (Universe::narrow_oop_base() != NULL) {
3298 sub(r, r, rheapbase);
3299 }
3300 if (Universe::narrow_oop_shift() != 0) {
3301 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3302 lsr(r, r, LogMinObjAlignmentInBytes);
3303 }
3304 }
3305
3306 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
3307 #ifdef ASSERT
3308 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
3309 if (CheckCompressedOops) {
3310 Label ok;
3311 cbnz(src, ok);
3312 stop("null oop passed to encode_heap_oop_not_null2");
3313 bind(ok);
3314 }
3315 #endif
3316 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
3317
3318 Register data = src;
3319 if (Universe::narrow_oop_base() != NULL) {
3320 sub(dst, src, rheapbase);
3321 data = dst;
3322 }
3323 if (Universe::narrow_oop_shift() != 0) {
3324 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3325 lsr(dst, data, LogMinObjAlignmentInBytes);
3326 data = dst;
3327 }
3328 if (data == src)
3329 mov(dst, src);
3330 }
3331
3332 void MacroAssembler::decode_heap_oop(Register d, Register s) {
3333 #ifdef ASSERT
3334 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
3335 #endif
3336 if (Universe::narrow_oop_base() == NULL) {
3337 if (Universe::narrow_oop_shift() != 0 || d != s) {
3338 lsl(d, s, Universe::narrow_oop_shift());
3339 }
3340 } else {
3341 Label done;
3342 if (d != s)
3343 mov(d, s);
3344 cbz(s, done);
3345 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
3346 bind(done);
3347 }
3348 verify_oop(d, "broken oop in decode_heap_oop");
3349 }
3350
3351 void MacroAssembler::decode_heap_oop_not_null(Register r) {
3352 assert (UseCompressedOops, "should only be used for compressed headers");
3353 assert (Universe::heap() != NULL, "java heap should be initialized");
3354 // Cannot assert, unverified entry point counts instructions (see .ad file)
3355 // vtableStubs also counts instructions in pd_code_size_limit.
3356 // Also do not verify_oop as this is called by verify_oop.
3357 if (Universe::narrow_oop_shift() != 0) {
3358 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3359 if (Universe::narrow_oop_base() != NULL) {
3360 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
3361 } else {
3362 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
3363 }
3364 } else {
3365 assert (Universe::narrow_oop_base() == NULL, "sanity");
3366 }
3367 }
3368
3369 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
3370 assert (UseCompressedOops, "should only be used for compressed headers");
3371 assert (Universe::heap() != NULL, "java heap should be initialized");
3372 // Cannot assert, unverified entry point counts instructions (see .ad file)
3373 // vtableStubs also counts instructions in pd_code_size_limit.
3374 // Also do not verify_oop as this is called by verify_oop.
3375 if (Universe::narrow_oop_shift() != 0) {
3376 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3377 if (Universe::narrow_oop_base() != NULL) {
3378 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
3379 } else {
3380 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
3381 }
3382 } else {
3383 assert (Universe::narrow_oop_base() == NULL, "sanity");
3384 if (dst != src) {
3385 mov(dst, src);
3386 }
3387 }
3388 }
3389
3390 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
3391 if (Universe::narrow_klass_base() == NULL) {
3392 if (Universe::narrow_klass_shift() != 0) {
3393 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3394 lsr(dst, src, LogKlassAlignmentInBytes);
3395 } else {
3396 if (dst != src) mov(dst, src);
3397 }
3398 return;
3399 }
3400
3401 if (use_XOR_for_compressed_class_base) {
3402 if (Universe::narrow_klass_shift() != 0) {
3403 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3404 lsr(dst, dst, LogKlassAlignmentInBytes);
3405 } else {
3406 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3407 }
3408 return;
3409 }
3410
3411 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3412 && Universe::narrow_klass_shift() == 0) {
3413 movw(dst, src);
3414 return;
3415 }
3416
3417 #ifdef ASSERT
3418 verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?");
3419 #endif
3420
3421 Register rbase = dst;
3422 if (dst == src) rbase = rheapbase;
3423 mov(rbase, (uint64_t)Universe::narrow_klass_base());
3424 sub(dst, src, rbase);
3425 if (Universe::narrow_klass_shift() != 0) {
3426 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3427 lsr(dst, dst, LogKlassAlignmentInBytes);
3428 }
3429 if (dst == src) reinit_heapbase();
3430 }
3431
3432 void MacroAssembler::encode_klass_not_null(Register r) {
3433 encode_klass_not_null(r, r);
3434 }
3435
3436 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
3437 Register rbase = dst;
3438 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3439
3440 if (Universe::narrow_klass_base() == NULL) {
3441 if (Universe::narrow_klass_shift() != 0) {
3442 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3443 lsl(dst, src, LogKlassAlignmentInBytes);
3444 } else {
3445 if (dst != src) mov(dst, src);
3446 }
3447 return;
3448 }
3449
3450 if (use_XOR_for_compressed_class_base) {
3451 if (Universe::narrow_klass_shift() != 0) {
3452 lsl(dst, src, LogKlassAlignmentInBytes);
3453 eor(dst, dst, (uint64_t)Universe::narrow_klass_base());
3454 } else {
3455 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3456 }
3457 return;
3458 }
3459
3460 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3461 && Universe::narrow_klass_shift() == 0) {
3462 if (dst != src)
3463 movw(dst, src);
3464 movk(dst, (uint64_t)Universe::narrow_klass_base() >> 32, 32);
3465 return;
3466 }
3467
3468 // Cannot assert, unverified entry point counts instructions (see .ad file)
3469 // vtableStubs also counts instructions in pd_code_size_limit.
3470 // Also do not verify_oop as this is called by verify_oop.
3471 if (dst == src) rbase = rheapbase;
3472 mov(rbase, (uint64_t)Universe::narrow_klass_base());
3473 if (Universe::narrow_klass_shift() != 0) {
3474 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3475 add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes);
3476 } else {
3477 add(dst, rbase, src);
3478 }
3479 if (dst == src) reinit_heapbase();
3480 }
3481
3482 void MacroAssembler::decode_klass_not_null(Register r) {
3483 decode_klass_not_null(r, r);
3484 }
3485
3486 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
3487 assert (UseCompressedOops, "should only be used for compressed oops");
3488 assert (Universe::heap() != NULL, "java heap should be initialized");
3489 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
3490
3491 int oop_index = oop_recorder()->find_index(obj);
3492 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop");
3493
3494 InstructionMark im(this);
3495 RelocationHolder rspec = oop_Relocation::spec(oop_index);
3496 code_section()->relocate(inst_mark(), rspec);
3497 movz(dst, 0xDEAD, 16);
3498 movk(dst, 0xBEEF);
3499 }
3500
3501 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
3502 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3503 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
3504 int index = oop_recorder()->find_index(k);
3505 assert(! Universe::heap()->is_in_reserved(k), "should not be an oop");
3506
3507 InstructionMark im(this);
3508 RelocationHolder rspec = metadata_Relocation::spec(index);
3509 code_section()->relocate(inst_mark(), rspec);
3510 narrowKlass nk = Klass::encode_klass(k);
3511 movz(dst, (nk >> 16), 16);
3512 movk(dst, nk & 0xffff);
3513 }
3514
3515 void MacroAssembler::load_heap_oop(Register dst, Address src)
3516 {
3517 if (UseCompressedOops) {
3518 ldrw(dst, src);
3519 decode_heap_oop(dst);
3520 } else {
3521 ldr(dst, src);
3522 }
3523 }
3524
3525 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src)
3526 {
3527 if (UseCompressedOops) {
3528 ldrw(dst, src);
3529 decode_heap_oop_not_null(dst);
3530 } else {
3531 ldr(dst, src);
3532 }
3533 }
3534
3535 void MacroAssembler::store_heap_oop(Address dst, Register src) {
3536 if (UseCompressedOops) {
3537 assert(!dst.uses(src), "not enough registers");
3538 encode_heap_oop(src);
3539 strw(src, dst);
3540 } else
3541 str(src, dst);
3542 }
3543
3544 // Used for storing NULLs.
3545 void MacroAssembler::store_heap_oop_null(Address dst) {
3546 if (UseCompressedOops) {
3547 strw(zr, dst);
3548 } else
3549 str(zr, dst);
3550 }
3551
3552 #if INCLUDE_ALL_GCS
3553 void MacroAssembler::g1_write_barrier_pre(Register obj,
3554 Register pre_val,
3555 Register thread,
3556 Register tmp,
3557 bool tosca_live,
3558 bool expand_call) {
3559 // If expand_call is true then we expand the call_VM_leaf macro
3560 // directly to skip generating the check by
3561 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
3562
3563 assert(thread == rthread, "must be");
3564
3565 Label done;
3566 Label runtime;
3567
3568 assert(pre_val != noreg, "check this code");
3569
3570 if (obj != noreg)
3571 assert_different_registers(obj, pre_val, tmp);
3572
3573 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
3574 SATBMarkQueue::byte_offset_of_active()));
3575 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
3576 SATBMarkQueue::byte_offset_of_index()));
3577 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
3578 SATBMarkQueue::byte_offset_of_buf()));
3579
3580
3581 // Is marking active?
3582 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
3583 ldrw(tmp, in_progress);
3584 } else {
3585 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
3586 ldrb(tmp, in_progress);
3587 }
3588 cbzw(tmp, done);
3589
3590 // Do we need to load the previous value?
3591 if (obj != noreg) {
3592 load_heap_oop(pre_val, Address(obj, 0));
3593 }
3594
3595 // Is the previous value null?
3596 cbz(pre_val, done);
3597
3598 // Can we store original value in the thread's buffer?
3599 // Is index == 0?
3600 // (The index field is typed as size_t.)
3601
3602 ldr(tmp, index); // tmp := *index_adr
3603 cbz(tmp, runtime); // tmp == 0?
3604 // If yes, goto runtime
3605
3606 sub(tmp, tmp, wordSize); // tmp := tmp - wordSize
3607 str(tmp, index); // *index_adr := tmp
3608 ldr(rscratch1, buffer);
3609 add(tmp, tmp, rscratch1); // tmp := tmp + *buffer_adr
3610
3611 // Record the previous value
3612 str(pre_val, Address(tmp, 0));
3613 b(done);
3614
3615 bind(runtime);
3616 // save the live input values
3617 push(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp);
3618
3619 // Calling the runtime using the regular call_VM_leaf mechanism generates
3620 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
3621 // that checks that the *(rfp+frame::interpreter_frame_last_sp) == NULL.
3622 //
3623 // If we care generating the pre-barrier without a frame (e.g. in the
3624 // intrinsified Reference.get() routine) then ebp might be pointing to
3625 // the caller frame and so this check will most likely fail at runtime.
3626 //
3627 // Expanding the call directly bypasses the generation of the check.
3628 // So when we do not have have a full interpreter frame on the stack
3629 // expand_call should be passed true.
3630
3631 if (expand_call) {
3632 assert(pre_val != c_rarg1, "smashed arg");
3633 pass_arg1(this, thread);
3634 pass_arg0(this, pre_val);
3635 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
3636 } else {
3637 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
3638 }
3639
3640 pop(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp);
3641
3642 bind(done);
3643 }
3644
3645 void MacroAssembler::g1_write_barrier_post(Register store_addr,
3646 Register new_val,
3647 Register thread,
3648 Register tmp,
3649 Register tmp2) {
3650 assert(thread == rthread, "must be");
3651
3652 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
3653 DirtyCardQueue::byte_offset_of_index()));
3654 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
3655 DirtyCardQueue::byte_offset_of_buf()));
3656
3657 BarrierSet* bs = Universe::heap()->barrier_set();
3658 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
3659 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3660
3661 Label done;
3662 Label runtime;
3663
3664 // Does store cross heap regions?
3665
3666 eor(tmp, store_addr, new_val);
3667 lsr(tmp, tmp, HeapRegion::LogOfHRGrainBytes);
3668 cbz(tmp, done);
3669
3670 // crosses regions, storing NULL?
3671
3672 cbz(new_val, done);
3673
3674 // storing region crossing non-NULL, is card already dirty?
3675
3676 ExternalAddress cardtable((address) ct->byte_map_base);
3677 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3678 const Register card_addr = tmp;
3679
3680 lsr(card_addr, store_addr, CardTableModRefBS::card_shift);
3681
3682 // get the address of the card
3683 load_byte_map_base(tmp2);
3684 add(card_addr, card_addr, tmp2);
3685 ldrb(tmp2, Address(card_addr));
3686 cmpw(tmp2, (int)G1SATBCardTableModRefBS::g1_young_card_val());
3687 br(Assembler::EQ, done);
3688
3689 assert((int)CardTableModRefBS::dirty_card_val() == 0, "must be 0");
3690
3691 membar(Assembler::StoreLoad);
3692
3693 ldrb(tmp2, Address(card_addr));
3694 cbzw(tmp2, done);
3695
3696 // storing a region crossing, non-NULL oop, card is clean.
3697 // dirty card and log.
3698
3699 strb(zr, Address(card_addr));
3700
3701 ldr(rscratch1, queue_index);
3702 cbz(rscratch1, runtime);
3703 sub(rscratch1, rscratch1, wordSize);
3704 str(rscratch1, queue_index);
3705
3706 ldr(tmp2, buffer);
3707 str(card_addr, Address(tmp2, rscratch1));
3708 b(done);
3709
3710 bind(runtime);
3711 // save the live input values
3712 push(store_addr->bit(true) | new_val->bit(true), sp);
3713 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
3714 pop(store_addr->bit(true) | new_val->bit(true), sp);
3715
3716 bind(done);
3717 }
3718
3719 #endif // INCLUDE_ALL_GCS
3720
3721 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
3722 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
3723 int index = oop_recorder()->allocate_metadata_index(obj);
3724 RelocationHolder rspec = metadata_Relocation::spec(index);
3725 return Address((address)obj, rspec);
3726 }
3727
3728 // Move an oop into a register. immediate is true if we want
3729 // immediate instrcutions, i.e. we are not going to patch this
3730 // instruction while the code is being executed by another thread. In
3731 // that case we can use move immediates rather than the constant pool.
3732 void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) {
3733 int oop_index;
3734 if (obj == NULL) {
3735 oop_index = oop_recorder()->allocate_oop_index(obj);
3736 } else {
3737 oop_index = oop_recorder()->find_index(obj);
3738 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop");
3739 }
3740 RelocationHolder rspec = oop_Relocation::spec(oop_index);
3741 if (! immediate) {
3742 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
3743 ldr_constant(dst, Address(dummy, rspec));
3744 } else
3745 mov(dst, Address((address)obj, rspec));
3746 }
3747
3748 // Move a metadata address into a register.
3749 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
3750 int oop_index;
3751 if (obj == NULL) {
3752 oop_index = oop_recorder()->allocate_metadata_index(obj);
3753 } else {
3754 oop_index = oop_recorder()->find_index(obj);
3755 }
3756 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
3757 mov(dst, Address((address)obj, rspec));
3758 }
3759
3760 Address MacroAssembler::constant_oop_address(jobject obj) {
3761 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
3762 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop");
3763 int oop_index = oop_recorder()->find_index(obj);
3764 return Address((address)obj, oop_Relocation::spec(oop_index));
3765 }
3766
3767 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3768 void MacroAssembler::tlab_allocate(Register obj,
3769 Register var_size_in_bytes,
3770 int con_size_in_bytes,
3771 Register t1,
3772 Register t2,
3773 Label& slow_case) {
3774 assert_different_registers(obj, t2);
3775 assert_different_registers(obj, var_size_in_bytes);
3776 Register end = t2;
3777
3778 // verify_tlab();
3779
3780 ldr(obj, Address(rthread, JavaThread::tlab_top_offset()));
3781 if (var_size_in_bytes == noreg) {
3782 lea(end, Address(obj, con_size_in_bytes));
3783 } else {
3784 lea(end, Address(obj, var_size_in_bytes));
3785 }
3786 ldr(rscratch1, Address(rthread, JavaThread::tlab_end_offset()));
3787 cmp(end, rscratch1);
3788 br(Assembler::HI, slow_case);
3789
3790 // update the tlab top pointer
3791 str(end, Address(rthread, JavaThread::tlab_top_offset()));
3792
3793 // recover var_size_in_bytes if necessary
3794 if (var_size_in_bytes == end) {
3795 sub(var_size_in_bytes, var_size_in_bytes, obj);
3796 }
3797 // verify_tlab();
3798 }
3799
3800 // Preserves r19, and r3.
3801 Register MacroAssembler::tlab_refill(Label& retry,
3802 Label& try_eden,
3803 Label& slow_case) {
3804 Register top = r0;
3805 Register t1 = r2;
3806 Register t2 = r4;
3807 assert_different_registers(top, rthread, t1, t2, /* preserve: */ r19, r3);
3808 Label do_refill, discard_tlab;
3809
3810 if (!Universe::heap()->supports_inline_contig_alloc()) {
3811 // No allocation in the shared eden.
3812 b(slow_case);
3813 }
3814
3815 ldr(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3816 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
3817
3818 // calculate amount of free space
3819 sub(t1, t1, top);
3820 lsr(t1, t1, LogHeapWordSize);
3821
3822 // Retain tlab and allocate object in shared space if
3823 // the amount free in the tlab is too large to discard.
3824
3825 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
3826 cmp(t1, rscratch1);
3827 br(Assembler::LE, discard_tlab);
3828
3829 // Retain
3830 // ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
3831 mov(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
3832 add(rscratch1, rscratch1, t2);
3833 str(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
3834
3835 if (TLABStats) {
3836 // increment number of slow_allocations
3837 addmw(Address(rthread, in_bytes(JavaThread::tlab_slow_allocations_offset())),
3838 1, rscratch1);
3839 }
3840 b(try_eden);
3841
3842 bind(discard_tlab);
3843 if (TLABStats) {
3844 // increment number of refills
3845 addmw(Address(rthread, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1,
3846 rscratch1);
3847 // accumulate wastage -- t1 is amount free in tlab
3848 addmw(Address(rthread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1,
3849 rscratch1);
3850 }
3851
3852 // if tlab is currently allocated (top or end != null) then
3853 // fill [top, end + alignment_reserve) with array object
3854 cbz(top, do_refill);
3855
3856 // set up the mark word
3857 mov(rscratch1, (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
3858 str(rscratch1, Address(top, oopDesc::mark_offset_in_bytes()));
3859 // set the length to the remaining space
3860 sub(t1, t1, typeArrayOopDesc::header_size(T_INT));
3861 add(t1, t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
3862 lsl(t1, t1, log2_intptr(HeapWordSize/sizeof(jint)));
3863 strw(t1, Address(top, arrayOopDesc::length_offset_in_bytes()));
3864 // set klass to intArrayKlass
3865 {
3866 unsigned long offset;
3867 // dubious reloc why not an oop reloc?
3868 adrp(rscratch1, ExternalAddress((address)Universe::intArrayKlassObj_addr()),
3869 offset);
3870 ldr(t1, Address(rscratch1, offset));
3871 }
3872 // store klass last. concurrent gcs assumes klass length is valid if
3873 // klass field is not null.
3874 store_klass(top, t1);
3875
3876 mov(t1, top);
3877 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
3878 sub(t1, t1, rscratch1);
3879 incr_allocated_bytes(rthread, t1, 0, rscratch1);
3880
3881 // refill the tlab with an eden allocation
3882 bind(do_refill);
3883 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_size_offset())));
3884 lsl(t1, t1, LogHeapWordSize);
3885 // allocate new tlab, address returned in top
3886 eden_allocate(top, t1, 0, t2, slow_case);
3887
3888 // Check that t1 was preserved in eden_allocate.
3889 #ifdef ASSERT
3890 if (UseTLAB) {
3891 Label ok;
3892 Register tsize = r4;
3893 assert_different_registers(tsize, rthread, t1);
3894 str(tsize, Address(pre(sp, -16)));
3895 ldr(tsize, Address(rthread, in_bytes(JavaThread::tlab_size_offset())));
3896 lsl(tsize, tsize, LogHeapWordSize);
3897 cmp(t1, tsize);
3898 br(Assembler::EQ, ok);
3899 STOP("assert(t1 != tlab size)");
3900 should_not_reach_here();
3901
3902 bind(ok);
3903 ldr(tsize, Address(post(sp, 16)));
3904 }
3905 #endif
3906 str(top, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
3907 str(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3908 add(top, top, t1);
3909 sub(top, top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
3910 str(top, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
3911 verify_tlab();
3912 b(retry);
3913
3914 return rthread; // for use by caller
3915 }
3916
3917 // Defines obj, preserves var_size_in_bytes
3918 void MacroAssembler::eden_allocate(Register obj,
3919 Register var_size_in_bytes,
3920 int con_size_in_bytes,
3921 Register t1,
3922 Label& slow_case) {
3923 assert_different_registers(obj, var_size_in_bytes, t1);
3924 if (!Universe::heap()->supports_inline_contig_alloc()) {
3925 b(slow_case);
3926 } else {
3927 Register end = t1;
3928 Register heap_end = rscratch2;
3929 Label retry;
3930 bind(retry);
3931 {
3932 unsigned long offset;
3933 adrp(rscratch1, ExternalAddress((address) Universe::heap()->end_addr()), offset);
3934 ldr(heap_end, Address(rscratch1, offset));
3935 }
3936
3937 ExternalAddress heap_top((address) Universe::heap()->top_addr());
3938
3939 // Get the current top of the heap
3940 {
3941 unsigned long offset;
3942 adrp(rscratch1, heap_top, offset);
3943 // Use add() here after ARDP, rather than lea().
3944 // lea() does not generate anything if its offset is zero.
3945 // However, relocs expect to find either an ADD or a load/store
3946 // insn after an ADRP. add() always generates an ADD insn, even
3947 // for add(Rn, Rn, 0).
3948 add(rscratch1, rscratch1, offset);
3949 ldaxr(obj, rscratch1);
3950 }
3951
3952 // Adjust it my the size of our new object
3953 if (var_size_in_bytes == noreg) {
3954 lea(end, Address(obj, con_size_in_bytes));
3955 } else {
3956 lea(end, Address(obj, var_size_in_bytes));
3957 }
3958
3959 // if end < obj then we wrapped around high memory
3960 cmp(end, obj);
3961 br(Assembler::LO, slow_case);
3962
3963 cmp(end, heap_end);
3964 br(Assembler::HI, slow_case);
3965
3966 // If heap_top hasn't been changed by some other thread, update it.
3967 stlxr(rscratch2, end, rscratch1);
3968 cbnzw(rscratch2, retry);
3969 }
3970 }
3971
3972 void MacroAssembler::verify_tlab() {
3973 #ifdef ASSERT
3974 if (UseTLAB && VerifyOops) {
3975 Label next, ok;
3976
3977 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
3978
3979 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3980 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
3981 cmp(rscratch2, rscratch1);
3982 br(Assembler::HS, next);
3983 STOP("assert(top >= start)");
3984 should_not_reach_here();
3985
3986 bind(next);
3987 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
3988 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
3989 cmp(rscratch2, rscratch1);
3990 br(Assembler::HS, ok);
3991 STOP("assert(top <= end)");
3992 should_not_reach_here();
3993
3994 bind(ok);
3995 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
3996 }
3997 #endif
3998 }
3999
4000 // Writes to stack successive pages until offset reached to check for
4001 // stack overflow + shadow pages. This clobbers tmp.
4002 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
4003 assert_different_registers(tmp, size, rscratch1);
4004 mov(tmp, sp);
4005 // Bang stack for total size given plus shadow page size.
4006 // Bang one page at a time because large size can bang beyond yellow and
4007 // red zones.
4008 Label loop;
4009 mov(rscratch1, os::vm_page_size());
4010 bind(loop);
4011 lea(tmp, Address(tmp, -os::vm_page_size()));
4012 subsw(size, size, rscratch1);
4013 str(size, Address(tmp));
4014 br(Assembler::GT, loop);
4015
4016 // Bang down shadow pages too.
4017 // At this point, (tmp-0) is the last address touched, so don't
4018 // touch it again. (It was touched as (tmp-pagesize) but then tmp
4019 // was post-decremented.) Skip this address by starting at i=1, and
4020 // touch a few more pages below. N.B. It is important to touch all
4021 // the way down to and including i=StackShadowPages.
4022 for (int i = 0; i < (int)(JavaThread::stack_shadow_zone_size() / os::vm_page_size()) - 1; i++) {
4023 // this could be any sized move but this is can be a debugging crumb
4024 // so the bigger the better.
4025 lea(tmp, Address(tmp, -os::vm_page_size()));
4026 str(size, Address(tmp));
4027 }
4028 }
4029
4030
4031 address MacroAssembler::read_polling_page(Register r, address page, relocInfo::relocType rtype) {
4032 unsigned long off;
4033 adrp(r, Address(page, rtype), off);
4034 InstructionMark im(this);
4035 code_section()->relocate(inst_mark(), rtype);
4036 ldrw(zr, Address(r, off));
4037 return inst_mark();
4038 }
4039
4040 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
4041 InstructionMark im(this);
4042 code_section()->relocate(inst_mark(), rtype);
4043 ldrw(zr, Address(r, 0));
4044 return inst_mark();
4045 }
4046
4047 void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
4048 relocInfo::relocType rtype = dest.rspec().reloc()->type();
4049 unsigned long low_page = (unsigned long)CodeCache::low_bound() >> 12;
4050 unsigned long high_page = (unsigned long)(CodeCache::high_bound()-1) >> 12;
4051 unsigned long dest_page = (unsigned long)dest.target() >> 12;
4052 long offset_low = dest_page - low_page;
4053 long offset_high = dest_page - high_page;
4054
4055 assert(is_valid_AArch64_address(dest.target()), "bad address");
4056 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
4057
4058 InstructionMark im(this);
4059 code_section()->relocate(inst_mark(), dest.rspec());
4060 // 8143067: Ensure that the adrp can reach the dest from anywhere within
4061 // the code cache so that if it is relocated we know it will still reach
4062 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
4063 _adrp(reg1, dest.target());
4064 } else {
4065 unsigned long target = (unsigned long)dest.target();
4066 unsigned long adrp_target
4067 = (target & 0xffffffffUL) | ((unsigned long)pc() & 0xffff00000000UL);
4068
4069 _adrp(reg1, (address)adrp_target);
4070 movk(reg1, target >> 32, 32);
4071 }
4072 byte_offset = (unsigned long)dest.target() & 0xfff;
4073 }
4074
4075 void MacroAssembler::load_byte_map_base(Register reg) {
4076 jbyte *byte_map_base =
4077 ((CardTableModRefBS*)(Universe::heap()->barrier_set()))->byte_map_base;
4078
4079 if (is_valid_AArch64_address((address)byte_map_base)) {
4080 // Strictly speaking the byte_map_base isn't an address at all,
4081 // and it might even be negative.
4082 unsigned long offset;
4083 adrp(reg, ExternalAddress((address)byte_map_base), offset);
4084 assert(offset == 0, "misaligned card table base");
4085 } else {
4086 mov(reg, (uint64_t)byte_map_base);
4087 }
4088 }
4089
4090 void MacroAssembler::build_frame(int framesize) {
4091 assert(framesize > 0, "framesize must be > 0");
4092 if (framesize < ((1 << 9) + 2 * wordSize)) {
4093 sub(sp, sp, framesize);
4094 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4095 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
4096 } else {
4097 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
4098 if (PreserveFramePointer) mov(rfp, sp);
4099 if (framesize < ((1 << 12) + 2 * wordSize))
4100 sub(sp, sp, framesize - 2 * wordSize);
4101 else {
4102 mov(rscratch1, framesize - 2 * wordSize);
4103 sub(sp, sp, rscratch1);
4104 }
4105 }
4106 }
4107
4108 void MacroAssembler::remove_frame(int framesize) {
4109 assert(framesize > 0, "framesize must be > 0");
4110 if (framesize < ((1 << 9) + 2 * wordSize)) {
4111 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4112 add(sp, sp, framesize);
4113 } else {
4114 if (framesize < ((1 << 12) + 2 * wordSize))
4115 add(sp, sp, framesize - 2 * wordSize);
4116 else {
4117 mov(rscratch1, framesize - 2 * wordSize);
4118 add(sp, sp, rscratch1);
4119 }
4120 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
4121 }
4122 }
4123
4124
4125 // Search for str1 in str2 and return index or -1
4126 void MacroAssembler::string_indexof(Register str2, Register str1,
4127 Register cnt2, Register cnt1,
4128 Register tmp1, Register tmp2,
4129 Register tmp3, Register tmp4,
4130 int icnt1, Register result) {
4131 Label BM, LINEARSEARCH, DONE, NOMATCH, MATCH;
4132
4133 Register ch1 = rscratch1;
4134 Register ch2 = rscratch2;
4135 Register cnt1tmp = tmp1;
4136 Register cnt2tmp = tmp2;
4137 Register cnt1_neg = cnt1;
4138 Register cnt2_neg = cnt2;
4139 Register result_tmp = tmp4;
4140
4141 // Note, inline_string_indexOf() generates checks:
4142 // if (substr.count > string.count) return -1;
4143 // if (substr.count == 0) return 0;
4144
4145 // We have two strings, a source string in str2, cnt2 and a pattern string
4146 // in str1, cnt1. Find the 1st occurence of pattern in source or return -1.
4147
4148 // For larger pattern and source we use a simplified Boyer Moore algorithm.
4149 // With a small pattern and source we use linear scan.
4150
4151 if (icnt1 == -1) {
4152 cmp(cnt1, 256); // Use Linear Scan if cnt1 < 8 || cnt1 >= 256
4153 ccmp(cnt1, 8, 0b0000, LO); // Can't handle skip >= 256 because we use
4154 br(LO, LINEARSEARCH); // a byte array.
4155 cmp(cnt1, cnt2, LSR, 2); // Source must be 4 * pattern for BM
4156 br(HS, LINEARSEARCH);
4157 }
4158
4159 // The Boyer Moore alogorithm is based on the description here:-
4160 //
4161 // http://en.wikipedia.org/wiki/Boyer%E2%80%93Moore_string_search_algorithm
4162 //
4163 // This describes and algorithm with 2 shift rules. The 'Bad Character' rule
4164 // and the 'Good Suffix' rule.
4165 //
4166 // These rules are essentially heuristics for how far we can shift the
4167 // pattern along the search string.
4168 //
4169 // The implementation here uses the 'Bad Character' rule only because of the
4170 // complexity of initialisation for the 'Good Suffix' rule.
4171 //
4172 // This is also known as the Boyer-Moore-Horspool algorithm:-
4173 //
4174 // http://en.wikipedia.org/wiki/Boyer-Moore-Horspool_algorithm
4175 //
4176 // #define ASIZE 128
4177 //
4178 // int bm(unsigned char *x, int m, unsigned char *y, int n) {
4179 // int i, j;
4180 // unsigned c;
4181 // unsigned char bc[ASIZE];
4182 //
4183 // /* Preprocessing */
4184 // for (i = 0; i < ASIZE; ++i)
4185 // bc[i] = 0;
4186 // for (i = 0; i < m - 1; ) {
4187 // c = x[i];
4188 // ++i;
4189 // if (c < ASIZE) bc[c] = i;
4190 // }
4191 //
4192 // /* Searching */
4193 // j = 0;
4194 // while (j <= n - m) {
4195 // c = y[i+j];
4196 // if (x[m-1] == c)
4197 // for (i = m - 2; i >= 0 && x[i] == y[i + j]; --i);
4198 // if (i < 0) return j;
4199 // if (c < ASIZE)
4200 // j = j - bc[y[j+m-1]] + m;
4201 // else
4202 // j += 1; // Advance by 1 only if char >= ASIZE
4203 // }
4204 // }
4205
4206 if (icnt1 == -1) {
4207 BIND(BM);
4208
4209 Label ZLOOP, BCLOOP, BCSKIP, BMLOOPSTR2, BMLOOPSTR1, BMSKIP;
4210 Label BMADV, BMMATCH, BMCHECKEND;
4211
4212 Register cnt1end = tmp2;
4213 Register str2end = cnt2;
4214 Register skipch = tmp2;
4215
4216 // Restrict ASIZE to 128 to reduce stack space/initialisation.
4217 // The presence of chars >= ASIZE in the target string does not affect
4218 // performance, but we must be careful not to initialise them in the stack
4219 // array.
4220 // The presence of chars >= ASIZE in the source string may adversely affect
4221 // performance since we can only advance by one when we encounter one.
4222
4223 stp(zr, zr, pre(sp, -128));
4224 for (int i = 1; i < 8; i++)
4225 stp(zr, zr, Address(sp, i*16));
4226
4227 mov(cnt1tmp, 0);
4228 sub(cnt1end, cnt1, 1);
4229 BIND(BCLOOP);
4230 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1)));
4231 cmp(ch1, 128);
4232 add(cnt1tmp, cnt1tmp, 1);
4233 br(HS, BCSKIP);
4234 strb(cnt1tmp, Address(sp, ch1));
4235 BIND(BCSKIP);
4236 cmp(cnt1tmp, cnt1end);
4237 br(LT, BCLOOP);
4238
4239 mov(result_tmp, str2);
4240
4241 sub(cnt2, cnt2, cnt1);
4242 add(str2end, str2, cnt2, LSL, 1);
4243 BIND(BMLOOPSTR2);
4244 sub(cnt1tmp, cnt1, 1);
4245 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1)));
4246 ldrh(skipch, Address(str2, cnt1tmp, Address::lsl(1)));
4247 cmp(ch1, skipch);
4248 br(NE, BMSKIP);
4249 subs(cnt1tmp, cnt1tmp, 1);
4250 br(LT, BMMATCH);
4251 BIND(BMLOOPSTR1);
4252 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1)));
4253 ldrh(ch2, Address(str2, cnt1tmp, Address::lsl(1)));
4254 cmp(ch1, ch2);
4255 br(NE, BMSKIP);
4256 subs(cnt1tmp, cnt1tmp, 1);
4257 br(GE, BMLOOPSTR1);
4258 BIND(BMMATCH);
4259 sub(result_tmp, str2, result_tmp);
4260 lsr(result, result_tmp, 1);
4261 add(sp, sp, 128);
4262 b(DONE);
4263 BIND(BMADV);
4264 add(str2, str2, 2);
4265 b(BMCHECKEND);
4266 BIND(BMSKIP);
4267 cmp(skipch, 128);
4268 br(HS, BMADV);
4269 ldrb(ch2, Address(sp, skipch));
4270 add(str2, str2, cnt1, LSL, 1);
4271 sub(str2, str2, ch2, LSL, 1);
4272 BIND(BMCHECKEND);
4273 cmp(str2, str2end);
4274 br(LE, BMLOOPSTR2);
4275 add(sp, sp, 128);
4276 b(NOMATCH);
4277 }
4278
4279 BIND(LINEARSEARCH);
4280 {
4281 Label DO1, DO2, DO3;
4282
4283 Register str2tmp = tmp2;
4284 Register first = tmp3;
4285
4286 if (icnt1 == -1)
4287 {
4288 Label DOSHORT, FIRST_LOOP, STR2_NEXT, STR1_LOOP, STR1_NEXT, LAST_WORD;
4289
4290 cmp(cnt1, 4);
4291 br(LT, DOSHORT);
4292
4293 sub(cnt2, cnt2, cnt1);
4294 sub(cnt1, cnt1, 4);
4295 mov(result_tmp, cnt2);
4296
4297 lea(str1, Address(str1, cnt1, Address::uxtw(1)));
4298 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4299 sub(cnt1_neg, zr, cnt1, LSL, 1);
4300 sub(cnt2_neg, zr, cnt2, LSL, 1);
4301 ldr(first, Address(str1, cnt1_neg));
4302
4303 BIND(FIRST_LOOP);
4304 ldr(ch2, Address(str2, cnt2_neg));
4305 cmp(first, ch2);
4306 br(EQ, STR1_LOOP);
4307 BIND(STR2_NEXT);
4308 adds(cnt2_neg, cnt2_neg, 2);
4309 br(LE, FIRST_LOOP);
4310 b(NOMATCH);
4311
4312 BIND(STR1_LOOP);
4313 adds(cnt1tmp, cnt1_neg, 8);
4314 add(cnt2tmp, cnt2_neg, 8);
4315 br(GE, LAST_WORD);
4316
4317 BIND(STR1_NEXT);
4318 ldr(ch1, Address(str1, cnt1tmp));
4319 ldr(ch2, Address(str2, cnt2tmp));
4320 cmp(ch1, ch2);
4321 br(NE, STR2_NEXT);
4322 adds(cnt1tmp, cnt1tmp, 8);
4323 add(cnt2tmp, cnt2tmp, 8);
4324 br(LT, STR1_NEXT);
4325
4326 BIND(LAST_WORD);
4327 ldr(ch1, Address(str1));
4328 sub(str2tmp, str2, cnt1_neg); // adjust to corresponding
4329 ldr(ch2, Address(str2tmp, cnt2_neg)); // word in str2
4330 cmp(ch1, ch2);
4331 br(NE, STR2_NEXT);
4332 b(MATCH);
4333
4334 BIND(DOSHORT);
4335 cmp(cnt1, 2);
4336 br(LT, DO1);
4337 br(GT, DO3);
4338 }
4339
4340 if (icnt1 == 4) {
4341 Label CH1_LOOP;
4342
4343 ldr(ch1, str1);
4344 sub(cnt2, cnt2, 4);
4345 mov(result_tmp, cnt2);
4346 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4347 sub(cnt2_neg, zr, cnt2, LSL, 1);
4348
4349 BIND(CH1_LOOP);
4350 ldr(ch2, Address(str2, cnt2_neg));
4351 cmp(ch1, ch2);
4352 br(EQ, MATCH);
4353 adds(cnt2_neg, cnt2_neg, 2);
4354 br(LE, CH1_LOOP);
4355 b(NOMATCH);
4356 }
4357
4358 if (icnt1 == -1 || icnt1 == 2) {
4359 Label CH1_LOOP;
4360
4361 BIND(DO2);
4362 ldrw(ch1, str1);
4363 sub(cnt2, cnt2, 2);
4364 mov(result_tmp, cnt2);
4365 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4366 sub(cnt2_neg, zr, cnt2, LSL, 1);
4367
4368 BIND(CH1_LOOP);
4369 ldrw(ch2, Address(str2, cnt2_neg));
4370 cmp(ch1, ch2);
4371 br(EQ, MATCH);
4372 adds(cnt2_neg, cnt2_neg, 2);
4373 br(LE, CH1_LOOP);
4374 b(NOMATCH);
4375 }
4376
4377 if (icnt1 == -1 || icnt1 == 3) {
4378 Label FIRST_LOOP, STR2_NEXT, STR1_LOOP;
4379
4380 BIND(DO3);
4381 ldrw(first, str1);
4382 ldrh(ch1, Address(str1, 4));
4383
4384 sub(cnt2, cnt2, 3);
4385 mov(result_tmp, cnt2);
4386 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4387 sub(cnt2_neg, zr, cnt2, LSL, 1);
4388
4389 BIND(FIRST_LOOP);
4390 ldrw(ch2, Address(str2, cnt2_neg));
4391 cmpw(first, ch2);
4392 br(EQ, STR1_LOOP);
4393 BIND(STR2_NEXT);
4394 adds(cnt2_neg, cnt2_neg, 2);
4395 br(LE, FIRST_LOOP);
4396 b(NOMATCH);
4397
4398 BIND(STR1_LOOP);
4399 add(cnt2tmp, cnt2_neg, 4);
4400 ldrh(ch2, Address(str2, cnt2tmp));
4401 cmp(ch1, ch2);
4402 br(NE, STR2_NEXT);
4403 b(MATCH);
4404 }
4405
4406 if (icnt1 == -1 || icnt1 == 1) {
4407 Label CH1_LOOP, HAS_ZERO;
4408 Label DO1_SHORT, DO1_LOOP;
4409
4410 BIND(DO1);
4411 ldrh(ch1, str1);
4412 cmp(cnt2, 4);
4413 br(LT, DO1_SHORT);
4414
4415 orr(ch1, ch1, ch1, LSL, 16);
4416 orr(ch1, ch1, ch1, LSL, 32);
4417
4418 sub(cnt2, cnt2, 4);
4419 mov(result_tmp, cnt2);
4420 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4421 sub(cnt2_neg, zr, cnt2, LSL, 1);
4422
4423 mov(tmp3, 0x0001000100010001);
4424 BIND(CH1_LOOP);
4425 ldr(ch2, Address(str2, cnt2_neg));
4426 eor(ch2, ch1, ch2);
4427 sub(tmp1, ch2, tmp3);
4428 orr(tmp2, ch2, 0x7fff7fff7fff7fff);
4429 bics(tmp1, tmp1, tmp2);
4430 br(NE, HAS_ZERO);
4431 adds(cnt2_neg, cnt2_neg, 8);
4432 br(LT, CH1_LOOP);
4433
4434 cmp(cnt2_neg, 8);
4435 mov(cnt2_neg, 0);
4436 br(LT, CH1_LOOP);
4437 b(NOMATCH);
4438
4439 BIND(HAS_ZERO);
4440 rev(tmp1, tmp1);
4441 clz(tmp1, tmp1);
4442 add(cnt2_neg, cnt2_neg, tmp1, LSR, 3);
4443 b(MATCH);
4444
4445 BIND(DO1_SHORT);
4446 mov(result_tmp, cnt2);
4447 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4448 sub(cnt2_neg, zr, cnt2, LSL, 1);
4449 BIND(DO1_LOOP);
4450 ldrh(ch2, Address(str2, cnt2_neg));
4451 cmpw(ch1, ch2);
4452 br(EQ, MATCH);
4453 adds(cnt2_neg, cnt2_neg, 2);
4454 br(LT, DO1_LOOP);
4455 }
4456 }
4457 BIND(NOMATCH);
4458 mov(result, -1);
4459 b(DONE);
4460 BIND(MATCH);
4461 add(result, result_tmp, cnt2_neg, ASR, 1);
4462 BIND(DONE);
4463 }
4464
4465 // Compare strings.
4466 void MacroAssembler::string_compare(Register str1, Register str2,
4467 Register cnt1, Register cnt2, Register result,
4468 Register tmp1) {
4469 Label LENGTH_DIFF, DONE, SHORT_LOOP, SHORT_STRING,
4470 NEXT_WORD, DIFFERENCE;
4471
4472 BLOCK_COMMENT("string_compare {");
4473
4474 // Compute the minimum of the string lengths and save the difference.
4475 subsw(tmp1, cnt1, cnt2);
4476 cselw(cnt2, cnt1, cnt2, Assembler::LE); // min
4477
4478 // A very short string
4479 cmpw(cnt2, 4);
4480 br(Assembler::LT, SHORT_STRING);
4481
4482 // Check if the strings start at the same location.
4483 cmp(str1, str2);
4484 br(Assembler::EQ, LENGTH_DIFF);
4485
4486 // Compare longwords
4487 {
4488 subw(cnt2, cnt2, 4); // The last longword is a special case
4489
4490 // Move both string pointers to the last longword of their
4491 // strings, negate the remaining count, and convert it to bytes.
4492 lea(str1, Address(str1, cnt2, Address::uxtw(1)));
4493 lea(str2, Address(str2, cnt2, Address::uxtw(1)));
4494 sub(cnt2, zr, cnt2, LSL, 1);
4495
4496 // Loop, loading longwords and comparing them into rscratch2.
4497 bind(NEXT_WORD);
4498 ldr(result, Address(str1, cnt2));
4499 ldr(cnt1, Address(str2, cnt2));
4500 adds(cnt2, cnt2, wordSize);
4501 eor(rscratch2, result, cnt1);
4502 cbnz(rscratch2, DIFFERENCE);
4503 br(Assembler::LT, NEXT_WORD);
4504
4505 // Last longword. In the case where length == 4 we compare the
4506 // same longword twice, but that's still faster than another
4507 // conditional branch.
4508
4509 ldr(result, Address(str1));
4510 ldr(cnt1, Address(str2));
4511 eor(rscratch2, result, cnt1);
4512 cbz(rscratch2, LENGTH_DIFF);
4513
4514 // Find the first different characters in the longwords and
4515 // compute their difference.
4516 bind(DIFFERENCE);
4517 rev(rscratch2, rscratch2);
4518 clz(rscratch2, rscratch2);
4519 andr(rscratch2, rscratch2, -16);
4520 lsrv(result, result, rscratch2);
4521 uxthw(result, result);
4522 lsrv(cnt1, cnt1, rscratch2);
4523 uxthw(cnt1, cnt1);
4524 subw(result, result, cnt1);
4525 b(DONE);
4526 }
4527
4528 bind(SHORT_STRING);
4529 // Is the minimum length zero?
4530 cbz(cnt2, LENGTH_DIFF);
4531
4532 bind(SHORT_LOOP);
4533 load_unsigned_short(result, Address(post(str1, 2)));
4534 load_unsigned_short(cnt1, Address(post(str2, 2)));
4535 subw(result, result, cnt1);
4536 cbnz(result, DONE);
4537 sub(cnt2, cnt2, 1);
4538 cbnz(cnt2, SHORT_LOOP);
4539
4540 // Strings are equal up to min length. Return the length difference.
4541 bind(LENGTH_DIFF);
4542 mov(result, tmp1);
4543
4544 // That's it
4545 bind(DONE);
4546
4547 BLOCK_COMMENT("} string_compare");
4548 }
4549
4550 // Compare Strings or char/byte arrays.
4551
4552 // is_string is true iff this is a string comparison.
4553
4554 // For Strings we're passed the address of the first characters in a1
4555 // and a2 and the length in cnt1.
4556
4557 // For byte and char arrays we're passed the arrays themselves and we
4558 // have to extract length fields and do null checks here.
4559
4560 // elem_size is the element size in bytes: either 1 or 2.
4561
4562 // There are two implementations. For arrays >= 8 bytes, all
4563 // comparisons (including the final one, which may overlap) are
4564 // performed 8 bytes at a time. For arrays < 8 bytes, we compare a
4565 // halfword, then a short, and then a byte.
4566
4567 void MacroAssembler::arrays_equals(Register a1, Register a2,
4568 Register result, Register cnt1,
4569 int elem_size, bool is_string)
4570 {
4571 Label SAME, DONE, SHORT, NEXT_WORD, ONE;
4572 Register tmp1 = rscratch1;
4573 Register tmp2 = rscratch2;
4574 Register cnt2 = tmp2; // cnt2 only used in array length compare
4575 int elem_per_word = wordSize/elem_size;
4576 int log_elem_size = exact_log2(elem_size);
4577 int length_offset = arrayOopDesc::length_offset_in_bytes();
4578 int base_offset
4579 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
4580
4581 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
4582 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
4583
4584 BLOCK_COMMENT(is_string ? "string_equals {" : "array_equals {");
4585
4586 mov(result, false);
4587
4588 if (!is_string) {
4589 // if (a==a2)
4590 // return true;
4591 eor(rscratch1, a1, a2);
4592 cbz(rscratch1, SAME);
4593 // if (a==null || a2==null)
4594 // return false;
4595 cbz(a1, DONE);
4596 cbz(a2, DONE);
4597 // if (a1.length != a2.length)
4598 // return false;
4599 ldrw(cnt1, Address(a1, length_offset));
4600 ldrw(cnt2, Address(a2, length_offset));
4601 eorw(tmp1, cnt1, cnt2);
4602 cbnzw(tmp1, DONE);
4603
4604 lea(a1, Address(a1, base_offset));
4605 lea(a2, Address(a2, base_offset));
4606 }
4607
4608 // Check for short strings, i.e. smaller than wordSize.
4609 subs(cnt1, cnt1, elem_per_word);
4610 br(Assembler::LT, SHORT);
4611 // Main 8 byte comparison loop.
4612 bind(NEXT_WORD); {
4613 ldr(tmp1, Address(post(a1, wordSize)));
4614 ldr(tmp2, Address(post(a2, wordSize)));
4615 subs(cnt1, cnt1, elem_per_word);
4616 eor(tmp1, tmp1, tmp2);
4617 cbnz(tmp1, DONE);
4618 } br(GT, NEXT_WORD);
4619 // Last longword. In the case where length == 4 we compare the
4620 // same longword twice, but that's still faster than another
4621 // conditional branch.
4622 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
4623 // length == 4.
4624 if (log_elem_size > 0)
4625 lsl(cnt1, cnt1, log_elem_size);
4626 ldr(tmp1, Address(a1, cnt1));
4627 ldr(tmp2, Address(a2, cnt1));
4628 eor(tmp1, tmp1, tmp2);
4629 cbnz(tmp1, DONE);
4630 b(SAME);
4631
4632 bind(SHORT);
4633 Label TAIL03, TAIL01;
4634
4635 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
4636 {
4637 ldrw(tmp1, Address(post(a1, 4)));
4638 ldrw(tmp2, Address(post(a2, 4)));
4639 eorw(tmp1, tmp1, tmp2);
4640 cbnzw(tmp1, DONE);
4641 }
4642 bind(TAIL03);
4643 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
4644 {
4645 ldrh(tmp1, Address(post(a1, 2)));
4646 ldrh(tmp2, Address(post(a2, 2)));
4647 eorw(tmp1, tmp1, tmp2);
4648 cbnzw(tmp1, DONE);
4649 }
4650 bind(TAIL01);
4651 if (elem_size == 1) { // Only needed when comparing byte arrays.
4652 tbz(cnt1, 0, SAME); // 0-1 bytes left.
4653 {
4654 ldrb(tmp1, a1);
4655 ldrb(tmp2, a2);
4656 eorw(tmp1, tmp1, tmp2);
4657 cbnzw(tmp1, DONE);
4658 }
4659 }
4660 // Arrays are equal.
4661 bind(SAME);
4662 mov(result, true);
4663
4664 // That's it.
4665 bind(DONE);
4666 BLOCK_COMMENT(is_string ? "} string_equals" : "} array_equals");
4667 }
4668
4669
4670 // encode char[] to byte[] in ISO_8859_1
4671 void MacroAssembler::encode_iso_array(Register src, Register dst,
4672 Register len, Register result,
4673 FloatRegister Vtmp1, FloatRegister Vtmp2,
4674 FloatRegister Vtmp3, FloatRegister Vtmp4)
4675 {
4676 Label DONE, NEXT_32, LOOP_8, NEXT_8, LOOP_1, NEXT_1;
4677 Register tmp1 = rscratch1;
4678
4679 mov(result, len); // Save initial len
4680
4681 #ifndef BUILTIN_SIM
4682 subs(len, len, 32);
4683 br(LT, LOOP_8);
4684
4685 // The following code uses the SIMD 'uqxtn' and 'uqxtn2' instructions
4686 // to convert chars to bytes. These set the 'QC' bit in the FPSR if
4687 // any char could not fit in a byte, so clear the FPSR so we can test it.
4688 clear_fpsr();
4689
4690 BIND(NEXT_32);
4691 ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src);
4692 uqxtn(Vtmp1, T8B, Vtmp1, T8H); // uqxtn - write bottom half
4693 uqxtn(Vtmp1, T16B, Vtmp2, T8H); // uqxtn2 - write top half
4694 uqxtn(Vtmp2, T8B, Vtmp3, T8H);
4695 uqxtn(Vtmp2, T16B, Vtmp4, T8H); // uqxtn2
4696 get_fpsr(tmp1);
4697 cbnzw(tmp1, LOOP_8);
4698 st1(Vtmp1, Vtmp2, T16B, post(dst, 32));
4699 subs(len, len, 32);
4700 add(src, src, 64);
4701 br(GE, NEXT_32);
4702
4703 BIND(LOOP_8);
4704 adds(len, len, 32-8);
4705 br(LT, LOOP_1);
4706 clear_fpsr(); // QC may be set from loop above, clear again
4707 BIND(NEXT_8);
4708 ld1(Vtmp1, T8H, src);
4709 uqxtn(Vtmp1, T8B, Vtmp1, T8H);
4710 get_fpsr(tmp1);
4711 cbnzw(tmp1, LOOP_1);
4712 st1(Vtmp1, T8B, post(dst, 8));
4713 subs(len, len, 8);
4714 add(src, src, 16);
4715 br(GE, NEXT_8);
4716
4717 BIND(LOOP_1);
4718 adds(len, len, 8);
4719 br(LE, DONE);
4720 #else
4721 cbz(len, DONE);
4722 #endif
4723 BIND(NEXT_1);
4724 ldrh(tmp1, Address(post(src, 2)));
4725 tst(tmp1, 0xff00);
4726 br(NE, DONE);
4727 strb(tmp1, Address(post(dst, 1)));
4728 subs(len, len, 1);
4729 br(GT, NEXT_1);
4730
4731 BIND(DONE);
4732 sub(result, result, len); // Return index where we stopped
4733 }
4734
4735 // get_thread() can be called anywhere inside generated code so we
4736 // need to save whatever non-callee save context might get clobbered
4737 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
4738 // the call setup code.
4739 //
4740 // aarch64_get_thread_helper() clobbers only r0, r1, and flags.
4741 //
4742 void MacroAssembler::get_thread(Register dst) {
4743 RegSet saved_regs = RegSet::range(r0, r1) + lr - dst;
4744 push(saved_regs, sp);
4745
4746 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
4747 blrt(lr, 1, 0, 1);
4748 if (dst != c_rarg0) {
4749 mov(dst, c_rarg0);
4750 }
4751
4752 pop(saved_regs, sp);
4753 }